@@ -1117,29 +1117,26 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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let rs1 = Register :: from( l. rs1( ) ) ;
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let src_expr = il. add( max_width, rs1, l. imm( ) ) ;
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- let load_expr = il. load( size, src_expr)
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- . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
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+ let load_expr = il. load( size, src_expr) . build( ) . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
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match ( size < max_width, l. zx( ) ) {
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( false , _) => load_expr,
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- ( true , true ) => il. zx( max_width, load_expr) ,
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- ( true , false ) => il. sx( max_width, load_expr) ,
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+ ( true , true ) => il. zx( max_width, load_expr) . build ( ) ,
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+ ( true , false ) => il. sx( max_width, load_expr) . build ( ) ,
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}
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} ) ,
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Op :: Store ( s) => {
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let size = s. width ( ) ;
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let dest = il. add ( max_width, Register :: from ( s. rs1 ( ) ) , s. imm ( ) ) ;
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let mut src = il
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. expression ( Register :: from ( s. rs2 ( ) ) )
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- . with_source_operand ( 0 ) ;
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+ . with_source_operand ( LowLevelILOperandIndex ( 0 ) ) ;
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if size < max_width {
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src = il. low_part ( size, src) . build ( ) ;
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}
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- il. store ( size, dest, src)
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- . with_source_operand ( LowLevelILOperandIndex ( 1 ) )
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- . append ( ) ;
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+ il. store ( size, dest, src) . build ( ) . with_source_operand ( LowLevelILOperandIndex ( 1 ) ) . append ( ) ;
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}
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Op :: AddI ( i) => simple_i ! ( i, |rs1, imm| il. add( max_width, rs1, imm) ) ,
@@ -1461,12 +1458,11 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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Op :: Lr ( a) => simple_op ! ( a, no_discard {
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let size = a. width( ) ;
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- let load_expr = il. load( size, Register :: from( a. rs1( ) ) )
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- . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
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+ let load_expr = il. load( size, Register :: from( a. rs1( ) ) ) . build( ) . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
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match size == max_width {
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true => load_expr,
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- false => il. sx( max_width, load_expr) ,
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+ false => il. sx( max_width, load_expr) . build ( ) ,
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}
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} ) ,
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Op :: Sc ( a) => {
@@ -1499,9 +1495,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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il. if_expr ( cond_expr, & mut t, & mut f) . append ( ) ;
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il. mark_label ( & mut t) ;
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- il. store ( size, Register :: from ( a. rs1 ( ) ) , Register :: from ( a. rs2 ( ) ) )
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- . with_source_operand ( LowLevelILOperandIndex ( 2 ) )
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- . append ( ) ;
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+ il. store ( size, Register :: from ( a. rs1 ( ) ) , Register :: from ( a. rs2 ( ) ) ) . build ( ) . with_source_operand ( LowLevelILOperandIndex ( 1 ) ) . append ( ) ;
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if new_false {
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il. mark_label ( & mut f) ;
@@ -1544,10 +1538,11 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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let mut load_expr = il
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. load ( size, Register :: from ( rs1) )
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+ . build ( )
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. with_source_operand ( LowLevelILOperandIndex ( 2 ) ) ;
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if size < max_width {
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- load_expr = il. sx ( max_width, load_expr) ;
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+ load_expr = il. sx ( max_width, load_expr) . build ( ) ;
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}
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il. set_reg ( max_width, dest_reg, load_expr) . append ( ) ;
@@ -1576,6 +1571,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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let load_expr = il
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. load ( m. width ( ) , il. add ( max_width, rs1, m. imm ( ) ) )
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+ . build ( )
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. with_source_operand ( LowLevelILOperandIndex ( 1 ) ) ;
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il. set_reg ( m. width ( ) , rd, load_expr) . append ( ) ;
@@ -1587,6 +1583,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
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let dest_expr = il. add ( max_width, rs1, m. imm ( ) ) ;
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il. store ( m. width ( ) , dest_expr, il. reg ( m. width ( ) , rs2) )
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+ . build ( )
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. with_source_operand ( LowLevelILOperandIndex ( 1 ) )
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. append ( ) ;
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}
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