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Add Avalon-MM and Avalon-ST Minimal interface packages
1 parent 5df447d commit 2880a0c

10 files changed

+227
-76
lines changed

‎Avalon/v1/AvalonMM.vhdl‎

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@@ -82,33 +82,4 @@ package AvalonMM is
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end view;
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alias AvalonMM_SlaveView is AvalonMM_MasterView'converse;
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-- Simplified interface without optional signals
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type AvalonMM_Simple_Interface is record
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-- Master signals
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Address : Address_Type;
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Read : std_ulogic;
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Write : std_ulogic;
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WriteData : Data_Type;
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ByteEnable : ByteEnable_Type;
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-- Slave signals
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ReadData : Data_Type;
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WaitRequest : std_ulogic;
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end record;
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type AvalonMM_Simple_Interface_Vector is array(natural range <>) of AvalonMM_Simple_Interface;
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view AvalonMM_Simple_MasterView of AvalonMM_Simple_Interface is
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-- Master outputs
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Address : out;
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Read : out;
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Write : out;
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WriteData : out;
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ByteEnable : out;
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-- Master inputs
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ReadData : in;
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WaitRequest : in;
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end view;
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alias AvalonMM_Simple_SlaveView is AvalonMM_Simple_MasterView'converse;
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end package;

‎Avalon/v1/AvalonMM_Generic.vhdl‎

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@@ -53,19 +53,4 @@ package AvalonMM_Generic is
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BurstCount(BURSTCOUNT_BITS - 1 downto 0)
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);
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-- Simplified Avalon-MM interface
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subtype AvalonMM_Simple_SizedInterface is AvalonMM_Simple_Interface(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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subtype AvalonMM_Simple_SizedInterface_Vector is AvalonMM_Simple_Interface_Vector(open)(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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end package;

‎Avalon/v1/AvalonMM_Minimal.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Minimal Avalon Memory-Mapped interface
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--
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-- Description:
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-- Simplified Avalon MM interface without optional signals for basic use cases
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.AvalonCommon.all;
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package AvalonMM_Minimal is
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-- Minimal Avalon MM interface (only essential signals)
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type AvalonMM_Minimal_Interface is record
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-- Master signals
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Address : Address_Type;
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Read : std_ulogic;
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Write : std_ulogic;
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WriteData : Data_Type;
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ByteEnable : ByteEnable_Type;
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-- Slave signals
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ReadData : Data_Type;
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WaitRequest : std_ulogic;
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end record;
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type AvalonMM_Minimal_Interface_Vector is array(natural range <>) of AvalonMM_Minimal_Interface;
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-- Master view
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view AvalonMM_Minimal_MasterView of AvalonMM_Minimal_Interface is
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-- Master outputs
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Address : out;
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Read : out;
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Write : out;
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WriteData : out;
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ByteEnable : out;
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-- Master inputs (slave outputs)
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ReadData : in;
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WaitRequest : in;
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end view;
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alias AvalonMM_Minimal_SlaveView is AvalonMM_Minimal_MasterView'converse;
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end package;

‎Avalon/v1/AvalonMM_Minimal_Generic.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Generic minimal Avalon Memory-Mapped interface for pre-constraining widths
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--
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-- Description:
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-- Provides sized versions of the minimal Avalon MM interface
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
22+
-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
25+
-- limitations under the License.
26+
-- =============================================================================
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28+
use work.AvalonMM_Minimal.all;
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package AvalonMM_Minimal_Generic is
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generic (
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constant ADDRESS_BITS : positive;
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constant DATA_BITS : positive
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);
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constant BYTEENABLE_BITS : positive := DATA_BITS / 8;
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-- Sized minimal interface
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subtype AvalonMM_Minimal_SizedInterface is AvalonMM_Minimal_Interface(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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subtype AvalonMM_Minimal_SizedInterface_Vector is AvalonMM_Minimal_Interface_Vector(open)(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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end package;

‎Avalon/v1/AvalonST.vhdl‎

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@@ -70,25 +70,4 @@ package AvalonST is
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end view;
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alias AvalonST_SinkView is AvalonST_SourceView'converse;
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-- Simplified interface without optional signals
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type AvalonST_Simple_Interface is record
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-- Handshake signals
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Valid : std_ulogic;
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Ready : std_ulogic;
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-- Payload signal
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Data : Data_Type;
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end record;
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type AvalonST_Simple_Interface_Vector is array(natural range <>) of AvalonST_Simple_Interface;
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view AvalonST_Simple_SourceView of AvalonST_Simple_Interface is
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-- Source outputs
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Valid : out;
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Data : out;
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-- Source inputs
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Ready : in;
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end view;
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alias AvalonST_Simple_SinkView is AvalonST_Simple_SourceView'converse;
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end package;

‎Avalon/v1/AvalonST_Generic.vhdl‎

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@@ -50,13 +50,4 @@ package AvalonST_Generic is
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Channel(CHANNEL_BITS - 1 downto 0)
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);
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-- Simplified Avalon-ST interface
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subtype AvalonST_Simple_SizedInterface is AvalonST_Simple_Interface(
55-
Data(DATA_BITS - 1 downto 0)
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);
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subtype AvalonST_Simple_SizedInterface_Vector is AvalonST_Simple_Interface_Vector(open)(
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Data(DATA_BITS - 1 downto 0)
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);
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end package;

‎Avalon/v1/AvalonST_Minimal.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Minimal Avalon Streaming interface
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--
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-- Description:
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-- Simplified Avalon ST interface without optional signals for basic streaming
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
17+
-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
20+
--
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-- Unless required by applicable law or agreed to in writing, software
22+
-- distributed under the License is distributed on an "AS IS" BASIS,
23+
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24+
-- See the License for the specific language governing permissions and
25+
-- limitations under the License.
26+
-- =============================================================================
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28+
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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32+
use work.AvalonCommon.all;
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34+
package AvalonST_Minimal is
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-- Minimal Avalon ST interface (only essential signals)
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type AvalonST_Minimal_Interface is record
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-- Source signals
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Data : Data_Type;
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Valid : std_ulogic;
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-- Sink signals
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Ready : std_ulogic;
43+
end record;
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type AvalonST_Minimal_Interface_Vector is array(natural range <>) of AvalonST_Minimal_Interface;
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-- Source view
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view AvalonST_Minimal_SourceView of AvalonST_Minimal_Interface is
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-- Source outputs
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Data : out;
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Valid : out;
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-- Source inputs (sink outputs)
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Ready : in;
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end view;
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alias AvalonST_Minimal_SinkView is AvalonST_Minimal_SourceView'converse;
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end package;

‎Avalon/v1/AvalonST_Minimal_Generic.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
6+
-- Generic minimal Avalon Streaming interface for pre-constraining widths
7+
--
8+
-- Description:
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-- Provides sized versions of the minimal Avalon ST interface
10+
--
11+
-- License:
12+
-- =============================================================================
13+
-- Copyright 2025-2025 Open Source VHDL Group
14+
--
15+
-- Licensed under the Apache License, Version 2.0 (the "License");
16+
-- you may not use this file except in compliance with the License.
17+
-- You may obtain a copy of the License at
18+
--
19+
-- http://www.apache.org/licenses/LICENSE-2.0
20+
--
21+
-- Unless required by applicable law or agreed to in writing, software
22+
-- distributed under the License is distributed on an "AS IS" BASIS,
23+
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24+
-- See the License for the specific language governing permissions and
25+
-- limitations under the License.
26+
-- =============================================================================
27+
28+
use work.AvalonST_Minimal.all;
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package AvalonST_Minimal_Generic is
31+
generic (
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constant DATA_BITS : positive
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);
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-- Sized minimal interface
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subtype AvalonST_Minimal_SizedInterface is AvalonST_Minimal_Interface(
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Data(DATA_BITS - 1 downto 0)
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);
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subtype AvalonST_Minimal_SizedInterface_Vector is AvalonST_Minimal_Interface_Vector(open)(
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Data(DATA_BITS - 1 downto 0)
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);
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end package;

‎build.pro‎

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@@ -57,5 +57,9 @@ analyze PoC/CSE.vhdl
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analyze Avalon/v1/AvalonCommon.vhdl
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analyze Avalon/v1/AvalonMM.vhdl
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analyze Avalon/v1/AvalonMM_Generic.vhdl
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analyze Avalon/v1/AvalonMM_Minimal.vhdl
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analyze Avalon/v1/AvalonMM_Minimal_Generic.vhdl
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analyze Avalon/v1/AvalonST.vhdl
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analyze Avalon/v1/AvalonST_Generic.vhdl
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analyze Avalon/v1/AvalonST_Minimal.vhdl
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analyze Avalon/v1/AvalonST_Minimal_Generic.vhdl

‎compileorder.list‎

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@@ -51,11 +51,13 @@ MIPI/M-PHY.vhdl
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# Miscellaneous interfaces
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PoC/CSE.vhdl
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# Avalon Memory-Mapped Interfaces
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Avalon/v1/AvalonCommon.vhdl
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Avalon/v1/AvalonMM.vhdl
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Avalon/v1/AvalonMM_Generic.vhdl
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Avalon/v1/AvalonMM_Minimal.vhdl
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Avalon/v1/AvalonMM_Minimal_Generic.vhdl
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Avalon/v1/AvalonST.vhdl
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Avalon/v1/AvalonST_Generic.vhdl
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Avalon/v1/AvalonST_Minimal.vhdl
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Avalon/v1/AvalonST_Minimal_Generic.vhdl

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