Need help in custom cell placement since they overlap with power grip

[OuDret]

Hello,

I'm trying to use openroad commands to place custom pdk cells but they overlap with power grid.

Here in https://github.com/OuDret/my_pdk/tree/main you can see all the files I'm using.

There are also all the commands I'm running in ./flow.txt. You can simply copy-paste all the lines in flow.txt file into OpenRoad command line at once to reproduce the case.

Unfortunately I'm using absolute path when loading tech and design so you may need to change it.

I'm trying to simplify the flow as much as I can so I may have forgotten to run some important steps.

Thank you for any advice you can provide

[EDIT] I forgot to show the 2 warnings that are raised when I run improve_placement which must be related to the overlap issue.

  [WARNING DPO-0201] Placement check failure during legalization.
  [WARNING DPO-0381] Encountered 57 issues when orienting cells for rows.

[maliberty]

Where is this process are you manually placing these cells? Are you marking them as fixed?

[OuDret]

I'm not manually placing those cells but using global + detailed placement tools:

# 3.1 global_place_skipping_io
global_placement -skip_io -density 0.3 -pad_left 0 -pad_right 0 

# io_placement
place_pins -ver_layer met3 -hor_layer met1

# global_place
set_dont_use FILL
set_global_routing_layer_adjustment met1-met3 0.3
set_routing_layers -signal met1-met3
global_placement -density 0.6 -pad_left 0 -pad_right 0 -routability_driven
estimate_parasitics -placement

# detail_placement
set_layer_rc -layer met1 -capacitance 1.72375E-04 -resistance 8.929e-04  
set_layer_rc -layer met2 -capacitance 1.36233E-04 -resistance 8.929e-04  
set_layer_rc -layer met3 -capacitance 2.14962E-04 -resistance 1.567e-04  
set_layer_rc -via via -resistance 4.5E-3                                
set_layer_rc -via via2 -resistance 3.368786E-3                           
set_wire_rc -signal -layer met3                                          
set_wire_rc -clock -layer met3        

set_placement_padding -global -left 0 -right 0
detailed_placement -disallow_one_site_gaps
improve_placement                                              # this command actually returns the warnings
optimize_mirroring
check_placement -verbose                                  # this line print nothing in command line

lef files can be found in the repository Iink above

I think I did not mark them as fixed since I don't know where to define it in case I needed to.

[maliberty]

The cells just happen to exactly align with the power straps in your image? It seems improbable

[maliberty]

Where is the script to run this?

[OuDret]

yes, they exactly align with the power straps, which are also aligned with stdcell edges

[maliberty]

I tried to run flow.txt but I get in global placement:

[ERROR GRT-0126] Layers met2 and met3 have the same preferred routing direction 
(VERTICAL).

This seems wrong - can you explain what the intention is?

[rovinski]

Is your version of OpenROAD up to date?

[maliberty]

Please show the header OR prints at startup.

[OuDret]

[maliberty]

That commit is from Aug 30 so please update and try again.

[OuDret]

Hello, I did update OpenRoad and got the same error you were encountering in global placement, so I edited the .lef tech file so now met1 & met3 DIRECTION is HORIZONTAL while met2 is VERTICAL.

Once solved, I tried running the following commands and found that cells keep overlapping with power grid. Do you have any idea of what's happening? Thanks.

# 2.1 floorplan init
read_liberty ./platforms/NandCellLibrary/lib/NandCellLibrary.lib
read_lef ./platforms/NandCellLibrary/lef/NandCellLibrary.tech.lef
read_lef ./platforms/NandCellLibrary/lef/NandCellLibrary.macro.lef  
#read_verilog ./designs/NandCellLibrary/inverter/src/inverter.v
#link_design inverter
#read_sdc ./designs/NandCellLibrary/inverter/constraint.sdc
read_verilog ./designs/NandCellLibrary/counter4bit/src/counter4bit.v
link_design counter4bit
read_sdc ./designs/NandCellLibrary/counter4bit/constraint.sdc

initialize_floorplan -die_area {0 0 100 100} -core_area {10 10 90 90} -site unithd

make_tracks met1 -x_offset 0.5 -x_pitch 0.5 -y_offset 0.5 -y_pitch 0.5
make_tracks met2 -x_offset 0.5 -x_pitch 0.5 -y_offset 0.5 -y_pitch 0.5
make_tracks met3 -x_offset 0.5 -x_pitch 0.5 -y_offset 0.5 -y_pitch 0.5

remove_buffers

# 2.2 place pins
place_pins -hor_layer met1 -ver_layer met2 -random

# 2.3 tdms place
global_placement -density 0.5 -pad_left 0 -pad_right 0

# 2.5 pdn
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground

set_voltage_domain -power {VDD} -ground {VSS}

define_pdn_grid -name "CORE"

add_pdn_stripe -grid "CORE" -layer {met1} -width 1 -pitch 10
add_pdn_stripe -grid "CORE" -layer {met3} -width 1 -pitch 10
add_pdn_connect -grid "CORE" -layers {met1 met3}

pdngen

# 3.1 global_place_skip_io.tcl
global_placement -skip_io -density 0.3 -pad_left 0 -pad_right 0 

# 3.2 io_placement
place_pins -ver_layer met2 -hor_layer met1

# 3.3 global_place
set_dont_use FILL
set_global_routing_layer_adjustment met1-met3 0.3
set_routing_layers -signal met1-met3
global_placement -density 0.6 -pad_left 0 -pad_right 0 -routability_driven
estimate_parasitics -placement

# 3.5 detail_placement
set_layer_rc -layer met1 -capacitance 1.72375E-04 -resistance 8.929e-04  
set_layer_rc -layer met2 -capacitance 1.36233E-04 -resistance 8.929e-04  
set_layer_rc -layer met3 -capacitance 2.14962E-04 -resistance 1.567e-04  
set_layer_rc -via via -resistance 4.5E-3                                
set_layer_rc -via via2 -resistance 3.368786E-3                           
set_wire_rc -signal -layer met3                                          
set_wire_rc -clock -layer met3        

set_placement_padding -global -left 0 -right 0
detailed_placement -disallow_one_site_gaps