Problem in Memory synthesis(Syntax Error)

[Prathmesh291]

I am using Yosys for synthesis of memory. Then I am taking the netlist generated to openroad for all the next sequence of steps. However, it is showing syntax error whenever I have a memory type element. Even if I try for a single port ram, it is showing syntax error at the line of memory.
By memory I mean (ex- reg [0:3] cpu [0:15])
I am using gcd nangate45 library

[maliberty]

reg [0:3] cpu [0:15] should not be in the output of synthesis so something is wrong there. It is not a structural construct. There is too little information to suggest anything. Please open an issue with a test case if possible.