Design size and memory usage

[lustefan97]

Hello,

I have a question regarding the relationship between the design size and the memory usage.

I use a virtual machine, with 16GB of RAM allocated to it. I tried to run an LDPC design, which made the memory usage skyrocket. I wanted to see some test to see what would have the most impact on memory usage, so I created a very simple and stupid adder design where I increased its input and output word size from 128bit to 5120bit. Then I ran the design through OpenROAD, where I started from a very large die (core_utilization=5 and placement_density=0.1) and reduced the die size incrementally (up to core_utilization=50and placement_density=0.8). These are the results that I obtained :

What surprised me was that even though, unsurprisingly, higher cell count and wire length (due to the larger adder) resulted in higher memory usage, the memory footprint was always higher when using a larger die area even if the design in itself was very small in comparison.

I was wondering why it was so, why is it that when the die is bigger so is the memory used, is it because objects such as filler cells are also loaded in ?
Since the memory used also increase during the run : would it be possible to run a design, too big to be done in one run, in two separated runs to alleviate the limited RAM available ? Or will the memory be filled as soon as the database is loaded in ?

[maliberty]

A bigger die area means more placement sites in the rows, more area to manage during placement, more fill cells, etc.

On what PDK was this experiment? In your highest memory case, what was the memory usage at each step?

If you split the design and the build an abstract (a .lef & .lib) for each piece then the top level will take less memory as it isn't seeing the details. This is a common strategy for hierarchical design. You can see an example of this in https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/asap7/mock-array

[lustefan97]

That makes perfect sense, I'll look into the example you gave me.

I am using the ASAP7 PDK, regarding the memory usage at each step the first report for memory in my logs occurs during the detailed placement step and goes as follows :

Which isn't surprising to me since there is quite a lot of wires and paths to handle there, and with your comment now I understand that the tool also still sees every other element of the chip which adds up. I look into the other method, but does the PDK really influence the memory footprint that much ?

[maliberty]

PDK is somewhat secondary but the more routing layers you have will somewhat increase router memory.

[lustefan97]

Ok now I understand, thank you !