Constraining a synchronizer

[scorbetta]

Hi, my design has a simple two-stages at the top-level, where two clocks CLK1 and CLK2 with same frequency but unknown phase exist.

// overflow generated at @CLK1

// CLK1->CLK2 synchronizer
always @(posedge CLK2) begin
   overflow_r1 <= overflow;
   overflow_r2 <= overflow_r1;
end

// @CLK2
assign debug_signal = overflow_r2;

Now, I would like to properly constraint this. I'm used to the FPGA way, where I set false path from the first clock CLK1 to the first register pin overflow_r1/D and then mark it as REG_ASYNC. How can I do it properly with OpenLane? I'm getting hard times since the netlist is already flattened at this point, so I lose all names and it is hard to find exactly that one register using Tcl...