unable to make file due to IEEE.STD_LOGIC_UNSIGNED.ALL

[saltyboi-1]

whenever i try to compile and build the vhdl code i get the following error which is

2024-11-25 18:34:59.520 [info] c:\Users\.vscode-oss\extensions\teros-technology.teroshdl-6.0.14-universal\resources\project_manager\examples\raptor_counter_vhdl\pin_mapping.pin has unknown file type 'pin'

2024-11-25 18:34:59.728 [info] "Creating libraries directories"

2024-11-25 18:34:59.732 [info] ghdl -i --std=08 c:\Users\.vscode-oss\extensions\teros-technology.teroshdl-6.0.14-universal\resources\project_manager\examples\raptor_counter_vhdl\UP_COUNTER.vhd

2024-11-25 18:35:00.057 [info] "Creating libraries directories"

2024-11-25 18:35:00.061 [info] ghdl -i --std=08 c:\Users\.vscode-oss\extensions\teros-technology.teroshdl-6.0.14-universal\resources\project_manager\examples\raptor_counter_vhdl\UP_COUNTER.vhd

2024-11-25 18:35:00.075 [info] ghdl -m --std=08 UP_COUNTER

2024-11-25 18:35:00.642 [info] c:\Users\.vscode-oss\extensions\teros-technology.teroshdl-6.0.14-universal\resources\project_manager\examples\raptor_counter_vhdl\UP_COUNTER.vhd:3:10:error: use of synopsys package "std_logic_unsigned" needs the -fsynopsys option
use IEEE.STD_LOGIC_UNSIGNED.ALL;
^

2024-11-25 18:35:00.644 [info] make: *** [Makefile:16: UP_COUNTER] Error 1

2024-11-25 18:35:00.649 [info]

---

---> Build directory: C:\Users\.teroshdl\build
---> Make installation folder path:
Error: '['make', 'run']' exited with an error: 2

and a problem log that says

error: use of synopsys package "std_logic_unsigned" needs the -fsynopsys option
error: entity "UP_COUNTER" was not analysed

for context this the code that am trying to build

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for up counter
entity UP_COUNTER is
Port ( clock0: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end UP_COUNTER;

architecture Behavioral of UP_COUNTER is
signal counter_up: std_logic_vector(3 downto 0);
begin
-- up counter
process(clock0)
begin
if(rising_edge(clock0)) then
if(reset='1') then
counter_up <= x"0";
else
counter_up <= counter_up + x"1";
end if;
end if;
end process;
counter <= counter_up;

end Behavioral;

which is an example program that is included with teroshdl

Please complete the following information:

• OS: windows11
• VSCodium 1.95.3
• teroshdl v6.0.14

[qarlosalberto]

You can follow this tutorial: https://terostechnology.github.io/terosHDLdoc/docs/tutorials/tutorial_vhdl