Why my code doesn't produce a FSM ?

[FinnNGrace]

Describe the bug
TerosHDL cannot produce a FSM

Code
timescale 1ns/1ns

module vending_machine(
input wire clk,
input wire rst_n,
input wire nickle,
input wire dime,
input wire quarter,
output reg soda,
output reg [2:0] change
);

localparam S0 = 4'd0, // soda = 0, change = 0
S5 = 4'd1, // soda = 0, change = 0
S10 = 4'd2, // soda = 0, change = 0
S15 = 4'd3, // soda = 0, change = 0
S20 = 4'd4, // soda = 1, change = 0
S25 = 4'd5, // soda = 1, change = 5
S30 = 4'd6, // soda = 1, change = 10
S35 = 4'd7, // soda = 1, change = 15
S40 = 4'd8; // soda = 1, change = 20

localparam C0 = 3'b000, // change = 0
C5 = 3'b001, // change = 5
C10 = 3'b010, // change = 10
C15 = 3'b011, // change = 15
C20 = 3'b100; // change = 20

reg [3:0] state, next_state;

// input equation
always @(*) begin
case (state)
S0: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = state;
endcase
S5: case({nickle, dime, quarter})
3'b100: next_state = S10;
3'b010: next_state = S15;
3'b001: next_state = S30;
default: next_state = state;
endcase
S10: case({nickle, dime, quarter})
3'b100: next_state = S15;
3'b010: next_state = S20;
3'b001: next_state = S35;
default: next_state = state;
endcase
S15: case({nickle, dime, quarter})
3'b100: next_state = S20;
3'b010: next_state = S25;
3'b001: next_state = S40;
default: next_state = state;
endcase
S20: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
S25: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
S30: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
S35: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
S40: case({nickle, dime, quarter})
3'b100: next_state = S5;
3'b010: next_state = S10;
3'b001: next_state = S25;
default: next_state = S0;
endcase
default: next_state = state;
endcase
end

// sequential logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= S0;
end
else begin
state <= next_state;
end
end

// output equation
always @(*) begin
case(state)
S0: begin soda = 0; change = C0; end
S5: begin soda = 0; change = C0; end
S10: begin soda = 0; change = C0; end
S15: begin soda = 0; change = C0; end
S20: begin soda = 1; change = C0; end
S25: begin soda = 1; change = C5; end
S30: begin soda = 1; change = C10; end
S35: begin soda = 1; change = C15; end
S40: begin soda = 1; change = C20; end
default: begin soda = 0; change = C0; end
endcase
end

endmodule
`

Please complete the following information:

• OS: Window 10 Pro 64 bit
• VSCode version version: Latest Version

Screenshots

[el3ctrician]

i think this style of fsm is not suppored. Not all style are supported as documented here but @qarlosalberto can confirm that

[qarlosalberto]

Yes, that's the problem.