Merge pull request #104 from StanfordVLSI/fpga_merge2

Get loopback emulation test working with mixed-signal emulation models

Author: zamyers

.buildkite/pipeline.yml

@@ -71,10 +71,18 @@ steps:
       - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.log"
       - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.bit"
       - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.ltx"
+      - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.xsa"
+      - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/ps7_init.tcl"
+      - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.hwdef"
+      - "tests/fpga_system_tests/*/build/*/prj/prj.runs/*/*.sysdef"
+      - "tests/fpga_system_tests/*/build/*/prj/prj.sdk/*/*/*.elf"
       - "tests/fpga_system_tests/*/build/*/prj/prj.sim/*/behav/xsim/*.log"
       - "tests/fpga_system_tests/*/build/*/prj/prj.sim/*/behav/xsim/*.sh"
       - "tests/fpga_system_tests/*/prj.yaml"
       - "tests/fpga_system_tests/*/source.yaml"
+      - "build/all/jtag/reg_list.json"
+      - "build/cpu_models/jtag/jtag_reg_pack.sv"
+      - "build/tb/jtag_drv_pack.sv"
     timeout_in_minutes: 60
     agents:
         fpga_verif: "true"

config/fpga/clk_delay.yml

@@ -1,3 +1,3 @@
 dt: 0.1e-6
-n_bits: 8
-t_per: 1.0e-9
+n_bits: 9
+t_per: 250.0e-12

config/fpga/osc_model.yml

@@ -1,4 +1 @@
-dt: 0.1e-6
-tlo: 0.5e-9
-thi: 0.5e-9
-tdel: 0.5e-9
+dt: 0.1e-6

config/fpga/rx_adc.yml

@@ -1,4 +1,3 @@
 dt: 0.1e-6
-vp: 1.0
-vn: -1.0
+vref: 0.4
 n: 8

config/fpga/system_fpga.yml

@@ -0,0 +1,67 @@
+parameter_list:
+  - &channel_width 16
+  - &code_precision 8
+  - &output_precision 10
+  - &ffe_length 4
+  - &ffe_weight_precision 10
+  - &estimate_depth 4
+  - &estimate_precision 8
+  - &sequence_length 3
+  - &decision_shift_precision 4
+  - &ffe_shift_precision 5
+  - &mlsd_bit_length 1
+  - &mlsd_est_cursor_pos 0
+
+generate:
+  channel:
+    class: "PulseChannel"
+    type: "dielectric1"
+    file_name: "impulse_response.txt"
+    parameters:
+      baud_rate: 1
+      sampling_pos: 0
+      channel_depth: 125
+      tau: 0.0087
+      sample_rate: 100
+      baud_rate: 1
+      cursor_pos: *mlsd_est_cursor_pos
+
+
+generic:
+  parameters:
+    channel_width: *channel_width
+    code_precision : *code_precision
+    ffe_length: *ffe_length
+    ffe_weight_precision: *ffe_weight_precision
+    ffe_shift: 8
+    mlsd_shift: 8
+  ffe:
+    parameters:
+      length : *ffe_length
+      width  : *channel_width
+      input_precision : *code_precision
+      output_precision: *output_precision
+      weight_precision: *ffe_weight_precision
+      shift_precision: *ffe_shift_precision
+    adaptation:
+      type: 'wiener'
+      args: { mu : 0.1 }
+  comp:
+    parameters:
+      width : *channel_width
+      input_precision : *output_precision
+      conf_precision  : 8
+      thresh_precision : *output_precision
+    threshold:
+      value: 0
+  mlsd:
+    parameters:
+      width: *channel_width
+      length: *sequence_length
+      code_precision : *code_precision
+      estimate_precision: *estimate_precision
+      estimate_depth: *estimate_depth
+      shift_precision: *decision_shift_precision
+      bit_length: *mlsd_bit_length
+      est_center: *mlsd_est_cursor_pos
+

config/fpga/tx.yml

@@ -1,3 +1,3 @@
 dt: 0.1e-6
-vp: 1.0
-vn: -1.0
+vp: 0.4
+vn: -0.4

conftest.py

@@ -4,14 +4,23 @@ def pytest_addoption(parser):
     parser.addoption(
         '--dump_waveforms', action='store_true', help='Dump waveforms from test.'
     )
+
     parser.addoption(
         '--board_name', default='ZC702', type=str, help='Name of the FPGA board.'
     )
 
+    parser.addoption(
+        '--ser_port', default='/dev/ttyUSB2', type=str, help='USB serial path.'
+    )
+
 @pytest.fixture
 def dump_waveforms(request):
     return request.config.getoption('--dump_waveforms')
 
 @pytest.fixture
 def board_name(request):
-    return request.config.getoption('--board_name')
+    return request.config.getoption('--board_name')
+
+@pytest.fixture
+def ser_port(request):
+    return request.config.getoption('--ser_port')

dragonphy/adapt_fir.py

@@ -1,7 +1,6 @@
-import numpy as np
 from pathlib import Path
 
-from dragonphy import Channel, Wiener, Quantizer, Packager
+from dragonphy import Channel, Packager
 
 class AdaptFir:
     def __init__(self,  filename=None, **system_values):
@@ -10,52 +9,18 @@ def __init__(self,  filename=None, **system_values):
         ffe_config      = system_values['generic']['ffe']
         constant_config = system_values['generic']
         mlsd_config     = system_values['generic']['mlsd']
-        comp_config      = system_values['generic']['comp']
+        comp_config     = system_values['generic']['comp']
+
         # create channel model
         kwargs = dict(
-            channel_type='arctan',
-            tau=0.25e-9,
-            t_delay=4e-9,
-            sampl_rate=10e9,
+            channel_type='exponent',
+            tau=25e-12,
+            t_delay=31.25e-12,
+            sampl_rate=160e9,
             resp_depth=500
         )
         chan = Channel(**kwargs)
 
-        # create a channel model delayed such that the optimal
-        # cursor position is an integer
-        # TODO: clean this up
-        kwargs_d = kwargs.copy()
-        kwargs_d['t_delay'] += 0.5e-9
-        chan_d = Channel(**kwargs_d)
-
-        # compute response of channel to codes
-        iterations = 200000
-        ideal_codes = np.random.randint(2, size=iterations) * 2 - 1
-        chan_out = chan_d.compute_output(ideal_codes)
-
-        # Adapt to the channel
-        cursor_pos = 5
-        adapt = Wiener(
-            step_size=ffe_config['adaptation']['args']['mu'],
-            num_taps=ffe_config['parameters']['length'],
-            cursor_pos=cursor_pos
-        )
-        for i in range(iterations - cursor_pos):
-            adapt.find_weights_pulse(ideal_codes[i - cursor_pos], chan_out[i])
-        weights = adapt.weights
-
-        # Uncomment this line for debugging purposes to
-        # use weights corresponding to a perfect channel
-        # weights = np.array([1.0, 0, 0])
-
-        # Normalize weights
-        weights = weights * (100.0 / np.sum(np.abs(weights)))
-
-        # Quantize the weights
-        # TODO: why isn't "quantized_weights" used?
-        qw = Quantizer(width=ffe_config['parameters']['weight_precision'], signed=True)
-        quantized_weights = qw.quantize_2s_comp(weights)
-
         # create constants package
         Packager(
             package_name='constant_gpack',
@@ -84,29 +49,6 @@ def __init__(self,  filename=None, **system_values):
             dir=build_dir
         ).create_package()
 
-        # Write impulse response to package
-        step_dt = 0.1e-9
-        _, v_step = chan.get_step_resp(f_sig=1 / step_dt, resp_depth=500)
-        Packager(
-            package_name='step_resp_pack',
-            parameters={
-                'step_len': len(v_step),
-                'step_dt': step_dt,
-                'v_step': v_step
-            },
-            dir=build_dir
-        ).create_package()
-
-        # Write weights to package
-        # TODO: why is "weights" used here instead of "quantized_weights"?
-        Packager(
-            package_name='weights_pack',
-            parameters={
-                'read_weights': [int(elem) for elem in weights]
-            },
-            dir=build_dir
-        ).create_package()
-
         # Write the step response data to a YAML file
         chan.to_file(build_dir / 'chan.npy')
         print(build_dir / 'chan.npy')

dragonphy/anasymod.py

@@ -2,16 +2,34 @@
 import yaml
 
 class AnasymodProjectConfig:
-    def __init__(self):
+    def __init__(self, fpga_sim_ctrl='UART_ZYNQ'):
         self.config = {
             'PROJECT': {
                 'dt': 50e-9,
                 'board_name': 'ZC702',
                 'plugins': ['msdsl'],
-                'emu_clk_freq': 20e6
+                'emu_clk_freq': 5e6,
+                'cpu_debug_mode': 0,
+                'cpu_debug_hierarchies': [],
+                'flatten_hierarchy': 'none'
+            },
+            'FPGA_TARGET': {
+                'fpga': {
+                    'fpga_sim_ctrl': fpga_sim_ctrl
+                }
             }
         }
 
+    def set_cpu_debug_mode(self, value):
+        self.config['PROJECT']['cpu_debug_mode'] = value
+
+    def set_flatten_hierarchy(self, value):
+        assert value in {'none', 'full', 'rebuilt'}, 'Invalid setting.'
+        self.config['PROJECT']['flatten_hierarchy'] = value
+
+    def add_debug_probe(self, depth, path):
+        self.config['PROJECT']['cpu_debug_hierarchies'].append([depth, path])
+
     def set_board_name(self, value):
         self.config['PROJECT']['board_name'] = value
 
@@ -61,6 +79,9 @@ def add_verilog_sources(self, file_list, fileset=None):
     def add_verilog_headers(self, header_list, fileset=None):
         self.add_generic_sources('verilog_headers', header_list, fileset)
 
+    def add_firmware_files(self, file_list, fileset=None):
+        self.add_generic_sources('firmware_files', file_list, fileset)
+
     def add_defines(self, defines, fileset=None):
         if 'defines' not in self.sources:
             self.sources['defines'] = {}

dragonphy/fpga_models/chan_core.py

@@ -12,6 +12,9 @@
 
 class ChannelCore:
     def __init__(self, filename=None, **system_values):
+        # set a fixed random seed for repeatability
+        np.random.seed(0)
+
         module_name = Path(filename).stem
         build_dir   = Path(filename).parent
 
@@ -30,7 +33,7 @@ def __init__(self, filename=None, **system_values):
         view = system_values['view']
 
         # read in the channel data
-        chan = Filter.from_file(get_file('build/' + view + '/adapt_fir/chan.npy'))
+        chan = Filter.from_file(get_file('build/fpga_models/adapt_fir/chan.npy'))
 
         # create a function
         domain = [chan.t_vec[0], chan.t_vec[-1]]

dragonphy/fpga_models/clk_delay_core.py

@@ -1,10 +1,14 @@
 from pathlib import Path
+import numpy as np
 from msdsl import MixedSignalModel, VerilogGenerator, min_op
 from msdsl.expr.expr import array, concatenate
 from msdsl.expr.extras import if_
 
 class ClkDelayCore:
     def __init__(self, filename=None, **system_values):
+        # set a fixed random seed for repeatability
+        np.random.seed(1)
+
         module_name = Path(filename).stem
         build_dir   = Path(filename).parent
 

dragonphy/fpga_models/osc_model_core.py

@@ -1,11 +1,15 @@
 from pathlib import Path
 from copy import deepcopy
+import numpy as np
 from msdsl import MixedSignalModel, VerilogGenerator
 from msdsl.expr.expr import array
 from msdsl.expr.extras import if_
 
 class OscModelCore:
     def __init__(self,  filename=None, **system_values):
+        # set a fixed random seed for repeatability
+        np.random.seed(2)
+
         module_name = Path(filename).stem
         build_dir   = Path(filename).parent
 
@@ -14,15 +18,14 @@ def __init__(self,  filename=None, **system_values):
             f'Cannot build {module_name}, Missing parameter in config file'
 
         m = MixedSignalModel(module_name, dt=system_values['dt'], build_dir=build_dir)
-        m.add_real_param('t_lo', default=system_values['tlo'])
-        m.add_real_param('t_hi', default=system_values['thi'])
+        m.add_real_param('t_del', 0)
         m.add_digital_input('emu_rst')
         m.add_digital_input('emu_clk')
+        m.add_analog_input('t_lo')
+        m.add_analog_input('t_hi')
         m.add_analog_input('emu_dt')
-        m.add_analog_output('dt_req', init=system_values['tdel'])
+        m.add_analog_output('dt_req', init='t_del')
         m.add_digital_output('clk_val')
-        m.add_digital_input('clk_i')
-        m.add_digital_output('clk_o')
 
         # determine if the request was granted
         m.bind_name('req_grant', m.dt_req == m.emu_dt)
@@ -55,15 +58,12 @@ def __init__(self,  filename=None, **system_values):
         m.bind_name('dt_req_imm', dt_req_imm_array, **dt_fmt_kwargs)
         m.set_next_cycle(m.dt_req, m.dt_req_imm, clk=m.emu_clk, rst=m.emu_rst)
 
-        # pass through clock input to clock output
-        m.set_this_cycle(m.clk_o, m.clk_i)
-
         # generate the model
         m.compile_to_file(VerilogGenerator())
 
         self.generated_files = [filename]
 
     @staticmethod
     def required_values():
-        return ['dt', 'tlo', 'thi', 'tdel']
+        return ['dt']