From e5551a4599e1be2b7dfc107e778a63e7956c38df Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Tue, 5 May 2020 10:41:33 -0700 Subject: [PATCH 01/16] try running mflowgen on regression server --- .buildkite/pipeline.yml | 16 +- flow/.mflowgen.yml | 1 + flow/construct-commercial-full.py | 172 +++++++ flow/construct-commercial.py | 128 +++++ flow/construct-open.py | 95 ++++ flow/rtl/GcdUnit-demo.v | 776 ++++++++++++++++++++++++++++++ flow/rtl/configure.yml | 5 + flow/rtl/outputs/design.v | 1 + regress.sh | 31 +- 9 files changed, 1210 insertions(+), 15 deletions(-) create mode 100644 flow/.mflowgen.yml create mode 100644 flow/construct-commercial-full.py create mode 100644 flow/construct-commercial.py create mode 100644 flow/construct-open.py create mode 100644 flow/rtl/GcdUnit-demo.v create mode 100644 flow/rtl/configure.yml create mode 120000 flow/rtl/outputs/design.v diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 04bff366..8d706b99 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -3,13 +3,19 @@ steps: # set up environment source /cad/modules/tcl/init/bash module load base xcelium dc_shell - export DRAGONPHY_PYTHON=/usr/local/miniconda/bin/python3.7 export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=cpu printenv + # create virtual environment + /usr/local/miniconda/bin/python3.7 -m venv venv + source venv/bin/activate + # run regression script source regress.sh + + # deactivate virtual environment + deactivate label: "test" timeout_in_minutes: 60 agents: @@ -17,14 +23,20 @@ steps: - command: | # set up environment source /etc/environment - export DRAGONPHY_PYTHON=python3.7 export FPGA_SERVER=1 export DW_TAP=/tools/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=fpga printenv + # create virtual environment + python3.7 -m venv venv + source venv/bin/activate + # run regression script source regress.sh + + # deactivate virtual environment + deactivate label: "test_emu" timeout_in_minutes: 60 agents: diff --git a/flow/.mflowgen.yml b/flow/.mflowgen.yml new file mode 100644 index 00000000..5de572db --- /dev/null +++ b/flow/.mflowgen.yml @@ -0,0 +1 @@ +construct: construct-commercial.py diff --git a/flow/construct-commercial-full.py b/flow/construct-commercial-full.py new file mode 100644 index 00000000..c11fc873 --- /dev/null +++ b/flow/construct-commercial-full.py @@ -0,0 +1,172 @@ +#========================================================================= +# construct.py +#========================================================================= +# Demo with 16-bit GcdUnit +# +# Author : Christopher Torng +# Date : June 2, 2019 +# + +import os + +from mflowgen.components import Graph, Step + +def construct(): + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + adk_name = 'freepdk-45nm' + adk_view = 'view-standard' + + parameters = { + 'construct_path' : __file__, + 'design_name' : 'GcdUnit', + 'clock_period' : 2.0, + 'adk' : adk_name, + 'adk_view' : adk_view, + 'topographical' : True, + } + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk( adk_name ) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step( this_dir + '/rtl' ) + + # Default steps + + info = Step( 'info', default=True ) + constraints = Step( 'constraints', default=True ) + dc = Step( 'synopsys-dc-synthesis', default=True ) + iflow = Step( 'cadence-innovus-flowsetup', default=True ) + init = Step( 'cadence-innovus-init', default=True ) + power = Step( 'cadence-innovus-power', default=True ) + place = Step( 'cadence-innovus-place', default=True ) + cts = Step( 'cadence-innovus-cts', default=True ) + postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) + route = Step( 'cadence-innovus-route', default=True ) + postroute = Step( 'cadence-innovus-postroute', default=True ) + postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) + signoff = Step( 'cadence-innovus-signoff', default=True ) + genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) + gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) + drc = Step( 'mentor-calibre-drc', default=True ) + lvs = Step( 'mentor-calibre-lvs', default=True ) + debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( constraints ) + g.add_step( dc ) + g.add_step( iflow ) + g.add_step( init ) + g.add_step( power ) + g.add_step( place ) + g.add_step( cts ) + g.add_step( postcts_hold ) + g.add_step( route ) + g.add_step( postroute ) + g.add_step( postroute_hold ) + g.add_step( signoff ) + g.add_step( genlibdb ) + g.add_step( gdsmerge ) + g.add_step( drc ) + g.add_step( lvs ) + g.add_step( debugcalibre ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + # Connect by name + + g.connect_by_name( adk, dc ) + g.connect_by_name( adk, iflow ) + g.connect_by_name( adk, init ) + g.connect_by_name( adk, power ) + g.connect_by_name( adk, place ) + g.connect_by_name( adk, cts ) + g.connect_by_name( adk, postcts_hold ) + g.connect_by_name( adk, route ) + g.connect_by_name( adk, postroute ) + g.connect_by_name( adk, postroute_hold ) + g.connect_by_name( adk, signoff ) + g.connect_by_name( adk, gdsmerge ) + g.connect_by_name( adk, drc ) + g.connect_by_name( adk, lvs ) + + g.connect_by_name( rtl, dc ) + g.connect_by_name( constraints, dc ) + + g.connect_by_name( dc, iflow ) + g.connect_by_name( dc, init ) + g.connect_by_name( dc, power ) + g.connect_by_name( dc, place ) + g.connect_by_name( dc, cts ) + + g.connect_by_name( iflow, init ) + g.connect_by_name( iflow, power ) + g.connect_by_name( iflow, place ) + g.connect_by_name( iflow, cts ) + g.connect_by_name( iflow, postcts_hold ) + g.connect_by_name( iflow, route ) + g.connect_by_name( iflow, postroute ) + g.connect_by_name( iflow, postroute_hold ) + g.connect_by_name( iflow, signoff ) + + g.connect_by_name( init, power ) + g.connect_by_name( power, place ) + g.connect_by_name( place, cts ) + g.connect_by_name( cts, postcts_hold ) + g.connect_by_name( postcts_hold, route ) + g.connect_by_name( route, postroute ) + g.connect_by_name( postroute, postroute_hold ) + g.connect_by_name( postroute_hold, signoff ) + + g.connect_by_name( signoff, genlibdb ) + g.connect_by_name( adk, genlibdb ) + + g.connect_by_name( signoff, gdsmerge ) + + g.connect_by_name( signoff, drc ) + g.connect_by_name( gdsmerge, drc ) + g.connect_by_name( signoff, lvs ) + g.connect_by_name( gdsmerge, lvs ) + + g.connect_by_name( adk, debugcalibre ) + g.connect_by_name( dc, debugcalibre ) + g.connect_by_name( iflow, debugcalibre ) + g.connect_by_name( signoff, debugcalibre ) + g.connect_by_name( drc, debugcalibre ) + g.connect_by_name( lvs, debugcalibre ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g + + +if __name__ == '__main__': + g = construct() +# g.plot() + diff --git a/flow/construct-commercial.py b/flow/construct-commercial.py new file mode 100644 index 00000000..88ef2770 --- /dev/null +++ b/flow/construct-commercial.py @@ -0,0 +1,128 @@ +#========================================================================= +# construct.py +#========================================================================= +# Demo with 16-bit GcdUnit +# +# Author : Christopher Torng +# Date : June 2, 2019 +# + +import os + +from mflowgen.components import Graph, Step + +def construct(): + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + adk_name = 'freepdk-45nm' + adk_view = 'view-standard' + + parameters = { + 'construct_path' : __file__, + 'design_name' : 'GcdUnit', + 'clock_period' : 2.0, + 'adk' : adk_name, + 'adk_view' : adk_view, + 'topographical' : True, + } + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk( adk_name ) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step( this_dir + '/rtl' ) + + # Default steps + + info = Step( 'info', default=True ) + constraints = Step( 'constraints', default=True ) + dc = Step( 'synopsys-dc-synthesis', default=True ) + iflow = Step( 'cadence-innovus-flowsetup', default=True ) + placeroute = Step( 'cadence-innovus-place-route', default=True ) + genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) + gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) + drc = Step( 'mentor-calibre-drc', default=True ) + lvs = Step( 'mentor-calibre-lvs', default=True ) + debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( constraints ) + g.add_step( dc ) + g.add_step( iflow ) + g.add_step( placeroute ) + g.add_step( genlibdb ) + g.add_step( gdsmerge ) + g.add_step( drc ) + g.add_step( lvs ) + g.add_step( debugcalibre ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + # Connect by name + + g.connect_by_name( rtl, dc ) + g.connect_by_name( adk, dc ) + g.connect_by_name( constraints, dc ) + + g.connect_by_name( adk, iflow ) + g.connect_by_name( dc, iflow ) + + g.connect_by_name( adk, placeroute ) + g.connect_by_name( dc, placeroute ) + g.connect_by_name( iflow, placeroute ) + + g.connect_by_name( placeroute, genlibdb ) + g.connect_by_name( adk, genlibdb ) + + g.connect_by_name( adk, drc ) + g.connect_by_name( placeroute, drc ) + + g.connect_by_name( adk, lvs ) + g.connect_by_name( placeroute, lvs ) + + g.connect_by_name( adk, gdsmerge ) + g.connect_by_name( placeroute, gdsmerge ) + + g.connect_by_name( gdsmerge, drc ) + g.connect_by_name( gdsmerge, lvs ) + + g.connect_by_name( adk, debugcalibre ) + g.connect_by_name( dc, debugcalibre ) + g.connect_by_name( iflow, debugcalibre ) + g.connect_by_name( placeroute, debugcalibre ) + g.connect_by_name( drc, debugcalibre ) + g.connect_by_name( lvs, debugcalibre ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g + +if __name__ == '__main__': + g = construct() +# g.plot() + diff --git a/flow/construct-open.py b/flow/construct-open.py new file mode 100644 index 00000000..a4cff051 --- /dev/null +++ b/flow/construct-open.py @@ -0,0 +1,95 @@ +#========================================================================= +# construct.py +#========================================================================= +# Demo with 16-bit GcdUnit +# +# Author : Christopher Torng +# Date : June 2, 2019 +# + +import os + +from mflowgen.components import Graph, Step + +def construct(): + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + adk_name = 'freepdk-45nm' + adk_view = 'view-tiny' + + parameters = { + 'construct_path' : __file__, + 'design_name' : 'GcdUnit', + 'clock_period' : 2.0, + 'adk' : adk_name, + 'adk_view' : adk_view, + } + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk( adk_name ) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step( this_dir + '/rtl' ) + + # Default steps + + info = Step( 'info', default=True ) + yosys = Step( 'open-yosys-synthesis', default=True ) + #replace = Step( 'open-replace-place', default=True ) + graywolf = Step( 'open-graywolf-place', default=True ) + qrouter = Step( 'open-qrouter-route', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( yosys ) + #g.add_step( replace ) + g.add_step( graywolf ) + g.add_step( qrouter ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + g.connect_by_name( rtl, yosys ) + g.connect_by_name( adk, yosys ) + + #g.connect_by_name( adk, replace ) + #g.connect_by_name( yosys, replace ) + g.connect_by_name( adk, graywolf ) + g.connect_by_name( yosys, graywolf ) + + g.connect_by_name( adk, qrouter ) + #g.connect_by_name( replace, qrouter ) + g.connect_by_name( graywolf, qrouter ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g + + +if __name__ == '__main__': + g = construct() +# g.plot() + diff --git a/flow/rtl/GcdUnit-demo.v b/flow/rtl/GcdUnit-demo.v new file mode 100644 index 00000000..3cd52f81 --- /dev/null +++ b/flow/rtl/GcdUnit-demo.v @@ -0,0 +1,776 @@ +//----------------------------------------------------------------------------- +// GcdUnit +//----------------------------------------------------------------------------- +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module GcdUnit +( + input wire [ 0:0] clk, + input wire [ 31:0] req_msg, + output wire [ 0:0] req_rdy, + input wire [ 0:0] req_val, + input wire [ 0:0] reset, + output wire [ 15:0] resp_msg, + input wire [ 0:0] resp_rdy, + output wire [ 0:0] resp_val +); + + // ctrl temporaries + wire [ 0:0] ctrl$is_b_zero; + wire [ 0:0] ctrl$resp_rdy; + wire [ 0:0] ctrl$clk; + wire [ 0:0] ctrl$is_a_lt_b; + wire [ 0:0] ctrl$req_val; + wire [ 0:0] ctrl$reset; + wire [ 1:0] ctrl$a_mux_sel; + wire [ 0:0] ctrl$resp_val; + wire [ 0:0] ctrl$b_mux_sel; + wire [ 0:0] ctrl$b_reg_en; + wire [ 0:0] ctrl$a_reg_en; + wire [ 0:0] ctrl$req_rdy; + + GcdUnitCtrlRTL_0x29124399ca008c5e ctrl + ( + .is_b_zero ( ctrl$is_b_zero ), + .resp_rdy ( ctrl$resp_rdy ), + .clk ( ctrl$clk ), + .is_a_lt_b ( ctrl$is_a_lt_b ), + .req_val ( ctrl$req_val ), + .reset ( ctrl$reset ), + .a_mux_sel ( ctrl$a_mux_sel ), + .resp_val ( ctrl$resp_val ), + .b_mux_sel ( ctrl$b_mux_sel ), + .b_reg_en ( ctrl$b_reg_en ), + .a_reg_en ( ctrl$a_reg_en ), + .req_rdy ( ctrl$req_rdy ) + ); + + // dpath temporaries + wire [ 1:0] dpath$a_mux_sel; + wire [ 0:0] dpath$clk; + wire [ 15:0] dpath$req_msg_b; + wire [ 15:0] dpath$req_msg_a; + wire [ 0:0] dpath$b_mux_sel; + wire [ 0:0] dpath$reset; + wire [ 0:0] dpath$b_reg_en; + wire [ 0:0] dpath$a_reg_en; + wire [ 0:0] dpath$is_b_zero; + wire [ 15:0] dpath$resp_msg; + wire [ 0:0] dpath$is_a_lt_b; + + GcdUnitDpathRTL_0x29124399ca008c5e dpath + ( + .a_mux_sel ( dpath$a_mux_sel ), + .clk ( dpath$clk ), + .req_msg_b ( dpath$req_msg_b ), + .req_msg_a ( dpath$req_msg_a ), + .b_mux_sel ( dpath$b_mux_sel ), + .reset ( dpath$reset ), + .b_reg_en ( dpath$b_reg_en ), + .a_reg_en ( dpath$a_reg_en ), + .is_b_zero ( dpath$is_b_zero ), + .resp_msg ( dpath$resp_msg ), + .is_a_lt_b ( dpath$is_a_lt_b ) + ); + + // signal connections + assign ctrl$clk = clk; + assign ctrl$is_a_lt_b = dpath$is_a_lt_b; + assign ctrl$is_b_zero = dpath$is_b_zero; + assign ctrl$req_val = req_val; + assign ctrl$reset = reset; + assign ctrl$resp_rdy = resp_rdy; + assign dpath$a_mux_sel = ctrl$a_mux_sel; + assign dpath$a_reg_en = ctrl$a_reg_en; + assign dpath$b_mux_sel = ctrl$b_mux_sel; + assign dpath$b_reg_en = ctrl$b_reg_en; + assign dpath$clk = clk; + assign dpath$req_msg_a = req_msg[31:16]; + assign dpath$req_msg_b = req_msg[15:0]; + assign dpath$reset = reset; + assign req_rdy = ctrl$req_rdy; + assign resp_msg = dpath$resp_msg; + assign resp_val = ctrl$resp_val; + + + +endmodule // GcdUnit +`default_nettype wire + +//----------------------------------------------------------------------------- +// GcdUnitCtrlRTL_0x29124399ca008c5e +//----------------------------------------------------------------------------- +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module GcdUnitCtrlRTL_0x29124399ca008c5e +( + output reg [ 1:0] a_mux_sel, + output reg [ 0:0] a_reg_en, + output reg [ 0:0] b_mux_sel, + output reg [ 0:0] b_reg_en, + input wire [ 0:0] clk, + input wire [ 0:0] is_a_lt_b, + input wire [ 0:0] is_b_zero, + output reg [ 0:0] req_rdy, + input wire [ 0:0] req_val, + input wire [ 0:0] reset, + input wire [ 0:0] resp_rdy, + output reg [ 0:0] resp_val +); + + // register declarations + reg [ 1:0] curr_state__0; + reg [ 1:0] current_state__1; + reg [ 0:0] do_sub; + reg [ 0:0] do_swap; + reg [ 1:0] next_state__0; + reg [ 1:0] state$in_; + + // localparam declarations + localparam A_MUX_SEL_B = 2; + localparam A_MUX_SEL_IN = 0; + localparam A_MUX_SEL_SUB = 1; + localparam A_MUX_SEL_X = 0; + localparam B_MUX_SEL_A = 0; + localparam B_MUX_SEL_IN = 1; + localparam B_MUX_SEL_X = 0; + localparam STATE_CALC = 1; + localparam STATE_DONE = 2; + localparam STATE_IDLE = 0; + + // state temporaries + wire [ 0:0] state$reset; + wire [ 0:0] state$clk; + wire [ 1:0] state$out; + + RegRst_0x9f365fdf6c8998a state + ( + .reset ( state$reset ), + .in_ ( state$in_ ), + .clk ( state$clk ), + .out ( state$out ) + ); + + // signal connections + assign state$clk = clk; + assign state$reset = reset; + + + // PYMTL SOURCE: + // + // @s.combinational + // def state_transitions(): + // + // curr_state = s.state.out + // next_state = s.state.out + // + // # Transitions out of IDLE state + // + // if ( curr_state == s.STATE_IDLE ): + // if ( s.req_val and s.req_rdy ): + // next_state = s.STATE_CALC + // + // # Transitions out of CALC state + // + // if ( curr_state == s.STATE_CALC ): + // if ( not s.is_a_lt_b and s.is_b_zero ): + // next_state = s.STATE_DONE + // + // # Transitions out of DONE state + // + // if ( curr_state == s.STATE_DONE ): + // if ( s.resp_val and s.resp_rdy ): + // next_state = s.STATE_IDLE + // + // s.state.in_.value = next_state + + // logic for state_transitions() + always @ (*) begin + curr_state__0 = state$out; + next_state__0 = state$out; + if ((curr_state__0 == STATE_IDLE)) begin + if ((req_val&&req_rdy)) begin + next_state__0 = STATE_CALC; + end + else begin + end + end + else begin + end + if ((curr_state__0 == STATE_CALC)) begin + if ((!is_a_lt_b&&is_b_zero)) begin + next_state__0 = STATE_DONE; + end + else begin + end + end + else begin + end + if ((curr_state__0 == STATE_DONE)) begin + if ((resp_val&&resp_rdy)) begin + next_state__0 = STATE_IDLE; + end + else begin + end + end + else begin + end + state$in_ = next_state__0; + end + + // PYMTL SOURCE: + // + // @s.combinational + // def state_outputs(): + // + // current_state = s.state.out + // + // # Avoid latches + // + // s.do_swap.value = 0 + // s.do_sub .value = 0 + // + // s.req_rdy.value = 0 + // s.resp_val.value = 0 + // s.a_mux_sel.value = 0 + // s.a_reg_en.value = 0 + // s.b_mux_sel.value = 0 + // s.b_reg_en.value = 0 + // + // # In IDLE state we simply wait for inputs to arrive and latch them + // + // if current_state == s.STATE_IDLE: + // s.req_rdy.value = 1 + // s.resp_val.value = 0 + // s.a_mux_sel.value = A_MUX_SEL_IN + // s.a_reg_en.value = 1 + // s.b_mux_sel.value = B_MUX_SEL_IN + // s.b_reg_en.value = 1 + // + // # In CALC state we iteratively swap/sub to calculate GCD + // + // elif current_state == s.STATE_CALC: + // + // s.do_swap.value = s.is_a_lt_b + // s.do_sub.value = ~s.is_b_zero + // + // s.req_rdy.value = 0 + // s.resp_val.value = 0 + // s.a_mux_sel.value = A_MUX_SEL_B if s.do_swap else A_MUX_SEL_SUB + // s.a_reg_en.value = 1 + // s.b_mux_sel.value = B_MUX_SEL_A + // s.b_reg_en.value = s.do_swap + // + // # In DONE state we simply wait for output transaction to occur + // + // elif current_state == s.STATE_DONE: + // s.req_rdy.value = 0 + // s.resp_val.value = 1 + // s.a_mux_sel.value = A_MUX_SEL_X + // s.a_reg_en.value = 0 + // s.b_mux_sel.value = B_MUX_SEL_X + // s.b_reg_en.value = 0 + + // logic for state_outputs() + always @ (*) begin + current_state__1 = state$out; + do_swap = 0; + do_sub = 0; + req_rdy = 0; + resp_val = 0; + a_mux_sel = 0; + a_reg_en = 0; + b_mux_sel = 0; + b_reg_en = 0; + if ((current_state__1 == STATE_IDLE)) begin + req_rdy = 1; + resp_val = 0; + a_mux_sel = A_MUX_SEL_IN; + a_reg_en = 1; + b_mux_sel = B_MUX_SEL_IN; + b_reg_en = 1; + end + else begin + if ((current_state__1 == STATE_CALC)) begin + do_swap = is_a_lt_b; + do_sub = ~is_b_zero; + req_rdy = 0; + resp_val = 0; + a_mux_sel = do_swap ? A_MUX_SEL_B : A_MUX_SEL_SUB; + a_reg_en = 1; + b_mux_sel = B_MUX_SEL_A; + b_reg_en = do_swap; + end + else begin + if ((current_state__1 == STATE_DONE)) begin + req_rdy = 0; + resp_val = 1; + a_mux_sel = A_MUX_SEL_X; + a_reg_en = 0; + b_mux_sel = B_MUX_SEL_X; + b_reg_en = 0; + end + else begin + end + end + end + end + + +endmodule // GcdUnitCtrlRTL_0x29124399ca008c5e +`default_nettype wire + +//----------------------------------------------------------------------------- +// RegRst_0x9f365fdf6c8998a +//----------------------------------------------------------------------------- +// dtype: 2 +// reset_value: 0 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module RegRst_0x9f365fdf6c8998a +( + input wire [ 0:0] clk, + input wire [ 1:0] in_, + output reg [ 1:0] out, + input wire [ 0:0] reset +); + + // localparam declarations + localparam reset_value = 0; + + + + // PYMTL SOURCE: + // + // @s.posedge_clk + // def seq_logic(): + // if s.reset: + // s.out.next = reset_value + // else: + // s.out.next = s.in_ + + // logic for seq_logic() + always @ (posedge clk) begin + if (reset) begin + out <= reset_value; + end + else begin + out <= in_; + end + end + + +endmodule // RegRst_0x9f365fdf6c8998a +`default_nettype wire + +//----------------------------------------------------------------------------- +// GcdUnitDpathRTL_0x29124399ca008c5e +//----------------------------------------------------------------------------- +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module GcdUnitDpathRTL_0x29124399ca008c5e +( + input wire [ 1:0] a_mux_sel, + input wire [ 0:0] a_reg_en, + input wire [ 0:0] b_mux_sel, + input wire [ 0:0] b_reg_en, + input wire [ 0:0] clk, + output wire [ 0:0] is_a_lt_b, + output wire [ 0:0] is_b_zero, + input wire [ 15:0] req_msg_a, + input wire [ 15:0] req_msg_b, + input wire [ 0:0] reset, + output wire [ 15:0] resp_msg +); + + // wire declarations + wire [ 15:0] sub_out; + wire [ 15:0] b_reg_out; + + + // a_reg temporaries + wire [ 0:0] a_reg$reset; + wire [ 15:0] a_reg$in_; + wire [ 0:0] a_reg$clk; + wire [ 0:0] a_reg$en; + wire [ 15:0] a_reg$out; + + RegEn_0x68db79c4ec1d6e5b a_reg + ( + .reset ( a_reg$reset ), + .in_ ( a_reg$in_ ), + .clk ( a_reg$clk ), + .en ( a_reg$en ), + .out ( a_reg$out ) + ); + + // a_lt_b temporaries + wire [ 0:0] a_lt_b$reset; + wire [ 0:0] a_lt_b$clk; + wire [ 15:0] a_lt_b$in0; + wire [ 15:0] a_lt_b$in1; + wire [ 0:0] a_lt_b$out; + + LtComparator_0x422b1f52edd46a85 a_lt_b + ( + .reset ( a_lt_b$reset ), + .clk ( a_lt_b$clk ), + .in0 ( a_lt_b$in0 ), + .in1 ( a_lt_b$in1 ), + .out ( a_lt_b$out ) + ); + + // b_zero temporaries + wire [ 0:0] b_zero$reset; + wire [ 15:0] b_zero$in_; + wire [ 0:0] b_zero$clk; + wire [ 0:0] b_zero$out; + + ZeroComparator_0x422b1f52edd46a85 b_zero + ( + .reset ( b_zero$reset ), + .in_ ( b_zero$in_ ), + .clk ( b_zero$clk ), + .out ( b_zero$out ) + ); + + // a_mux temporaries + wire [ 0:0] a_mux$reset; + wire [ 15:0] a_mux$in_$000; + wire [ 15:0] a_mux$in_$001; + wire [ 15:0] a_mux$in_$002; + wire [ 0:0] a_mux$clk; + wire [ 1:0] a_mux$sel; + wire [ 15:0] a_mux$out; + + Mux_0x683fa1a418b072c9 a_mux + ( + .reset ( a_mux$reset ), + .in_$000 ( a_mux$in_$000 ), + .in_$001 ( a_mux$in_$001 ), + .in_$002 ( a_mux$in_$002 ), + .clk ( a_mux$clk ), + .sel ( a_mux$sel ), + .out ( a_mux$out ) + ); + + // b_mux temporaries + wire [ 0:0] b_mux$reset; + wire [ 15:0] b_mux$in_$000; + wire [ 15:0] b_mux$in_$001; + wire [ 0:0] b_mux$clk; + wire [ 0:0] b_mux$sel; + wire [ 15:0] b_mux$out; + + Mux_0xdd6473406d1a99a b_mux + ( + .reset ( b_mux$reset ), + .in_$000 ( b_mux$in_$000 ), + .in_$001 ( b_mux$in_$001 ), + .clk ( b_mux$clk ), + .sel ( b_mux$sel ), + .out ( b_mux$out ) + ); + + // sub temporaries + wire [ 0:0] sub$reset; + wire [ 0:0] sub$clk; + wire [ 15:0] sub$in0; + wire [ 15:0] sub$in1; + wire [ 15:0] sub$out; + + Subtractor_0x422b1f52edd46a85 sub + ( + .reset ( sub$reset ), + .clk ( sub$clk ), + .in0 ( sub$in0 ), + .in1 ( sub$in1 ), + .out ( sub$out ) + ); + + // b_reg temporaries + wire [ 0:0] b_reg$reset; + wire [ 15:0] b_reg$in_; + wire [ 0:0] b_reg$clk; + wire [ 0:0] b_reg$en; + wire [ 15:0] b_reg$out; + + RegEn_0x68db79c4ec1d6e5b b_reg + ( + .reset ( b_reg$reset ), + .in_ ( b_reg$in_ ), + .clk ( b_reg$clk ), + .en ( b_reg$en ), + .out ( b_reg$out ) + ); + + // signal connections + assign a_lt_b$clk = clk; + assign a_lt_b$in0 = a_reg$out; + assign a_lt_b$in1 = b_reg$out; + assign a_lt_b$reset = reset; + assign a_mux$clk = clk; + assign a_mux$in_$000 = req_msg_a; + assign a_mux$in_$001 = sub_out; + assign a_mux$in_$002 = b_reg_out; + assign a_mux$reset = reset; + assign a_mux$sel = a_mux_sel; + assign a_reg$clk = clk; + assign a_reg$en = a_reg_en; + assign a_reg$in_ = a_mux$out; + assign a_reg$reset = reset; + assign b_mux$clk = clk; + assign b_mux$in_$000 = a_reg$out; + assign b_mux$in_$001 = req_msg_b; + assign b_mux$reset = reset; + assign b_mux$sel = b_mux_sel; + assign b_reg$clk = clk; + assign b_reg$en = b_reg_en; + assign b_reg$in_ = b_mux$out; + assign b_reg$reset = reset; + assign b_reg_out = b_reg$out; + assign b_zero$clk = clk; + assign b_zero$in_ = b_reg$out; + assign b_zero$reset = reset; + assign is_a_lt_b = a_lt_b$out; + assign is_b_zero = b_zero$out; + assign resp_msg = sub$out; + assign sub$clk = clk; + assign sub$in0 = a_reg$out; + assign sub$in1 = b_reg$out; + assign sub$reset = reset; + assign sub_out = sub$out; + + + +endmodule // GcdUnitDpathRTL_0x29124399ca008c5e +`default_nettype wire + +//----------------------------------------------------------------------------- +// RegEn_0x68db79c4ec1d6e5b +//----------------------------------------------------------------------------- +// dtype: 16 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module RegEn_0x68db79c4ec1d6e5b +( + input wire [ 0:0] clk, + input wire [ 0:0] en, + input wire [ 15:0] in_, + output reg [ 15:0] out, + input wire [ 0:0] reset +); + + + + // PYMTL SOURCE: + // + // @s.posedge_clk + // def seq_logic(): + // if s.en: + // s.out.next = s.in_ + + // logic for seq_logic() + always @ (posedge clk) begin + if (en) begin + out <= in_; + end + else begin + end + end + + +endmodule // RegEn_0x68db79c4ec1d6e5b +`default_nettype wire + +//----------------------------------------------------------------------------- +// LtComparator_0x422b1f52edd46a85 +//----------------------------------------------------------------------------- +// nbits: 16 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module LtComparator_0x422b1f52edd46a85 +( + input wire [ 0:0] clk, + input wire [ 15:0] in0, + input wire [ 15:0] in1, + output reg [ 0:0] out, + input wire [ 0:0] reset +); + + + + // PYMTL SOURCE: + // + // @s.combinational + // def comb_logic(): + // s.out.value = s.in0 < s.in1 + + // logic for comb_logic() + always @ (*) begin + out = (in0 < in1); + end + + +endmodule // LtComparator_0x422b1f52edd46a85 +`default_nettype wire + +//----------------------------------------------------------------------------- +// ZeroComparator_0x422b1f52edd46a85 +//----------------------------------------------------------------------------- +// nbits: 16 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module ZeroComparator_0x422b1f52edd46a85 +( + input wire [ 0:0] clk, + input wire [ 15:0] in_, + output reg [ 0:0] out, + input wire [ 0:0] reset +); + + + + // PYMTL SOURCE: + // + // @s.combinational + // def comb_logic(): + // s.out.value = s.in_ == 0 + + // logic for comb_logic() + always @ (*) begin + out = (in_ == 0); + end + + +endmodule // ZeroComparator_0x422b1f52edd46a85 +`default_nettype wire + +//----------------------------------------------------------------------------- +// Mux_0x683fa1a418b072c9 +//----------------------------------------------------------------------------- +// dtype: 16 +// nports: 3 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module Mux_0x683fa1a418b072c9 +( + input wire [ 0:0] clk, + input wire [ 15:0] in_$000, + input wire [ 15:0] in_$001, + input wire [ 15:0] in_$002, + output reg [ 15:0] out, + input wire [ 0:0] reset, + input wire [ 1:0] sel +); + + // localparam declarations + localparam nports = 3; + + + // array declarations + wire [ 15:0] in_[0:2]; + assign in_[ 0] = in_$000; + assign in_[ 1] = in_$001; + assign in_[ 2] = in_$002; + + // PYMTL SOURCE: + // + // @s.combinational + // def comb_logic(): + // assert s.sel < nports + // s.out.v = s.in_[ s.sel ] + + // logic for comb_logic() + always @ (*) begin + out = in_[sel]; + end + + +endmodule // Mux_0x683fa1a418b072c9 +`default_nettype wire + +//----------------------------------------------------------------------------- +// Mux_0xdd6473406d1a99a +//----------------------------------------------------------------------------- +// dtype: 16 +// nports: 2 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module Mux_0xdd6473406d1a99a +( + input wire [ 0:0] clk, + input wire [ 15:0] in_$000, + input wire [ 15:0] in_$001, + output reg [ 15:0] out, + input wire [ 0:0] reset, + input wire [ 0:0] sel +); + + // localparam declarations + localparam nports = 2; + + + // array declarations + wire [ 15:0] in_[0:1]; + assign in_[ 0] = in_$000; + assign in_[ 1] = in_$001; + + // PYMTL SOURCE: + // + // @s.combinational + // def comb_logic(): + // assert s.sel < nports + // s.out.v = s.in_[ s.sel ] + + // logic for comb_logic() + always @ (*) begin + out = in_[sel]; + end + + +endmodule // Mux_0xdd6473406d1a99a +`default_nettype wire + +//----------------------------------------------------------------------------- +// Subtractor_0x422b1f52edd46a85 +//----------------------------------------------------------------------------- +// nbits: 16 +// dump-vcd: False +// verilator-xinit: zeros +`default_nettype none +module Subtractor_0x422b1f52edd46a85 +( + input wire [ 0:0] clk, + input wire [ 15:0] in0, + input wire [ 15:0] in1, + output reg [ 15:0] out, + input wire [ 0:0] reset +); + + + + // PYMTL SOURCE: + // + // @s.combinational + // def comb_logic(): + // s.out.value = s.in0 - s.in1 + + // logic for comb_logic() + always @ (*) begin + out = (in0-in1); + end + + +endmodule // Subtractor_0x422b1f52edd46a85 +`default_nettype wire + diff --git a/flow/rtl/configure.yml b/flow/rtl/configure.yml new file mode 100644 index 00000000..7ced64e8 --- /dev/null +++ b/flow/rtl/configure.yml @@ -0,0 +1,5 @@ +name: rtl + +outputs: + - design.v + diff --git a/flow/rtl/outputs/design.v b/flow/rtl/outputs/design.v new file mode 120000 index 00000000..10e6ecde --- /dev/null +++ b/flow/rtl/outputs/design.v @@ -0,0 +1 @@ +../GcdUnit-demo.v \ No newline at end of file diff --git a/regress.sh b/regress.sh index be6d7213..452b3173 100644 --- a/regress.sh +++ b/regress.sh @@ -1,7 +1,3 @@ -# create virtual environment -$DRAGONPHY_PYTHON -m venv venv -source venv/bin/activate - # upgrade pip pip install -U pip @@ -18,6 +14,12 @@ export PATH="$GENESIS_HOME/gui/bin:$PATH" git clone --single-branch --branch pwl_cos https://github.com/StanfordVLSI/DaVE.git export mLINGUA_DIR=`realpath DaVE/mLingua` +# install mflowgen +git clone https://github.com/cornell-brg/mflowgen +cd mflowgen +pip install -e . +cd .. + # install dragonphy pip install -e . @@ -27,15 +29,18 @@ python make.py --view asic python make.py --view fpga python make.py --view cpu - # install pytest pip install pytest pytest-cov -# run tests -pytest tests -s -v -r s --cov-report=xml --cov=dragonphy --durations=0 - -# upload coverage -bash <(curl -s https://codecov.io/bash) - -# deactivate virtual env -deactivate +# run tests and upload coverage +# pytest tests -s -v -r s --cov-report=xml --cov=dragonphy --durations=0 +# bash <(curl -s https://codecov.io/bash) + +# run mflowgen as long as we're not on the FPGA server +if [ -z "$FPGA_SERVER" ] +then + mkdir -p build/mflowgen + cd build/mflowgen + mflowgen run --design ../../flow + make synopsys-dc-synthesis +fi From 3784da5a993741c339629c1f398130b5ccc5904d Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Tue, 5 May 2020 10:52:33 -0700 Subject: [PATCH 02/16] test commercial-full --- flow/.mflowgen.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/.mflowgen.yml b/flow/.mflowgen.yml index 5de572db..189d498a 100644 --- a/flow/.mflowgen.yml +++ b/flow/.mflowgen.yml @@ -1 +1 @@ -construct: construct-commercial.py +construct: construct-commercial-full.py From 7ea37757c6a3340acf1a44d7955d2b21fe3c85e5 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Tue, 5 May 2020 11:04:50 -0700 Subject: [PATCH 03/16] try running tests with package versions used by garnet --- .buildkite/pipeline.yml | 3 +- flow/construct-commercial.py | 128 ----------------------------------- flow/construct-open.py | 95 -------------------------- 3 files changed, 2 insertions(+), 224 deletions(-) delete mode 100644 flow/construct-commercial.py delete mode 100644 flow/construct-open.py diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 8d706b99..85020627 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -1,8 +1,9 @@ steps: - command: | # set up environment + # modules loaded aim to match those used by Garnet source /cad/modules/tcl/init/bash - module load base xcelium dc_shell + module load base xcelium lc syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1 export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=cpu printenv diff --git a/flow/construct-commercial.py b/flow/construct-commercial.py deleted file mode 100644 index 88ef2770..00000000 --- a/flow/construct-commercial.py +++ /dev/null @@ -1,128 +0,0 @@ -#========================================================================= -# construct.py -#========================================================================= -# Demo with 16-bit GcdUnit -# -# Author : Christopher Torng -# Date : June 2, 2019 -# - -import os - -from mflowgen.components import Graph, Step - -def construct(): - - g = Graph() - - #----------------------------------------------------------------------- - # Parameters - #----------------------------------------------------------------------- - - adk_name = 'freepdk-45nm' - adk_view = 'view-standard' - - parameters = { - 'construct_path' : __file__, - 'design_name' : 'GcdUnit', - 'clock_period' : 2.0, - 'adk' : adk_name, - 'adk_view' : adk_view, - 'topographical' : True, - } - - #----------------------------------------------------------------------- - # Create nodes - #----------------------------------------------------------------------- - - this_dir = os.path.dirname( os.path.abspath( __file__ ) ) - - # ADK step - - g.set_adk( adk_name ) - adk = g.get_adk_step() - - # Custom steps - - rtl = Step( this_dir + '/rtl' ) - - # Default steps - - info = Step( 'info', default=True ) - constraints = Step( 'constraints', default=True ) - dc = Step( 'synopsys-dc-synthesis', default=True ) - iflow = Step( 'cadence-innovus-flowsetup', default=True ) - placeroute = Step( 'cadence-innovus-place-route', default=True ) - genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) - gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) - drc = Step( 'mentor-calibre-drc', default=True ) - lvs = Step( 'mentor-calibre-lvs', default=True ) - debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) - - #----------------------------------------------------------------------- - # Graph -- Add nodes - #----------------------------------------------------------------------- - - g.add_step( info ) - g.add_step( rtl ) - g.add_step( constraints ) - g.add_step( dc ) - g.add_step( iflow ) - g.add_step( placeroute ) - g.add_step( genlibdb ) - g.add_step( gdsmerge ) - g.add_step( drc ) - g.add_step( lvs ) - g.add_step( debugcalibre ) - - #----------------------------------------------------------------------- - # Graph -- Add edges - #----------------------------------------------------------------------- - - # Connect by name - - g.connect_by_name( rtl, dc ) - g.connect_by_name( adk, dc ) - g.connect_by_name( constraints, dc ) - - g.connect_by_name( adk, iflow ) - g.connect_by_name( dc, iflow ) - - g.connect_by_name( adk, placeroute ) - g.connect_by_name( dc, placeroute ) - g.connect_by_name( iflow, placeroute ) - - g.connect_by_name( placeroute, genlibdb ) - g.connect_by_name( adk, genlibdb ) - - g.connect_by_name( adk, drc ) - g.connect_by_name( placeroute, drc ) - - g.connect_by_name( adk, lvs ) - g.connect_by_name( placeroute, lvs ) - - g.connect_by_name( adk, gdsmerge ) - g.connect_by_name( placeroute, gdsmerge ) - - g.connect_by_name( gdsmerge, drc ) - g.connect_by_name( gdsmerge, lvs ) - - g.connect_by_name( adk, debugcalibre ) - g.connect_by_name( dc, debugcalibre ) - g.connect_by_name( iflow, debugcalibre ) - g.connect_by_name( placeroute, debugcalibre ) - g.connect_by_name( drc, debugcalibre ) - g.connect_by_name( lvs, debugcalibre ) - - #----------------------------------------------------------------------- - # Parameterize - #----------------------------------------------------------------------- - - g.update_params( parameters ) - - return g - -if __name__ == '__main__': - g = construct() -# g.plot() - diff --git a/flow/construct-open.py b/flow/construct-open.py deleted file mode 100644 index a4cff051..00000000 --- a/flow/construct-open.py +++ /dev/null @@ -1,95 +0,0 @@ -#========================================================================= -# construct.py -#========================================================================= -# Demo with 16-bit GcdUnit -# -# Author : Christopher Torng -# Date : June 2, 2019 -# - -import os - -from mflowgen.components import Graph, Step - -def construct(): - - g = Graph() - - #----------------------------------------------------------------------- - # Parameters - #----------------------------------------------------------------------- - - adk_name = 'freepdk-45nm' - adk_view = 'view-tiny' - - parameters = { - 'construct_path' : __file__, - 'design_name' : 'GcdUnit', - 'clock_period' : 2.0, - 'adk' : adk_name, - 'adk_view' : adk_view, - } - - #----------------------------------------------------------------------- - # Create nodes - #----------------------------------------------------------------------- - - this_dir = os.path.dirname( os.path.abspath( __file__ ) ) - - # ADK step - - g.set_adk( adk_name ) - adk = g.get_adk_step() - - # Custom steps - - rtl = Step( this_dir + '/rtl' ) - - # Default steps - - info = Step( 'info', default=True ) - yosys = Step( 'open-yosys-synthesis', default=True ) - #replace = Step( 'open-replace-place', default=True ) - graywolf = Step( 'open-graywolf-place', default=True ) - qrouter = Step( 'open-qrouter-route', default=True ) - - #----------------------------------------------------------------------- - # Graph -- Add nodes - #----------------------------------------------------------------------- - - g.add_step( info ) - g.add_step( rtl ) - g.add_step( yosys ) - #g.add_step( replace ) - g.add_step( graywolf ) - g.add_step( qrouter ) - - #----------------------------------------------------------------------- - # Graph -- Add edges - #----------------------------------------------------------------------- - - g.connect_by_name( rtl, yosys ) - g.connect_by_name( adk, yosys ) - - #g.connect_by_name( adk, replace ) - #g.connect_by_name( yosys, replace ) - g.connect_by_name( adk, graywolf ) - g.connect_by_name( yosys, graywolf ) - - g.connect_by_name( adk, qrouter ) - #g.connect_by_name( replace, qrouter ) - g.connect_by_name( graywolf, qrouter ) - - #----------------------------------------------------------------------- - # Parameterize - #----------------------------------------------------------------------- - - g.update_params( parameters ) - - return g - - -if __name__ == '__main__': - g = construct() -# g.plot() - From 25f9c607be15cc4f7addfb94f0663848807bacce Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Tue, 5 May 2020 11:45:30 -0700 Subject: [PATCH 04/16] try running mflowgen tests on prbs checker --- .gitignore | 1 + flow/construct-commercial-full.py | 11 +- flow/rtl/GcdUnit-demo.v | 776 ----------------------- flow/rtl/configure.yml | 6 +- flow/rtl/gen_rtl.py | 20 + flow/rtl/outputs/design.v | 1 - vlog/new_chip_src/prbs/prbs_checker.sv | 17 +- vlog/new_chip_src/prbs/prbs_generator.sv | 2 + 8 files changed, 42 insertions(+), 792 deletions(-) delete mode 100644 flow/rtl/GcdUnit-demo.v create mode 100644 flow/rtl/gen_rtl.py delete mode 120000 flow/rtl/outputs/design.v diff --git a/.gitignore b/.gitignore index f744dd19..1b9d09ee 100644 --- a/.gitignore +++ b/.gitignore @@ -33,6 +33,7 @@ qrcTechFile* tcbn16* pnr/data pnr/gate_size_test +flow/*/outputs ######################### # other files to ignore # diff --git a/flow/construct-commercial-full.py b/flow/construct-commercial-full.py index c11fc873..6a6fb690 100644 --- a/flow/construct-commercial-full.py +++ b/flow/construct-commercial-full.py @@ -1,11 +1,4 @@ -#========================================================================= -# construct.py -#========================================================================= -# Demo with 16-bit GcdUnit -# -# Author : Christopher Torng -# Date : June 2, 2019 -# +# Adapted from mflowgen GcdUnit example import os @@ -24,7 +17,7 @@ def construct(): parameters = { 'construct_path' : __file__, - 'design_name' : 'GcdUnit', + 'design_name' : 'prbs_checker', 'clock_period' : 2.0, 'adk' : adk_name, 'adk_view' : adk_view, diff --git a/flow/rtl/GcdUnit-demo.v b/flow/rtl/GcdUnit-demo.v deleted file mode 100644 index 3cd52f81..00000000 --- a/flow/rtl/GcdUnit-demo.v +++ /dev/null @@ -1,776 +0,0 @@ -//----------------------------------------------------------------------------- -// GcdUnit -//----------------------------------------------------------------------------- -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module GcdUnit -( - input wire [ 0:0] clk, - input wire [ 31:0] req_msg, - output wire [ 0:0] req_rdy, - input wire [ 0:0] req_val, - input wire [ 0:0] reset, - output wire [ 15:0] resp_msg, - input wire [ 0:0] resp_rdy, - output wire [ 0:0] resp_val -); - - // ctrl temporaries - wire [ 0:0] ctrl$is_b_zero; - wire [ 0:0] ctrl$resp_rdy; - wire [ 0:0] ctrl$clk; - wire [ 0:0] ctrl$is_a_lt_b; - wire [ 0:0] ctrl$req_val; - wire [ 0:0] ctrl$reset; - wire [ 1:0] ctrl$a_mux_sel; - wire [ 0:0] ctrl$resp_val; - wire [ 0:0] ctrl$b_mux_sel; - wire [ 0:0] ctrl$b_reg_en; - wire [ 0:0] ctrl$a_reg_en; - wire [ 0:0] ctrl$req_rdy; - - GcdUnitCtrlRTL_0x29124399ca008c5e ctrl - ( - .is_b_zero ( ctrl$is_b_zero ), - .resp_rdy ( ctrl$resp_rdy ), - .clk ( ctrl$clk ), - .is_a_lt_b ( ctrl$is_a_lt_b ), - .req_val ( ctrl$req_val ), - .reset ( ctrl$reset ), - .a_mux_sel ( ctrl$a_mux_sel ), - .resp_val ( ctrl$resp_val ), - .b_mux_sel ( ctrl$b_mux_sel ), - .b_reg_en ( ctrl$b_reg_en ), - .a_reg_en ( ctrl$a_reg_en ), - .req_rdy ( ctrl$req_rdy ) - ); - - // dpath temporaries - wire [ 1:0] dpath$a_mux_sel; - wire [ 0:0] dpath$clk; - wire [ 15:0] dpath$req_msg_b; - wire [ 15:0] dpath$req_msg_a; - wire [ 0:0] dpath$b_mux_sel; - wire [ 0:0] dpath$reset; - wire [ 0:0] dpath$b_reg_en; - wire [ 0:0] dpath$a_reg_en; - wire [ 0:0] dpath$is_b_zero; - wire [ 15:0] dpath$resp_msg; - wire [ 0:0] dpath$is_a_lt_b; - - GcdUnitDpathRTL_0x29124399ca008c5e dpath - ( - .a_mux_sel ( dpath$a_mux_sel ), - .clk ( dpath$clk ), - .req_msg_b ( dpath$req_msg_b ), - .req_msg_a ( dpath$req_msg_a ), - .b_mux_sel ( dpath$b_mux_sel ), - .reset ( dpath$reset ), - .b_reg_en ( dpath$b_reg_en ), - .a_reg_en ( dpath$a_reg_en ), - .is_b_zero ( dpath$is_b_zero ), - .resp_msg ( dpath$resp_msg ), - .is_a_lt_b ( dpath$is_a_lt_b ) - ); - - // signal connections - assign ctrl$clk = clk; - assign ctrl$is_a_lt_b = dpath$is_a_lt_b; - assign ctrl$is_b_zero = dpath$is_b_zero; - assign ctrl$req_val = req_val; - assign ctrl$reset = reset; - assign ctrl$resp_rdy = resp_rdy; - assign dpath$a_mux_sel = ctrl$a_mux_sel; - assign dpath$a_reg_en = ctrl$a_reg_en; - assign dpath$b_mux_sel = ctrl$b_mux_sel; - assign dpath$b_reg_en = ctrl$b_reg_en; - assign dpath$clk = clk; - assign dpath$req_msg_a = req_msg[31:16]; - assign dpath$req_msg_b = req_msg[15:0]; - assign dpath$reset = reset; - assign req_rdy = ctrl$req_rdy; - assign resp_msg = dpath$resp_msg; - assign resp_val = ctrl$resp_val; - - - -endmodule // GcdUnit -`default_nettype wire - -//----------------------------------------------------------------------------- -// GcdUnitCtrlRTL_0x29124399ca008c5e -//----------------------------------------------------------------------------- -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module GcdUnitCtrlRTL_0x29124399ca008c5e -( - output reg [ 1:0] a_mux_sel, - output reg [ 0:0] a_reg_en, - output reg [ 0:0] b_mux_sel, - output reg [ 0:0] b_reg_en, - input wire [ 0:0] clk, - input wire [ 0:0] is_a_lt_b, - input wire [ 0:0] is_b_zero, - output reg [ 0:0] req_rdy, - input wire [ 0:0] req_val, - input wire [ 0:0] reset, - input wire [ 0:0] resp_rdy, - output reg [ 0:0] resp_val -); - - // register declarations - reg [ 1:0] curr_state__0; - reg [ 1:0] current_state__1; - reg [ 0:0] do_sub; - reg [ 0:0] do_swap; - reg [ 1:0] next_state__0; - reg [ 1:0] state$in_; - - // localparam declarations - localparam A_MUX_SEL_B = 2; - localparam A_MUX_SEL_IN = 0; - localparam A_MUX_SEL_SUB = 1; - localparam A_MUX_SEL_X = 0; - localparam B_MUX_SEL_A = 0; - localparam B_MUX_SEL_IN = 1; - localparam B_MUX_SEL_X = 0; - localparam STATE_CALC = 1; - localparam STATE_DONE = 2; - localparam STATE_IDLE = 0; - - // state temporaries - wire [ 0:0] state$reset; - wire [ 0:0] state$clk; - wire [ 1:0] state$out; - - RegRst_0x9f365fdf6c8998a state - ( - .reset ( state$reset ), - .in_ ( state$in_ ), - .clk ( state$clk ), - .out ( state$out ) - ); - - // signal connections - assign state$clk = clk; - assign state$reset = reset; - - - // PYMTL SOURCE: - // - // @s.combinational - // def state_transitions(): - // - // curr_state = s.state.out - // next_state = s.state.out - // - // # Transitions out of IDLE state - // - // if ( curr_state == s.STATE_IDLE ): - // if ( s.req_val and s.req_rdy ): - // next_state = s.STATE_CALC - // - // # Transitions out of CALC state - // - // if ( curr_state == s.STATE_CALC ): - // if ( not s.is_a_lt_b and s.is_b_zero ): - // next_state = s.STATE_DONE - // - // # Transitions out of DONE state - // - // if ( curr_state == s.STATE_DONE ): - // if ( s.resp_val and s.resp_rdy ): - // next_state = s.STATE_IDLE - // - // s.state.in_.value = next_state - - // logic for state_transitions() - always @ (*) begin - curr_state__0 = state$out; - next_state__0 = state$out; - if ((curr_state__0 == STATE_IDLE)) begin - if ((req_val&&req_rdy)) begin - next_state__0 = STATE_CALC; - end - else begin - end - end - else begin - end - if ((curr_state__0 == STATE_CALC)) begin - if ((!is_a_lt_b&&is_b_zero)) begin - next_state__0 = STATE_DONE; - end - else begin - end - end - else begin - end - if ((curr_state__0 == STATE_DONE)) begin - if ((resp_val&&resp_rdy)) begin - next_state__0 = STATE_IDLE; - end - else begin - end - end - else begin - end - state$in_ = next_state__0; - end - - // PYMTL SOURCE: - // - // @s.combinational - // def state_outputs(): - // - // current_state = s.state.out - // - // # Avoid latches - // - // s.do_swap.value = 0 - // s.do_sub .value = 0 - // - // s.req_rdy.value = 0 - // s.resp_val.value = 0 - // s.a_mux_sel.value = 0 - // s.a_reg_en.value = 0 - // s.b_mux_sel.value = 0 - // s.b_reg_en.value = 0 - // - // # In IDLE state we simply wait for inputs to arrive and latch them - // - // if current_state == s.STATE_IDLE: - // s.req_rdy.value = 1 - // s.resp_val.value = 0 - // s.a_mux_sel.value = A_MUX_SEL_IN - // s.a_reg_en.value = 1 - // s.b_mux_sel.value = B_MUX_SEL_IN - // s.b_reg_en.value = 1 - // - // # In CALC state we iteratively swap/sub to calculate GCD - // - // elif current_state == s.STATE_CALC: - // - // s.do_swap.value = s.is_a_lt_b - // s.do_sub.value = ~s.is_b_zero - // - // s.req_rdy.value = 0 - // s.resp_val.value = 0 - // s.a_mux_sel.value = A_MUX_SEL_B if s.do_swap else A_MUX_SEL_SUB - // s.a_reg_en.value = 1 - // s.b_mux_sel.value = B_MUX_SEL_A - // s.b_reg_en.value = s.do_swap - // - // # In DONE state we simply wait for output transaction to occur - // - // elif current_state == s.STATE_DONE: - // s.req_rdy.value = 0 - // s.resp_val.value = 1 - // s.a_mux_sel.value = A_MUX_SEL_X - // s.a_reg_en.value = 0 - // s.b_mux_sel.value = B_MUX_SEL_X - // s.b_reg_en.value = 0 - - // logic for state_outputs() - always @ (*) begin - current_state__1 = state$out; - do_swap = 0; - do_sub = 0; - req_rdy = 0; - resp_val = 0; - a_mux_sel = 0; - a_reg_en = 0; - b_mux_sel = 0; - b_reg_en = 0; - if ((current_state__1 == STATE_IDLE)) begin - req_rdy = 1; - resp_val = 0; - a_mux_sel = A_MUX_SEL_IN; - a_reg_en = 1; - b_mux_sel = B_MUX_SEL_IN; - b_reg_en = 1; - end - else begin - if ((current_state__1 == STATE_CALC)) begin - do_swap = is_a_lt_b; - do_sub = ~is_b_zero; - req_rdy = 0; - resp_val = 0; - a_mux_sel = do_swap ? A_MUX_SEL_B : A_MUX_SEL_SUB; - a_reg_en = 1; - b_mux_sel = B_MUX_SEL_A; - b_reg_en = do_swap; - end - else begin - if ((current_state__1 == STATE_DONE)) begin - req_rdy = 0; - resp_val = 1; - a_mux_sel = A_MUX_SEL_X; - a_reg_en = 0; - b_mux_sel = B_MUX_SEL_X; - b_reg_en = 0; - end - else begin - end - end - end - end - - -endmodule // GcdUnitCtrlRTL_0x29124399ca008c5e -`default_nettype wire - -//----------------------------------------------------------------------------- -// RegRst_0x9f365fdf6c8998a -//----------------------------------------------------------------------------- -// dtype: 2 -// reset_value: 0 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module RegRst_0x9f365fdf6c8998a -( - input wire [ 0:0] clk, - input wire [ 1:0] in_, - output reg [ 1:0] out, - input wire [ 0:0] reset -); - - // localparam declarations - localparam reset_value = 0; - - - - // PYMTL SOURCE: - // - // @s.posedge_clk - // def seq_logic(): - // if s.reset: - // s.out.next = reset_value - // else: - // s.out.next = s.in_ - - // logic for seq_logic() - always @ (posedge clk) begin - if (reset) begin - out <= reset_value; - end - else begin - out <= in_; - end - end - - -endmodule // RegRst_0x9f365fdf6c8998a -`default_nettype wire - -//----------------------------------------------------------------------------- -// GcdUnitDpathRTL_0x29124399ca008c5e -//----------------------------------------------------------------------------- -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module GcdUnitDpathRTL_0x29124399ca008c5e -( - input wire [ 1:0] a_mux_sel, - input wire [ 0:0] a_reg_en, - input wire [ 0:0] b_mux_sel, - input wire [ 0:0] b_reg_en, - input wire [ 0:0] clk, - output wire [ 0:0] is_a_lt_b, - output wire [ 0:0] is_b_zero, - input wire [ 15:0] req_msg_a, - input wire [ 15:0] req_msg_b, - input wire [ 0:0] reset, - output wire [ 15:0] resp_msg -); - - // wire declarations - wire [ 15:0] sub_out; - wire [ 15:0] b_reg_out; - - - // a_reg temporaries - wire [ 0:0] a_reg$reset; - wire [ 15:0] a_reg$in_; - wire [ 0:0] a_reg$clk; - wire [ 0:0] a_reg$en; - wire [ 15:0] a_reg$out; - - RegEn_0x68db79c4ec1d6e5b a_reg - ( - .reset ( a_reg$reset ), - .in_ ( a_reg$in_ ), - .clk ( a_reg$clk ), - .en ( a_reg$en ), - .out ( a_reg$out ) - ); - - // a_lt_b temporaries - wire [ 0:0] a_lt_b$reset; - wire [ 0:0] a_lt_b$clk; - wire [ 15:0] a_lt_b$in0; - wire [ 15:0] a_lt_b$in1; - wire [ 0:0] a_lt_b$out; - - LtComparator_0x422b1f52edd46a85 a_lt_b - ( - .reset ( a_lt_b$reset ), - .clk ( a_lt_b$clk ), - .in0 ( a_lt_b$in0 ), - .in1 ( a_lt_b$in1 ), - .out ( a_lt_b$out ) - ); - - // b_zero temporaries - wire [ 0:0] b_zero$reset; - wire [ 15:0] b_zero$in_; - wire [ 0:0] b_zero$clk; - wire [ 0:0] b_zero$out; - - ZeroComparator_0x422b1f52edd46a85 b_zero - ( - .reset ( b_zero$reset ), - .in_ ( b_zero$in_ ), - .clk ( b_zero$clk ), - .out ( b_zero$out ) - ); - - // a_mux temporaries - wire [ 0:0] a_mux$reset; - wire [ 15:0] a_mux$in_$000; - wire [ 15:0] a_mux$in_$001; - wire [ 15:0] a_mux$in_$002; - wire [ 0:0] a_mux$clk; - wire [ 1:0] a_mux$sel; - wire [ 15:0] a_mux$out; - - Mux_0x683fa1a418b072c9 a_mux - ( - .reset ( a_mux$reset ), - .in_$000 ( a_mux$in_$000 ), - .in_$001 ( a_mux$in_$001 ), - .in_$002 ( a_mux$in_$002 ), - .clk ( a_mux$clk ), - .sel ( a_mux$sel ), - .out ( a_mux$out ) - ); - - // b_mux temporaries - wire [ 0:0] b_mux$reset; - wire [ 15:0] b_mux$in_$000; - wire [ 15:0] b_mux$in_$001; - wire [ 0:0] b_mux$clk; - wire [ 0:0] b_mux$sel; - wire [ 15:0] b_mux$out; - - Mux_0xdd6473406d1a99a b_mux - ( - .reset ( b_mux$reset ), - .in_$000 ( b_mux$in_$000 ), - .in_$001 ( b_mux$in_$001 ), - .clk ( b_mux$clk ), - .sel ( b_mux$sel ), - .out ( b_mux$out ) - ); - - // sub temporaries - wire [ 0:0] sub$reset; - wire [ 0:0] sub$clk; - wire [ 15:0] sub$in0; - wire [ 15:0] sub$in1; - wire [ 15:0] sub$out; - - Subtractor_0x422b1f52edd46a85 sub - ( - .reset ( sub$reset ), - .clk ( sub$clk ), - .in0 ( sub$in0 ), - .in1 ( sub$in1 ), - .out ( sub$out ) - ); - - // b_reg temporaries - wire [ 0:0] b_reg$reset; - wire [ 15:0] b_reg$in_; - wire [ 0:0] b_reg$clk; - wire [ 0:0] b_reg$en; - wire [ 15:0] b_reg$out; - - RegEn_0x68db79c4ec1d6e5b b_reg - ( - .reset ( b_reg$reset ), - .in_ ( b_reg$in_ ), - .clk ( b_reg$clk ), - .en ( b_reg$en ), - .out ( b_reg$out ) - ); - - // signal connections - assign a_lt_b$clk = clk; - assign a_lt_b$in0 = a_reg$out; - assign a_lt_b$in1 = b_reg$out; - assign a_lt_b$reset = reset; - assign a_mux$clk = clk; - assign a_mux$in_$000 = req_msg_a; - assign a_mux$in_$001 = sub_out; - assign a_mux$in_$002 = b_reg_out; - assign a_mux$reset = reset; - assign a_mux$sel = a_mux_sel; - assign a_reg$clk = clk; - assign a_reg$en = a_reg_en; - assign a_reg$in_ = a_mux$out; - assign a_reg$reset = reset; - assign b_mux$clk = clk; - assign b_mux$in_$000 = a_reg$out; - assign b_mux$in_$001 = req_msg_b; - assign b_mux$reset = reset; - assign b_mux$sel = b_mux_sel; - assign b_reg$clk = clk; - assign b_reg$en = b_reg_en; - assign b_reg$in_ = b_mux$out; - assign b_reg$reset = reset; - assign b_reg_out = b_reg$out; - assign b_zero$clk = clk; - assign b_zero$in_ = b_reg$out; - assign b_zero$reset = reset; - assign is_a_lt_b = a_lt_b$out; - assign is_b_zero = b_zero$out; - assign resp_msg = sub$out; - assign sub$clk = clk; - assign sub$in0 = a_reg$out; - assign sub$in1 = b_reg$out; - assign sub$reset = reset; - assign sub_out = sub$out; - - - -endmodule // GcdUnitDpathRTL_0x29124399ca008c5e -`default_nettype wire - -//----------------------------------------------------------------------------- -// RegEn_0x68db79c4ec1d6e5b -//----------------------------------------------------------------------------- -// dtype: 16 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module RegEn_0x68db79c4ec1d6e5b -( - input wire [ 0:0] clk, - input wire [ 0:0] en, - input wire [ 15:0] in_, - output reg [ 15:0] out, - input wire [ 0:0] reset -); - - - - // PYMTL SOURCE: - // - // @s.posedge_clk - // def seq_logic(): - // if s.en: - // s.out.next = s.in_ - - // logic for seq_logic() - always @ (posedge clk) begin - if (en) begin - out <= in_; - end - else begin - end - end - - -endmodule // RegEn_0x68db79c4ec1d6e5b -`default_nettype wire - -//----------------------------------------------------------------------------- -// LtComparator_0x422b1f52edd46a85 -//----------------------------------------------------------------------------- -// nbits: 16 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module LtComparator_0x422b1f52edd46a85 -( - input wire [ 0:0] clk, - input wire [ 15:0] in0, - input wire [ 15:0] in1, - output reg [ 0:0] out, - input wire [ 0:0] reset -); - - - - // PYMTL SOURCE: - // - // @s.combinational - // def comb_logic(): - // s.out.value = s.in0 < s.in1 - - // logic for comb_logic() - always @ (*) begin - out = (in0 < in1); - end - - -endmodule // LtComparator_0x422b1f52edd46a85 -`default_nettype wire - -//----------------------------------------------------------------------------- -// ZeroComparator_0x422b1f52edd46a85 -//----------------------------------------------------------------------------- -// nbits: 16 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module ZeroComparator_0x422b1f52edd46a85 -( - input wire [ 0:0] clk, - input wire [ 15:0] in_, - output reg [ 0:0] out, - input wire [ 0:0] reset -); - - - - // PYMTL SOURCE: - // - // @s.combinational - // def comb_logic(): - // s.out.value = s.in_ == 0 - - // logic for comb_logic() - always @ (*) begin - out = (in_ == 0); - end - - -endmodule // ZeroComparator_0x422b1f52edd46a85 -`default_nettype wire - -//----------------------------------------------------------------------------- -// Mux_0x683fa1a418b072c9 -//----------------------------------------------------------------------------- -// dtype: 16 -// nports: 3 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module Mux_0x683fa1a418b072c9 -( - input wire [ 0:0] clk, - input wire [ 15:0] in_$000, - input wire [ 15:0] in_$001, - input wire [ 15:0] in_$002, - output reg [ 15:0] out, - input wire [ 0:0] reset, - input wire [ 1:0] sel -); - - // localparam declarations - localparam nports = 3; - - - // array declarations - wire [ 15:0] in_[0:2]; - assign in_[ 0] = in_$000; - assign in_[ 1] = in_$001; - assign in_[ 2] = in_$002; - - // PYMTL SOURCE: - // - // @s.combinational - // def comb_logic(): - // assert s.sel < nports - // s.out.v = s.in_[ s.sel ] - - // logic for comb_logic() - always @ (*) begin - out = in_[sel]; - end - - -endmodule // Mux_0x683fa1a418b072c9 -`default_nettype wire - -//----------------------------------------------------------------------------- -// Mux_0xdd6473406d1a99a -//----------------------------------------------------------------------------- -// dtype: 16 -// nports: 2 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module Mux_0xdd6473406d1a99a -( - input wire [ 0:0] clk, - input wire [ 15:0] in_$000, - input wire [ 15:0] in_$001, - output reg [ 15:0] out, - input wire [ 0:0] reset, - input wire [ 0:0] sel -); - - // localparam declarations - localparam nports = 2; - - - // array declarations - wire [ 15:0] in_[0:1]; - assign in_[ 0] = in_$000; - assign in_[ 1] = in_$001; - - // PYMTL SOURCE: - // - // @s.combinational - // def comb_logic(): - // assert s.sel < nports - // s.out.v = s.in_[ s.sel ] - - // logic for comb_logic() - always @ (*) begin - out = in_[sel]; - end - - -endmodule // Mux_0xdd6473406d1a99a -`default_nettype wire - -//----------------------------------------------------------------------------- -// Subtractor_0x422b1f52edd46a85 -//----------------------------------------------------------------------------- -// nbits: 16 -// dump-vcd: False -// verilator-xinit: zeros -`default_nettype none -module Subtractor_0x422b1f52edd46a85 -( - input wire [ 0:0] clk, - input wire [ 15:0] in0, - input wire [ 15:0] in1, - output reg [ 15:0] out, - input wire [ 0:0] reset -); - - - - // PYMTL SOURCE: - // - // @s.combinational - // def comb_logic(): - // s.out.value = s.in0 - s.in1 - - // logic for comb_logic() - always @ (*) begin - out = (in0-in1); - end - - -endmodule // Subtractor_0x422b1f52edd46a85 -`default_nettype wire - diff --git a/flow/rtl/configure.yml b/flow/rtl/configure.yml index 7ced64e8..b842ba66 100644 --- a/flow/rtl/configure.yml +++ b/flow/rtl/configure.yml @@ -1,5 +1,7 @@ name: rtl -outputs: - - design.v +commands: + - python gen_rtl.py +outputs: + - design.v \ No newline at end of file diff --git a/flow/rtl/gen_rtl.py b/flow/rtl/gen_rtl.py new file mode 100644 index 00000000..b95da3f1 --- /dev/null +++ b/flow/rtl/gen_rtl.py @@ -0,0 +1,20 @@ +from pathlib import Path +from dragonphy import * + +TOP_CELL = 'prbs_checker' +OUTPUT_FILE = 'design.v' + +# build up a list of source files +src_files = [] +src_files += get_deps_new_asic(TOP_CELL) + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write source files in order +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + for src_file in src_files: + f.write(f'// Content from file: {src_file}\n') + f.write(open(src_file, 'r').read()) + f.write('\n') diff --git a/flow/rtl/outputs/design.v b/flow/rtl/outputs/design.v deleted file mode 120000 index 10e6ecde..00000000 --- a/flow/rtl/outputs/design.v +++ /dev/null @@ -1 +0,0 @@ -../GcdUnit-demo.v \ No newline at end of file diff --git a/vlog/new_chip_src/prbs/prbs_checker.sv b/vlog/new_chip_src/prbs/prbs_checker.sv index 1f2216c4..035c0ab8 100644 --- a/vlog/new_chip_src/prbs/prbs_checker.sv +++ b/vlog/new_chip_src/prbs/prbs_checker.sv @@ -20,6 +20,7 @@ module prbs_checker #( // 2'b00: RESET // 2'b01: ALIGN // 2'b10: TEST + // 2'b11: FREEZE input wire logic [1:0] checker_mode, // outputs @@ -29,9 +30,10 @@ module prbs_checker #( ); // TODO: consider using enum here - localparam logic [1:0] RESET = 2'b00; - localparam logic [1:0] ALIGN = 2'b01; - localparam logic [1:0] TEST = 2'b10; + localparam logic [1:0] RESET = 2'b00; + localparam logic [1:0] ALIGN = 2'b01; + localparam logic [1:0] TEST = 2'b10; + localparam logic [1:0] FREEZE = 2'b11; // control signals for the checker core logic prbs_rst, prbs_cke, prbs_match; @@ -87,13 +89,20 @@ module prbs_checker #( end correct_bits <= 0; total_bits <= 0; - end else begin + end else if (checker_mode == TEST) begin prbs_rst <= 0; prbs_cke <= 1; rx_shift <= rx_shift; correct_bits <= correct_bits + prbs_match_bits; total_bits <= total_bits + n_channels; err_count <= 0; + end else begin + prbs_rst <= prbs_rst; + prbs_cke <= prbs_cke; + rx_shift <= rx_shift; + correct_bits <= correct_bits; + total_bits <= total_bits; + err_count <= err_count; end end diff --git a/vlog/new_chip_src/prbs/prbs_generator.sv b/vlog/new_chip_src/prbs/prbs_generator.sv index be71dc4f..72aab0eb 100644 --- a/vlog/new_chip_src/prbs/prbs_generator.sv +++ b/vlog/new_chip_src/prbs/prbs_generator.sv @@ -34,9 +34,11 @@ module prbs_generator #( end else if (n_prbs == 31) begin assign next_bit = data[30] ^ data[27]; end else begin + // synopsys translate_off initial begin $error("Invalid value for n_prbs: %0d", n_prbs); end + // synopsys translate_on end endgenerate From 6dc1b63a5e1792baad823ab65beb6493cbabb6b1 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Tue, 5 May 2020 12:11:29 -0700 Subject: [PATCH 05/16] try running tests with custom constraints --- flow/constraints/configure.yml | 15 +++++ flow/constraints/constraints.tcl | 92 +++++++++++++++++++++++++++++++ flow/construct-commercial-full.py | 2 +- 3 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 flow/constraints/configure.yml create mode 100644 flow/constraints/constraints.tcl diff --git a/flow/constraints/configure.yml b/flow/constraints/configure.yml new file mode 100644 index 00000000..f3507574 --- /dev/null +++ b/flow/constraints/configure.yml @@ -0,0 +1,15 @@ +# Adapted from Garnet + +name: constraints + +commands: + - mkdir -p outputs + - cp constraints.tcl outputs/. + +outputs: + - constraints.tcl + +# TODO: are these needed? +parameters: + clock_period: 1.0 + design_name: undefined diff --git a/flow/constraints/constraints.tcl b/flow/constraints/constraints.tcl new file mode 100644 index 00000000..572abeb9 --- /dev/null +++ b/flow/constraints/constraints.tcl @@ -0,0 +1,92 @@ +# Adapted from Garnet + +# Clock Names +set clock_names [list clk] +set design_clocks [concat $clock_names] + +# PARAMETER: clock period +set clock_period(clk) 2.0 + +# PARAMETER: clock port +set clock_port(clk) clk + +# PARAMETER: pre-cts skew estimate +set clock_skew(clk) 0.00 + +# PARAMETER: clock duty cycle jitter +set clock_jitter(clk) 0.02 + +# PARAMETER: clock extra setup margin +set clock_extra_setup(clk) 0.00 + +# PARAMETER: clock extra hold margin +set clock_extra_hold(clk) 0.00 + +# PARAMETER: pre-cts clock maximum latency +set clock_max_latency(clk) 0.00 + +# PARAMETER: pre-cts clock minimum latency +set clock_min_latency(clk) 0.00 + +# PARAMETER: clock setup uncertainty +set clock_uncertainty_setup(clk) \ + [expr $clock_skew(clk) + $clock_jitter(clk) + $clock_extra_setup(clk)] + +# PARAMETER: clock hold uncertainty +set clock_uncertainty_hold(clk) \ + [expr $clock_jitter(clk) + $clock_extra_hold(clk)] + +# ============================================================================== +# Clock Creation +# ============================================================================== + +foreach clock_name $clock_names { + create_clock -name $clock_name -period $clock_period($clock_name) \ + [get_ports $clock_port($clock_name)] + set_clock_latency -max $clock_max_latency($clock_name) [get_clocks $clock_name] + set_clock_latency -min $clock_min_latency($clock_name) [get_clocks $clock_name] + set_clock_uncertainty -setup $clock_uncertainty_setup($clock_name) [get_clocks $clock_name] + set_clock_uncertainty -hold $clock_uncertainty_hold($clock_name) [get_clocks $clock_name] +} + +# ============================================================================== +# Clock Path Exceptions / False Paths +# ============================================================================== + +# from master clock +# set false_paths(clk) [list ] + +# foreach clock_name $design_clocks { +# set_false_path -from [get_clocks $clock_name] -to [get_clocks $false_paths($clock_name)] +# } + +# This constraint sets the load capacitance in picofarads of the +# output pins of your design. + +set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +set_driving_cell -no_design_rule \ + -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# Make all signals limit their fanout + +set_max_fanout 20 $dc_design_name + +# Make all signals meet good slew + +set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name + +# sr 02/2020 +# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( +# Without dont_touch, they disappear during dc-synthesis +# set_dont_touch [ get_cells ANAIOPAD* ] + +# sr 02/2020 +# Arg turns out not all IOPAD cells have dont_touch property I guess +# set_dont_touch [ get_cells IOPAD* ] \ No newline at end of file diff --git a/flow/construct-commercial-full.py b/flow/construct-commercial-full.py index 6a6fb690..6ab8ad4b 100644 --- a/flow/construct-commercial-full.py +++ b/flow/construct-commercial-full.py @@ -38,11 +38,11 @@ def construct(): # Custom steps rtl = Step( this_dir + '/rtl' ) + constraints = Step( this_dir + '/constraints') # Default steps info = Step( 'info', default=True ) - constraints = Step( 'constraints', default=True ) dc = Step( 'synopsys-dc-synthesis', default=True ) iflow = Step( 'cadence-innovus-flowsetup', default=True ) init = Step( 'cadence-innovus-init', default=True ) From 2fd602b9997df13ec8399a4bdfce9fb30267aad6 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 6 May 2020 10:41:02 -0700 Subject: [PATCH 06/16] work in progress --- dragonphy/views.py | 13 +- flow/constraints/configure.yml | 36 +- flow/constraints/constraints.tcl | 92 ----- flow/constraints/gen_constraints.py | 131 +++++++ flow/construct-commercial-full.py | 323 +++++++++--------- flow/rtl/configure.yml | 5 +- flow/rtl/gen_rtl.py | 38 ++- tests/test_config/test_config.py | 4 +- vlog/new_chip_stubs/DW_tap.sv | 33 -- .../new_chip_stubs/analog_core/analog_core.sv | 260 ++++++++++++++ 10 files changed, 641 insertions(+), 294 deletions(-) delete mode 100644 flow/constraints/constraints.tcl create mode 100644 flow/constraints/gen_constraints.py delete mode 100644 vlog/new_chip_stubs/DW_tap.sv create mode 100644 vlog/new_chip_stubs/analog_core/analog_core.sv diff --git a/dragonphy/views.py b/dragonphy/views.py index b5e6381a..e3cdc52a 100644 --- a/dragonphy/views.py +++ b/dragonphy/views.py @@ -140,8 +140,17 @@ def get_deps_new_asic(cell_name=None, impl_file=None): deps += get_deps( cell_name=cell_name, impl_file=impl_file, - view_order=['new_pack', 'new_chip_src', 'new_chip_stubs'], - includes=[get_dir('inc/new_asic')] + view_order=['new_pack', 'new_chip_src'], + includes=[get_dir('inc/new_asic')], + override={ + 'sram': 'new_chip_stubs', + 'output_buffer': 'new_chip_stubs', + 'input_buffer': 'new_chip_stubs', + 'analog_core': 'new_chip_stubs' + }, + skip={ + 'DW_tap' # Don't use a stub for a DesignWare block + } ) deps.insert(0, Directory.path() + '/build/new_chip_src/adapt_fir/ffe_gpack.sv') diff --git a/flow/constraints/configure.yml b/flow/constraints/configure.yml index f3507574..6380e3b8 100644 --- a/flow/constraints/configure.yml +++ b/flow/constraints/configure.yml @@ -3,13 +3,39 @@ name: constraints commands: - - mkdir -p outputs - - cp constraints.tcl outputs/. + - python gen_constraints.py outputs: - constraints.tcl -# TODO: are these needed? parameters: - clock_period: 1.0 - design_name: undefined + # time in ns and capacitance in pF + + # Main clocks in the design + clk_retimer_period: 0.7 + clk_in_period: 0.7 + clk_jtag_period: 100.0 + + # Retimer clock uncertainty + clk_retimer_setup_uncertainty: 0.03 + clk_retimer_hold_uncertainty: 0.03 + + # JTAG clock uncertainty + clk_jtag_setup_uncertainty: 1.0 + clk_jtag_hold_uncertainty: 0.03 + + # Capacitance and transition time + max_capacitance: 0.1 + max_transition: 0.2 + max_clock_transition: 0.1 + + # Clocks that can be monitored from analog_core + clk_hs_period: 0.25 + clk_hs_transition: 0.025 + + # I/O delays and transitions + digital_input_delay: 0.05 + digital_input_transition: 0.5 + input_transition: 0.03 + output_load: 0.02 + output_delay: 0.7 diff --git a/flow/constraints/constraints.tcl b/flow/constraints/constraints.tcl deleted file mode 100644 index 572abeb9..00000000 --- a/flow/constraints/constraints.tcl +++ /dev/null @@ -1,92 +0,0 @@ -# Adapted from Garnet - -# Clock Names -set clock_names [list clk] -set design_clocks [concat $clock_names] - -# PARAMETER: clock period -set clock_period(clk) 2.0 - -# PARAMETER: clock port -set clock_port(clk) clk - -# PARAMETER: pre-cts skew estimate -set clock_skew(clk) 0.00 - -# PARAMETER: clock duty cycle jitter -set clock_jitter(clk) 0.02 - -# PARAMETER: clock extra setup margin -set clock_extra_setup(clk) 0.00 - -# PARAMETER: clock extra hold margin -set clock_extra_hold(clk) 0.00 - -# PARAMETER: pre-cts clock maximum latency -set clock_max_latency(clk) 0.00 - -# PARAMETER: pre-cts clock minimum latency -set clock_min_latency(clk) 0.00 - -# PARAMETER: clock setup uncertainty -set clock_uncertainty_setup(clk) \ - [expr $clock_skew(clk) + $clock_jitter(clk) + $clock_extra_setup(clk)] - -# PARAMETER: clock hold uncertainty -set clock_uncertainty_hold(clk) \ - [expr $clock_jitter(clk) + $clock_extra_hold(clk)] - -# ============================================================================== -# Clock Creation -# ============================================================================== - -foreach clock_name $clock_names { - create_clock -name $clock_name -period $clock_period($clock_name) \ - [get_ports $clock_port($clock_name)] - set_clock_latency -max $clock_max_latency($clock_name) [get_clocks $clock_name] - set_clock_latency -min $clock_min_latency($clock_name) [get_clocks $clock_name] - set_clock_uncertainty -setup $clock_uncertainty_setup($clock_name) [get_clocks $clock_name] - set_clock_uncertainty -hold $clock_uncertainty_hold($clock_name) [get_clocks $clock_name] -} - -# ============================================================================== -# Clock Path Exceptions / False Paths -# ============================================================================== - -# from master clock -# set false_paths(clk) [list ] - -# foreach clock_name $design_clocks { -# set_false_path -from [get_clocks $clock_name] -to [get_clocks $false_paths($clock_name)] -# } - -# This constraint sets the load capacitance in picofarads of the -# output pins of your design. - -set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] - -# This constraint sets the input drive strength of the input pins of -# your design. We specifiy a specific standard cell which models what -# would be driving the inputs. This should usually be a small inverter -# which is reasonable if another block of on-chip logic is driving -# your inputs. - -set_driving_cell -no_design_rule \ - -lib_cell $ADK_DRIVING_CELL [all_inputs] - -# Make all signals limit their fanout - -set_max_fanout 20 $dc_design_name - -# Make all signals meet good slew - -set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name - -# sr 02/2020 -# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( -# Without dont_touch, they disappear during dc-synthesis -# set_dont_touch [ get_cells ANAIOPAD* ] - -# sr 02/2020 -# Arg turns out not all IOPAD cells have dont_touch property I guess -# set_dont_touch [ get_cells IOPAD* ] \ No newline at end of file diff --git a/flow/constraints/gen_constraints.py b/flow/constraints/gen_constraints.py new file mode 100644 index 00000000..7e850ae5 --- /dev/null +++ b/flow/constraints/gen_constraints.py @@ -0,0 +1,131 @@ +import os +from pathlib import Path + +OUTPUT_FILE = 'constraints.tcl' + +e = os.environ +output = f'''\ +# Modified from ButterPHY and Garnet constraints + +# Design constraints for synthesis +# time unit : ns +# cap unit: pF + +######### +# Params +######### + +# primary I/Os being treated as don't touch nets + +set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\ + ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\ + ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\ + ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}} + +set analog_net [get_pins ibuf_*/clk] + +set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\ + jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\ + jtag_intf_i.phy_trst_n}} + +######### +# Clocks +######### + +create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] +create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] +create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] +set_dont_touch_network [get_pins {{iacore/clk_adc}}] +set_dont_touch_network [get_port jtag_intf_i.phy_tck] + +set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer +set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer +set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag +set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag + +########### +# Net const +########### + +set_max_capacitance {e["max_capacitance"]} [current_design] +set_max_transition {e["max_transition"]} [current_design] +set_max_transition {e["max_clock_transition"]} [all_clocks] + +set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\ + iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\ + iacore/*del_out_pi*}}] + +foreach x [get_object_name $hs_nets] {{ + create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x] + set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x] +}} + +echo [all_clocks] + +########### +# Analog nets +########### + +set_dont_touch_network [get_ports $analog_io] +set_dont_touch_network $analog_net +set_dont_touch_network [all_outputs] + +########### +# I/O const +########### + +set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs] +set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs] + +set_input_transition {e["input_transition"]} [all_inputs] +set_load {e["output_load"]} [all_outputs] +set_output_delay {e["output_delay"]} [all_outputs] + +############ +# False path +############ + +set_false_path -from clk_retimer -to clk_jtag +set_false_path -from clk_jtag -to clk_retimer + +################ +# DONT USE CELLS +################ + +# foreach lib $mvt_target_libs {{ +# set_dont_use [file rootname [file tail $lib]]/*D0BWP* +# }} + +# Settings from Garnet to consider +# (all commented out at the moment) + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +# set_driving_cell -no_design_rule \\ +# -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# Make all signals limit their fanout +# set_max_fanout 20 $dc_design_name + +# sr 02/2020 +# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( +# Without dont_touch, they disappear during dc-synthesis +# set_dont_touch [ get_cells ANAIOPAD* ] + +# sr 02/2020 +# Arg turns out not all IOPAD cells have dont_touch property I guess +# set_dont_touch [ get_cells IOPAD* ] +''' + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write output text +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + f.write(output) + diff --git a/flow/construct-commercial-full.py b/flow/construct-commercial-full.py index 6ab8ad4b..c7198fb7 100644 --- a/flow/construct-commercial-full.py +++ b/flow/construct-commercial-full.py @@ -1,165 +1,182 @@ # Adapted from mflowgen GcdUnit example +# To select the process, set the DRAGONPHY_PROCESS environment variable +# to either FREEPDK45 or TSMC16 + import os from mflowgen.components import Graph, Step def construct(): - g = Graph() - - #----------------------------------------------------------------------- - # Parameters - #----------------------------------------------------------------------- - - adk_name = 'freepdk-45nm' - adk_view = 'view-standard' - - parameters = { - 'construct_path' : __file__, - 'design_name' : 'prbs_checker', - 'clock_period' : 2.0, - 'adk' : adk_name, - 'adk_view' : adk_view, - 'topographical' : True, - } - - #----------------------------------------------------------------------- - # Create nodes - #----------------------------------------------------------------------- - - this_dir = os.path.dirname( os.path.abspath( __file__ ) ) - - # ADK step - - g.set_adk( adk_name ) - adk = g.get_adk_step() - - # Custom steps - - rtl = Step( this_dir + '/rtl' ) - constraints = Step( this_dir + '/constraints') - - # Default steps - - info = Step( 'info', default=True ) - dc = Step( 'synopsys-dc-synthesis', default=True ) - iflow = Step( 'cadence-innovus-flowsetup', default=True ) - init = Step( 'cadence-innovus-init', default=True ) - power = Step( 'cadence-innovus-power', default=True ) - place = Step( 'cadence-innovus-place', default=True ) - cts = Step( 'cadence-innovus-cts', default=True ) - postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) - route = Step( 'cadence-innovus-route', default=True ) - postroute = Step( 'cadence-innovus-postroute', default=True ) - postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) - signoff = Step( 'cadence-innovus-signoff', default=True ) - genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) - gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) - drc = Step( 'mentor-calibre-drc', default=True ) - lvs = Step( 'mentor-calibre-lvs', default=True ) - debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) - - #----------------------------------------------------------------------- - # Graph -- Add nodes - #----------------------------------------------------------------------- - - g.add_step( info ) - g.add_step( rtl ) - g.add_step( constraints ) - g.add_step( dc ) - g.add_step( iflow ) - g.add_step( init ) - g.add_step( power ) - g.add_step( place ) - g.add_step( cts ) - g.add_step( postcts_hold ) - g.add_step( route ) - g.add_step( postroute ) - g.add_step( postroute_hold ) - g.add_step( signoff ) - g.add_step( genlibdb ) - g.add_step( gdsmerge ) - g.add_step( drc ) - g.add_step( lvs ) - g.add_step( debugcalibre ) - - #----------------------------------------------------------------------- - # Graph -- Add edges - #----------------------------------------------------------------------- - - # Connect by name - - g.connect_by_name( adk, dc ) - g.connect_by_name( adk, iflow ) - g.connect_by_name( adk, init ) - g.connect_by_name( adk, power ) - g.connect_by_name( adk, place ) - g.connect_by_name( adk, cts ) - g.connect_by_name( adk, postcts_hold ) - g.connect_by_name( adk, route ) - g.connect_by_name( adk, postroute ) - g.connect_by_name( adk, postroute_hold ) - g.connect_by_name( adk, signoff ) - g.connect_by_name( adk, gdsmerge ) - g.connect_by_name( adk, drc ) - g.connect_by_name( adk, lvs ) - - g.connect_by_name( rtl, dc ) - g.connect_by_name( constraints, dc ) - - g.connect_by_name( dc, iflow ) - g.connect_by_name( dc, init ) - g.connect_by_name( dc, power ) - g.connect_by_name( dc, place ) - g.connect_by_name( dc, cts ) - - g.connect_by_name( iflow, init ) - g.connect_by_name( iflow, power ) - g.connect_by_name( iflow, place ) - g.connect_by_name( iflow, cts ) - g.connect_by_name( iflow, postcts_hold ) - g.connect_by_name( iflow, route ) - g.connect_by_name( iflow, postroute ) - g.connect_by_name( iflow, postroute_hold ) - g.connect_by_name( iflow, signoff ) - - g.connect_by_name( init, power ) - g.connect_by_name( power, place ) - g.connect_by_name( place, cts ) - g.connect_by_name( cts, postcts_hold ) - g.connect_by_name( postcts_hold, route ) - g.connect_by_name( route, postroute ) - g.connect_by_name( postroute, postroute_hold ) - g.connect_by_name( postroute_hold, signoff ) - - g.connect_by_name( signoff, genlibdb ) - g.connect_by_name( adk, genlibdb ) - - g.connect_by_name( signoff, gdsmerge ) - - g.connect_by_name( signoff, drc ) - g.connect_by_name( gdsmerge, drc ) - g.connect_by_name( signoff, lvs ) - g.connect_by_name( gdsmerge, lvs ) - - g.connect_by_name( adk, debugcalibre ) - g.connect_by_name( dc, debugcalibre ) - g.connect_by_name( iflow, debugcalibre ) - g.connect_by_name( signoff, debugcalibre ) - g.connect_by_name( drc, debugcalibre ) - g.connect_by_name( lvs, debugcalibre ) - - #----------------------------------------------------------------------- - # Parameterize - #----------------------------------------------------------------------- - - g.update_params( parameters ) - - return g + # Get the name of the process to be used from the environment + if 'DRAGONPHY_PROCESS' in os.environ: + DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] + else: + DRAGONPHY_PROCESS = 'FREEPDK45' + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + parameters = { + 'construct_path': __file__, + 'design_name': 'dragonphy_top', + 'topographical': True + } + + if DRAGONPHY_PROCESS == 'FREEPDK45': + parameters['adk_name'] = 'freepdk-45nm' + parameters['adk_view'] = 'view-standard' + # override some timing parameters + parameters['clk_retimer_period'] = 10.0 + parameters['clk_in_period'] = 10.0 + parameters['clk_jtag_period'] = 100.0 + elif DRAGONPHY_PROCESS == 'TSMC16': + parameters['adk_name'] = 'tsmc16' + parameters['adk_view'] = 'stdview' + # use default timing parameters specified in configure.yml + else: + raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk(parameters['adk_name']) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step(this_dir + '/rtl') + constraints = Step(this_dir + '/constraints') + + # Default steps + + info = Step( 'info', default=True ) + dc = Step( 'synopsys-dc-synthesis', default=True ) + iflow = Step( 'cadence-innovus-flowsetup', default=True ) + init = Step( 'cadence-innovus-init', default=True ) + power = Step( 'cadence-innovus-power', default=True ) + place = Step( 'cadence-innovus-place', default=True ) + cts = Step( 'cadence-innovus-cts', default=True ) + postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) + route = Step( 'cadence-innovus-route', default=True ) + postroute = Step( 'cadence-innovus-postroute', default=True ) + postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) + signoff = Step( 'cadence-innovus-signoff', default=True ) + genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) + gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) + drc = Step( 'mentor-calibre-drc', default=True ) + lvs = Step( 'mentor-calibre-lvs', default=True ) + debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( constraints ) + g.add_step( dc ) + g.add_step( iflow ) + g.add_step( init ) + g.add_step( power ) + g.add_step( place ) + g.add_step( cts ) + g.add_step( postcts_hold ) + g.add_step( route ) + g.add_step( postroute ) + g.add_step( postroute_hold ) + g.add_step( signoff ) + g.add_step( genlibdb ) + g.add_step( gdsmerge ) + g.add_step( drc ) + g.add_step( lvs ) + g.add_step( debugcalibre ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + # Connect by name + + g.connect_by_name( adk, dc ) + g.connect_by_name( adk, iflow ) + g.connect_by_name( adk, init ) + g.connect_by_name( adk, power ) + g.connect_by_name( adk, place ) + g.connect_by_name( adk, cts ) + g.connect_by_name( adk, postcts_hold ) + g.connect_by_name( adk, route ) + g.connect_by_name( adk, postroute ) + g.connect_by_name( adk, postroute_hold ) + g.connect_by_name( adk, signoff ) + g.connect_by_name( adk, gdsmerge ) + g.connect_by_name( adk, drc ) + g.connect_by_name( adk, lvs ) + + g.connect_by_name( rtl, dc ) + g.connect_by_name( constraints, dc ) + + g.connect_by_name( dc, iflow ) + g.connect_by_name( dc, init ) + g.connect_by_name( dc, power ) + g.connect_by_name( dc, place ) + g.connect_by_name( dc, cts ) + + g.connect_by_name( iflow, init ) + g.connect_by_name( iflow, power ) + g.connect_by_name( iflow, place ) + g.connect_by_name( iflow, cts ) + g.connect_by_name( iflow, postcts_hold ) + g.connect_by_name( iflow, route ) + g.connect_by_name( iflow, postroute ) + g.connect_by_name( iflow, postroute_hold ) + g.connect_by_name( iflow, signoff ) + + g.connect_by_name( init, power ) + g.connect_by_name( power, place ) + g.connect_by_name( place, cts ) + g.connect_by_name( cts, postcts_hold ) + g.connect_by_name( postcts_hold, route ) + g.connect_by_name( route, postroute ) + g.connect_by_name( postroute, postroute_hold ) + g.connect_by_name( postroute_hold, signoff ) + + g.connect_by_name( signoff, genlibdb ) + g.connect_by_name( adk, genlibdb ) + + g.connect_by_name( signoff, gdsmerge ) + + g.connect_by_name( signoff, drc ) + g.connect_by_name( gdsmerge, drc ) + g.connect_by_name( signoff, lvs ) + g.connect_by_name( gdsmerge, lvs ) + + g.connect_by_name( adk, debugcalibre ) + g.connect_by_name( dc, debugcalibre ) + g.connect_by_name( iflow, debugcalibre ) + g.connect_by_name( signoff, debugcalibre ) + g.connect_by_name( drc, debugcalibre ) + g.connect_by_name( lvs, debugcalibre ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g if __name__ == '__main__': - g = construct() -# g.plot() + g = construct() +# g.plot() diff --git a/flow/rtl/configure.yml b/flow/rtl/configure.yml index b842ba66..bba47d90 100644 --- a/flow/rtl/configure.yml +++ b/flow/rtl/configure.yml @@ -4,4 +4,7 @@ commands: - python gen_rtl.py outputs: - - design.v \ No newline at end of file + - design.v + +parameters: + design_name: None \ No newline at end of file diff --git a/flow/rtl/gen_rtl.py b/flow/rtl/gen_rtl.py index b95da3f1..cb00de0b 100644 --- a/flow/rtl/gen_rtl.py +++ b/flow/rtl/gen_rtl.py @@ -1,20 +1,46 @@ +import os +import re from pathlib import Path from dragonphy import * -TOP_CELL = 'prbs_checker' +TOP_CELL = os.environ.get('design_name', 'dragonphy_top') OUTPUT_FILE = 'design.v' +INC_DIRS = [get_dir('inc/new_asic')] + +def resolve_include_file(name): + if Path(name).is_absolute(): + return Path(name) + else: + for inc_dir in INC_DIRS: + if (inc_dir / name).is_file(): + return (inc_dir / name) + raise Exception(f'Could not find include file: {name}') # build up a list of source files src_files = [] +src_files += [get_file('vlog/new_chip_src/jtag/jtag_intf.sv')] src_files += get_deps_new_asic(TOP_CELL) +# generate the output text +output = '' +inc_pat = re.compile(r'\s*`include\s+"?([a-zA-Z0-9_./]+)"?') +for src_file in src_files: + output += f'// Content from file: {src_file}\n' + for line in open(src_file, 'r').readlines(): + match = inc_pat.match(line) + if match is None: + output += line + else: + filename = resolve_include_file(match.groups()[0]) + output += f'// Content from included file: {filename}\n' + output += open(filename, 'r').read() + output += '\n' + output += '\n' + # create output directory OUTPUT_DIR = Path('outputs') OUTPUT_DIR.mkdir(exist_ok=True, parents=True) -# write source files in order +# write output text with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: - for src_file in src_files: - f.write(f'// Content from file: {src_file}\n') - f.write(open(src_file, 'r').read()) - f.write('\n') + f.write(output) diff --git a/tests/test_config/test_config.py b/tests/test_config/test_config.py index 7c44eeb2..23fdfc8d 100644 --- a/tests/test_config/test_config.py +++ b/tests/test_config/test_config.py @@ -1,8 +1,8 @@ from dragonphy import * def test_new_asic(): - print('Test New ASIC Config (analog_core)') - print(get_deps_new_asic('analog_core')) + print('Test New ASIC Config') + print(get_deps_new_asic('dragonphy_top')) def test_new_chip_src_config(): print('Test New Chip Source Config') diff --git a/vlog/new_chip_stubs/DW_tap.sv b/vlog/new_chip_stubs/DW_tap.sv deleted file mode 100644 index fe1d9a2f..00000000 --- a/vlog/new_chip_stubs/DW_tap.sv +++ /dev/null @@ -1,33 +0,0 @@ -// just a stub... - -module DW_tap #( - parameter width = 2, - parameter id = 0, - parameter version = 0, - parameter part = 0, - parameter man_num = 0, - parameter sync_mode = 0 -) ( - input tck, - input trst_n, - input tms, - input tdi, - input so, - input bypass_sel, - input [(width - 2):0] sentinel_val, - - output clock_dr, - output shift_dr, - output update_dr, - output tdo, - output tdo_en, - output [15:0] tap_state, - output extest, - output samp_load, - output [(width - 1):0] instructions, - output sync_capture_en, - output sync_update_dr, - - input test -); -endmodule \ No newline at end of file diff --git a/vlog/new_chip_stubs/analog_core/analog_core.sv b/vlog/new_chip_stubs/analog_core/analog_core.sv new file mode 100644 index 00000000..f54e878a --- /dev/null +++ b/vlog/new_chip_stubs/analog_core/analog_core.sv @@ -0,0 +1,260 @@ +`include "iotype.sv" +//`include "/aha/sjkim85/github_repo/dragonphy/inc/new_asic/iotype.sv" + +module analog_core import const_pack::*; #( +) ( + input `pwl_t rx_inp, // RX input (+) (from pad) + input `pwl_t rx_inn, // RX input (-) (from pad) + input `real_t Vcm, // common mode voltate for termination + // (from pad/inout) + + input `pwl_t rx_inp_test, // RX input (+) for replica ADC (from pad) + input `pwl_t rx_inn_test, // RX input (-) for replica ADC (from pad) + + input wire logic ext_clk, // (+) 4GHz clock input (from pad) + input wire logic mdll_clk, // (+) 4GHz clock input (from mdll) + + input wire logic ext_clk_test0, // (+) 4GHz clock input (from pad) + input wire logic ext_clk_test1, // (-) 4GHz clock input (from pad) + + input wire logic clk_cdr, // cdr loop filter clock (from DCORE) + input wire logic clk_async, // asynchronous clock for phase measurement + // (from DCORE) + input wire logic [Npi-1:0] ctl_pi[Nout-1:0], // PI control code (from DCORE) + + input `real_t Vcal, // bias voltage for V2T (from pad) + + output wire logic clk_adc, // clock for retiming adc data assigned from ADC_0 + // (to DCORE) + output wire logic [Nadc-1:0] adder_out [Nti-1:0], // adc output (to DCORE) + output wire logic [Nti-1:0] sign_out, // adc output (to DCORE) + + output wire logic [Nadc-1:0] adder_out_rep [1:0], // adc_rep output (to DCORE) + output wire logic [1:0] sign_out_rep, // adc_rep_output (to DOORE) + + acore_debug_intf.acore adbg_intf_i +); + + // internal signals + `pwl_t VinP_slice [Nout-1:0]; + `pwl_t VinN_slice [Nout-1:0]; + + logic [Nti-1:0] en_sync_in; + logic [Nti-1:0] en_sync_out; + logic [Nti-1:0] clk_v2t_prev; + logic [Nti-1:0] clk_v2t_next; + logic [Nti-1:0] clk_div; + logic [1:0] clk_v2t_next_rep; + logic [1:0] clk_div_rep; + + logic [Nout-1:0] clk_interp_slice; + logic [Nout-1:0] clk_interp_sw; + logic [Nout-1:0] clk_interp_swb; + logic clk_in_pi; + + assign clk_adc = clk_div[0]; + + // termination + termination iterm( + .VinP(rx_inp), + .VinN(rx_inn), + .Vcm(Vcm) + ); + + // 1st-level SnH + snh iSnH ( + .clk(clk_interp_sw), + .clkb(clk_interp_swb), + .in_p(rx_inp), + .in_n(rx_inn), + .out_p(VinP_slice), + .out_n(VinN_slice) + ); + + // 16-way TI ADC + generate + for (genvar k=0; k Date: Wed, 6 May 2020 12:10:01 -0700 Subject: [PATCH 07/16] try running synthesis test on dragonphy_top --- flow/construct-commercial-full.py | 34 +- flow/rtl/gen_rtl.py | 4 + .../assertion_helpers.py | 67 ++ flow/synopsys-dc-synthesis/configure.yml | 93 +++ flow/synopsys-dc-synthesis/dc.tcl | 598 ++++++++++++++++++ .../designer_interface.tcl | 90 +++ flow/synopsys-dc-synthesis/pre_synth.tcl | 49 ++ flow/synopsys-dc-synthesis/run.sh | 114 ++++ vlog/new_chip_src/analog_core/analog_core.sv | 3 +- .../new_chip_src/digital_core/digital_core.sv | 3 +- .../new_chip_stubs/analog_core/analog_core.sv | 236 +------ 11 files changed, 1057 insertions(+), 234 deletions(-) create mode 100644 flow/synopsys-dc-synthesis/assertion_helpers.py create mode 100644 flow/synopsys-dc-synthesis/configure.yml create mode 100644 flow/synopsys-dc-synthesis/dc.tcl create mode 100644 flow/synopsys-dc-synthesis/designer_interface.tcl create mode 100644 flow/synopsys-dc-synthesis/pre_synth.tcl create mode 100755 flow/synopsys-dc-synthesis/run.sh diff --git a/flow/construct-commercial-full.py b/flow/construct-commercial-full.py index c7198fb7..5ab92a26 100644 --- a/flow/construct-commercial-full.py +++ b/flow/construct-commercial-full.py @@ -34,6 +34,38 @@ def construct(): parameters['clk_retimer_period'] = 10.0 parameters['clk_in_period'] = 10.0 parameters['clk_jtag_period'] = 100.0 + + # update timing parameters + slowdown=10 + parameters.update(dict( + clk_retimer_period=0.7*slowdown, + clk_in_period=0.7*slowdown, + clk_jtag_period=100.0*slowdown, + + # Retimer clock uncertainty + clk_retimer_setup_uncertainty=0.03*slowdown, + clk_retimer_hold_uncertainty=0.03*slowdown, + + # JTAG clock uncertainty + clk_jtag_setup_uncertainty=1.0*slowdown, + clk_jtag_hold_uncertainty=0.03*slowdown, + + # Capacitance and transition time + max_capacitance=0.1*slowdown, + max_transition=0.2*slowdown, + max_clock_transition=0.1*slowdown, + + # Clocks that can be monitored from analog_core + clk_hs_period=0.25*slowdown, + clk_hs_transition=0.025*slowdown, + + # I/O delays and transitions + digital_input_delay=0.05*slowdown, + digital_input_transition=0.5*slowdown, + input_transition=0.03*slowdown, + output_load=0.02*slowdown, + output_delay=0.7*slowdown + )) elif DRAGONPHY_PROCESS == 'TSMC16': parameters['adk_name'] = 'tsmc16' parameters['adk_view'] = 'stdview' @@ -56,11 +88,11 @@ def construct(): rtl = Step(this_dir + '/rtl') constraints = Step(this_dir + '/constraints') + dc = Step(this_dir + '/synopsys-dc-synthesis') # Default steps info = Step( 'info', default=True ) - dc = Step( 'synopsys-dc-synthesis', default=True ) iflow = Step( 'cadence-innovus-flowsetup', default=True ) init = Step( 'cadence-innovus-init', default=True ) power = Step( 'cadence-innovus-power', default=True ) diff --git a/flow/rtl/gen_rtl.py b/flow/rtl/gen_rtl.py index cb00de0b..0220505c 100644 --- a/flow/rtl/gen_rtl.py +++ b/flow/rtl/gen_rtl.py @@ -23,6 +23,10 @@ def resolve_include_file(name): # generate the output text output = '' + +# TODO: remove this! +output += '`define SYNTHESIS_DEBUG\n' + inc_pat = re.compile(r'\s*`include\s+"?([a-zA-Z0-9_./]+)"?') for src_file in src_files: output += f'// Content from file: {src_file}\n' diff --git a/flow/synopsys-dc-synthesis/assertion_helpers.py b/flow/synopsys-dc-synthesis/assertion_helpers.py new file mode 100644 index 00000000..c873bdd0 --- /dev/null +++ b/flow/synopsys-dc-synthesis/assertion_helpers.py @@ -0,0 +1,67 @@ +#========================================================================= +# assertion_helpers.py +#========================================================================= +# Helper functions for assertions +# +# Author : Christopher Torng +# Date : March 14, 2020 +# + +from glob import glob + +import re + +# percent_clock_gated +# +# Reads the clock-gating report and returns a float representing the +# percentage of registers that are clock gated. +# + +def percent_clock_gated(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the clock-gating percentage, which looks like this: + # + # | Number of Gated registers | 32 (94.12%) | + # + + gate_line = [ l for l in lines if 'Number of Gated registers' in l ][0] + + # Extract the percentage between parentheses + + percentage = float( re.search( r'\((.*?)%\)', gate_line ).group(1) )/100 + + return percentage + +# n_regs +# +# Reads the clock-gating report and returns an integer for the number of +# registers that exist in the design. +# + +def n_regs(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the number of registers, which looks like this: + # + # | Total number of registers | 34 | + # + + regs_line = [ l for l in lines if 'Total number of registers' in l ][0] + + # Extract the number + + regs = int( re.search( r'\|\s*(\d*)\s*\|', regs_line ).group(1) ) + + return regs + + + diff --git a/flow/synopsys-dc-synthesis/configure.yml b/flow/synopsys-dc-synthesis/configure.yml new file mode 100644 index 00000000..47a7538e --- /dev/null +++ b/flow/synopsys-dc-synthesis/configure.yml @@ -0,0 +1,93 @@ +#========================================================================= +# Synopsys DC Synthesis +#========================================================================= +# Author : Christopher Torng, Yanghui Ou +# Date : June 7, 2019 +# + +name: synopsys-dc-synthesis + +#------------------------------------------------------------------------- +# Inputs and Outputs +#------------------------------------------------------------------------- + +inputs: + - adk + - design.v + - constraints.tcl + - run.saif + +outputs: + - design.v + - design.sdc + - design.namemap + +#------------------------------------------------------------------------- +# Commands +#------------------------------------------------------------------------- + +commands: + - bash run.sh + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +parameters: + clock_period: 1.0 + design_name: undefined + # Path to the design instance in run.saif (e.g., tb/dut) + saif_instance: undefined + flatten_effort: 0 + topographical: True + nthreads: 16 # multithreading available to the tool + +#------------------------------------------------------------------------- +# Debug +#------------------------------------------------------------------------- + +debug: + - export DC_EXIT_AFTER_SETUP=1 + - ln -sf results/*.mapped.ddc debug.ddc + - design_vision-xg -topographical -x "source dc.tcl; read_ddc debug.ddc" + +#------------------------------------------------------------------------- +# Assertions +#------------------------------------------------------------------------- + +preconditions: + + - assert Tool( 'dc_shell-xg-t' ) # tool check + - assert File( 'inputs/adk' ) # must exist + - assert File( 'inputs/design.v' ) # must exist + - assert File( 'inputs/constraints.tcl' ) # must exist + +postconditions: + + - assert File( 'outputs/design.v' ) # must exist + - assert File( 'outputs/design.sdc' ) # must exist + + # Basic error checking + + - assert 'error' not in File( 'logs/dc.log' ) + - assert 'Unresolved references' not in File( 'logs/dc.log' ) + - assert 'Unable to resolve' not in File( 'logs/dc.log' ) + + # If GTECH is found, that means this design was not mapped to a + # technology library and is still in DC's generic representation + + - assert 'GTECH' not in File( 'outputs/design.v' ) + + # Sanity check that there is a clock in the constraints + + - assert 'create_clock' in File( 'outputs/design.sdc' ) + + # Check that at least N% of registers were clock-gated + # TODO add this check back + +# - | +# from assertion_helpers import percent_clock_gated, n_regs +# if n_regs() > 10: +# assert percent_clock_gated() > 0.50 + + diff --git a/flow/synopsys-dc-synthesis/dc.tcl b/flow/synopsys-dc-synthesis/dc.tcl new file mode 100644 index 00000000..19b255e8 --- /dev/null +++ b/flow/synopsys-dc-synthesis/dc.tcl @@ -0,0 +1,598 @@ +#========================================================================= +# dc.tcl +#========================================================================= +# We use Synopsys DC to synthesize a single RTL netlist file into gates. +# +# This script has evolved over time inspired by (1) the Synopsys reference +# methodology scripts that are released year after year on Solvnet, (2) +# synthesis scripts from other research groups, as well as (3) reference +# papers from user groups online. +# +# If you make a major update to this script (e.g., update inspired by the +# latest version of the Synopsys reference methodology), please list the +# changeset in the version history below. +# +# Author : Christopher Torng +# Date : September 30, 2018 +# +#------------------------------------------------------------------------- +# Version History +#------------------------------------------------------------------------- +# +# - 09/30/2018 -- Christopher Torng +# - Clean slate DC scripts +# - We are now independent of the Synopsys Reference Methodology +# - Version of Synopsys DC running "% dc_shell -v": +# dc_shell version - M-2016.12 +# dc_shell build date - Nov 21, 2016 +# +# - 04/08/2018 -- Christopher Torng +# - Our original version was based on the Synopsys reference +# methodology (D-2010.03-SP1) +# - Big update now inspired by the Celerity Synopsys DC scripts, which +# were in turn also based on the Synopsys reference methodology +# (L-2016.03-SP2) +# +#------------------------------------------------------------------------- + +#------------------------------------------------------------------------- +# Designer interface +#------------------------------------------------------------------------- +# Source the designer interface script, which sets up variables from the +# build system, sets up ASIC design kit variables, etc. + +source -echo -verbose designer_interface.tcl + +#------------------------------------------------------------------------- +# Pre-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_pre_synthesis_plugin]]} { + puts "Info: Reading pre-synth plugin: $dc_pre_synthesis_plugin" + source -echo -verbose $dc_pre_synthesis_plugin +} + +#------------------------------------------------------------------------- +# Setup +#------------------------------------------------------------------------- + +# Set up variables for this specific ASIC design kit + +set SYNOPSYS_TOOL "dc-syn" +source -echo -verbose $dc_adk_tcl + +# Multicore support -- watch how many licenses we have! + +set_host_options -max_cores $dc_num_cores + +# Set up alib caching for faster consecutive runs + +set_app_var alib_library_analysis_path $dc_alib_dir + +# Set up tracking for Synopsys Formality + +set_svf ${dc_results_dir}/${dc_design_name}.mapped.svf + +# Set up search path for libraries and design files + +set_app_var search_path ". $dc_additional_search_path $search_path" + +# Important app vars +# +# - target_library -- DC maps the design to gates in this library (db) +# - synthetic_library -- DesignWare library (sldb) +# - link_library -- Libraries for any other design references (e.g., +# SRAMs, hierarchical blocks, macros, IO libs) (db) + +set_app_var target_library $dc_target_libraries +set_app_var synthetic_library dw_foundation.sldb +set_app_var link_library [join " + * + $target_library + $dc_extra_link_libraries + $synthetic_library + "] + + +# SAIF mapping. + # +saif_map -start + +# Create Milkyway library +# +# By default, Milkyway libraries only have 180 or so layers available to +# use (255 total, but some are reserved). The extend_mw_layers command +# expands the Milkyway library to accommodate up to 4095 layers. + +# Only create new Milkyway design library if it doesn't already exist + +set milkyway_library ${dc_design_name}_lib + +if {![file isdirectory $milkyway_library ]} { + + # Create a new Milkyway library + + extend_mw_layers + create_mw_lib -technology $dc_milkyway_tf \ + -mw_reference_library $dc_milkyway_ref_libraries \ + $milkyway_library + +} else { + + # Reuse existing Milkyway library, but ensure that it is consistent with + # the provided reference Milkyway libraries. + + set_mw_lib_reference $milkyway_library \ + -mw_reference_library $dc_milkyway_ref_libraries + +} + +open_mw_lib $milkyway_library + +# Set up TLU plus (if the files exist) + +if { $dc_topographical == True } { + if {[file exists [which $dc_tluplus_max]]} { + set_tlu_plus_files -max_tluplus $dc_tluplus_max \ + -min_tluplus $dc_tluplus_min \ + -tech2itf_map $dc_tluplus_map + + check_tlu_plus_files + } +} + +# Avoiding X-propagation for synchronous reset DFFs +# +# There are two key variables that help avoid X-propagation for +# synchronous reset DFFs: +# +# - set hdlin_ff_always_sync_set_reset true +# +# - Tells DC to use every constant 0 loaded into a DFF with a clock +# for synchronous reset, and every constant 1 loaded into a DFF with a +# clock for synchronous set +# +# - set compile_seqmap_honor_sync_set_reset true +# +# - Tells DC to preserve synchronous reset or preset logic close to +# the flip-flop +# +# So the hdlin variable first tells DC to treat resets as synchronous, and +# the compile variable tells DC that for all these synchronous reset DFFs, +# keep the logic simple and close to the DFF to avoid X-propagation. The +# hdlin variable applies to the analyze step when we read in the RTL, so +# it must be set before we read in the Verilog. The second variable +# applies to compile and must be set before we run compile_ultra. +# +# Note: Instead of setting the hdlin_ff_always_sync_set_reset variable to +# true, you can specifically tell DC about a particular DFF reset using +# the //synopsys sync_set_reset "reset, int_reset" pragma. +# +# By default, the hdlin_ff_always_async_set_reset variable is set to true, +# and the hdlin_ff_always_sync_set_reset variable is set to false. + +set hdlin_ff_always_sync_set_reset true +set compile_seqmap_honor_sync_set_reset true + +# Remove new variable info messages from the end of the log file + +set_app_var sh_new_variable_message false + +# Corners +# +# If we want to do corners in DC, then we would use this command to set +# the min and max libraries: + +#set_min_library $max_library -min_version $min_library + +# SAIF Name Mapping Database + +#if { ${VINAME} != "NONE" } { +# saif_map -start +#} + +# Hook to drop into interactive Design Compiler shell after setup + +if {[info exists ::env(DC_EXIT_AFTER_SETUP)]} { return } + +#------------------------------------------------------------------------- +# Read design +#------------------------------------------------------------------------- + +# Check libraries + +check_library > $dc_reports_dir/${dc_design_name}.check_library.rpt + +# The first "WORK" is a reserved word for Design Compiler. The value for +# the -path option is customizable. + +define_design_lib WORK -path ${dc_results_dir}/WORK + +# Analyze the RTL source files +# +# Source the read design plugin if it exists. Otherwise, we do a default +# read and elaborate the design. + +if {[file exists [which $dc_read_design_plugin]]} { + puts "Info: Reading read design plugin: $dc_read_design_plugin" + source -echo -verbose $dc_read_design_plugin +} else { + # Since no read design plugin exists, we do a default read + if { ![analyze -format sverilog $dc_rtl_handoff] } { exit 1 } + if {[file exists [which setup-design-params.txt]]} { + elaborate $dc_design_name -file_parameters setup-design-params.txt + rename_design $dc_design_name* $dc_design_name + } else { + elaborate $dc_design_name + } +} + +current_design $dc_design_name +link + +#------------------------------------------------------------------------- +# Write out useful files +#------------------------------------------------------------------------- + +# This ddc can be used as a checkpoint to load up to the current state + +write -hierarchy -format ddc \ + -output ${dc_results_dir}/${dc_design_name}.elab.ddc + +# This Verilog is useful to double-check the netlist that dc will use for +# mapping + +write -hierarchy -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.elab.v + +#------------------------------------------------------------------------- +# Apply design constraints +#------------------------------------------------------------------------- + +# Apply logical design constraints + +puts "Info: Reading constraints file plugin: $dc_constraints_plugin" + +source -echo -verbose $dc_constraints_plugin + +# The check_timing command checks for constraint problems such as +# undefined clocking, undefined input arrival times, and undefined output +# constraints. These constraint problems could cause you to overlook +# timing violations. For this reason, the check_timing command is +# recommended whenever you apply new constraints such as clock +# definitions, I/O delays, or timing exceptions. + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.premapped.checktiming.rpt \ + {check_timing} + +# Path groups + +set ports_clock_root [filter_collection \ + [get_attribute [get_clocks] sources] \ + object_class==port] + +group_path -name REGOUT \ + -to [all_outputs] + +group_path -name REGIN \ + -from [remove_from_collection [all_inputs] $ports_clock_root] + +group_path -name FEEDTHROUGH \ + -from [remove_from_collection [all_inputs] $ports_clock_root] \ + -to [all_outputs] + +# Apply physical design constraints +# +# Set the minimum and maximum routing layers used in DC topographical mode + +if { $dc_topographical == True } { + set_ignored_layers -min_routing_layer $ADK_MIN_ROUTING_LAYER_DC + set_ignored_layers -max_routing_layer $ADK_MAX_ROUTING_LAYER_DC + + report_ignored_layers +} + +#------------------------------------------------------------------------- +# Additional options +#------------------------------------------------------------------------- + +# Replace special characters with non-special ones before writing out the +# synthesized netlist (e.g., "\bus[5]" -> "bus_5_") + +set_app_var verilogout_no_tri true + +# Prevent assignment statements in the Verilog netlist. + +set_fix_multiple_port_nets -all -buffer_constants + +# Choose design flattening options + +if {[info exists DC_FLATTEN_EFFORT]} { + set dc_flatten_effort $DC_FLATTEN_EFFORT + if {"$dc_flatten_effort" == ""} { + set dc_flatten_effort 0 + } +} else { + set dc_flatten_effort 0 +} + +puts "Info: Flattening effort (DC_FLATTEN_EFFORT) = $dc_flatten_effort" + +set compile_ultra_options "" +if {$dc_flatten_effort == 0} { + puts "Info: All design hierarchies are preserved unless otherwise specified." + set_app_var compile_ultra_ungroup_dw false + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 1} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is disabled." + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 2} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + append compile_ultra_options "" + +} elseif {$dc_flatten_effort == 3} { + set ungroup_start_level 2 + ungroup -start_level $ungroup_start_level -all -flatten + puts "Info: All hierarchical cells starting from level $ungroup_start_level are flattened." + puts "Info: Unconditionally ungroup the DesignWare cells." + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + set_app_var compile_ultra_ungroup_dw true + append compile_ultra_options "" + +} else { + puts "Info: Unrecognizable DC_FLATTEN_EFFORT value: $dc_flatten_effort" + exit +} + +# Enable or disable clock gating + +if {[info exists DC_GATE_CLOCK]} { + set dc_gate_clock $DC_GATE_CLOCK + if {"$dc_gate_clock" == ""} { + set dc_gate_clock true + } +} else { + set dc_gate_clock true +} + +puts "Info: Clock gating (DC_GATE_CLOCK) = $dc_gate_clock" + +if {$dc_gate_clock == true} { + append compile_ultra_options " -gate_clock" +} + +# Check design for consistency +# +# Most problems with synthesis will be caught in this report + +check_design -summary +check_design \ + > ${dc_reports_dir}/${dc_design_name}.premapped.checkdesign.rpt + +#------------------------------------------------------------------------- +# Compile +#------------------------------------------------------------------------- + +puts "Info: DC compile_ultra options = $compile_ultra_options" + +eval "compile_ultra $compile_ultra_options" + +# High-effort area optimization +# +# This command was introduced in I-2013.12 and performs monotonic +# gate-to-gate optimization on mapped designs. It is supposed to improve +# area without degrading timing or leakage. + +# Skip this step by setting the DC_SKIP_OPTIMIZE_NETLIST variable in the +# pre-synthesis plugin + +if {!([info exists DC_SKIP_OPTIMIZE_NETLIST] && $DC_SKIP_OPTIMIZE_NETLIST)} { + optimize_netlist -area +} + +# Check design + +check_design -summary +check_design > ${dc_reports_dir}/${dc_design_name}.mapped.checkdesign.rpt + +# Write the .namemap file for the Energy analysis + +if {[file exists "inputs/run.saif" ]} { + saif_map \ + -create_map \ + -input "inputs/run.saif" \ + -source_instance ${dc_saif_instance} +} + +#------------------------------------------------------------------------- +# Write out the design +#------------------------------------------------------------------------- + +# Synopsys Formality + +set_svf -off + +# Use naming rules to preserve structs + +define_name_rules verilog -preserve_struct_ports + +report_names \ + -rules verilog \ + > ${dc_reports_dir}/${dc_design_name}.mapped.naming.rpt + +change_names -rules verilog -hierarchy + +# Write out files + +write -format ddc \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.ddc + +write -format verilog \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.v + +write -format svsim \ + -output ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v + +# Dump the mapped.v and svwrapper.v into one svsim.v file to make it +# easier to include a single file for gate-level simulation. The svwrapper +# matches the interface of the original RTL even if using SystemVerilog +# features (e.g., array of arrays, uses parameters, etc.). + +sh cat ${dc_results_dir}/${dc_design_name}.mapped.v \ + ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v \ + > ${dc_results_dir}/${dc_design_name}.mapped.svsim.v + +# Write top-level verilog view needed for block instantiation + +write \ + -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.mapped.top.v + +# Floorplan + +if { $dc_topographical == True } { + write_floorplan -all ${dc_results_dir}/${dc_design_name}.mapped.fp +} + +# Parasitics + +write_parasitics -output ${dc_results_dir}/${dc_design_name}.mapped.spef + +# SDF for back-annotated gate-level simulation + +write_sdf ${dc_results_dir}/${dc_design_name}.mapped.sdf + +# Do not write out net RC info into SDC + +set_app_var write_sdc_output_lumped_net_capacitance false +set_app_var write_sdc_output_net_resistance false + +# SDC constraints + +write_sdc -nosplit ${dc_results_dir}/${dc_design_name}.mapped.sdc + +#------------------------------------------------------------------------- +# Final reports +#------------------------------------------------------------------------- + +# Report units + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.mapped.units.rpt \ + {report_units} + +# Report QOR + +report_qor > ${dc_reports_dir}/${dc_design_name}.mapped.qor.rpt + +# Report timing + +report_clock_timing \ + -type summary \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.clock.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type max \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.setup.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type min \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.hold.rpt + +# Report constraints + +report_constraint \ + -nosplit \ + -verbose \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.rpt + +report_constraint \ + -nosplit \ + -verbose \ + -all_violators \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.violators.rpt + +report_timing_requirements \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.requirements.rpt + +# Report area + +report_area \ + -hierarchy \ + -physical \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.area.rpt + +# Report references and resources + +report_reference \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.reference.rpt + +report_resources \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.resources.rpt + +# Report power +# +# Use SAIF file for power analysis +if {[file exists "inputs/run.saif" ]} { + read_saif \ + -map_names \ + -input "inputs/run.saif" \ + -instance_name $dc_saif_instance \ + -verbose + + report_saif \ + -hier \ + -annotated_flag \ + -rtl_saif \ + > ${dc_reports_dir}/${dc_design_name}.mapped.saif.rpt + + saif_map \ + -type ptpx \ + -write_map \ + ${dc_reports_dir}/${dc_design_name}.namemap +} + +report_power \ + -nosplit \ + -hier \ + > ${dc_reports_dir}/${dc_design_name}.mapped.power.rpt + +report_clock_gating \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.clock_gating.rpt + +#------------------------------------------------------------------------- +# Post-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_post_synthesis_plugin]]} { + puts "Info: Reading post-synthesis plugin: $dc_post_synthesis_plugin" + source -echo -verbose $dc_post_synthesis_plugin +} + +exit + diff --git a/flow/synopsys-dc-synthesis/designer_interface.tcl b/flow/synopsys-dc-synthesis/designer_interface.tcl new file mode 100644 index 00000000..0996d017 --- /dev/null +++ b/flow/synopsys-dc-synthesis/designer_interface.tcl @@ -0,0 +1,90 @@ +#========================================================================= +# designer_interface.tcl +#========================================================================= +# The designer_interface.tcl file is the first script run by Design +# Compiler (see the top of dc.tcl). It is the interface that connects the +# dc-synthesis scripts with the following: +# +# - Build system parameters +# - Build system inputs +# - ASIC design kit +# - Plugin scripts +# +# Author : Christopher Torng +# Date : April 8, 2018 + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +set dc_design_name $::env(design_name) +set dc_saif_instance $::env(saif_instance) +set dc_clock_period $::env(clock_period) +set dc_flatten_effort $::env(flatten_effort) +set dc_topographical $::env(topographical) + +#------------------------------------------------------------------------- +# Inputs +#------------------------------------------------------------------------- + +set dc_rtl_handoff inputs/design.v +set adk_dir inputs/adk + +# Extra libraries +# +# The glob below will capture any libraries collected by the build system +# (e.g., SRAM libraries) generated from steps that synthesis depends on. +# +# To add more link libraries (e.g., IO cells, hierarchical blocks), append +# to the "dc_extra_link_libraries" variable in the pre-synthesis plugin +# like this: +# +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +set dc_extra_link_libraries [join " + [glob -nocomplain inputs/*.db] + [glob -nocomplain inputs/adk/*.db] + "] + +#------------------------------------------------------------------------- +# Interface to the ASIC design kit +#------------------------------------------------------------------------- + +set dc_milkyway_ref_libraries $adk_dir/stdcells.mwlib +set dc_milkyway_tf $adk_dir/rtk-tech.tf +set dc_tluplus_map $adk_dir/rtk-tluplus.map +set dc_tluplus_max $adk_dir/rtk-max.tluplus +set dc_tluplus_min $adk_dir/rtk-min.tluplus +set dc_adk_tcl $adk_dir/adk.tcl +set dc_target_libraries stdcells.db + +# Extra libraries + +set dc_additional_search_path $adk_dir + +#------------------------------------------------------------------------- +# Directories +#------------------------------------------------------------------------- + +set dc_flow_dir . +set dc_plugins_dir . +set dc_logs_dir logs +set dc_reports_dir reports +set dc_results_dir results +set dc_alib_dir alib + +#------------------------------------------------------------------------- +# Interface to plugins +#------------------------------------------------------------------------- + +set dc_pre_synthesis_plugin pre_synth.tcl +set dc_read_design_plugin read_design.tcl +set dc_constraints_plugin inputs/constraints.tcl +set dc_post_synthesis_plugin post_synth.tcl + + diff --git a/flow/synopsys-dc-synthesis/pre_synth.tcl b/flow/synopsys-dc-synthesis/pre_synth.tcl new file mode 100644 index 00000000..e5cab31f --- /dev/null +++ b/flow/synopsys-dc-synthesis/pre_synth.tcl @@ -0,0 +1,49 @@ +#========================================================================= +# pre_synth.tcl +#========================================================================= +# This plug-in script is called before synthesis +# +# Author : Christopher Torng +# Date : May 14, 2018 + +# Number of cores for multicore optimization + +set dc_num_cores $env(nthreads) + +# Add more link libraries (e.g., IO cells, hierarchical blocks) + +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +# Enable additional area optimizations (skip false = enable optimizations) + +set DC_SKIP_OPTIMIZE_NETLIST true + +# Enable clock-gating + +set DC_GATE_CLOCK true + +# DC flatten effort +# +# - Effort 0: No auto-ungrouping / boundary optimizations (strict hierarchy) +# - Effort 1: No auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 2: Enable auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 3: Everything ungrouped + level param for how deep to ungroup +# +# Note that even with boundary optimizations off, DC will still propagate +# constants across the boundary, although this can be disabled with a +# variable if we really wanted to disable it. + +set DC_FLATTEN_EFFORT $env(flatten_effort) + +# When boundary optimizations are off, set this variable to true to still +# allow unconnected registers to be removed. + +set compile_optimize_unloaded_seq_logic_with_no_bound_opt true + diff --git a/flow/synopsys-dc-synthesis/run.sh b/flow/synopsys-dc-synthesis/run.sh new file mode 100755 index 00000000..ae57c1f0 --- /dev/null +++ b/flow/synopsys-dc-synthesis/run.sh @@ -0,0 +1,114 @@ +#! /usr/bin/env bash +#========================================================================= +# run.sh +#========================================================================= +# Author : Christopher Torng +# Date : June 2, 2019 +# + +# Print commands during execution + +set -x + +# DC shell + +dc_exec='dc_shell-xg-t -64bit' + +# Build directories + +rm -rf ./logs +rm -rf ./reports +rm -rf ./results + +mkdir -p logs +mkdir -p reports +mkdir -p results + +# alib +# +# Design Compiler caches analyzed libraries to improve performance using +# ".alib" directories. The alib takes a while to generate but is reused on +# subsequent runs. It is useful to store a centralized copy of the alib to +# avoid re-generating the alib (usually only several minutes but can be +# annoying) on every new clone of the ASIC repo. +# +# However, if DC sees a .db that does not have an associated .alib it will +# try to automatically create one. This is not usually a problem when +# students just use standard cells, but if a student is trying to use +# SRAMs, then they will be using new .db files that DC has not seen yet. +# The problem is that students do not have write permissions to the +# centralized copy of the alib in the ADK. +# +# The solution we use is to create a local alib directory in the current +# build directory with _per-file_ symlinks to the centralized alib (and +# with the same directory hierarchy). This allows students to reuse the +# centralized copies of the alib files while allowing new alibs (e.g., for +# SRAMs) to be generated locally. +# +# This is possible because the alibs are stored in a directory that holds +# a ".db.alib" file for each db file: +# +# - alib +# - alib-52 +# - iocells.db.alib +# - stdcells.db.alib +# +# This new alib directory just needs to contain symlinks to each saved +# alib in the ADK. This can be done simply by using "cp -srf" of the ADK +# alib to the build directory, which generates symbolic links to each file +# instead of copying. This way, the student can access the master copy of +# the saved alibs in the ADK, and if there are any additional db's +# specified, their alibs will be saved in the local build directory. + +rm -rf alib +mkdir -p alib + +cp -srf $PWD/inputs/adk/alib/* alib || true + +# Run the synthesis script + +if [ "x$topographical" == "xTrue" ]; then + opt_topographical='-topographical_mode' +else + opt_topographical= +fi + +$dc_exec $opt_topographical -f dc.tcl -output_log_file logs/dc.log || exit 1 + +# Compress the spef file + +cd results +gzip *.mapped.spef +cd .. + +# Set up the outputs + +mkdir -p outputs && cd outputs + +ln -sf ../results/*.mapped.v design.v +ln -sf ../results/*.mapped.sdc design.sdc +ln -sf ../results/*.mapped.spef.gz design.spef.gz +ln -sf ../reports/*.namemap design.namemap + +cd .. + +# Grep for failure messages + +grep --color "^Error" logs/dc.log || true +grep --color -B 3 "*** Presto compilation terminated" logs/dc.log || true +grep --color "unresolved references." logs/dc.log || true + +# ELAB-405 +# +# When using a Verilog generation tool, there may be a +# generation/translation mistake that defines a net twice. This will give +# a message like this: +# +# Warning: ./inputs/design.v:2473: Net mul__recv__msg__opd_b[0] or a +# directly connected net may be driven by more than one process or block. +# (ELAB-405) +# +# This is usually a bad sign.. +# + +grep --color "ELAB-405" logs/dc.log || true diff --git a/vlog/new_chip_src/analog_core/analog_core.sv b/vlog/new_chip_src/analog_core/analog_core.sv index f54e878a..3a2269c6 100644 --- a/vlog/new_chip_src/analog_core/analog_core.sv +++ b/vlog/new_chip_src/analog_core/analog_core.sv @@ -1,5 +1,4 @@ `include "iotype.sv" -//`include "/aha/sjkim85/github_repo/dragonphy/inc/new_asic/iotype.sv" module analog_core import const_pack::*; #( ) ( @@ -11,7 +10,7 @@ module analog_core import const_pack::*; #( input `pwl_t rx_inp_test, // RX input (+) for replica ADC (from pad) input `pwl_t rx_inn_test, // RX input (-) for replica ADC (from pad) - input wire logic ext_clk, // (+) 4GHz clock input (from pad) + input wire logic ext_clk, // (+) 4GHz clock input (from pad) input wire logic mdll_clk, // (+) 4GHz clock input (from mdll) input wire logic ext_clk_test0, // (+) 4GHz clock input (from pad) diff --git a/vlog/new_chip_src/digital_core/digital_core.sv b/vlog/new_chip_src/digital_core/digital_core.sv index 96f509ca..ea10b50d 100644 --- a/vlog/new_chip_src/digital_core/digital_core.sv +++ b/vlog/new_chip_src/digital_core/digital_core.sv @@ -275,7 +275,7 @@ module digital_core import const_pack::*; ( ); // JTAG - + `ifndef SYNTHESIS_DEBUG jtag jtag_i ( .clk(clk_adc), .rstb(ext_rstb), @@ -286,6 +286,7 @@ module digital_core import const_pack::*; ( .pdbg_intf_i(pdbg_intf_i), .jtag_intf_i(jtag_intf_i) ); + `endif endmodule diff --git a/vlog/new_chip_stubs/analog_core/analog_core.sv b/vlog/new_chip_stubs/analog_core/analog_core.sv index f54e878a..e74a4c1b 100644 --- a/vlog/new_chip_stubs/analog_core/analog_core.sv +++ b/vlog/new_chip_stubs/analog_core/analog_core.sv @@ -1,5 +1,4 @@ `include "iotype.sv" -//`include "/aha/sjkim85/github_repo/dragonphy/inc/new_asic/iotype.sv" module analog_core import const_pack::*; #( ) ( @@ -7,23 +6,23 @@ module analog_core import const_pack::*; #( input `pwl_t rx_inn, // RX input (-) (from pad) input `real_t Vcm, // common mode voltate for termination // (from pad/inout) - + input `pwl_t rx_inp_test, // RX input (+) for replica ADC (from pad) input `pwl_t rx_inn_test, // RX input (-) for replica ADC (from pad) - - input wire logic ext_clk, // (+) 4GHz clock input (from pad) + + input wire logic ext_clk, // (+) 4GHz clock input (from pad) input wire logic mdll_clk, // (+) 4GHz clock input (from mdll) input wire logic ext_clk_test0, // (+) 4GHz clock input (from pad) input wire logic ext_clk_test1, // (-) 4GHz clock input (from pad) - + input wire logic clk_cdr, // cdr loop filter clock (from DCORE) input wire logic clk_async, // asynchronous clock for phase measurement // (from DCORE) input wire logic [Npi-1:0] ctl_pi[Nout-1:0], // PI control code (from DCORE) input `real_t Vcal, // bias voltage for V2T (from pad) - + output wire logic clk_adc, // clock for retiming adc data assigned from ADC_0 // (to DCORE) output wire logic [Nadc-1:0] adder_out [Nti-1:0], // adc output (to DCORE) @@ -31,230 +30,7 @@ module analog_core import const_pack::*; #( output wire logic [Nadc-1:0] adder_out_rep [1:0], // adc_rep output (to DCORE) output wire logic [1:0] sign_out_rep, // adc_rep_output (to DOORE) - + acore_debug_intf.acore adbg_intf_i ); - - // internal signals - `pwl_t VinP_slice [Nout-1:0]; - `pwl_t VinN_slice [Nout-1:0]; - - logic [Nti-1:0] en_sync_in; - logic [Nti-1:0] en_sync_out; - logic [Nti-1:0] clk_v2t_prev; - logic [Nti-1:0] clk_v2t_next; - logic [Nti-1:0] clk_div; - logic [1:0] clk_v2t_next_rep; - logic [1:0] clk_div_rep; - - logic [Nout-1:0] clk_interp_slice; - logic [Nout-1:0] clk_interp_sw; - logic [Nout-1:0] clk_interp_swb; - logic clk_in_pi; - - assign clk_adc = clk_div[0]; - - // termination - termination iterm( - .VinP(rx_inp), - .VinN(rx_inn), - .Vcm(Vcm) - ); - - // 1st-level SnH - snh iSnH ( - .clk(clk_interp_sw), - .clkb(clk_interp_swb), - .in_p(rx_inp), - .in_n(rx_inn), - .out_p(VinP_slice), - .out_n(VinN_slice) - ); - - // 16-way TI ADC - generate - for (genvar k=0; k Date: Wed, 6 May 2020 13:35:19 -0700 Subject: [PATCH 08/16] update synthesis for latest master branch. weight_manager and jtag are still problematic --- .buildkite/pipeline.yml | 12 +++++++----- flow/constraints/configure.yml | 3 +++ flow/constraints/gen_constraints.py | 3 ++- vlog/new_chip_src/digital_core/digital_core.sv | 4 +++- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 85020627..a9492b57 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -1,5 +1,6 @@ steps: - - command: | + - label: "test" + command: | # set up environment # modules loaded aim to match those used by Garnet source /cad/modules/tcl/init/bash @@ -16,12 +17,14 @@ steps: source regress.sh # deactivate virtual environment - deactivate - label: "test" + deactivate + artifact_paths: + - "tests/new_tests/*/build/*.eps" timeout_in_minutes: 60 agents: fault2: "true" - - command: | + - label: "test_emu" + command: | # set up environment source /etc/environment export FPGA_SERVER=1 @@ -38,7 +41,6 @@ steps: # deactivate virtual environment deactivate - label: "test_emu" timeout_in_minutes: 60 agents: fpga_verif: "true" diff --git a/flow/constraints/configure.yml b/flow/constraints/configure.yml index 6380e3b8..9c869605 100644 --- a/flow/constraints/configure.yml +++ b/flow/constraints/configure.yml @@ -11,6 +11,9 @@ outputs: parameters: # time in ns and capacitance in pF + # Name of the design + design_name: undefined + # Main clocks in the design clk_retimer_period: 0.7 clk_in_period: 0.7 diff --git a/flow/constraints/gen_constraints.py b/flow/constraints/gen_constraints.py index 7e850ae5..dffb48b1 100644 --- a/flow/constraints/gen_constraints.py +++ b/flow/constraints/gen_constraints.py @@ -109,7 +109,8 @@ # -lib_cell $ADK_DRIVING_CELL [all_inputs] # Make all signals limit their fanout -# set_max_fanout 20 $dc_design_name +# TODO: should this be included? +# set_max_fanout 20 {e["design_name"]} # sr 02/2020 # haha IOPAD cells already have dont_touch property but not ANAIOPAD :( diff --git a/vlog/new_chip_src/digital_core/digital_core.sv b/vlog/new_chip_src/digital_core/digital_core.sv index e715bd83..aa8d7094 100644 --- a/vlog/new_chip_src/digital_core/digital_core.sv +++ b/vlog/new_chip_src/digital_core/digital_core.sv @@ -31,7 +31,7 @@ module digital_core import const_pack::*; ( prbs_debug_intf pdbg_intf_i (); wme_debug_intf wdbg_intf_i (); - + // internal signals wire logic rstb; @@ -211,6 +211,7 @@ module digital_core import const_pack::*; ( assign dsp_dbg_intf_i.mlsd_shift = ddbg_intf_i.mlsd_shift; assign dsp_dbg_intf_i.thresh = ddbg_intf_i.cmp_thresh; + `ifndef SYNTHESIS_DEBUG weight_manager #(.width(Nti), .depth(10), .bitwidth(10)) wme_ffe_i ( .data (wdbg_intf_i.wme_ffe_data), .inst (wdbg_intf_i.wme_ffe_inst), @@ -230,6 +231,7 @@ module digital_core import const_pack::*; ( .read_reg(wdbg_intf_i.wme_mlsd_read), .weights (dsp_dbg_intf_i.channel_est) ); + `endif dsp_backend dsp_i( .codes(adcout_unfolded[Nti-1:0]), From 80b72a05964188554cd65d177f030d7a809209cf Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 6 May 2020 15:02:00 -0700 Subject: [PATCH 09/16] try running synthesis tests on dragonphy_top (minus jtag and weight_manager), then jtag and weight_manager separately --- {flow => designs/dragonphy_top}/.mflowgen.yml | 0 .../dragonphy_top}/constraints/configure.yml | 0 .../constraints/gen_constraints.py | 0 .../construct-commercial-full.py | 4 - .../dragonphy_top}/rtl/configure.yml | 0 .../dragonphy_top}/rtl/gen_rtl.py | 0 .../assertion_helpers.py | 0 .../synopsys-dc-synthesis/configure.yml | 0 .../synopsys-dc-synthesis/dc.tcl | 0 .../designer_interface.tcl | 0 .../synopsys-dc-synthesis/pre_synth.tcl | 0 .../synopsys-dc-synthesis/run.sh | 0 designs/jtag/.mflowgen.yml | 1 + designs/jtag/constraints/configure.yml | 23 + designs/jtag/constraints/constraints.tcl | 54 ++ .../jtag/constraints/outputs/constraints.tcl | 1 + designs/jtag/construct-commercial-full.py | 177 ++++++ designs/jtag/rtl/configure.yml | 10 + designs/jtag/rtl/gen_rtl.py | 40 ++ .../assertion_helpers.py | 67 ++ .../jtag/synopsys-dc-synthesis/configure.yml | 93 +++ designs/jtag/synopsys-dc-synthesis/dc.tcl | 598 ++++++++++++++++++ .../designer_interface.tcl | 90 +++ .../jtag/synopsys-dc-synthesis/pre_synth.tcl | 49 ++ designs/jtag/synopsys-dc-synthesis/run.sh | 114 ++++ designs/weight_manager/.mflowgen.yml | 1 + .../weight_manager/constraints/configure.yml | 23 + .../constraints/constraints.tcl | 55 ++ .../constraints/outputs/constraints.tcl | 1 + .../construct-commercial-full.py | 179 ++++++ designs/weight_manager/rtl/configure.yml | 10 + designs/weight_manager/rtl/gen_rtl.py | 27 + .../assertion_helpers.py | 67 ++ .../synopsys-dc-synthesis/configure.yml | 93 +++ .../synopsys-dc-synthesis/dc.tcl | 598 ++++++++++++++++++ .../designer_interface.tcl | 90 +++ .../synopsys-dc-synthesis/pre_synth.tcl | 49 ++ .../synopsys-dc-synthesis/run.sh | 114 ++++ regress.sh | 19 +- 39 files changed, 2640 insertions(+), 7 deletions(-) rename {flow => designs/dragonphy_top}/.mflowgen.yml (100%) rename {flow => designs/dragonphy_top}/constraints/configure.yml (100%) rename {flow => designs/dragonphy_top}/constraints/gen_constraints.py (100%) rename {flow => designs/dragonphy_top}/construct-commercial-full.py (97%) rename {flow => designs/dragonphy_top}/rtl/configure.yml (100%) rename {flow => designs/dragonphy_top}/rtl/gen_rtl.py (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/assertion_helpers.py (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/configure.yml (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/dc.tcl (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/designer_interface.tcl (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/pre_synth.tcl (100%) rename {flow => designs/dragonphy_top}/synopsys-dc-synthesis/run.sh (100%) create mode 100644 designs/jtag/.mflowgen.yml create mode 100644 designs/jtag/constraints/configure.yml create mode 100644 designs/jtag/constraints/constraints.tcl create mode 120000 designs/jtag/constraints/outputs/constraints.tcl create mode 100644 designs/jtag/construct-commercial-full.py create mode 100644 designs/jtag/rtl/configure.yml create mode 100644 designs/jtag/rtl/gen_rtl.py create mode 100644 designs/jtag/synopsys-dc-synthesis/assertion_helpers.py create mode 100644 designs/jtag/synopsys-dc-synthesis/configure.yml create mode 100644 designs/jtag/synopsys-dc-synthesis/dc.tcl create mode 100644 designs/jtag/synopsys-dc-synthesis/designer_interface.tcl create mode 100644 designs/jtag/synopsys-dc-synthesis/pre_synth.tcl create mode 100755 designs/jtag/synopsys-dc-synthesis/run.sh create mode 100644 designs/weight_manager/.mflowgen.yml create mode 100644 designs/weight_manager/constraints/configure.yml create mode 100644 designs/weight_manager/constraints/constraints.tcl create mode 120000 designs/weight_manager/constraints/outputs/constraints.tcl create mode 100644 designs/weight_manager/construct-commercial-full.py create mode 100644 designs/weight_manager/rtl/configure.yml create mode 100644 designs/weight_manager/rtl/gen_rtl.py create mode 100644 designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py create mode 100644 designs/weight_manager/synopsys-dc-synthesis/configure.yml create mode 100644 designs/weight_manager/synopsys-dc-synthesis/dc.tcl create mode 100644 designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl create mode 100644 designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl create mode 100755 designs/weight_manager/synopsys-dc-synthesis/run.sh diff --git a/flow/.mflowgen.yml b/designs/dragonphy_top/.mflowgen.yml similarity index 100% rename from flow/.mflowgen.yml rename to designs/dragonphy_top/.mflowgen.yml diff --git a/flow/constraints/configure.yml b/designs/dragonphy_top/constraints/configure.yml similarity index 100% rename from flow/constraints/configure.yml rename to designs/dragonphy_top/constraints/configure.yml diff --git a/flow/constraints/gen_constraints.py b/designs/dragonphy_top/constraints/gen_constraints.py similarity index 100% rename from flow/constraints/gen_constraints.py rename to designs/dragonphy_top/constraints/gen_constraints.py diff --git a/flow/construct-commercial-full.py b/designs/dragonphy_top/construct-commercial-full.py similarity index 97% rename from flow/construct-commercial-full.py rename to designs/dragonphy_top/construct-commercial-full.py index 5ab92a26..4caa2e0e 100644 --- a/flow/construct-commercial-full.py +++ b/designs/dragonphy_top/construct-commercial-full.py @@ -30,10 +30,6 @@ def construct(): if DRAGONPHY_PROCESS == 'FREEPDK45': parameters['adk_name'] = 'freepdk-45nm' parameters['adk_view'] = 'view-standard' - # override some timing parameters - parameters['clk_retimer_period'] = 10.0 - parameters['clk_in_period'] = 10.0 - parameters['clk_jtag_period'] = 100.0 # update timing parameters slowdown=10 diff --git a/flow/rtl/configure.yml b/designs/dragonphy_top/rtl/configure.yml similarity index 100% rename from flow/rtl/configure.yml rename to designs/dragonphy_top/rtl/configure.yml diff --git a/flow/rtl/gen_rtl.py b/designs/dragonphy_top/rtl/gen_rtl.py similarity index 100% rename from flow/rtl/gen_rtl.py rename to designs/dragonphy_top/rtl/gen_rtl.py diff --git a/flow/synopsys-dc-synthesis/assertion_helpers.py b/designs/dragonphy_top/synopsys-dc-synthesis/assertion_helpers.py similarity index 100% rename from flow/synopsys-dc-synthesis/assertion_helpers.py rename to designs/dragonphy_top/synopsys-dc-synthesis/assertion_helpers.py diff --git a/flow/synopsys-dc-synthesis/configure.yml b/designs/dragonphy_top/synopsys-dc-synthesis/configure.yml similarity index 100% rename from flow/synopsys-dc-synthesis/configure.yml rename to designs/dragonphy_top/synopsys-dc-synthesis/configure.yml diff --git a/flow/synopsys-dc-synthesis/dc.tcl b/designs/dragonphy_top/synopsys-dc-synthesis/dc.tcl similarity index 100% rename from flow/synopsys-dc-synthesis/dc.tcl rename to designs/dragonphy_top/synopsys-dc-synthesis/dc.tcl diff --git a/flow/synopsys-dc-synthesis/designer_interface.tcl b/designs/dragonphy_top/synopsys-dc-synthesis/designer_interface.tcl similarity index 100% rename from flow/synopsys-dc-synthesis/designer_interface.tcl rename to designs/dragonphy_top/synopsys-dc-synthesis/designer_interface.tcl diff --git a/flow/synopsys-dc-synthesis/pre_synth.tcl b/designs/dragonphy_top/synopsys-dc-synthesis/pre_synth.tcl similarity index 100% rename from flow/synopsys-dc-synthesis/pre_synth.tcl rename to designs/dragonphy_top/synopsys-dc-synthesis/pre_synth.tcl diff --git a/flow/synopsys-dc-synthesis/run.sh b/designs/dragonphy_top/synopsys-dc-synthesis/run.sh similarity index 100% rename from flow/synopsys-dc-synthesis/run.sh rename to designs/dragonphy_top/synopsys-dc-synthesis/run.sh diff --git a/designs/jtag/.mflowgen.yml b/designs/jtag/.mflowgen.yml new file mode 100644 index 00000000..189d498a --- /dev/null +++ b/designs/jtag/.mflowgen.yml @@ -0,0 +1 @@ +construct: construct-commercial-full.py diff --git a/designs/jtag/constraints/configure.yml b/designs/jtag/constraints/configure.yml new file mode 100644 index 00000000..e5992188 --- /dev/null +++ b/designs/jtag/constraints/configure.yml @@ -0,0 +1,23 @@ +#========================================================================= +# Constraints +#========================================================================= +# Author : Alex Carsello +# Date : Nov 1, 2019 +# + +name: constraints + +#------------------------------------------------------------------------- +# Inputs and Outputs +#------------------------------------------------------------------------- + +outputs: + - constraints.tcl + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +parameters: + clock_period: 1.0 + design_name: undefined diff --git a/designs/jtag/constraints/constraints.tcl b/designs/jtag/constraints/constraints.tcl new file mode 100644 index 00000000..e2d2a3f8 --- /dev/null +++ b/designs/jtag/constraints/constraints.tcl @@ -0,0 +1,54 @@ +#========================================================================= +# Design Constraints File +#========================================================================= + +# This constraint sets the target clock period for the chip in +# nanoseconds. Note that the first parameter is the name of the clock +# signal in your verlog design. If you called it something different than +# clk you will need to change this. You should set this constraint +# carefully. If the period is unrealistically small then the tools will +# spend forever trying to meet timing and ultimately fail. If the period +# is too large the tools will have no trouble but you will get a very +# conservative implementation. + +create_clock -name system_clock -period 10.0 [get_ports clk] +create_clock -name test_clock -period 100.0 [get_ports jtag_intf_i.phy_tck] + +set_false_path -from system_clock -to test_clock +set_false_path -from test_clock -to system_clock + +# This constraint sets the load capacitance in picofarads of the +# output pins of your design. + +set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +set_driving_cell -no_design_rule \ + -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# set_input_delay constraints for input ports +# +# - make this non-zero to avoid hold buffers on input-registered designs + +# set_input_delay -clock ${clock_name} [expr ${dc_clock_period}/2.0] [all_inputs] + +# set_output_delay constraints for output ports + +# set_output_delay -clock ${clock_name} 0 [all_outputs] + +# Make all signals limit their fanout + +set_max_fanout 20 $dc_design_name + +# Make all signals meet good slew + +# set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name + +#set_input_transition 1 [all_inputs] +#set_max_transition 10 [all_outputs] + diff --git a/designs/jtag/constraints/outputs/constraints.tcl b/designs/jtag/constraints/outputs/constraints.tcl new file mode 120000 index 00000000..50630c20 --- /dev/null +++ b/designs/jtag/constraints/outputs/constraints.tcl @@ -0,0 +1 @@ +../constraints.tcl \ No newline at end of file diff --git a/designs/jtag/construct-commercial-full.py b/designs/jtag/construct-commercial-full.py new file mode 100644 index 00000000..7134a597 --- /dev/null +++ b/designs/jtag/construct-commercial-full.py @@ -0,0 +1,177 @@ +# Adapted from mflowgen GcdUnit example + +# To select the process, set the DRAGONPHY_PROCESS environment variable +# to either FREEPDK45 or TSMC16 + +import os + +from mflowgen.components import Graph, Step + +def construct(): + + # Get the name of the process to be used from the environment + if 'DRAGONPHY_PROCESS' in os.environ: + DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] + else: + DRAGONPHY_PROCESS = 'FREEPDK45' + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + parameters = { + 'construct_path': __file__, + 'design_name': 'jtag', + 'topographical': True + } + + if DRAGONPHY_PROCESS == 'FREEPDK45': + parameters['adk_name'] = 'freepdk-45nm' + parameters['adk_view'] = 'view-standard' + elif DRAGONPHY_PROCESS == 'TSMC16': + parameters['adk_name'] = 'tsmc16' + parameters['adk_view'] = 'stdview' + else: + raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk(parameters['adk_name']) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step(this_dir + '/rtl') + constraints = Step(this_dir + '/constraints') + dc = Step(this_dir + '/synopsys-dc-synthesis') + + # Default steps + + info = Step( 'info', default=True ) + iflow = Step( 'cadence-innovus-flowsetup', default=True ) + init = Step( 'cadence-innovus-init', default=True ) + power = Step( 'cadence-innovus-power', default=True ) + place = Step( 'cadence-innovus-place', default=True ) + cts = Step( 'cadence-innovus-cts', default=True ) + postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) + route = Step( 'cadence-innovus-route', default=True ) + postroute = Step( 'cadence-innovus-postroute', default=True ) + postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) + signoff = Step( 'cadence-innovus-signoff', default=True ) + genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) + gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) + drc = Step( 'mentor-calibre-drc', default=True ) + lvs = Step( 'mentor-calibre-lvs', default=True ) + debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( constraints ) + g.add_step( dc ) + g.add_step( iflow ) + g.add_step( init ) + g.add_step( power ) + g.add_step( place ) + g.add_step( cts ) + g.add_step( postcts_hold ) + g.add_step( route ) + g.add_step( postroute ) + g.add_step( postroute_hold ) + g.add_step( signoff ) + g.add_step( genlibdb ) + g.add_step( gdsmerge ) + g.add_step( drc ) + g.add_step( lvs ) + g.add_step( debugcalibre ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + # Connect by name + + g.connect_by_name( adk, dc ) + g.connect_by_name( adk, iflow ) + g.connect_by_name( adk, init ) + g.connect_by_name( adk, power ) + g.connect_by_name( adk, place ) + g.connect_by_name( adk, cts ) + g.connect_by_name( adk, postcts_hold ) + g.connect_by_name( adk, route ) + g.connect_by_name( adk, postroute ) + g.connect_by_name( adk, postroute_hold ) + g.connect_by_name( adk, signoff ) + g.connect_by_name( adk, gdsmerge ) + g.connect_by_name( adk, drc ) + g.connect_by_name( adk, lvs ) + + g.connect_by_name( rtl, dc ) + g.connect_by_name( constraints, dc ) + + g.connect_by_name( dc, iflow ) + g.connect_by_name( dc, init ) + g.connect_by_name( dc, power ) + g.connect_by_name( dc, place ) + g.connect_by_name( dc, cts ) + + g.connect_by_name( iflow, init ) + g.connect_by_name( iflow, power ) + g.connect_by_name( iflow, place ) + g.connect_by_name( iflow, cts ) + g.connect_by_name( iflow, postcts_hold ) + g.connect_by_name( iflow, route ) + g.connect_by_name( iflow, postroute ) + g.connect_by_name( iflow, postroute_hold ) + g.connect_by_name( iflow, signoff ) + + g.connect_by_name( init, power ) + g.connect_by_name( power, place ) + g.connect_by_name( place, cts ) + g.connect_by_name( cts, postcts_hold ) + g.connect_by_name( postcts_hold, route ) + g.connect_by_name( route, postroute ) + g.connect_by_name( postroute, postroute_hold ) + g.connect_by_name( postroute_hold, signoff ) + + g.connect_by_name( signoff, genlibdb ) + g.connect_by_name( adk, genlibdb ) + + g.connect_by_name( signoff, gdsmerge ) + + g.connect_by_name( signoff, drc ) + g.connect_by_name( gdsmerge, drc ) + g.connect_by_name( signoff, lvs ) + g.connect_by_name( gdsmerge, lvs ) + + g.connect_by_name( adk, debugcalibre ) + g.connect_by_name( dc, debugcalibre ) + g.connect_by_name( iflow, debugcalibre ) + g.connect_by_name( signoff, debugcalibre ) + g.connect_by_name( drc, debugcalibre ) + g.connect_by_name( lvs, debugcalibre ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g + + +if __name__ == '__main__': + g = construct() +# g.plot() + diff --git a/designs/jtag/rtl/configure.yml b/designs/jtag/rtl/configure.yml new file mode 100644 index 00000000..bba47d90 --- /dev/null +++ b/designs/jtag/rtl/configure.yml @@ -0,0 +1,10 @@ +name: rtl + +commands: + - python gen_rtl.py + +outputs: + - design.v + +parameters: + design_name: None \ No newline at end of file diff --git a/designs/jtag/rtl/gen_rtl.py b/designs/jtag/rtl/gen_rtl.py new file mode 100644 index 00000000..0828f5f9 --- /dev/null +++ b/designs/jtag/rtl/gen_rtl.py @@ -0,0 +1,40 @@ +import os +import re +from pathlib import Path +from dragonphy import * + +TOP_CELL = os.environ.get('design_name', 'jtag') +OUTPUT_FILE = 'design.v' + +def remove_dup(seq): + # fast method to remove duplicates from a list while preserving order + # source: Raymond Hettinger (https://twitter.com/raymondh/status/944125570534621185) + return list(dict.fromkeys(seq)) + +# build up a list of source files +src_files = [] +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/jtag/jtag_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/analog_core/acore_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/mm_cdr/cdr_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/digital_core/dcore_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/sram/sram_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/prbs/prbs_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/weight_manager/wme_debug_intf.sv')) +src_files += get_deps_new_asic(TOP_CELL) +src_files = remove_dup(src_files) + +# generate the output text +output = '' + +for src_file in src_files: + output += f'// Content from file: {src_file}\n' + output += open(src_file, 'r').read() + output += '\n' + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write output text +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + f.write(output) diff --git a/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py b/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py new file mode 100644 index 00000000..c873bdd0 --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py @@ -0,0 +1,67 @@ +#========================================================================= +# assertion_helpers.py +#========================================================================= +# Helper functions for assertions +# +# Author : Christopher Torng +# Date : March 14, 2020 +# + +from glob import glob + +import re + +# percent_clock_gated +# +# Reads the clock-gating report and returns a float representing the +# percentage of registers that are clock gated. +# + +def percent_clock_gated(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the clock-gating percentage, which looks like this: + # + # | Number of Gated registers | 32 (94.12%) | + # + + gate_line = [ l for l in lines if 'Number of Gated registers' in l ][0] + + # Extract the percentage between parentheses + + percentage = float( re.search( r'\((.*?)%\)', gate_line ).group(1) )/100 + + return percentage + +# n_regs +# +# Reads the clock-gating report and returns an integer for the number of +# registers that exist in the design. +# + +def n_regs(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the number of registers, which looks like this: + # + # | Total number of registers | 34 | + # + + regs_line = [ l for l in lines if 'Total number of registers' in l ][0] + + # Extract the number + + regs = int( re.search( r'\|\s*(\d*)\s*\|', regs_line ).group(1) ) + + return regs + + + diff --git a/designs/jtag/synopsys-dc-synthesis/configure.yml b/designs/jtag/synopsys-dc-synthesis/configure.yml new file mode 100644 index 00000000..47a7538e --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/configure.yml @@ -0,0 +1,93 @@ +#========================================================================= +# Synopsys DC Synthesis +#========================================================================= +# Author : Christopher Torng, Yanghui Ou +# Date : June 7, 2019 +# + +name: synopsys-dc-synthesis + +#------------------------------------------------------------------------- +# Inputs and Outputs +#------------------------------------------------------------------------- + +inputs: + - adk + - design.v + - constraints.tcl + - run.saif + +outputs: + - design.v + - design.sdc + - design.namemap + +#------------------------------------------------------------------------- +# Commands +#------------------------------------------------------------------------- + +commands: + - bash run.sh + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +parameters: + clock_period: 1.0 + design_name: undefined + # Path to the design instance in run.saif (e.g., tb/dut) + saif_instance: undefined + flatten_effort: 0 + topographical: True + nthreads: 16 # multithreading available to the tool + +#------------------------------------------------------------------------- +# Debug +#------------------------------------------------------------------------- + +debug: + - export DC_EXIT_AFTER_SETUP=1 + - ln -sf results/*.mapped.ddc debug.ddc + - design_vision-xg -topographical -x "source dc.tcl; read_ddc debug.ddc" + +#------------------------------------------------------------------------- +# Assertions +#------------------------------------------------------------------------- + +preconditions: + + - assert Tool( 'dc_shell-xg-t' ) # tool check + - assert File( 'inputs/adk' ) # must exist + - assert File( 'inputs/design.v' ) # must exist + - assert File( 'inputs/constraints.tcl' ) # must exist + +postconditions: + + - assert File( 'outputs/design.v' ) # must exist + - assert File( 'outputs/design.sdc' ) # must exist + + # Basic error checking + + - assert 'error' not in File( 'logs/dc.log' ) + - assert 'Unresolved references' not in File( 'logs/dc.log' ) + - assert 'Unable to resolve' not in File( 'logs/dc.log' ) + + # If GTECH is found, that means this design was not mapped to a + # technology library and is still in DC's generic representation + + - assert 'GTECH' not in File( 'outputs/design.v' ) + + # Sanity check that there is a clock in the constraints + + - assert 'create_clock' in File( 'outputs/design.sdc' ) + + # Check that at least N% of registers were clock-gated + # TODO add this check back + +# - | +# from assertion_helpers import percent_clock_gated, n_regs +# if n_regs() > 10: +# assert percent_clock_gated() > 0.50 + + diff --git a/designs/jtag/synopsys-dc-synthesis/dc.tcl b/designs/jtag/synopsys-dc-synthesis/dc.tcl new file mode 100644 index 00000000..19b255e8 --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/dc.tcl @@ -0,0 +1,598 @@ +#========================================================================= +# dc.tcl +#========================================================================= +# We use Synopsys DC to synthesize a single RTL netlist file into gates. +# +# This script has evolved over time inspired by (1) the Synopsys reference +# methodology scripts that are released year after year on Solvnet, (2) +# synthesis scripts from other research groups, as well as (3) reference +# papers from user groups online. +# +# If you make a major update to this script (e.g., update inspired by the +# latest version of the Synopsys reference methodology), please list the +# changeset in the version history below. +# +# Author : Christopher Torng +# Date : September 30, 2018 +# +#------------------------------------------------------------------------- +# Version History +#------------------------------------------------------------------------- +# +# - 09/30/2018 -- Christopher Torng +# - Clean slate DC scripts +# - We are now independent of the Synopsys Reference Methodology +# - Version of Synopsys DC running "% dc_shell -v": +# dc_shell version - M-2016.12 +# dc_shell build date - Nov 21, 2016 +# +# - 04/08/2018 -- Christopher Torng +# - Our original version was based on the Synopsys reference +# methodology (D-2010.03-SP1) +# - Big update now inspired by the Celerity Synopsys DC scripts, which +# were in turn also based on the Synopsys reference methodology +# (L-2016.03-SP2) +# +#------------------------------------------------------------------------- + +#------------------------------------------------------------------------- +# Designer interface +#------------------------------------------------------------------------- +# Source the designer interface script, which sets up variables from the +# build system, sets up ASIC design kit variables, etc. + +source -echo -verbose designer_interface.tcl + +#------------------------------------------------------------------------- +# Pre-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_pre_synthesis_plugin]]} { + puts "Info: Reading pre-synth plugin: $dc_pre_synthesis_plugin" + source -echo -verbose $dc_pre_synthesis_plugin +} + +#------------------------------------------------------------------------- +# Setup +#------------------------------------------------------------------------- + +# Set up variables for this specific ASIC design kit + +set SYNOPSYS_TOOL "dc-syn" +source -echo -verbose $dc_adk_tcl + +# Multicore support -- watch how many licenses we have! + +set_host_options -max_cores $dc_num_cores + +# Set up alib caching for faster consecutive runs + +set_app_var alib_library_analysis_path $dc_alib_dir + +# Set up tracking for Synopsys Formality + +set_svf ${dc_results_dir}/${dc_design_name}.mapped.svf + +# Set up search path for libraries and design files + +set_app_var search_path ". $dc_additional_search_path $search_path" + +# Important app vars +# +# - target_library -- DC maps the design to gates in this library (db) +# - synthetic_library -- DesignWare library (sldb) +# - link_library -- Libraries for any other design references (e.g., +# SRAMs, hierarchical blocks, macros, IO libs) (db) + +set_app_var target_library $dc_target_libraries +set_app_var synthetic_library dw_foundation.sldb +set_app_var link_library [join " + * + $target_library + $dc_extra_link_libraries + $synthetic_library + "] + + +# SAIF mapping. + # +saif_map -start + +# Create Milkyway library +# +# By default, Milkyway libraries only have 180 or so layers available to +# use (255 total, but some are reserved). The extend_mw_layers command +# expands the Milkyway library to accommodate up to 4095 layers. + +# Only create new Milkyway design library if it doesn't already exist + +set milkyway_library ${dc_design_name}_lib + +if {![file isdirectory $milkyway_library ]} { + + # Create a new Milkyway library + + extend_mw_layers + create_mw_lib -technology $dc_milkyway_tf \ + -mw_reference_library $dc_milkyway_ref_libraries \ + $milkyway_library + +} else { + + # Reuse existing Milkyway library, but ensure that it is consistent with + # the provided reference Milkyway libraries. + + set_mw_lib_reference $milkyway_library \ + -mw_reference_library $dc_milkyway_ref_libraries + +} + +open_mw_lib $milkyway_library + +# Set up TLU plus (if the files exist) + +if { $dc_topographical == True } { + if {[file exists [which $dc_tluplus_max]]} { + set_tlu_plus_files -max_tluplus $dc_tluplus_max \ + -min_tluplus $dc_tluplus_min \ + -tech2itf_map $dc_tluplus_map + + check_tlu_plus_files + } +} + +# Avoiding X-propagation for synchronous reset DFFs +# +# There are two key variables that help avoid X-propagation for +# synchronous reset DFFs: +# +# - set hdlin_ff_always_sync_set_reset true +# +# - Tells DC to use every constant 0 loaded into a DFF with a clock +# for synchronous reset, and every constant 1 loaded into a DFF with a +# clock for synchronous set +# +# - set compile_seqmap_honor_sync_set_reset true +# +# - Tells DC to preserve synchronous reset or preset logic close to +# the flip-flop +# +# So the hdlin variable first tells DC to treat resets as synchronous, and +# the compile variable tells DC that for all these synchronous reset DFFs, +# keep the logic simple and close to the DFF to avoid X-propagation. The +# hdlin variable applies to the analyze step when we read in the RTL, so +# it must be set before we read in the Verilog. The second variable +# applies to compile and must be set before we run compile_ultra. +# +# Note: Instead of setting the hdlin_ff_always_sync_set_reset variable to +# true, you can specifically tell DC about a particular DFF reset using +# the //synopsys sync_set_reset "reset, int_reset" pragma. +# +# By default, the hdlin_ff_always_async_set_reset variable is set to true, +# and the hdlin_ff_always_sync_set_reset variable is set to false. + +set hdlin_ff_always_sync_set_reset true +set compile_seqmap_honor_sync_set_reset true + +# Remove new variable info messages from the end of the log file + +set_app_var sh_new_variable_message false + +# Corners +# +# If we want to do corners in DC, then we would use this command to set +# the min and max libraries: + +#set_min_library $max_library -min_version $min_library + +# SAIF Name Mapping Database + +#if { ${VINAME} != "NONE" } { +# saif_map -start +#} + +# Hook to drop into interactive Design Compiler shell after setup + +if {[info exists ::env(DC_EXIT_AFTER_SETUP)]} { return } + +#------------------------------------------------------------------------- +# Read design +#------------------------------------------------------------------------- + +# Check libraries + +check_library > $dc_reports_dir/${dc_design_name}.check_library.rpt + +# The first "WORK" is a reserved word for Design Compiler. The value for +# the -path option is customizable. + +define_design_lib WORK -path ${dc_results_dir}/WORK + +# Analyze the RTL source files +# +# Source the read design plugin if it exists. Otherwise, we do a default +# read and elaborate the design. + +if {[file exists [which $dc_read_design_plugin]]} { + puts "Info: Reading read design plugin: $dc_read_design_plugin" + source -echo -verbose $dc_read_design_plugin +} else { + # Since no read design plugin exists, we do a default read + if { ![analyze -format sverilog $dc_rtl_handoff] } { exit 1 } + if {[file exists [which setup-design-params.txt]]} { + elaborate $dc_design_name -file_parameters setup-design-params.txt + rename_design $dc_design_name* $dc_design_name + } else { + elaborate $dc_design_name + } +} + +current_design $dc_design_name +link + +#------------------------------------------------------------------------- +# Write out useful files +#------------------------------------------------------------------------- + +# This ddc can be used as a checkpoint to load up to the current state + +write -hierarchy -format ddc \ + -output ${dc_results_dir}/${dc_design_name}.elab.ddc + +# This Verilog is useful to double-check the netlist that dc will use for +# mapping + +write -hierarchy -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.elab.v + +#------------------------------------------------------------------------- +# Apply design constraints +#------------------------------------------------------------------------- + +# Apply logical design constraints + +puts "Info: Reading constraints file plugin: $dc_constraints_plugin" + +source -echo -verbose $dc_constraints_plugin + +# The check_timing command checks for constraint problems such as +# undefined clocking, undefined input arrival times, and undefined output +# constraints. These constraint problems could cause you to overlook +# timing violations. For this reason, the check_timing command is +# recommended whenever you apply new constraints such as clock +# definitions, I/O delays, or timing exceptions. + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.premapped.checktiming.rpt \ + {check_timing} + +# Path groups + +set ports_clock_root [filter_collection \ + [get_attribute [get_clocks] sources] \ + object_class==port] + +group_path -name REGOUT \ + -to [all_outputs] + +group_path -name REGIN \ + -from [remove_from_collection [all_inputs] $ports_clock_root] + +group_path -name FEEDTHROUGH \ + -from [remove_from_collection [all_inputs] $ports_clock_root] \ + -to [all_outputs] + +# Apply physical design constraints +# +# Set the minimum and maximum routing layers used in DC topographical mode + +if { $dc_topographical == True } { + set_ignored_layers -min_routing_layer $ADK_MIN_ROUTING_LAYER_DC + set_ignored_layers -max_routing_layer $ADK_MAX_ROUTING_LAYER_DC + + report_ignored_layers +} + +#------------------------------------------------------------------------- +# Additional options +#------------------------------------------------------------------------- + +# Replace special characters with non-special ones before writing out the +# synthesized netlist (e.g., "\bus[5]" -> "bus_5_") + +set_app_var verilogout_no_tri true + +# Prevent assignment statements in the Verilog netlist. + +set_fix_multiple_port_nets -all -buffer_constants + +# Choose design flattening options + +if {[info exists DC_FLATTEN_EFFORT]} { + set dc_flatten_effort $DC_FLATTEN_EFFORT + if {"$dc_flatten_effort" == ""} { + set dc_flatten_effort 0 + } +} else { + set dc_flatten_effort 0 +} + +puts "Info: Flattening effort (DC_FLATTEN_EFFORT) = $dc_flatten_effort" + +set compile_ultra_options "" +if {$dc_flatten_effort == 0} { + puts "Info: All design hierarchies are preserved unless otherwise specified." + set_app_var compile_ultra_ungroup_dw false + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 1} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is disabled." + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 2} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + append compile_ultra_options "" + +} elseif {$dc_flatten_effort == 3} { + set ungroup_start_level 2 + ungroup -start_level $ungroup_start_level -all -flatten + puts "Info: All hierarchical cells starting from level $ungroup_start_level are flattened." + puts "Info: Unconditionally ungroup the DesignWare cells." + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + set_app_var compile_ultra_ungroup_dw true + append compile_ultra_options "" + +} else { + puts "Info: Unrecognizable DC_FLATTEN_EFFORT value: $dc_flatten_effort" + exit +} + +# Enable or disable clock gating + +if {[info exists DC_GATE_CLOCK]} { + set dc_gate_clock $DC_GATE_CLOCK + if {"$dc_gate_clock" == ""} { + set dc_gate_clock true + } +} else { + set dc_gate_clock true +} + +puts "Info: Clock gating (DC_GATE_CLOCK) = $dc_gate_clock" + +if {$dc_gate_clock == true} { + append compile_ultra_options " -gate_clock" +} + +# Check design for consistency +# +# Most problems with synthesis will be caught in this report + +check_design -summary +check_design \ + > ${dc_reports_dir}/${dc_design_name}.premapped.checkdesign.rpt + +#------------------------------------------------------------------------- +# Compile +#------------------------------------------------------------------------- + +puts "Info: DC compile_ultra options = $compile_ultra_options" + +eval "compile_ultra $compile_ultra_options" + +# High-effort area optimization +# +# This command was introduced in I-2013.12 and performs monotonic +# gate-to-gate optimization on mapped designs. It is supposed to improve +# area without degrading timing or leakage. + +# Skip this step by setting the DC_SKIP_OPTIMIZE_NETLIST variable in the +# pre-synthesis plugin + +if {!([info exists DC_SKIP_OPTIMIZE_NETLIST] && $DC_SKIP_OPTIMIZE_NETLIST)} { + optimize_netlist -area +} + +# Check design + +check_design -summary +check_design > ${dc_reports_dir}/${dc_design_name}.mapped.checkdesign.rpt + +# Write the .namemap file for the Energy analysis + +if {[file exists "inputs/run.saif" ]} { + saif_map \ + -create_map \ + -input "inputs/run.saif" \ + -source_instance ${dc_saif_instance} +} + +#------------------------------------------------------------------------- +# Write out the design +#------------------------------------------------------------------------- + +# Synopsys Formality + +set_svf -off + +# Use naming rules to preserve structs + +define_name_rules verilog -preserve_struct_ports + +report_names \ + -rules verilog \ + > ${dc_reports_dir}/${dc_design_name}.mapped.naming.rpt + +change_names -rules verilog -hierarchy + +# Write out files + +write -format ddc \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.ddc + +write -format verilog \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.v + +write -format svsim \ + -output ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v + +# Dump the mapped.v and svwrapper.v into one svsim.v file to make it +# easier to include a single file for gate-level simulation. The svwrapper +# matches the interface of the original RTL even if using SystemVerilog +# features (e.g., array of arrays, uses parameters, etc.). + +sh cat ${dc_results_dir}/${dc_design_name}.mapped.v \ + ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v \ + > ${dc_results_dir}/${dc_design_name}.mapped.svsim.v + +# Write top-level verilog view needed for block instantiation + +write \ + -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.mapped.top.v + +# Floorplan + +if { $dc_topographical == True } { + write_floorplan -all ${dc_results_dir}/${dc_design_name}.mapped.fp +} + +# Parasitics + +write_parasitics -output ${dc_results_dir}/${dc_design_name}.mapped.spef + +# SDF for back-annotated gate-level simulation + +write_sdf ${dc_results_dir}/${dc_design_name}.mapped.sdf + +# Do not write out net RC info into SDC + +set_app_var write_sdc_output_lumped_net_capacitance false +set_app_var write_sdc_output_net_resistance false + +# SDC constraints + +write_sdc -nosplit ${dc_results_dir}/${dc_design_name}.mapped.sdc + +#------------------------------------------------------------------------- +# Final reports +#------------------------------------------------------------------------- + +# Report units + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.mapped.units.rpt \ + {report_units} + +# Report QOR + +report_qor > ${dc_reports_dir}/${dc_design_name}.mapped.qor.rpt + +# Report timing + +report_clock_timing \ + -type summary \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.clock.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type max \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.setup.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type min \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.hold.rpt + +# Report constraints + +report_constraint \ + -nosplit \ + -verbose \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.rpt + +report_constraint \ + -nosplit \ + -verbose \ + -all_violators \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.violators.rpt + +report_timing_requirements \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.requirements.rpt + +# Report area + +report_area \ + -hierarchy \ + -physical \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.area.rpt + +# Report references and resources + +report_reference \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.reference.rpt + +report_resources \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.resources.rpt + +# Report power +# +# Use SAIF file for power analysis +if {[file exists "inputs/run.saif" ]} { + read_saif \ + -map_names \ + -input "inputs/run.saif" \ + -instance_name $dc_saif_instance \ + -verbose + + report_saif \ + -hier \ + -annotated_flag \ + -rtl_saif \ + > ${dc_reports_dir}/${dc_design_name}.mapped.saif.rpt + + saif_map \ + -type ptpx \ + -write_map \ + ${dc_reports_dir}/${dc_design_name}.namemap +} + +report_power \ + -nosplit \ + -hier \ + > ${dc_reports_dir}/${dc_design_name}.mapped.power.rpt + +report_clock_gating \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.clock_gating.rpt + +#------------------------------------------------------------------------- +# Post-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_post_synthesis_plugin]]} { + puts "Info: Reading post-synthesis plugin: $dc_post_synthesis_plugin" + source -echo -verbose $dc_post_synthesis_plugin +} + +exit + diff --git a/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl b/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl new file mode 100644 index 00000000..0996d017 --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl @@ -0,0 +1,90 @@ +#========================================================================= +# designer_interface.tcl +#========================================================================= +# The designer_interface.tcl file is the first script run by Design +# Compiler (see the top of dc.tcl). It is the interface that connects the +# dc-synthesis scripts with the following: +# +# - Build system parameters +# - Build system inputs +# - ASIC design kit +# - Plugin scripts +# +# Author : Christopher Torng +# Date : April 8, 2018 + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +set dc_design_name $::env(design_name) +set dc_saif_instance $::env(saif_instance) +set dc_clock_period $::env(clock_period) +set dc_flatten_effort $::env(flatten_effort) +set dc_topographical $::env(topographical) + +#------------------------------------------------------------------------- +# Inputs +#------------------------------------------------------------------------- + +set dc_rtl_handoff inputs/design.v +set adk_dir inputs/adk + +# Extra libraries +# +# The glob below will capture any libraries collected by the build system +# (e.g., SRAM libraries) generated from steps that synthesis depends on. +# +# To add more link libraries (e.g., IO cells, hierarchical blocks), append +# to the "dc_extra_link_libraries" variable in the pre-synthesis plugin +# like this: +# +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +set dc_extra_link_libraries [join " + [glob -nocomplain inputs/*.db] + [glob -nocomplain inputs/adk/*.db] + "] + +#------------------------------------------------------------------------- +# Interface to the ASIC design kit +#------------------------------------------------------------------------- + +set dc_milkyway_ref_libraries $adk_dir/stdcells.mwlib +set dc_milkyway_tf $adk_dir/rtk-tech.tf +set dc_tluplus_map $adk_dir/rtk-tluplus.map +set dc_tluplus_max $adk_dir/rtk-max.tluplus +set dc_tluplus_min $adk_dir/rtk-min.tluplus +set dc_adk_tcl $adk_dir/adk.tcl +set dc_target_libraries stdcells.db + +# Extra libraries + +set dc_additional_search_path $adk_dir + +#------------------------------------------------------------------------- +# Directories +#------------------------------------------------------------------------- + +set dc_flow_dir . +set dc_plugins_dir . +set dc_logs_dir logs +set dc_reports_dir reports +set dc_results_dir results +set dc_alib_dir alib + +#------------------------------------------------------------------------- +# Interface to plugins +#------------------------------------------------------------------------- + +set dc_pre_synthesis_plugin pre_synth.tcl +set dc_read_design_plugin read_design.tcl +set dc_constraints_plugin inputs/constraints.tcl +set dc_post_synthesis_plugin post_synth.tcl + + diff --git a/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl b/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl new file mode 100644 index 00000000..e5cab31f --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl @@ -0,0 +1,49 @@ +#========================================================================= +# pre_synth.tcl +#========================================================================= +# This plug-in script is called before synthesis +# +# Author : Christopher Torng +# Date : May 14, 2018 + +# Number of cores for multicore optimization + +set dc_num_cores $env(nthreads) + +# Add more link libraries (e.g., IO cells, hierarchical blocks) + +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +# Enable additional area optimizations (skip false = enable optimizations) + +set DC_SKIP_OPTIMIZE_NETLIST true + +# Enable clock-gating + +set DC_GATE_CLOCK true + +# DC flatten effort +# +# - Effort 0: No auto-ungrouping / boundary optimizations (strict hierarchy) +# - Effort 1: No auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 2: Enable auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 3: Everything ungrouped + level param for how deep to ungroup +# +# Note that even with boundary optimizations off, DC will still propagate +# constants across the boundary, although this can be disabled with a +# variable if we really wanted to disable it. + +set DC_FLATTEN_EFFORT $env(flatten_effort) + +# When boundary optimizations are off, set this variable to true to still +# allow unconnected registers to be removed. + +set compile_optimize_unloaded_seq_logic_with_no_bound_opt true + diff --git a/designs/jtag/synopsys-dc-synthesis/run.sh b/designs/jtag/synopsys-dc-synthesis/run.sh new file mode 100755 index 00000000..ae57c1f0 --- /dev/null +++ b/designs/jtag/synopsys-dc-synthesis/run.sh @@ -0,0 +1,114 @@ +#! /usr/bin/env bash +#========================================================================= +# run.sh +#========================================================================= +# Author : Christopher Torng +# Date : June 2, 2019 +# + +# Print commands during execution + +set -x + +# DC shell + +dc_exec='dc_shell-xg-t -64bit' + +# Build directories + +rm -rf ./logs +rm -rf ./reports +rm -rf ./results + +mkdir -p logs +mkdir -p reports +mkdir -p results + +# alib +# +# Design Compiler caches analyzed libraries to improve performance using +# ".alib" directories. The alib takes a while to generate but is reused on +# subsequent runs. It is useful to store a centralized copy of the alib to +# avoid re-generating the alib (usually only several minutes but can be +# annoying) on every new clone of the ASIC repo. +# +# However, if DC sees a .db that does not have an associated .alib it will +# try to automatically create one. This is not usually a problem when +# students just use standard cells, but if a student is trying to use +# SRAMs, then they will be using new .db files that DC has not seen yet. +# The problem is that students do not have write permissions to the +# centralized copy of the alib in the ADK. +# +# The solution we use is to create a local alib directory in the current +# build directory with _per-file_ symlinks to the centralized alib (and +# with the same directory hierarchy). This allows students to reuse the +# centralized copies of the alib files while allowing new alibs (e.g., for +# SRAMs) to be generated locally. +# +# This is possible because the alibs are stored in a directory that holds +# a ".db.alib" file for each db file: +# +# - alib +# - alib-52 +# - iocells.db.alib +# - stdcells.db.alib +# +# This new alib directory just needs to contain symlinks to each saved +# alib in the ADK. This can be done simply by using "cp -srf" of the ADK +# alib to the build directory, which generates symbolic links to each file +# instead of copying. This way, the student can access the master copy of +# the saved alibs in the ADK, and if there are any additional db's +# specified, their alibs will be saved in the local build directory. + +rm -rf alib +mkdir -p alib + +cp -srf $PWD/inputs/adk/alib/* alib || true + +# Run the synthesis script + +if [ "x$topographical" == "xTrue" ]; then + opt_topographical='-topographical_mode' +else + opt_topographical= +fi + +$dc_exec $opt_topographical -f dc.tcl -output_log_file logs/dc.log || exit 1 + +# Compress the spef file + +cd results +gzip *.mapped.spef +cd .. + +# Set up the outputs + +mkdir -p outputs && cd outputs + +ln -sf ../results/*.mapped.v design.v +ln -sf ../results/*.mapped.sdc design.sdc +ln -sf ../results/*.mapped.spef.gz design.spef.gz +ln -sf ../reports/*.namemap design.namemap + +cd .. + +# Grep for failure messages + +grep --color "^Error" logs/dc.log || true +grep --color -B 3 "*** Presto compilation terminated" logs/dc.log || true +grep --color "unresolved references." logs/dc.log || true + +# ELAB-405 +# +# When using a Verilog generation tool, there may be a +# generation/translation mistake that defines a net twice. This will give +# a message like this: +# +# Warning: ./inputs/design.v:2473: Net mul__recv__msg__opd_b[0] or a +# directly connected net may be driven by more than one process or block. +# (ELAB-405) +# +# This is usually a bad sign.. +# + +grep --color "ELAB-405" logs/dc.log || true diff --git a/designs/weight_manager/.mflowgen.yml b/designs/weight_manager/.mflowgen.yml new file mode 100644 index 00000000..189d498a --- /dev/null +++ b/designs/weight_manager/.mflowgen.yml @@ -0,0 +1 @@ +construct: construct-commercial-full.py diff --git a/designs/weight_manager/constraints/configure.yml b/designs/weight_manager/constraints/configure.yml new file mode 100644 index 00000000..e5992188 --- /dev/null +++ b/designs/weight_manager/constraints/configure.yml @@ -0,0 +1,23 @@ +#========================================================================= +# Constraints +#========================================================================= +# Author : Alex Carsello +# Date : Nov 1, 2019 +# + +name: constraints + +#------------------------------------------------------------------------- +# Inputs and Outputs +#------------------------------------------------------------------------- + +outputs: + - constraints.tcl + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +parameters: + clock_period: 1.0 + design_name: undefined diff --git a/designs/weight_manager/constraints/constraints.tcl b/designs/weight_manager/constraints/constraints.tcl new file mode 100644 index 00000000..18c009f3 --- /dev/null +++ b/designs/weight_manager/constraints/constraints.tcl @@ -0,0 +1,55 @@ +#========================================================================= +# Design Constraints File +#========================================================================= + +# This constraint sets the target clock period for the chip in +# nanoseconds. Note that the first parameter is the name of the clock +# signal in your verlog design. If you called it something different than +# clk you will need to change this. You should set this constraint +# carefully. If the period is unrealistically small then the tools will +# spend forever trying to meet timing and ultimately fail. If the period +# is too large the tools will have no trouble but you will get a very +# conservative implementation. + +set clock_net clk +set clock_name ideal_clock + +create_clock -name ${clock_name} \ + -period ${dc_clock_period} \ + [get_ports ${clock_net}] + +# This constraint sets the load capacitance in picofarads of the +# output pins of your design. + +set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +set_driving_cell -no_design_rule \ + -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# set_input_delay constraints for input ports +# +# - make this non-zero to avoid hold buffers on input-registered designs + +set_input_delay -clock ${clock_name} [expr ${dc_clock_period}/2.0] [all_inputs] + +# set_output_delay constraints for output ports + +set_output_delay -clock ${clock_name} 0 [all_outputs] + +# Make all signals limit their fanout + +set_max_fanout 20 $dc_design_name + +# Make all signals meet good slew + +set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name + +#set_input_transition 1 [all_inputs] +#set_max_transition 10 [all_outputs] + diff --git a/designs/weight_manager/constraints/outputs/constraints.tcl b/designs/weight_manager/constraints/outputs/constraints.tcl new file mode 120000 index 00000000..50630c20 --- /dev/null +++ b/designs/weight_manager/constraints/outputs/constraints.tcl @@ -0,0 +1 @@ +../constraints.tcl \ No newline at end of file diff --git a/designs/weight_manager/construct-commercial-full.py b/designs/weight_manager/construct-commercial-full.py new file mode 100644 index 00000000..d481881c --- /dev/null +++ b/designs/weight_manager/construct-commercial-full.py @@ -0,0 +1,179 @@ +# Adapted from mflowgen GcdUnit example + +# To select the process, set the DRAGONPHY_PROCESS environment variable +# to either FREEPDK45 or TSMC16 + +import os + +from mflowgen.components import Graph, Step + +def construct(): + + # Get the name of the process to be used from the environment + if 'DRAGONPHY_PROCESS' in os.environ: + DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] + else: + DRAGONPHY_PROCESS = 'FREEPDK45' + + g = Graph() + + #----------------------------------------------------------------------- + # Parameters + #----------------------------------------------------------------------- + + parameters = { + 'construct_path': __file__, + 'design_name': 'weight_manager', + 'topographical': True + } + + if DRAGONPHY_PROCESS == 'FREEPDK45': + parameters['adk_name'] = 'freepdk-45nm' + parameters['adk_view'] = 'view-standard' + parameters['clock_period'] = 7.0 + elif DRAGONPHY_PROCESS == 'TSMC16': + parameters['adk_name'] = 'tsmc16' + parameters['adk_view'] = 'stdview' + parameters['clock_period'] = 0.7 + else: + raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') + + #----------------------------------------------------------------------- + # Create nodes + #----------------------------------------------------------------------- + + this_dir = os.path.dirname( os.path.abspath( __file__ ) ) + + # ADK step + + g.set_adk(parameters['adk_name']) + adk = g.get_adk_step() + + # Custom steps + + rtl = Step(this_dir + '/rtl') + constraints = Step(this_dir + '/constraints') + dc = Step(this_dir + '/synopsys-dc-synthesis') + + # Default steps + + info = Step( 'info', default=True ) + iflow = Step( 'cadence-innovus-flowsetup', default=True ) + init = Step( 'cadence-innovus-init', default=True ) + power = Step( 'cadence-innovus-power', default=True ) + place = Step( 'cadence-innovus-place', default=True ) + cts = Step( 'cadence-innovus-cts', default=True ) + postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) + route = Step( 'cadence-innovus-route', default=True ) + postroute = Step( 'cadence-innovus-postroute', default=True ) + postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) + signoff = Step( 'cadence-innovus-signoff', default=True ) + genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) + gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) + drc = Step( 'mentor-calibre-drc', default=True ) + lvs = Step( 'mentor-calibre-lvs', default=True ) + debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + + #----------------------------------------------------------------------- + # Graph -- Add nodes + #----------------------------------------------------------------------- + + g.add_step( info ) + g.add_step( rtl ) + g.add_step( constraints ) + g.add_step( dc ) + g.add_step( iflow ) + g.add_step( init ) + g.add_step( power ) + g.add_step( place ) + g.add_step( cts ) + g.add_step( postcts_hold ) + g.add_step( route ) + g.add_step( postroute ) + g.add_step( postroute_hold ) + g.add_step( signoff ) + g.add_step( genlibdb ) + g.add_step( gdsmerge ) + g.add_step( drc ) + g.add_step( lvs ) + g.add_step( debugcalibre ) + + #----------------------------------------------------------------------- + # Graph -- Add edges + #----------------------------------------------------------------------- + + # Connect by name + + g.connect_by_name( adk, dc ) + g.connect_by_name( adk, iflow ) + g.connect_by_name( adk, init ) + g.connect_by_name( adk, power ) + g.connect_by_name( adk, place ) + g.connect_by_name( adk, cts ) + g.connect_by_name( adk, postcts_hold ) + g.connect_by_name( adk, route ) + g.connect_by_name( adk, postroute ) + g.connect_by_name( adk, postroute_hold ) + g.connect_by_name( adk, signoff ) + g.connect_by_name( adk, gdsmerge ) + g.connect_by_name( adk, drc ) + g.connect_by_name( adk, lvs ) + + g.connect_by_name( rtl, dc ) + g.connect_by_name( constraints, dc ) + + g.connect_by_name( dc, iflow ) + g.connect_by_name( dc, init ) + g.connect_by_name( dc, power ) + g.connect_by_name( dc, place ) + g.connect_by_name( dc, cts ) + + g.connect_by_name( iflow, init ) + g.connect_by_name( iflow, power ) + g.connect_by_name( iflow, place ) + g.connect_by_name( iflow, cts ) + g.connect_by_name( iflow, postcts_hold ) + g.connect_by_name( iflow, route ) + g.connect_by_name( iflow, postroute ) + g.connect_by_name( iflow, postroute_hold ) + g.connect_by_name( iflow, signoff ) + + g.connect_by_name( init, power ) + g.connect_by_name( power, place ) + g.connect_by_name( place, cts ) + g.connect_by_name( cts, postcts_hold ) + g.connect_by_name( postcts_hold, route ) + g.connect_by_name( route, postroute ) + g.connect_by_name( postroute, postroute_hold ) + g.connect_by_name( postroute_hold, signoff ) + + g.connect_by_name( signoff, genlibdb ) + g.connect_by_name( adk, genlibdb ) + + g.connect_by_name( signoff, gdsmerge ) + + g.connect_by_name( signoff, drc ) + g.connect_by_name( gdsmerge, drc ) + g.connect_by_name( signoff, lvs ) + g.connect_by_name( gdsmerge, lvs ) + + g.connect_by_name( adk, debugcalibre ) + g.connect_by_name( dc, debugcalibre ) + g.connect_by_name( iflow, debugcalibre ) + g.connect_by_name( signoff, debugcalibre ) + g.connect_by_name( drc, debugcalibre ) + g.connect_by_name( lvs, debugcalibre ) + + #----------------------------------------------------------------------- + # Parameterize + #----------------------------------------------------------------------- + + g.update_params( parameters ) + + return g + + +if __name__ == '__main__': + g = construct() +# g.plot() + diff --git a/designs/weight_manager/rtl/configure.yml b/designs/weight_manager/rtl/configure.yml new file mode 100644 index 00000000..bba47d90 --- /dev/null +++ b/designs/weight_manager/rtl/configure.yml @@ -0,0 +1,10 @@ +name: rtl + +commands: + - python gen_rtl.py + +outputs: + - design.v + +parameters: + design_name: None \ No newline at end of file diff --git a/designs/weight_manager/rtl/gen_rtl.py b/designs/weight_manager/rtl/gen_rtl.py new file mode 100644 index 00000000..4bf4f7ca --- /dev/null +++ b/designs/weight_manager/rtl/gen_rtl.py @@ -0,0 +1,27 @@ +import os +import re +from pathlib import Path +from dragonphy import * + +TOP_CELL = os.environ.get('design_name', 'weight_manager') +OUTPUT_FILE = 'design.v' + +# build up a list of source files +src_files = [] +src_files += get_deps_new_asic(TOP_CELL) + +# generate the output text +output = '' + +for src_file in src_files: + output += f'// Content from file: {src_file}\n' + output += open(src_file, 'r').read() + output += '\n' + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write output text +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + f.write(output) diff --git a/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py b/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py new file mode 100644 index 00000000..c873bdd0 --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py @@ -0,0 +1,67 @@ +#========================================================================= +# assertion_helpers.py +#========================================================================= +# Helper functions for assertions +# +# Author : Christopher Torng +# Date : March 14, 2020 +# + +from glob import glob + +import re + +# percent_clock_gated +# +# Reads the clock-gating report and returns a float representing the +# percentage of registers that are clock gated. +# + +def percent_clock_gated(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the clock-gating percentage, which looks like this: + # + # | Number of Gated registers | 32 (94.12%) | + # + + gate_line = [ l for l in lines if 'Number of Gated registers' in l ][0] + + # Extract the percentage between parentheses + + percentage = float( re.search( r'\((.*?)%\)', gate_line ).group(1) )/100 + + return percentage + +# n_regs +# +# Reads the clock-gating report and returns an integer for the number of +# registers that exist in the design. +# + +def n_regs(): + + # Read the clock-gating report + + with open( glob('reports/*clock_gating.rpt')[0] ) as fd: + lines = fd.readlines() + + # Get the line with the number of registers, which looks like this: + # + # | Total number of registers | 34 | + # + + regs_line = [ l for l in lines if 'Total number of registers' in l ][0] + + # Extract the number + + regs = int( re.search( r'\|\s*(\d*)\s*\|', regs_line ).group(1) ) + + return regs + + + diff --git a/designs/weight_manager/synopsys-dc-synthesis/configure.yml b/designs/weight_manager/synopsys-dc-synthesis/configure.yml new file mode 100644 index 00000000..47a7538e --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/configure.yml @@ -0,0 +1,93 @@ +#========================================================================= +# Synopsys DC Synthesis +#========================================================================= +# Author : Christopher Torng, Yanghui Ou +# Date : June 7, 2019 +# + +name: synopsys-dc-synthesis + +#------------------------------------------------------------------------- +# Inputs and Outputs +#------------------------------------------------------------------------- + +inputs: + - adk + - design.v + - constraints.tcl + - run.saif + +outputs: + - design.v + - design.sdc + - design.namemap + +#------------------------------------------------------------------------- +# Commands +#------------------------------------------------------------------------- + +commands: + - bash run.sh + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +parameters: + clock_period: 1.0 + design_name: undefined + # Path to the design instance in run.saif (e.g., tb/dut) + saif_instance: undefined + flatten_effort: 0 + topographical: True + nthreads: 16 # multithreading available to the tool + +#------------------------------------------------------------------------- +# Debug +#------------------------------------------------------------------------- + +debug: + - export DC_EXIT_AFTER_SETUP=1 + - ln -sf results/*.mapped.ddc debug.ddc + - design_vision-xg -topographical -x "source dc.tcl; read_ddc debug.ddc" + +#------------------------------------------------------------------------- +# Assertions +#------------------------------------------------------------------------- + +preconditions: + + - assert Tool( 'dc_shell-xg-t' ) # tool check + - assert File( 'inputs/adk' ) # must exist + - assert File( 'inputs/design.v' ) # must exist + - assert File( 'inputs/constraints.tcl' ) # must exist + +postconditions: + + - assert File( 'outputs/design.v' ) # must exist + - assert File( 'outputs/design.sdc' ) # must exist + + # Basic error checking + + - assert 'error' not in File( 'logs/dc.log' ) + - assert 'Unresolved references' not in File( 'logs/dc.log' ) + - assert 'Unable to resolve' not in File( 'logs/dc.log' ) + + # If GTECH is found, that means this design was not mapped to a + # technology library and is still in DC's generic representation + + - assert 'GTECH' not in File( 'outputs/design.v' ) + + # Sanity check that there is a clock in the constraints + + - assert 'create_clock' in File( 'outputs/design.sdc' ) + + # Check that at least N% of registers were clock-gated + # TODO add this check back + +# - | +# from assertion_helpers import percent_clock_gated, n_regs +# if n_regs() > 10: +# assert percent_clock_gated() > 0.50 + + diff --git a/designs/weight_manager/synopsys-dc-synthesis/dc.tcl b/designs/weight_manager/synopsys-dc-synthesis/dc.tcl new file mode 100644 index 00000000..19b255e8 --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/dc.tcl @@ -0,0 +1,598 @@ +#========================================================================= +# dc.tcl +#========================================================================= +# We use Synopsys DC to synthesize a single RTL netlist file into gates. +# +# This script has evolved over time inspired by (1) the Synopsys reference +# methodology scripts that are released year after year on Solvnet, (2) +# synthesis scripts from other research groups, as well as (3) reference +# papers from user groups online. +# +# If you make a major update to this script (e.g., update inspired by the +# latest version of the Synopsys reference methodology), please list the +# changeset in the version history below. +# +# Author : Christopher Torng +# Date : September 30, 2018 +# +#------------------------------------------------------------------------- +# Version History +#------------------------------------------------------------------------- +# +# - 09/30/2018 -- Christopher Torng +# - Clean slate DC scripts +# - We are now independent of the Synopsys Reference Methodology +# - Version of Synopsys DC running "% dc_shell -v": +# dc_shell version - M-2016.12 +# dc_shell build date - Nov 21, 2016 +# +# - 04/08/2018 -- Christopher Torng +# - Our original version was based on the Synopsys reference +# methodology (D-2010.03-SP1) +# - Big update now inspired by the Celerity Synopsys DC scripts, which +# were in turn also based on the Synopsys reference methodology +# (L-2016.03-SP2) +# +#------------------------------------------------------------------------- + +#------------------------------------------------------------------------- +# Designer interface +#------------------------------------------------------------------------- +# Source the designer interface script, which sets up variables from the +# build system, sets up ASIC design kit variables, etc. + +source -echo -verbose designer_interface.tcl + +#------------------------------------------------------------------------- +# Pre-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_pre_synthesis_plugin]]} { + puts "Info: Reading pre-synth plugin: $dc_pre_synthesis_plugin" + source -echo -verbose $dc_pre_synthesis_plugin +} + +#------------------------------------------------------------------------- +# Setup +#------------------------------------------------------------------------- + +# Set up variables for this specific ASIC design kit + +set SYNOPSYS_TOOL "dc-syn" +source -echo -verbose $dc_adk_tcl + +# Multicore support -- watch how many licenses we have! + +set_host_options -max_cores $dc_num_cores + +# Set up alib caching for faster consecutive runs + +set_app_var alib_library_analysis_path $dc_alib_dir + +# Set up tracking for Synopsys Formality + +set_svf ${dc_results_dir}/${dc_design_name}.mapped.svf + +# Set up search path for libraries and design files + +set_app_var search_path ". $dc_additional_search_path $search_path" + +# Important app vars +# +# - target_library -- DC maps the design to gates in this library (db) +# - synthetic_library -- DesignWare library (sldb) +# - link_library -- Libraries for any other design references (e.g., +# SRAMs, hierarchical blocks, macros, IO libs) (db) + +set_app_var target_library $dc_target_libraries +set_app_var synthetic_library dw_foundation.sldb +set_app_var link_library [join " + * + $target_library + $dc_extra_link_libraries + $synthetic_library + "] + + +# SAIF mapping. + # +saif_map -start + +# Create Milkyway library +# +# By default, Milkyway libraries only have 180 or so layers available to +# use (255 total, but some are reserved). The extend_mw_layers command +# expands the Milkyway library to accommodate up to 4095 layers. + +# Only create new Milkyway design library if it doesn't already exist + +set milkyway_library ${dc_design_name}_lib + +if {![file isdirectory $milkyway_library ]} { + + # Create a new Milkyway library + + extend_mw_layers + create_mw_lib -technology $dc_milkyway_tf \ + -mw_reference_library $dc_milkyway_ref_libraries \ + $milkyway_library + +} else { + + # Reuse existing Milkyway library, but ensure that it is consistent with + # the provided reference Milkyway libraries. + + set_mw_lib_reference $milkyway_library \ + -mw_reference_library $dc_milkyway_ref_libraries + +} + +open_mw_lib $milkyway_library + +# Set up TLU plus (if the files exist) + +if { $dc_topographical == True } { + if {[file exists [which $dc_tluplus_max]]} { + set_tlu_plus_files -max_tluplus $dc_tluplus_max \ + -min_tluplus $dc_tluplus_min \ + -tech2itf_map $dc_tluplus_map + + check_tlu_plus_files + } +} + +# Avoiding X-propagation for synchronous reset DFFs +# +# There are two key variables that help avoid X-propagation for +# synchronous reset DFFs: +# +# - set hdlin_ff_always_sync_set_reset true +# +# - Tells DC to use every constant 0 loaded into a DFF with a clock +# for synchronous reset, and every constant 1 loaded into a DFF with a +# clock for synchronous set +# +# - set compile_seqmap_honor_sync_set_reset true +# +# - Tells DC to preserve synchronous reset or preset logic close to +# the flip-flop +# +# So the hdlin variable first tells DC to treat resets as synchronous, and +# the compile variable tells DC that for all these synchronous reset DFFs, +# keep the logic simple and close to the DFF to avoid X-propagation. The +# hdlin variable applies to the analyze step when we read in the RTL, so +# it must be set before we read in the Verilog. The second variable +# applies to compile and must be set before we run compile_ultra. +# +# Note: Instead of setting the hdlin_ff_always_sync_set_reset variable to +# true, you can specifically tell DC about a particular DFF reset using +# the //synopsys sync_set_reset "reset, int_reset" pragma. +# +# By default, the hdlin_ff_always_async_set_reset variable is set to true, +# and the hdlin_ff_always_sync_set_reset variable is set to false. + +set hdlin_ff_always_sync_set_reset true +set compile_seqmap_honor_sync_set_reset true + +# Remove new variable info messages from the end of the log file + +set_app_var sh_new_variable_message false + +# Corners +# +# If we want to do corners in DC, then we would use this command to set +# the min and max libraries: + +#set_min_library $max_library -min_version $min_library + +# SAIF Name Mapping Database + +#if { ${VINAME} != "NONE" } { +# saif_map -start +#} + +# Hook to drop into interactive Design Compiler shell after setup + +if {[info exists ::env(DC_EXIT_AFTER_SETUP)]} { return } + +#------------------------------------------------------------------------- +# Read design +#------------------------------------------------------------------------- + +# Check libraries + +check_library > $dc_reports_dir/${dc_design_name}.check_library.rpt + +# The first "WORK" is a reserved word for Design Compiler. The value for +# the -path option is customizable. + +define_design_lib WORK -path ${dc_results_dir}/WORK + +# Analyze the RTL source files +# +# Source the read design plugin if it exists. Otherwise, we do a default +# read and elaborate the design. + +if {[file exists [which $dc_read_design_plugin]]} { + puts "Info: Reading read design plugin: $dc_read_design_plugin" + source -echo -verbose $dc_read_design_plugin +} else { + # Since no read design plugin exists, we do a default read + if { ![analyze -format sverilog $dc_rtl_handoff] } { exit 1 } + if {[file exists [which setup-design-params.txt]]} { + elaborate $dc_design_name -file_parameters setup-design-params.txt + rename_design $dc_design_name* $dc_design_name + } else { + elaborate $dc_design_name + } +} + +current_design $dc_design_name +link + +#------------------------------------------------------------------------- +# Write out useful files +#------------------------------------------------------------------------- + +# This ddc can be used as a checkpoint to load up to the current state + +write -hierarchy -format ddc \ + -output ${dc_results_dir}/${dc_design_name}.elab.ddc + +# This Verilog is useful to double-check the netlist that dc will use for +# mapping + +write -hierarchy -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.elab.v + +#------------------------------------------------------------------------- +# Apply design constraints +#------------------------------------------------------------------------- + +# Apply logical design constraints + +puts "Info: Reading constraints file plugin: $dc_constraints_plugin" + +source -echo -verbose $dc_constraints_plugin + +# The check_timing command checks for constraint problems such as +# undefined clocking, undefined input arrival times, and undefined output +# constraints. These constraint problems could cause you to overlook +# timing violations. For this reason, the check_timing command is +# recommended whenever you apply new constraints such as clock +# definitions, I/O delays, or timing exceptions. + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.premapped.checktiming.rpt \ + {check_timing} + +# Path groups + +set ports_clock_root [filter_collection \ + [get_attribute [get_clocks] sources] \ + object_class==port] + +group_path -name REGOUT \ + -to [all_outputs] + +group_path -name REGIN \ + -from [remove_from_collection [all_inputs] $ports_clock_root] + +group_path -name FEEDTHROUGH \ + -from [remove_from_collection [all_inputs] $ports_clock_root] \ + -to [all_outputs] + +# Apply physical design constraints +# +# Set the minimum and maximum routing layers used in DC topographical mode + +if { $dc_topographical == True } { + set_ignored_layers -min_routing_layer $ADK_MIN_ROUTING_LAYER_DC + set_ignored_layers -max_routing_layer $ADK_MAX_ROUTING_LAYER_DC + + report_ignored_layers +} + +#------------------------------------------------------------------------- +# Additional options +#------------------------------------------------------------------------- + +# Replace special characters with non-special ones before writing out the +# synthesized netlist (e.g., "\bus[5]" -> "bus_5_") + +set_app_var verilogout_no_tri true + +# Prevent assignment statements in the Verilog netlist. + +set_fix_multiple_port_nets -all -buffer_constants + +# Choose design flattening options + +if {[info exists DC_FLATTEN_EFFORT]} { + set dc_flatten_effort $DC_FLATTEN_EFFORT + if {"$dc_flatten_effort" == ""} { + set dc_flatten_effort 0 + } +} else { + set dc_flatten_effort 0 +} + +puts "Info: Flattening effort (DC_FLATTEN_EFFORT) = $dc_flatten_effort" + +set compile_ultra_options "" +if {$dc_flatten_effort == 0} { + puts "Info: All design hierarchies are preserved unless otherwise specified." + set_app_var compile_ultra_ungroup_dw false + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 1} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is disabled." + puts "Info: Design Compiler compile_ultra boundary optimization is disabled." + append compile_ultra_options " -no_autoungroup -no_boundary_optimization" + +} elseif {$dc_flatten_effort == 2} { + puts "Info: Unconditionally ungroup the DesignWare cells." + set_app_var compile_ultra_ungroup_dw true + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + append compile_ultra_options "" + +} elseif {$dc_flatten_effort == 3} { + set ungroup_start_level 2 + ungroup -start_level $ungroup_start_level -all -flatten + puts "Info: All hierarchical cells starting from level $ungroup_start_level are flattened." + puts "Info: Unconditionally ungroup the DesignWare cells." + puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." + puts "Info: Design Compiler compile_ultra boundary optimization is enabled." + set_app_var compile_ultra_ungroup_dw true + append compile_ultra_options "" + +} else { + puts "Info: Unrecognizable DC_FLATTEN_EFFORT value: $dc_flatten_effort" + exit +} + +# Enable or disable clock gating + +if {[info exists DC_GATE_CLOCK]} { + set dc_gate_clock $DC_GATE_CLOCK + if {"$dc_gate_clock" == ""} { + set dc_gate_clock true + } +} else { + set dc_gate_clock true +} + +puts "Info: Clock gating (DC_GATE_CLOCK) = $dc_gate_clock" + +if {$dc_gate_clock == true} { + append compile_ultra_options " -gate_clock" +} + +# Check design for consistency +# +# Most problems with synthesis will be caught in this report + +check_design -summary +check_design \ + > ${dc_reports_dir}/${dc_design_name}.premapped.checkdesign.rpt + +#------------------------------------------------------------------------- +# Compile +#------------------------------------------------------------------------- + +puts "Info: DC compile_ultra options = $compile_ultra_options" + +eval "compile_ultra $compile_ultra_options" + +# High-effort area optimization +# +# This command was introduced in I-2013.12 and performs monotonic +# gate-to-gate optimization on mapped designs. It is supposed to improve +# area without degrading timing or leakage. + +# Skip this step by setting the DC_SKIP_OPTIMIZE_NETLIST variable in the +# pre-synthesis plugin + +if {!([info exists DC_SKIP_OPTIMIZE_NETLIST] && $DC_SKIP_OPTIMIZE_NETLIST)} { + optimize_netlist -area +} + +# Check design + +check_design -summary +check_design > ${dc_reports_dir}/${dc_design_name}.mapped.checkdesign.rpt + +# Write the .namemap file for the Energy analysis + +if {[file exists "inputs/run.saif" ]} { + saif_map \ + -create_map \ + -input "inputs/run.saif" \ + -source_instance ${dc_saif_instance} +} + +#------------------------------------------------------------------------- +# Write out the design +#------------------------------------------------------------------------- + +# Synopsys Formality + +set_svf -off + +# Use naming rules to preserve structs + +define_name_rules verilog -preserve_struct_ports + +report_names \ + -rules verilog \ + > ${dc_reports_dir}/${dc_design_name}.mapped.naming.rpt + +change_names -rules verilog -hierarchy + +# Write out files + +write -format ddc \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.ddc + +write -format verilog \ + -hierarchy \ + -output ${dc_results_dir}/${dc_design_name}.mapped.v + +write -format svsim \ + -output ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v + +# Dump the mapped.v and svwrapper.v into one svsim.v file to make it +# easier to include a single file for gate-level simulation. The svwrapper +# matches the interface of the original RTL even if using SystemVerilog +# features (e.g., array of arrays, uses parameters, etc.). + +sh cat ${dc_results_dir}/${dc_design_name}.mapped.v \ + ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v \ + > ${dc_results_dir}/${dc_design_name}.mapped.svsim.v + +# Write top-level verilog view needed for block instantiation + +write \ + -format verilog \ + -output ${dc_results_dir}/${dc_design_name}.mapped.top.v + +# Floorplan + +if { $dc_topographical == True } { + write_floorplan -all ${dc_results_dir}/${dc_design_name}.mapped.fp +} + +# Parasitics + +write_parasitics -output ${dc_results_dir}/${dc_design_name}.mapped.spef + +# SDF for back-annotated gate-level simulation + +write_sdf ${dc_results_dir}/${dc_design_name}.mapped.sdf + +# Do not write out net RC info into SDC + +set_app_var write_sdc_output_lumped_net_capacitance false +set_app_var write_sdc_output_net_resistance false + +# SDC constraints + +write_sdc -nosplit ${dc_results_dir}/${dc_design_name}.mapped.sdc + +#------------------------------------------------------------------------- +# Final reports +#------------------------------------------------------------------------- + +# Report units + +redirect -tee \ + ${dc_reports_dir}/${dc_design_name}.mapped.units.rpt \ + {report_units} + +# Report QOR + +report_qor > ${dc_reports_dir}/${dc_design_name}.mapped.qor.rpt + +# Report timing + +report_clock_timing \ + -type summary \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.clock.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type max \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.setup.rpt + +report_timing \ + -input_pins -capacitance -transition_time \ + -nets -significant_digits 4 -nosplit \ + -path_type full_clock -attributes \ + -nworst 10 -max_paths 30 -delay_type min \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.hold.rpt + +# Report constraints + +report_constraint \ + -nosplit \ + -verbose \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.rpt + +report_constraint \ + -nosplit \ + -verbose \ + -all_violators \ + > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.violators.rpt + +report_timing_requirements \ + > ${dc_reports_dir}/${dc_design_name}.mapped.timing.requirements.rpt + +# Report area + +report_area \ + -hierarchy \ + -physical \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.area.rpt + +# Report references and resources + +report_reference \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.reference.rpt + +report_resources \ + -nosplit \ + -hierarchy \ + > ${dc_reports_dir}/${dc_design_name}.mapped.resources.rpt + +# Report power +# +# Use SAIF file for power analysis +if {[file exists "inputs/run.saif" ]} { + read_saif \ + -map_names \ + -input "inputs/run.saif" \ + -instance_name $dc_saif_instance \ + -verbose + + report_saif \ + -hier \ + -annotated_flag \ + -rtl_saif \ + > ${dc_reports_dir}/${dc_design_name}.mapped.saif.rpt + + saif_map \ + -type ptpx \ + -write_map \ + ${dc_reports_dir}/${dc_design_name}.namemap +} + +report_power \ + -nosplit \ + -hier \ + > ${dc_reports_dir}/${dc_design_name}.mapped.power.rpt + +report_clock_gating \ + -nosplit \ + > ${dc_reports_dir}/${dc_design_name}.mapped.clock_gating.rpt + +#------------------------------------------------------------------------- +# Post-synthesis plugin +#------------------------------------------------------------------------- + +if {[file exists [which $dc_post_synthesis_plugin]]} { + puts "Info: Reading post-synthesis plugin: $dc_post_synthesis_plugin" + source -echo -verbose $dc_post_synthesis_plugin +} + +exit + diff --git a/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl b/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl new file mode 100644 index 00000000..0996d017 --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl @@ -0,0 +1,90 @@ +#========================================================================= +# designer_interface.tcl +#========================================================================= +# The designer_interface.tcl file is the first script run by Design +# Compiler (see the top of dc.tcl). It is the interface that connects the +# dc-synthesis scripts with the following: +# +# - Build system parameters +# - Build system inputs +# - ASIC design kit +# - Plugin scripts +# +# Author : Christopher Torng +# Date : April 8, 2018 + +#------------------------------------------------------------------------- +# Parameters +#------------------------------------------------------------------------- + +set dc_design_name $::env(design_name) +set dc_saif_instance $::env(saif_instance) +set dc_clock_period $::env(clock_period) +set dc_flatten_effort $::env(flatten_effort) +set dc_topographical $::env(topographical) + +#------------------------------------------------------------------------- +# Inputs +#------------------------------------------------------------------------- + +set dc_rtl_handoff inputs/design.v +set adk_dir inputs/adk + +# Extra libraries +# +# The glob below will capture any libraries collected by the build system +# (e.g., SRAM libraries) generated from steps that synthesis depends on. +# +# To add more link libraries (e.g., IO cells, hierarchical blocks), append +# to the "dc_extra_link_libraries" variable in the pre-synthesis plugin +# like this: +# +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +set dc_extra_link_libraries [join " + [glob -nocomplain inputs/*.db] + [glob -nocomplain inputs/adk/*.db] + "] + +#------------------------------------------------------------------------- +# Interface to the ASIC design kit +#------------------------------------------------------------------------- + +set dc_milkyway_ref_libraries $adk_dir/stdcells.mwlib +set dc_milkyway_tf $adk_dir/rtk-tech.tf +set dc_tluplus_map $adk_dir/rtk-tluplus.map +set dc_tluplus_max $adk_dir/rtk-max.tluplus +set dc_tluplus_min $adk_dir/rtk-min.tluplus +set dc_adk_tcl $adk_dir/adk.tcl +set dc_target_libraries stdcells.db + +# Extra libraries + +set dc_additional_search_path $adk_dir + +#------------------------------------------------------------------------- +# Directories +#------------------------------------------------------------------------- + +set dc_flow_dir . +set dc_plugins_dir . +set dc_logs_dir logs +set dc_reports_dir reports +set dc_results_dir results +set dc_alib_dir alib + +#------------------------------------------------------------------------- +# Interface to plugins +#------------------------------------------------------------------------- + +set dc_pre_synthesis_plugin pre_synth.tcl +set dc_read_design_plugin read_design.tcl +set dc_constraints_plugin inputs/constraints.tcl +set dc_post_synthesis_plugin post_synth.tcl + + diff --git a/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl b/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl new file mode 100644 index 00000000..e5cab31f --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl @@ -0,0 +1,49 @@ +#========================================================================= +# pre_synth.tcl +#========================================================================= +# This plug-in script is called before synthesis +# +# Author : Christopher Torng +# Date : May 14, 2018 + +# Number of cores for multicore optimization + +set dc_num_cores $env(nthreads) + +# Add more link libraries (e.g., IO cells, hierarchical blocks) + +# set dc_extra_link_libraries [join " +# $dc_extra_link_libraries +# extra1.db +# extra2.db +# extra3.db +# "] + +# Enable additional area optimizations (skip false = enable optimizations) + +set DC_SKIP_OPTIMIZE_NETLIST true + +# Enable clock-gating + +set DC_GATE_CLOCK true + +# DC flatten effort +# +# - Effort 0: No auto-ungrouping / boundary optimizations (strict hierarchy) +# - Effort 1: No auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 2: Enable auto-ungrouping / boundary optimizations +# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) +# - Effort 3: Everything ungrouped + level param for how deep to ungroup +# +# Note that even with boundary optimizations off, DC will still propagate +# constants across the boundary, although this can be disabled with a +# variable if we really wanted to disable it. + +set DC_FLATTEN_EFFORT $env(flatten_effort) + +# When boundary optimizations are off, set this variable to true to still +# allow unconnected registers to be removed. + +set compile_optimize_unloaded_seq_logic_with_no_bound_opt true + diff --git a/designs/weight_manager/synopsys-dc-synthesis/run.sh b/designs/weight_manager/synopsys-dc-synthesis/run.sh new file mode 100755 index 00000000..ae57c1f0 --- /dev/null +++ b/designs/weight_manager/synopsys-dc-synthesis/run.sh @@ -0,0 +1,114 @@ +#! /usr/bin/env bash +#========================================================================= +# run.sh +#========================================================================= +# Author : Christopher Torng +# Date : June 2, 2019 +# + +# Print commands during execution + +set -x + +# DC shell + +dc_exec='dc_shell-xg-t -64bit' + +# Build directories + +rm -rf ./logs +rm -rf ./reports +rm -rf ./results + +mkdir -p logs +mkdir -p reports +mkdir -p results + +# alib +# +# Design Compiler caches analyzed libraries to improve performance using +# ".alib" directories. The alib takes a while to generate but is reused on +# subsequent runs. It is useful to store a centralized copy of the alib to +# avoid re-generating the alib (usually only several minutes but can be +# annoying) on every new clone of the ASIC repo. +# +# However, if DC sees a .db that does not have an associated .alib it will +# try to automatically create one. This is not usually a problem when +# students just use standard cells, but if a student is trying to use +# SRAMs, then they will be using new .db files that DC has not seen yet. +# The problem is that students do not have write permissions to the +# centralized copy of the alib in the ADK. +# +# The solution we use is to create a local alib directory in the current +# build directory with _per-file_ symlinks to the centralized alib (and +# with the same directory hierarchy). This allows students to reuse the +# centralized copies of the alib files while allowing new alibs (e.g., for +# SRAMs) to be generated locally. +# +# This is possible because the alibs are stored in a directory that holds +# a ".db.alib" file for each db file: +# +# - alib +# - alib-52 +# - iocells.db.alib +# - stdcells.db.alib +# +# This new alib directory just needs to contain symlinks to each saved +# alib in the ADK. This can be done simply by using "cp -srf" of the ADK +# alib to the build directory, which generates symbolic links to each file +# instead of copying. This way, the student can access the master copy of +# the saved alibs in the ADK, and if there are any additional db's +# specified, their alibs will be saved in the local build directory. + +rm -rf alib +mkdir -p alib + +cp -srf $PWD/inputs/adk/alib/* alib || true + +# Run the synthesis script + +if [ "x$topographical" == "xTrue" ]; then + opt_topographical='-topographical_mode' +else + opt_topographical= +fi + +$dc_exec $opt_topographical -f dc.tcl -output_log_file logs/dc.log || exit 1 + +# Compress the spef file + +cd results +gzip *.mapped.spef +cd .. + +# Set up the outputs + +mkdir -p outputs && cd outputs + +ln -sf ../results/*.mapped.v design.v +ln -sf ../results/*.mapped.sdc design.sdc +ln -sf ../results/*.mapped.spef.gz design.spef.gz +ln -sf ../reports/*.namemap design.namemap + +cd .. + +# Grep for failure messages + +grep --color "^Error" logs/dc.log || true +grep --color -B 3 "*** Presto compilation terminated" logs/dc.log || true +grep --color "unresolved references." logs/dc.log || true + +# ELAB-405 +# +# When using a Verilog generation tool, there may be a +# generation/translation mistake that defines a net twice. This will give +# a message like this: +# +# Warning: ./inputs/design.v:2473: Net mul__recv__msg__opd_b[0] or a +# directly connected net may be driven by more than one process or block. +# (ELAB-405) +# +# This is usually a bad sign.. +# + +grep --color "ELAB-405" logs/dc.log || true diff --git a/regress.sh b/regress.sh index 452b3173..596fe291 100644 --- a/regress.sh +++ b/regress.sh @@ -39,8 +39,21 @@ pip install pytest pytest-cov # run mflowgen as long as we're not on the FPGA server if [ -z "$FPGA_SERVER" ] then - mkdir -p build/mflowgen - cd build/mflowgen - mflowgen run --design ../../flow + mkdir -p build/mflowgen_dragonphy_top + cd build/mflowgen_dragonphy_top + mflowgen run --design ../../designs/dragonphy_top make synopsys-dc-synthesis + cd .. + + mkdir -p build/mflowgen_jtag + cd build/mflowgen_jtag + mflowgen run --design ../../designs/jtag + make synopsys-dc-synthesis + cd .. + + mkdir -p build/mflowgen_weight_manager + cd build/mflowgen_weight_manager + mflowgen run --design ../../designs/weight_manager + make synopsys-dc-synthesis + cd .. fi From f58af8a7201a554ea8f45196be5315046ff9afec Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 6 May 2020 15:22:58 -0700 Subject: [PATCH 10/16] fix regression script and make weight_manager synthesis test more realistic --- designs/weight_manager/rtl/gen_rtl.py | 11 ++++++-- .../rtl/weight_manager_insts.sv | 26 +++++++++++++++++++ regress.sh | 6 ++--- 3 files changed, 38 insertions(+), 5 deletions(-) create mode 100644 designs/weight_manager/rtl/weight_manager_insts.sv diff --git a/designs/weight_manager/rtl/gen_rtl.py b/designs/weight_manager/rtl/gen_rtl.py index 4bf4f7ca..5fcfccc5 100644 --- a/designs/weight_manager/rtl/gen_rtl.py +++ b/designs/weight_manager/rtl/gen_rtl.py @@ -3,12 +3,19 @@ from pathlib import Path from dragonphy import * -TOP_CELL = os.environ.get('design_name', 'weight_manager') OUTPUT_FILE = 'design.v' +def remove_dup(seq): + # fast method to remove duplicates from a list while preserving order + # source: Raymond Hettinger (https://twitter.com/raymondh/status/944125570534621185) + return list(dict.fromkeys(seq)) + # build up a list of source files src_files = [] -src_files += get_deps_new_asic(TOP_CELL) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/digital_core/dsp_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/weight_manager/wme_debug_intf.sv')) +src_files += get_deps_new_asic(impl_file='weight_manager_insts.sv') +src_files = remove_dup(src_files) # generate the output text output = '' diff --git a/designs/weight_manager/rtl/weight_manager_insts.sv b/designs/weight_manager/rtl/weight_manager_insts.sv new file mode 100644 index 00000000..39a903d2 --- /dev/null +++ b/designs/weight_manager/rtl/weight_manager_insts.sv @@ -0,0 +1,26 @@ +module weight_manager_insts import const_pack::*; ( + input wire logic clk_adc, + input wire logic rstb, + wme_debug_intf.wme wdbg_intf_i, + dsp_debug_intf.dsp dsp_dbg_intf_i +); + weight_manager #(.width(Nti), .depth(10), .bitwidth(10)) wme_ffe_i ( + .data (wdbg_intf_i.wme_ffe_data), + .inst (wdbg_intf_i.wme_ffe_inst), + .exec (wdbg_intf_i.wme_ffe_exec), + .clk (clk_adc), + .rstb (rstb), + .read_reg(wdbg_intf_i.wme_ffe_read), + .weights (dsp_dbg_intf_i.weights) + ); + + weight_manager #(.width(Nti), .depth(30), .bitwidth(8)) wme_channel_est_i ( + .data (wdbg_intf_i.wme_mlsd_data), + .inst (wdbg_intf_i.wme_mlsd_inst), + .exec (wdbg_intf_i.wme_mlsd_exec), + .clk (clk_adc), + .rstb (rstb), + .read_reg(wdbg_intf_i.wme_mlsd_read), + .weights (dsp_dbg_intf_i.channel_est) + ); +endmodule diff --git a/regress.sh b/regress.sh index 596fe291..fe23bb6e 100644 --- a/regress.sh +++ b/regress.sh @@ -43,17 +43,17 @@ then cd build/mflowgen_dragonphy_top mflowgen run --design ../../designs/dragonphy_top make synopsys-dc-synthesis - cd .. + cd ../.. mkdir -p build/mflowgen_jtag cd build/mflowgen_jtag mflowgen run --design ../../designs/jtag make synopsys-dc-synthesis - cd .. + cd ../.. mkdir -p build/mflowgen_weight_manager cd build/mflowgen_weight_manager mflowgen run --design ../../designs/weight_manager make synopsys-dc-synthesis - cd .. + cd ../.. fi From bdae2fbadfc9aea30382b5674e63923840ee75e7 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 6 May 2020 19:47:01 -0700 Subject: [PATCH 11/16] work in progress --- .buildkite/pipeline.yml | 1 + .gitignore | 1 + .../openram-gen-sram/configure.yml | 44 ++++++ .../openram-gen-sram/gen_constraints.py | 132 ++++++++++++++++++ .../openram-gen-sram/myconfig.py | 15 ++ designs/dragonphy_top/qtm/configure.yml | 44 ++++++ designs/dragonphy_top/qtm/gen_constraints.py | 132 ++++++++++++++++++ designs/dragonphy_top/rtl/gen_rtl.py | 2 +- regress.sh | 4 + 9 files changed, 374 insertions(+), 1 deletion(-) create mode 100644 designs/dragonphy_top/openram-gen-sram/configure.yml create mode 100644 designs/dragonphy_top/openram-gen-sram/gen_constraints.py create mode 100644 designs/dragonphy_top/openram-gen-sram/myconfig.py create mode 100644 designs/dragonphy_top/qtm/configure.yml create mode 100644 designs/dragonphy_top/qtm/gen_constraints.py diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index a9492b57..182a564a 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -7,6 +7,7 @@ steps: module load base xcelium lc syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1 export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=cpu + export FREEPDK45=/cad/freepdk/FreePDK45 printenv # create virtual environment diff --git a/.gitignore b/.gitignore index 1b9d09ee..6549e349 100644 --- a/.gitignore +++ b/.gitignore @@ -34,6 +34,7 @@ tcbn16* pnr/data pnr/gate_size_test flow/*/outputs +designs/*/*/temp/ ######################### # other files to ignore # diff --git a/designs/dragonphy_top/openram-gen-sram/configure.yml b/designs/dragonphy_top/openram-gen-sram/configure.yml new file mode 100644 index 00000000..9c869605 --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/configure.yml @@ -0,0 +1,44 @@ +# Adapted from Garnet + +name: constraints + +commands: + - python gen_constraints.py + +outputs: + - constraints.tcl + +parameters: + # time in ns and capacitance in pF + + # Name of the design + design_name: undefined + + # Main clocks in the design + clk_retimer_period: 0.7 + clk_in_period: 0.7 + clk_jtag_period: 100.0 + + # Retimer clock uncertainty + clk_retimer_setup_uncertainty: 0.03 + clk_retimer_hold_uncertainty: 0.03 + + # JTAG clock uncertainty + clk_jtag_setup_uncertainty: 1.0 + clk_jtag_hold_uncertainty: 0.03 + + # Capacitance and transition time + max_capacitance: 0.1 + max_transition: 0.2 + max_clock_transition: 0.1 + + # Clocks that can be monitored from analog_core + clk_hs_period: 0.25 + clk_hs_transition: 0.025 + + # I/O delays and transitions + digital_input_delay: 0.05 + digital_input_transition: 0.5 + input_transition: 0.03 + output_load: 0.02 + output_delay: 0.7 diff --git a/designs/dragonphy_top/openram-gen-sram/gen_constraints.py b/designs/dragonphy_top/openram-gen-sram/gen_constraints.py new file mode 100644 index 00000000..dffb48b1 --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/gen_constraints.py @@ -0,0 +1,132 @@ +import os +from pathlib import Path + +OUTPUT_FILE = 'constraints.tcl' + +e = os.environ +output = f'''\ +# Modified from ButterPHY and Garnet constraints + +# Design constraints for synthesis +# time unit : ns +# cap unit: pF + +######### +# Params +######### + +# primary I/Os being treated as don't touch nets + +set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\ + ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\ + ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\ + ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}} + +set analog_net [get_pins ibuf_*/clk] + +set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\ + jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\ + jtag_intf_i.phy_trst_n}} + +######### +# Clocks +######### + +create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] +create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] +create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] +set_dont_touch_network [get_pins {{iacore/clk_adc}}] +set_dont_touch_network [get_port jtag_intf_i.phy_tck] + +set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer +set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer +set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag +set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag + +########### +# Net const +########### + +set_max_capacitance {e["max_capacitance"]} [current_design] +set_max_transition {e["max_transition"]} [current_design] +set_max_transition {e["max_clock_transition"]} [all_clocks] + +set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\ + iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\ + iacore/*del_out_pi*}}] + +foreach x [get_object_name $hs_nets] {{ + create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x] + set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x] +}} + +echo [all_clocks] + +########### +# Analog nets +########### + +set_dont_touch_network [get_ports $analog_io] +set_dont_touch_network $analog_net +set_dont_touch_network [all_outputs] + +########### +# I/O const +########### + +set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs] +set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs] + +set_input_transition {e["input_transition"]} [all_inputs] +set_load {e["output_load"]} [all_outputs] +set_output_delay {e["output_delay"]} [all_outputs] + +############ +# False path +############ + +set_false_path -from clk_retimer -to clk_jtag +set_false_path -from clk_jtag -to clk_retimer + +################ +# DONT USE CELLS +################ + +# foreach lib $mvt_target_libs {{ +# set_dont_use [file rootname [file tail $lib]]/*D0BWP* +# }} + +# Settings from Garnet to consider +# (all commented out at the moment) + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +# set_driving_cell -no_design_rule \\ +# -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# Make all signals limit their fanout +# TODO: should this be included? +# set_max_fanout 20 {e["design_name"]} + +# sr 02/2020 +# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( +# Without dont_touch, they disappear during dc-synthesis +# set_dont_touch [ get_cells ANAIOPAD* ] + +# sr 02/2020 +# Arg turns out not all IOPAD cells have dont_touch property I guess +# set_dont_touch [ get_cells IOPAD* ] +''' + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write output text +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + f.write(output) + diff --git a/designs/dragonphy_top/openram-gen-sram/myconfig.py b/designs/dragonphy_top/openram-gen-sram/myconfig.py new file mode 100644 index 00000000..b700a906 --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/myconfig.py @@ -0,0 +1,15 @@ +# Data word size +word_size = 144 +# Number of words in the memory +num_words = 1024 + +# Technology to use in $OPENRAM_TECH +tech_name = "freepdk45" + +# You can use the technology nominal corner only +nominal_corner_only = True + +# Output directory for the results +output_path = "temp" +# Output file base name +output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) \ No newline at end of file diff --git a/designs/dragonphy_top/qtm/configure.yml b/designs/dragonphy_top/qtm/configure.yml new file mode 100644 index 00000000..9c869605 --- /dev/null +++ b/designs/dragonphy_top/qtm/configure.yml @@ -0,0 +1,44 @@ +# Adapted from Garnet + +name: constraints + +commands: + - python gen_constraints.py + +outputs: + - constraints.tcl + +parameters: + # time in ns and capacitance in pF + + # Name of the design + design_name: undefined + + # Main clocks in the design + clk_retimer_period: 0.7 + clk_in_period: 0.7 + clk_jtag_period: 100.0 + + # Retimer clock uncertainty + clk_retimer_setup_uncertainty: 0.03 + clk_retimer_hold_uncertainty: 0.03 + + # JTAG clock uncertainty + clk_jtag_setup_uncertainty: 1.0 + clk_jtag_hold_uncertainty: 0.03 + + # Capacitance and transition time + max_capacitance: 0.1 + max_transition: 0.2 + max_clock_transition: 0.1 + + # Clocks that can be monitored from analog_core + clk_hs_period: 0.25 + clk_hs_transition: 0.025 + + # I/O delays and transitions + digital_input_delay: 0.05 + digital_input_transition: 0.5 + input_transition: 0.03 + output_load: 0.02 + output_delay: 0.7 diff --git a/designs/dragonphy_top/qtm/gen_constraints.py b/designs/dragonphy_top/qtm/gen_constraints.py new file mode 100644 index 00000000..dffb48b1 --- /dev/null +++ b/designs/dragonphy_top/qtm/gen_constraints.py @@ -0,0 +1,132 @@ +import os +from pathlib import Path + +OUTPUT_FILE = 'constraints.tcl' + +e = os.environ +output = f'''\ +# Modified from ButterPHY and Garnet constraints + +# Design constraints for synthesis +# time unit : ns +# cap unit: pF + +######### +# Params +######### + +# primary I/Os being treated as don't touch nets + +set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\ + ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\ + ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\ + ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}} + +set analog_net [get_pins ibuf_*/clk] + +set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\ + jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\ + jtag_intf_i.phy_trst_n}} + +######### +# Clocks +######### + +create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] +create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] +create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] +set_dont_touch_network [get_pins {{iacore/clk_adc}}] +set_dont_touch_network [get_port jtag_intf_i.phy_tck] + +set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer +set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer +set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag +set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag + +########### +# Net const +########### + +set_max_capacitance {e["max_capacitance"]} [current_design] +set_max_transition {e["max_transition"]} [current_design] +set_max_transition {e["max_clock_transition"]} [all_clocks] + +set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\ + iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\ + iacore/*del_out_pi*}}] + +foreach x [get_object_name $hs_nets] {{ + create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x] + set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x] +}} + +echo [all_clocks] + +########### +# Analog nets +########### + +set_dont_touch_network [get_ports $analog_io] +set_dont_touch_network $analog_net +set_dont_touch_network [all_outputs] + +########### +# I/O const +########### + +set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs] +set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs] + +set_input_transition {e["input_transition"]} [all_inputs] +set_load {e["output_load"]} [all_outputs] +set_output_delay {e["output_delay"]} [all_outputs] + +############ +# False path +############ + +set_false_path -from clk_retimer -to clk_jtag +set_false_path -from clk_jtag -to clk_retimer + +################ +# DONT USE CELLS +################ + +# foreach lib $mvt_target_libs {{ +# set_dont_use [file rootname [file tail $lib]]/*D0BWP* +# }} + +# Settings from Garnet to consider +# (all commented out at the moment) + +# This constraint sets the input drive strength of the input pins of +# your design. We specifiy a specific standard cell which models what +# would be driving the inputs. This should usually be a small inverter +# which is reasonable if another block of on-chip logic is driving +# your inputs. + +# set_driving_cell -no_design_rule \\ +# -lib_cell $ADK_DRIVING_CELL [all_inputs] + +# Make all signals limit their fanout +# TODO: should this be included? +# set_max_fanout 20 {e["design_name"]} + +# sr 02/2020 +# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( +# Without dont_touch, they disappear during dc-synthesis +# set_dont_touch [ get_cells ANAIOPAD* ] + +# sr 02/2020 +# Arg turns out not all IOPAD cells have dont_touch property I guess +# set_dont_touch [ get_cells IOPAD* ] +''' + +# create output directory +OUTPUT_DIR = Path('outputs') +OUTPUT_DIR.mkdir(exist_ok=True, parents=True) + +# write output text +with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: + f.write(output) + diff --git a/designs/dragonphy_top/rtl/gen_rtl.py b/designs/dragonphy_top/rtl/gen_rtl.py index 0220505c..2999e399 100644 --- a/designs/dragonphy_top/rtl/gen_rtl.py +++ b/designs/dragonphy_top/rtl/gen_rtl.py @@ -25,7 +25,7 @@ def resolve_include_file(name): output = '' # TODO: remove this! -output += '`define SYNTHESIS_DEBUG\n' +# output += '`define SYNTHESIS_DEBUG\n' inc_pat = re.compile(r'\s*`include\s+"?([a-zA-Z0-9_./]+)"?') for src_file in src_files: diff --git a/regress.sh b/regress.sh index fe23bb6e..01768d4c 100644 --- a/regress.sh +++ b/regress.sh @@ -39,6 +39,10 @@ pip install pytest pytest-cov # run mflowgen as long as we're not on the FPGA server if [ -z "$FPGA_SERVER" ] then + git clone https://github.com/VLSIDA/OpenRAM.git + export OPENRAM_HOME=`realpath OpenRAM/compiler` + export OPENRAM_TECH=`realpath OpenRAM/technology` + mkdir -p build/mflowgen_dragonphy_top cd build/mflowgen_dragonphy_top mflowgen run --design ../../designs/dragonphy_top From 6671a20956e9077ad3123dcb9c7d5016b8daf38f Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 7 May 2020 10:45:34 -0700 Subject: [PATCH 12/16] work in progress --- .buildkite/pipeline.yml | 28 +- .../constraints/gen_constraints.py | 32 +- .../construct-commercial-full.py | 8 + designs/dragonphy_top/qtm/configure.yml | 44 +- designs/dragonphy_top/qtm/gen_constraints.py | 132 -- .../dragonphy_top/qtm/output_buffer.qtm.tcl | 46 + designs/dragonphy_top/qtm/run_dc.tcl | 8 + designs/dragonphy_top/rtl/gen_rtl.py | 3 - dragonphy/views.py | 6 +- mflowgen.sh | 37 + regress.sh | 34 +- synthesis/scripts/QTM/analog_core.qtm.tcl | 1665 +++++++++++++++++ synthesis/scripts/QTM/butterphy_top.qtm.tcl | 8 + synthesis/scripts/QTM/output_buffer.qtm.tcl | 46 + synthesis/scripts/QTM/run.sh | 4 + synthesis/scripts/QTM/run_lc.tcl | 6 + synthesis/scripts/QTM/run_pt.tcl | 13 + 17 files changed, 1904 insertions(+), 216 deletions(-) delete mode 100644 designs/dragonphy_top/qtm/gen_constraints.py create mode 100644 designs/dragonphy_top/qtm/output_buffer.qtm.tcl create mode 100644 designs/dragonphy_top/qtm/run_dc.tcl create mode 100644 mflowgen.sh create mode 100644 synthesis/scripts/QTM/analog_core.qtm.tcl create mode 100644 synthesis/scripts/QTM/butterphy_top.qtm.tcl create mode 100644 synthesis/scripts/QTM/output_buffer.qtm.tcl create mode 100755 synthesis/scripts/QTM/run.sh create mode 100644 synthesis/scripts/QTM/run_lc.tcl create mode 100644 synthesis/scripts/QTM/run_pt.tcl diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 182a564a..09e6e310 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -2,12 +2,10 @@ steps: - label: "test" command: | # set up environment - # modules loaded aim to match those used by Garnet source /cad/modules/tcl/init/bash - module load base xcelium lc syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1 + module load base xcelium dc_shell export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=cpu - export FREEPDK45=/cad/freepdk/FreePDK45 printenv # create virtual environment @@ -24,6 +22,30 @@ steps: timeout_in_minutes: 60 agents: fault2: "true" + - label: "test_mflowgen" + command: | + # set up environment + # modules loaded aim to match those used by Garnet + source /cad/modules/tcl/init/bash + module load base xcelium lc pts syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1 + export BUILD_VIEW=asic + export FREEPDK45=/cad/freepdk/FreePDK45 + printenv + + # create virtual environment + /usr/local/miniconda/bin/python3.7 -m venv venv + source venv/bin/activate + + # run mflowgen script + source mflowgen.sh + + # deactivate virtual environment + deactivate + artifact_paths: + - "tests/new_tests/*/build/*.eps" + timeout_in_minutes: 60 + agents: + fault2: "true" - label: "test_emu" command: | # set up environment diff --git a/designs/dragonphy_top/constraints/gen_constraints.py b/designs/dragonphy_top/constraints/gen_constraints.py index dffb48b1..a86a3145 100644 --- a/designs/dragonphy_top/constraints/gen_constraints.py +++ b/designs/dragonphy_top/constraints/gen_constraints.py @@ -35,6 +35,7 @@ create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] + set_dont_touch_network [get_pins {{iacore/clk_adc}}] set_dont_touch_network [get_port jtag_intf_i.phy_tck] @@ -47,7 +48,9 @@ # Net const ########### -set_max_capacitance {e["max_capacitance"]} [current_design] +# This constraint causes a huge number of buffers to be inserted +# set_max_capacitance {e["max_capacitance"]} [current_design] + set_max_transition {e["max_transition"]} [current_design] set_max_transition {e["max_clock_transition"]} [all_clocks] @@ -85,9 +88,32 @@ # False path ############ +# asynchronous clock domains set_false_path -from clk_retimer -to clk_jtag set_false_path -from clk_jtag -to clk_retimer +# top-level ports +set_false_path -through [get_ports] + +# analog core +set_false_path -through [get_pins -of_objects iacore] + +# digital core +set_false_path -through [get_pins -of_objects idcore] + +# black box buffers +set_false_path -through [get_pins -of_objects ibuf_async] +set_false_path -through [get_pins -of_objects ibuf_main] +set_false_path -through [get_pins -of_objects ibuf_test0] +set_false_path -through [get_pins -of_objects ibuf_test1] + +################ +# Other options +################ + +# Make all signals limit their fanout +set_max_fanout 20 {e["design_name"]} + ################ # DONT USE CELLS ################ @@ -108,10 +134,6 @@ # set_driving_cell -no_design_rule \\ # -lib_cell $ADK_DRIVING_CELL [all_inputs] -# Make all signals limit their fanout -# TODO: should this be included? -# set_max_fanout 20 {e["design_name"]} - # sr 02/2020 # haha IOPAD cells already have dont_touch property but not ANAIOPAD :( # Without dont_touch, they disappear during dc-synthesis diff --git a/designs/dragonphy_top/construct-commercial-full.py b/designs/dragonphy_top/construct-commercial-full.py index 4caa2e0e..11089764 100644 --- a/designs/dragonphy_top/construct-commercial-full.py +++ b/designs/dragonphy_top/construct-commercial-full.py @@ -85,6 +85,7 @@ def construct(): rtl = Step(this_dir + '/rtl') constraints = Step(this_dir + '/constraints') dc = Step(this_dir + '/synopsys-dc-synthesis') + qtm = Step(this_dir + '/qtm') # Default steps @@ -105,6 +106,11 @@ def construct(): lvs = Step( 'mentor-calibre-lvs', default=True ) debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) + # Add *.db files to synthesis inputs + dc.extend_inputs([ + 'output_buffer.db' + ]) + #----------------------------------------------------------------------- # Graph -- Add nodes #----------------------------------------------------------------------- @@ -113,6 +119,7 @@ def construct(): g.add_step( rtl ) g.add_step( constraints ) g.add_step( dc ) + g.add_step( qtm ) g.add_step( iflow ) g.add_step( init ) g.add_step( power ) @@ -152,6 +159,7 @@ def construct(): g.connect_by_name( rtl, dc ) g.connect_by_name( constraints, dc ) + g.connect_by_name( qtm, dc ) g.connect_by_name( dc, iflow ) g.connect_by_name( dc, init ) diff --git a/designs/dragonphy_top/qtm/configure.yml b/designs/dragonphy_top/qtm/configure.yml index 9c869605..3040420a 100644 --- a/designs/dragonphy_top/qtm/configure.yml +++ b/designs/dragonphy_top/qtm/configure.yml @@ -1,44 +1,12 @@ # Adapted from Garnet -name: constraints +name: qtm commands: - - python gen_constraints.py + - mkdir -p build + - mkdir -p outputs + - cd build && pt_shell -f ../output_buffer.qtm.tcl + - cd build && dc_shell-xg-t -f ../run_dc.tcl outputs: - - constraints.tcl - -parameters: - # time in ns and capacitance in pF - - # Name of the design - design_name: undefined - - # Main clocks in the design - clk_retimer_period: 0.7 - clk_in_period: 0.7 - clk_jtag_period: 100.0 - - # Retimer clock uncertainty - clk_retimer_setup_uncertainty: 0.03 - clk_retimer_hold_uncertainty: 0.03 - - # JTAG clock uncertainty - clk_jtag_setup_uncertainty: 1.0 - clk_jtag_hold_uncertainty: 0.03 - - # Capacitance and transition time - max_capacitance: 0.1 - max_transition: 0.2 - max_clock_transition: 0.1 - - # Clocks that can be monitored from analog_core - clk_hs_period: 0.25 - clk_hs_transition: 0.025 - - # I/O delays and transitions - digital_input_delay: 0.05 - digital_input_transition: 0.5 - input_transition: 0.03 - output_load: 0.02 - output_delay: 0.7 + - output_buffer.db diff --git a/designs/dragonphy_top/qtm/gen_constraints.py b/designs/dragonphy_top/qtm/gen_constraints.py deleted file mode 100644 index dffb48b1..00000000 --- a/designs/dragonphy_top/qtm/gen_constraints.py +++ /dev/null @@ -1,132 +0,0 @@ -import os -from pathlib import Path - -OUTPUT_FILE = 'constraints.tcl' - -e = os.environ -output = f'''\ -# Modified from ButterPHY and Garnet constraints - -# Design constraints for synthesis -# time unit : ns -# cap unit: pF - -######### -# Params -######### - -# primary I/Os being treated as don't touch nets - -set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\ - ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\ - ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\ - ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}} - -set analog_net [get_pins ibuf_*/clk] - -set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\ - jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\ - jtag_intf_i.phy_trst_n}} - -######### -# Clocks -######### - -create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] -create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] -create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] -set_dont_touch_network [get_pins {{iacore/clk_adc}}] -set_dont_touch_network [get_port jtag_intf_i.phy_tck] - -set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer -set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer -set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag -set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag - -########### -# Net const -########### - -set_max_capacitance {e["max_capacitance"]} [current_design] -set_max_transition {e["max_transition"]} [current_design] -set_max_transition {e["max_clock_transition"]} [all_clocks] - -set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\ - iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\ - iacore/*del_out_pi*}}] - -foreach x [get_object_name $hs_nets] {{ - create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x] - set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x] -}} - -echo [all_clocks] - -########### -# Analog nets -########### - -set_dont_touch_network [get_ports $analog_io] -set_dont_touch_network $analog_net -set_dont_touch_network [all_outputs] - -########### -# I/O const -########### - -set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs] -set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs] - -set_input_transition {e["input_transition"]} [all_inputs] -set_load {e["output_load"]} [all_outputs] -set_output_delay {e["output_delay"]} [all_outputs] - -############ -# False path -############ - -set_false_path -from clk_retimer -to clk_jtag -set_false_path -from clk_jtag -to clk_retimer - -################ -# DONT USE CELLS -################ - -# foreach lib $mvt_target_libs {{ -# set_dont_use [file rootname [file tail $lib]]/*D0BWP* -# }} - -# Settings from Garnet to consider -# (all commented out at the moment) - -# This constraint sets the input drive strength of the input pins of -# your design. We specifiy a specific standard cell which models what -# would be driving the inputs. This should usually be a small inverter -# which is reasonable if another block of on-chip logic is driving -# your inputs. - -# set_driving_cell -no_design_rule \\ -# -lib_cell $ADK_DRIVING_CELL [all_inputs] - -# Make all signals limit their fanout -# TODO: should this be included? -# set_max_fanout 20 {e["design_name"]} - -# sr 02/2020 -# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( -# Without dont_touch, they disappear during dc-synthesis -# set_dont_touch [ get_cells ANAIOPAD* ] - -# sr 02/2020 -# Arg turns out not all IOPAD cells have dont_touch property I guess -# set_dont_touch [ get_cells IOPAD* ] -''' - -# create output directory -OUTPUT_DIR = Path('outputs') -OUTPUT_DIR.mkdir(exist_ok=True, parents=True) - -# write output text -with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: - f.write(output) - diff --git a/designs/dragonphy_top/qtm/output_buffer.qtm.tcl b/designs/dragonphy_top/qtm/output_buffer.qtm.tcl new file mode 100644 index 00000000..683aa3f3 --- /dev/null +++ b/designs/dragonphy_top/qtm/output_buffer.qtm.tcl @@ -0,0 +1,46 @@ +create_qtm_model output_buffer + +# inputs +create_qtm_port { \ + bypass_out_div \ + bypass_trig_div \ + en_outbuff \ + en_trigbuff \ + sel_trigbuff[3:0] \ + bufferend_signals[15:0] \ + Ndiv_trigbuff[2:0] \ + Ndiv_outbuff[2:0] \ + sel_outbuff[3:0] \ +} -type input + +# outputs +create_qtm_port { \ + clock_out_n \ + clock_out_p \ + trigg_out_n \ + trigg_out_p \ +} -type output + +set_qtm_port_load { \ + bypass_out_div \ + bypass_trig_div \ + en_outbuff \ + en_trigbuff \ + sel_trigbuff[3:0] \ + bufferend_signals[15:0] \ + Ndiv_trigbuff[2:0] \ + Ndiv_outbuff[2:0] \ + sel_outbuff[3:0] \ +} -value 0.02 + +set_qtm_port_drive { \ + clock_out_n \ + clock_out_p \ + trigg_out_n \ + trigg_out_p \ +} -value 1 + +report_qtm_model +save_qtm_model -format lib -library_cell + +exit \ No newline at end of file diff --git a/designs/dragonphy_top/qtm/run_dc.tcl b/designs/dragonphy_top/qtm/run_dc.tcl new file mode 100644 index 00000000..afe4c642 --- /dev/null +++ b/designs/dragonphy_top/qtm/run_dc.tcl @@ -0,0 +1,8 @@ +# required in order to write libraries +enable_write_lib_mode + +# write the *.db for the output buffer +read_lib output_buffer.lib +write_lib -format db output_buffer -output ../outputs/output_buffer.db + +exit \ No newline at end of file diff --git a/designs/dragonphy_top/rtl/gen_rtl.py b/designs/dragonphy_top/rtl/gen_rtl.py index 2999e399..fffb1efb 100644 --- a/designs/dragonphy_top/rtl/gen_rtl.py +++ b/designs/dragonphy_top/rtl/gen_rtl.py @@ -24,9 +24,6 @@ def resolve_include_file(name): # generate the output text output = '' -# TODO: remove this! -# output += '`define SYNTHESIS_DEBUG\n' - inc_pat = re.compile(r'\s*`include\s+"?([a-zA-Z0-9_./]+)"?') for src_file in src_files: output += f'// Content from file: {src_file}\n' diff --git a/dragonphy/views.py b/dragonphy/views.py index e3cdc52a..ad7c462b 100644 --- a/dragonphy/views.py +++ b/dragonphy/views.py @@ -143,13 +143,15 @@ def get_deps_new_asic(cell_name=None, impl_file=None): view_order=['new_pack', 'new_chip_src'], includes=[get_dir('inc/new_asic')], override={ + # TODO: replace all of these with *.db files 'sram': 'new_chip_stubs', - 'output_buffer': 'new_chip_stubs', 'input_buffer': 'new_chip_stubs', 'analog_core': 'new_chip_stubs' }, skip={ - 'DW_tap' # Don't use a stub for a DesignWare block + # these blocks are defined from *.db files + 'DW_tap', + 'output_buffer' } ) diff --git a/mflowgen.sh b/mflowgen.sh new file mode 100644 index 00000000..e600683c --- /dev/null +++ b/mflowgen.sh @@ -0,0 +1,37 @@ +# upgrade pip +pip install -U pip + +# install Genesis2 +git clone https://github.com/StanfordVLSI/Genesis2.git +export GENESIS_HOME=`realpath Genesis2/Genesis2Tools` +export PERL5LIB="$GENESIS_HOME/PerlLibs/ExtrasForOldPerlDistributions" +export PATH="$GENESIS_HOME/bin:$PATH" +export PATH="$GENESIS_HOME/gui/bin:$PATH" +/bin/rm -rf $GENESIS_HOME/PerlLibs/ExtrasForOldPerlDistributions/Compress + +# install mflowgen +git clone https://github.com/cornell-brg/mflowgen +cd mflowgen +pip install -e . +cd .. + +# install OpenRAM +git clone https://github.com/VLSIDA/OpenRAM.git +export OPENRAM_HOME=`realpath OpenRAM/compiler` +export OPENRAM_TECH=`realpath OpenRAM/technology` + +# install dragonphy +pip install -e . + +# make dependencies for design +# TODO: should other views be used as well? +python make.py --view asic +python make.py --view fpga +python make.py --view cpu + +# run mflowgen +mkdir -p build/mflowgen_dragonphy_top +cd build/mflowgen_dragonphy_top +mflowgen run --design ../../designs/dragonphy_top +make synopsys-dc-synthesis +cd ../.. \ No newline at end of file diff --git a/regress.sh b/regress.sh index 01768d4c..d4b0f8f4 100644 --- a/regress.sh +++ b/regress.sh @@ -14,12 +14,6 @@ export PATH="$GENESIS_HOME/gui/bin:$PATH" git clone --single-branch --branch pwl_cos https://github.com/StanfordVLSI/DaVE.git export mLINGUA_DIR=`realpath DaVE/mLingua` -# install mflowgen -git clone https://github.com/cornell-brg/mflowgen -cd mflowgen -pip install -e . -cd .. - # install dragonphy pip install -e . @@ -34,30 +28,4 @@ pip install pytest pytest-cov # run tests and upload coverage # pytest tests -s -v -r s --cov-report=xml --cov=dragonphy --durations=0 -# bash <(curl -s https://codecov.io/bash) - -# run mflowgen as long as we're not on the FPGA server -if [ -z "$FPGA_SERVER" ] -then - git clone https://github.com/VLSIDA/OpenRAM.git - export OPENRAM_HOME=`realpath OpenRAM/compiler` - export OPENRAM_TECH=`realpath OpenRAM/technology` - - mkdir -p build/mflowgen_dragonphy_top - cd build/mflowgen_dragonphy_top - mflowgen run --design ../../designs/dragonphy_top - make synopsys-dc-synthesis - cd ../.. - - mkdir -p build/mflowgen_jtag - cd build/mflowgen_jtag - mflowgen run --design ../../designs/jtag - make synopsys-dc-synthesis - cd ../.. - - mkdir -p build/mflowgen_weight_manager - cd build/mflowgen_weight_manager - mflowgen run --design ../../designs/weight_manager - make synopsys-dc-synthesis - cd ../.. -fi +# bash <(curl -s https://codecov.io/bash) \ No newline at end of file diff --git a/synthesis/scripts/QTM/analog_core.qtm.tcl b/synthesis/scripts/QTM/analog_core.qtm.tcl new file mode 100644 index 00000000..affbb156 --- /dev/null +++ b/synthesis/scripts/QTM/analog_core.qtm.tcl @@ -0,0 +1,1665 @@ +create_qtm_model analog_core +create_qtm_port -type input { rx_inp } +set_qtm_port_load -value 0.010000 { rx_inp } +create_qtm_port -type input { rx_inn } +set_qtm_port_load -value 0.010000 { rx_inn } +create_qtm_port -type input { Vcm } +set_qtm_port_load -value 0.010000 { Vcm } +create_qtm_port -type input { rx_inp_test } +set_qtm_port_load -value 0.010000 { rx_inp_test } +create_qtm_port -type input { rx_inn_test } +set_qtm_port_load -value 0.010000 { rx_inn_test } +create_qtm_port -type clock { ext_clkp } +set_qtm_port_load -value 0.010000 { ext_clkp } +create_qtm_port -type input { ext_clkn } +set_qtm_port_load -value 0.010000 { ext_clkn } +create_qtm_port -type input { ext_clk_aux } +set_qtm_port_load -value 0.010000 { ext_clk_aux } +create_qtm_port -type input { ext_clk_test0 } +set_qtm_port_load -value 0.010000 { ext_clk_test0 } +create_qtm_port -type input { ext_clk_test1 } +set_qtm_port_load -value 0.010000 { ext_clk_test1 } +create_qtm_port -type input { clk_cdr } +set_qtm_port_load -value 0.010000 { clk_cdr } +create_qtm_port -type input { clk_async } +set_qtm_port_load -value 0.010000 { clk_async } +create_qtm_port -type input { ctl_pi[35:0] } +set_qtm_port_load -value 0.010000 { ctl_pi[35:0] } +create_qtm_port -type inout { Vcal } +set_qtm_port_load -value 0.010000 { Vcal } +create_qtm_port -type input { adbg_intf_i_rstb } +set_qtm_port_load -value 0.010000 { adbg_intf_i_rstb } +create_qtm_port -type input { adbg_intf_i_en_v2t } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_v2t } +create_qtm_port -type input { adbg_intf_i_en_slice[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_slice[15:0] } +create_qtm_port -type input { adbg_intf_i_ctl_v2tn[79:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_v2tn[79:0] } +create_qtm_port -type input { adbg_intf_i_ctl_v2tp[79:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_v2tp[79:0] } +create_qtm_port -type input { adbg_intf_i_init[31:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_init[31:0] } +create_qtm_port -type input { adbg_intf_i_ALWS_ON[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ALWS_ON[15:0] } +create_qtm_port -type input { adbg_intf_i_sel_pm_sign[31:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pm_sign[31:0] } +create_qtm_port -type input { adbg_intf_i_sel_pm_in[31:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pm_in[31:0] } +create_qtm_port -type input { adbg_intf_i_sel_clk_TDC[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_clk_TDC[15:0] } +create_qtm_port -type input { adbg_intf_i_en_pm[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_pm[15:0] } +create_qtm_port -type input { adbg_intf_i_en_v2t_clk_next[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_v2t_clk_next[15:0] } +create_qtm_port -type input { adbg_intf_i_en_sw_test[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_sw_test[15:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_late[31:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_late[31:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_early[31:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_early[31:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_TDC[79:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_TDC[79:0] } +create_qtm_port -type input { adbg_intf_i_en_gf } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_gf } +create_qtm_port -type input { adbg_intf_i_en_arb_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_arb_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_en_delay_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_delay_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_en_ext_Qperi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_ext_Qperi[3:0] } +create_qtm_port -type input { adbg_intf_i_en_pm_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_pm_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_en_cal_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_cal_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_ext_Qperi[19:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ext_Qperi[19:0] } +create_qtm_port -type input { adbg_intf_i_sel_pm_sign_pi[7:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pm_sign_pi[7:0] } +create_qtm_port -type input { adbg_intf_i_del_inc[127:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_del_inc[127:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_slice[7:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_slice[7:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_sw[7:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_sw[7:0] } +create_qtm_port -type input { adbg_intf_i_disable_state[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_disable_state[3:0] } +create_qtm_port -type input { adbg_intf_i_en_clk_sw[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_clk_sw[3:0] } +create_qtm_port -type input { adbg_intf_i_en_meas_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_meas_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_sel_meas_pi[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_meas_pi[3:0] } +create_qtm_port -type input { adbg_intf_i_en_slice_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_slice_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_ctl_v2tn_rep[9:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_v2tn_rep[9:0] } +create_qtm_port -type input { adbg_intf_i_ctl_v2tp_rep[9:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_v2tp_rep[9:0] } +create_qtm_port -type input { adbg_intf_i_init_rep[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_init_rep[3:0] } +create_qtm_port -type input { adbg_intf_i_ALWS_ON_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ALWS_ON_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_sel_pm_sign_rep[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pm_sign_rep[3:0] } +create_qtm_port -type input { adbg_intf_i_sel_pm_in_rep[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pm_in_rep[3:0] } +create_qtm_port -type input { adbg_intf_i_sel_clk_TDC_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_clk_TDC_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_en_pm_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_pm_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_en_v2t_clk_next_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_v2t_clk_next_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_en_sw_test_rep[1:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_sw_test_rep[1:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_late_rep[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_late_rep[3:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_early_rep[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_early_rep[3:0] } +create_qtm_port -type input { adbg_intf_i_ctl_dcdl_TDC_rep[9:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_dcdl_TDC_rep[9:0] } + +#create_qtm_port -type input { adbg_intf_i_disable_ibuf_async } +#set_qtm_port_load -value 0.010000 { adbg_intf_i_disable_ibuf_async } +#create_qtm_port -type input { adbg_intf_i_disable_ibuf_aux } +#set_qtm_port_load -value 0.010000 { adbg_intf_i_disable_ibuf_aux } +#create_qtm_port -type input { adbg_intf_i_disable_ibuf_test0 } +#set_qtm_port_load -value 0.010000 { adbg_intf_i_disable_ibuf_test0 } +#create_qtm_port -type input { adbg_intf_i_disable_ibuf_test1 } +#set_qtm_port_load -value 0.010000 { adbg_intf_i_disable_ibuf_test1 } + +create_qtm_port -type input { adbg_intf_i_en_inbuf } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_inbuf } +create_qtm_port -type input { adbg_intf_i_sel_inbuf_in } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_inbuf_in } +create_qtm_port -type input { adbg_intf_i_bypass_inbuf_div } +set_qtm_port_load -value 0.010000 { adbg_intf_i_bypass_inbuf_div } +create_qtm_port -type input { adbg_intf_i_inbuf_ndiv[2:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_inbuf_ndiv[2:0] } +create_qtm_port -type input { adbg_intf_i_en_inbuf_meas } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_inbuf_meas } +create_qtm_port -type input { adbg_intf_i_en_biasgen[3:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_biasgen[3:0] } +create_qtm_port -type input { adbg_intf_i_ctl_biasgen[15:0] } +set_qtm_port_load -value 0.010000 { adbg_intf_i_ctl_biasgen[15:0] } +create_qtm_port -type input { adbg_intf_i_sel_pfd_in } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pfd_in } +create_qtm_port -type input { adbg_intf_i_sel_pfd_in_meas } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_pfd_in_meas } +create_qtm_port -type input { adbg_intf_i_en_pfd_inp_meas } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_pfd_inp_meas } +create_qtm_port -type input { adbg_intf_i_en_pfd_inn_meas } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_pfd_inn_meas } +create_qtm_port -type input { adbg_intf_i_sel_del_out } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_del_out } +create_qtm_port -type input { adbg_intf_i_sel_del_out_pi } +set_qtm_port_load -value 0.010000 { adbg_intf_i_sel_del_out_pi } +create_qtm_port -type input { adbg_intf_i_en_del_out_pi } +set_qtm_port_load -value 0.010000 { adbg_intf_i_en_del_out_pi } +set_qtm_port_drive -value 1.000000 { Vcal } +create_qtm_port -type output { clk_adc } +set_qtm_port_drive -value 1.000000 { clk_adc } +create_qtm_port -type output { adder_out[127:0] } +set_qtm_port_drive -value 1.000000 { adder_out[127:0] } +create_qtm_port -type output { sign_out[15:0] } +set_qtm_port_drive -value 1.000000 { sign_out[15:0] } +create_qtm_port -type output { adder_out_rep[15:0] } +set_qtm_port_drive -value 1.000000 { adder_out_rep[15:0] } +create_qtm_port -type output { sign_out_rep[1:0] } +set_qtm_port_drive -value 1.000000 { sign_out_rep[1:0] } +create_qtm_port -type output { adbg_intf_i_pm_out[319:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pm_out[319:0] } +create_qtm_port -type output { adbg_intf_i_del_out[15:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_del_out[15:0] } +create_qtm_port -type output { adbg_intf_i_pm_out_pi[79:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pm_out_pi[79:0] } +create_qtm_port -type output { adbg_intf_i_del_out_pi } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_del_out_pi } +create_qtm_port -type output { adbg_intf_i_cal_out_pi[3:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_cal_out_pi[3:0] } +create_qtm_port -type output { adbg_intf_i_Qperi[19:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_Qperi[19:0] } +create_qtm_port -type output { adbg_intf_i_max_sel_mux[19:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_max_sel_mux[19:0] } +create_qtm_port -type output { adbg_intf_i_pi_out_meas[3:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pi_out_meas[3:0] } +create_qtm_port -type output { adbg_intf_i_pm_out_rep[39:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pm_out_rep[39:0] } +create_qtm_port -type output { adbg_intf_i_del_out_rep[1:0] } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_del_out_rep[1:0] } +create_qtm_port -type output { adbg_intf_i_inbuf_out_meas } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_inbuf_out_meas } +create_qtm_port -type output { adbg_intf_i_pfd_inp_meas } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pfd_inp_meas } +create_qtm_port -type output { adbg_intf_i_pfd_inn_meas } +set_qtm_port_drive -value 1.000000 { adbg_intf_i_pfd_inn_meas } + +create_qtm_delay_arc -from { ext_clkp } -to { Vcal } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { Vcal } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { clk_adc } -from_edge rise -to_edge rise -value 0.000000 +create_qtm_delay_arc -from { ext_clkp } -to { clk_adc } -from_edge rise -to_edge fall -value 0.000000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[319] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[319] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[318] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[318] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[317] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[317] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[316] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[316] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[315] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[315] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[314] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[314] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[313] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[313] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[312] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[312] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[311] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[311] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[310] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[310] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[309] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[309] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[308] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[308] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[307] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[307] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[306] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[306] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[305] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[305] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[304] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[304] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[303] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[303] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[302] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[302] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[301] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[301] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[300] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[300] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[299] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[299] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[298] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[298] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[297] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[297] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[296] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[296] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[295] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[295] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[294] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[294] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[293] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[293] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[292] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[292] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[291] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[291] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[290] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[290] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[289] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[289] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[288] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[288] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[287] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[287] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[286] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[286] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[285] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[285] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[284] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[284] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[283] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[283] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[282] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[282] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[281] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[281] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[280] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[280] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[279] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[279] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[278] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[278] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[277] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[277] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[276] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[276] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[275] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[275] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[274] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[274] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[273] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[273] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[272] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[272] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[271] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[271] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[270] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[270] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[269] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[269] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[268] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[268] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[267] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[267] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[266] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[266] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[265] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[265] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[264] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[264] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[263] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[263] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[262] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[262] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[261] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[261] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[260] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[260] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[259] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[259] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[258] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[258] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[257] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[257] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[256] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[256] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[255] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[255] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[254] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[254] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[253] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[253] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[252] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[252] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[251] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[251] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[250] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[250] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[249] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[249] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[248] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[248] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[247] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[247] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[246] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[246] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[245] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[245] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[244] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[244] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[243] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[243] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[242] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[242] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[241] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[241] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[240] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[240] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[239] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[239] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[238] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[238] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[237] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[237] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[236] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[236] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[235] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[235] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[234] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[234] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[233] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[233] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[232] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[232] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[231] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[231] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[230] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[230] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[229] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[229] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[228] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[228] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[227] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[227] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[226] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[226] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[225] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[225] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[224] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[224] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[223] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[223] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[222] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[222] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[221] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[221] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[220] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[220] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[219] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[219] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[218] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[218] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[217] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[217] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[216] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[216] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[215] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[215] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[214] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[214] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[213] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[213] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[212] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[212] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[211] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[211] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[210] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[210] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[209] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[209] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[208] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[208] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[207] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[207] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[206] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[206] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[205] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[205] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[204] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[204] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[203] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[203] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[202] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[202] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[201] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[201] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[200] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[200] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[199] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[199] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[198] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[198] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[197] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[197] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[196] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[196] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[195] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[195] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[194] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[194] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[193] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[193] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[192] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[192] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[191] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[191] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[190] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[190] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[189] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[189] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[188] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[188] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[187] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[187] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[186] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[186] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[185] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[185] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[184] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[184] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[183] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[183] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[182] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[182] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[181] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[181] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[180] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[180] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[179] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[179] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[178] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[178] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[177] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[177] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[176] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[176] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[175] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[175] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[174] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[174] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[173] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[173] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[172] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[172] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[171] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[171] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[170] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[170] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[169] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[169] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[168] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[168] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[167] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[167] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[166] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[166] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[165] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[165] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[164] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[164] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[163] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[163] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[162] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[162] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[161] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[161] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[160] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[160] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[159] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[159] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[158] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[158] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[157] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[157] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[156] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[156] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[155] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[155] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[154] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[154] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[153] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[153] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[152] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[152] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[151] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[151] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[150] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[150] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[149] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[149] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[148] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[148] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[147] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[147] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[146] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[146] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[145] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[145] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[144] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[144] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[143] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[143] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[142] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[142] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[141] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[141] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[140] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[140] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[139] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[139] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[138] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[138] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[137] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[137] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[136] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[136] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[135] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[135] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[134] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[134] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[133] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[133] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[132] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[132] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[131] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[131] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[130] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[130] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[129] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[129] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[128] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[128] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[127] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[127] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[126] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[126] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[125] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[125] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[124] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[124] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[123] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[123] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[122] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[122] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[121] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[121] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[120] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[120] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[119] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[119] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[118] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[118] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[117] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[117] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[116] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[116] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[115] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[115] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[114] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[114] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[113] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[113] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[112] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[112] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[111] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[111] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[110] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[110] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[109] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[109] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[108] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[108] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[107] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[107] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[106] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[106] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[105] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[105] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[104] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[104] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[103] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[103] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[102] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[102] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[101] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[101] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[100] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[100] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[99] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[99] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[98] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[98] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[97] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[97] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[96] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[96] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[95] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[95] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[94] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[94] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[93] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[93] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[92] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[92] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[91] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[91] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[90] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[90] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[89] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[89] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[88] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[88] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[87] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[87] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[86] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[86] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[85] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[85] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[84] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[84] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[83] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[83] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[82] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[82] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[81] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[81] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[80] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[80] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[79] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[79] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[78] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[78] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[77] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[77] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[76] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[76] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[75] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[75] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[74] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[74] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[73] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[73] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[72] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[72] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[71] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[71] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[70] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[70] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[69] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[69] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[68] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[68] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[67] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[67] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[66] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[66] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[65] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[65] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[64] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[64] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[63] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[63] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[62] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[62] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[61] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[61] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[60] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[60] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[59] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[59] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[58] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[58] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[57] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[57] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[56] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[56] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[55] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[55] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[54] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[54] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[53] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[53] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[52] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[52] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[51] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[51] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[50] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[50] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[49] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[49] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[48] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[48] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[47] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[47] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[46] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[46] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[45] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[45] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[44] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[44] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[43] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[43] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[42] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[42] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[41] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[41] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[40] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[40] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[39] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[39] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[38] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[38] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[37] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[37] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[36] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[36] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[35] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[35] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[34] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[34] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[33] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[33] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[32] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[32] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[31] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[31] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[30] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[30] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[29] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[29] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[28] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[28] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[27] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[27] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[26] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[26] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[25] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[25] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[24] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[24] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[23] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[23] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[22] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[22] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[21] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[21] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[20] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[20] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[19] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[19] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[18] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[18] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[17] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[17] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[16] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[16] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[79] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[79] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[78] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[78] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[77] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[77] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[76] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[76] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[75] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[75] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[74] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[74] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[73] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[73] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[72] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[72] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[71] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[71] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[70] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[70] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[69] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[69] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[68] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[68] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[67] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[67] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[66] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[66] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[65] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[65] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[64] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[64] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[63] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[63] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[62] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[62] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[61] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[61] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[60] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[60] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[59] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[59] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[58] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[58] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[57] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[57] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[56] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[56] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[55] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[55] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[54] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[54] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[53] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[53] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[52] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[52] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[51] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[51] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[50] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[50] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[49] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[49] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[48] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[48] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[47] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[47] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[46] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[46] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[45] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[45] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[44] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[44] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[43] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[43] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[42] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[42] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[41] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[41] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[40] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[40] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[39] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[39] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[38] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[38] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[37] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[37] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[36] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[36] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[35] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[35] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[34] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[34] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[33] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[33] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[32] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[32] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[31] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[31] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[30] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[30] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[29] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[29] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[28] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[28] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[27] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[27] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[26] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[26] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[25] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[25] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[24] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[24] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[23] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[23] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[22] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[22] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[21] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[21] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[20] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[20] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[19] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[19] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[18] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[18] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[17] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[17] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[16] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[16] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_pi[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_pi } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_pi } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_cal_out_pi[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[19] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[19] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[18] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[18] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[17] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[17] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[16] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[16] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_Qperi[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[19] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[19] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[18] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[18] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[17] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[17] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[16] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[16] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_max_sel_mux[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pi_out_meas[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[39] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[39] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[38] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[38] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[37] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[37] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[36] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[36] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[35] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[35] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[34] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[34] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[33] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[33] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[32] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[32] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[31] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[31] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[30] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[30] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[29] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[29] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[28] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[28] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[27] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[27] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[26] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[26] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[25] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[25] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[24] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[24] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[23] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[23] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[22] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[22] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[21] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[21] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[20] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[20] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[19] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[19] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[18] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[18] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[17] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[17] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[16] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[16] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[15] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[15] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[14] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[14] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[13] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[13] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[12] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[12] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[11] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[11] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[10] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[10] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[9] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[9] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[8] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[8] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[7] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[7] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[6] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[6] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[5] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[5] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[4] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[4] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[3] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[3] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[2] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[2] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[1] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[1] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[0] } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[0] } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_inbuf_out_meas } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_inbuf_out_meas } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pfd_inp_meas } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pfd_inp_meas } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pfd_inn_meas } -from_edge rise -to_edge rise -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pfd_inn_meas } -from_edge rise -to_edge fall -value 0.020000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[0] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[1] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[1] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[2] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[2] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[3] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[3] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[4] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[4] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[5] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[5] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[6] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[6] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[7] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[7] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[0] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[8] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[8] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[9] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[9] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[10] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[10] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[11] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[11] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[12] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[12] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[13] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[13] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[14] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[14] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[15] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[15] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[1] } -from_edge rise -to_edge rise -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[1] } -from_edge rise -to_edge fall -value 0.112500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[16] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[16] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[17] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[17] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[18] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[18] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[19] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[19] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[20] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[20] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[21] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[21] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[22] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[22] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[23] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[23] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[2] } -from_edge rise -to_edge rise -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[2] } -from_edge rise -to_edge fall -value 0.175000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[24] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[24] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[25] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[25] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[26] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[26] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[27] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[27] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[28] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[28] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[29] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[29] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[30] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[30] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[31] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[31] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[3] } -from_edge rise -to_edge rise -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[3] } -from_edge rise -to_edge fall -value 0.237500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[32] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[32] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[33] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[33] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[34] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[34] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[35] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[35] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[36] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[36] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[37] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[37] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[38] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[38] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[39] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[39] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[4] } -from_edge rise -to_edge rise -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[4] } -from_edge rise -to_edge fall -value 0.300000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[40] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[40] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[41] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[41] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[42] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[42] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[43] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[43] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[44] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[44] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[45] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[45] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[46] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[46] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[47] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[47] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[5] } -from_edge rise -to_edge rise -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[5] } -from_edge rise -to_edge fall -value 0.362500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[48] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[48] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[49] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[49] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[50] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[50] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[51] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[51] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[52] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[52] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[53] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[53] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[54] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[54] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[55] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[55] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[6] } -from_edge rise -to_edge rise -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[6] } -from_edge rise -to_edge fall -value 0.425000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[56] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[56] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[57] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[57] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[58] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[58] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[59] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[59] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[60] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[60] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[61] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[61] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[62] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[62] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[63] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[63] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[7] } -from_edge rise -to_edge rise -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[7] } -from_edge rise -to_edge fall -value 0.487500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[64] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[64] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[65] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[65] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[66] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[66] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[67] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[67] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[68] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[68] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[69] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[69] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[70] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[70] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[71] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[71] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[8] } -from_edge rise -to_edge rise -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[8] } -from_edge rise -to_edge fall -value 0.550000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[72] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[72] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[73] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[73] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[74] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[74] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[75] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[75] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[76] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[76] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[77] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[77] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[78] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[78] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[79] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[79] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[9] } -from_edge rise -to_edge rise -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[9] } -from_edge rise -to_edge fall -value 0.612500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[80] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[80] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[81] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[81] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[82] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[82] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[83] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[83] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[84] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[84] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[85] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[85] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[86] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[86] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[87] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[87] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[10] } -from_edge rise -to_edge rise -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[10] } -from_edge rise -to_edge fall -value 0.675000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[88] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[88] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[89] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[89] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[90] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[90] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[91] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[91] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[92] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[92] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[93] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[93] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[94] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[94] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[95] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[95] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[11] } -from_edge rise -to_edge rise -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[11] } -from_edge rise -to_edge fall -value 0.737500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[96] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[96] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[97] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[97] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[98] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[98] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[99] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[99] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[100] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[100] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[101] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[101] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[102] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[102] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[103] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[103] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[12] } -from_edge rise -to_edge rise -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[12] } -from_edge rise -to_edge fall -value 0.800000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[104] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[104] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[105] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[105] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[106] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[106] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[107] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[107] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[108] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[108] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[109] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[109] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[110] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[110] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[111] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[111] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[13] } -from_edge rise -to_edge rise -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[13] } -from_edge rise -to_edge fall -value 0.862500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[112] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[112] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[113] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[113] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[114] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[114] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[115] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[115] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[116] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[116] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[117] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[117] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[118] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[118] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[119] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[119] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[14] } -from_edge rise -to_edge rise -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[14] } -from_edge rise -to_edge fall -value 0.925000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[120] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[120] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[121] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[121] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[122] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[122] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[123] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[123] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[124] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[124] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[125] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[125] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[126] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[126] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[127] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out[127] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[15] } -from_edge rise -to_edge rise -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out[15] } -from_edge rise -to_edge fall -value 0.987500 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[15] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[15] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[14] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[14] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[13] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[13] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[12] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[12] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[11] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[11] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[10] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[10] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[9] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[9] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[8] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[8] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[7] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[7] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[6] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[6] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[5] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[5] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[4] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[4] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[3] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[3] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[2] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[2] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[1] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[1] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adder_out_rep[0] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[1] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[1] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { sign_out_rep[0] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[39] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[39] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[38] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[38] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[37] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[37] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[36] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[36] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[35] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[35] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[34] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[34] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[33] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[33] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[32] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[32] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[31] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[31] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[30] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[30] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[29] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[29] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[28] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[28] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[27] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[27] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[26] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[26] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[25] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[25] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[24] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[24] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[23] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[23] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[22] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[22] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[21] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[21] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[20] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[20] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[19] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[19] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[18] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[18] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[17] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[17] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[16] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[16] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[15] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[15] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[14] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[14] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[13] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[13] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[12] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[12] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[11] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[11] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[10] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[10] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[9] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[9] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[8] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[8] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[7] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[7] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[6] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[6] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[5] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[5] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[4] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[4] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[3] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[3] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[2] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[2] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[1] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[1] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_pm_out_rep[0] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[1] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[1] } -from_edge rise -to_edge fall -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[0] } -from_edge rise -to_edge rise -value 0.050000 +create_qtm_delay_arc -from { ext_clkp } -to { adbg_intf_i_del_out_rep[0] } -from_edge rise -to_edge fall -value 0.050000 + +report_qtm_model diff --git a/synthesis/scripts/QTM/butterphy_top.qtm.tcl b/synthesis/scripts/QTM/butterphy_top.qtm.tcl new file mode 100644 index 00000000..fe490cff --- /dev/null +++ b/synthesis/scripts/QTM/butterphy_top.qtm.tcl @@ -0,0 +1,8 @@ +create_qtm_model butterphy_top +create_qtm_port {ext_Vcal ext_rx_inp ext_rx_inn ext_Vcm ext_rx_inp_test ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp ext_clkn ext_rstb ext_dump_start jtag_intf_i_phy_tdi jtag_intf_i_phy_tck jtag_intf_i_phy_tms jtag_intf_i_phy_trst_n} -type input +create_qtm_port { clk_out_p clk_out_n clk_trig_p clk_trig_n jtag_intf_i_phy_tdo } -type output +set_qtm_port_load {ext_Vcal ext_rx_inp ext_rx_inn ext_Vcm ext_rx_inp_test ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp ext_clkn ext_rstb ext_dump_start jtag_intf_i_phy_tdi jtag_intf_i_phy_tck jtag_intf_i_phy_tms jtag_intf_i_phy_trst_n} -value 0.1 +set_qtm_port_drive {clk_out_p clk_out_n clk_trig_p clk_trig_n jtag_intf_i_phy_tdo} -value 1 +redirect qtm.rpt report_qtm_model +save_qtm_model -format {lib db} -library_cell +exit diff --git a/synthesis/scripts/QTM/output_buffer.qtm.tcl b/synthesis/scripts/QTM/output_buffer.qtm.tcl new file mode 100644 index 00000000..2c1eed31 --- /dev/null +++ b/synthesis/scripts/QTM/output_buffer.qtm.tcl @@ -0,0 +1,46 @@ +create_qtm_model output_buffer + +# inputs +create_qtm_port { \ + bypass_out_div \ + bypass_trig_div \ + en_outbuff \ + en_trigbuff \ + sel_trigbuff[3:0] \ + bufferend_signals[15:0] \ + Ndiv_trigbuff[2:0] \ + Ndiv_outbuff[2:0] \ + sel_outbuff[3:0] \ +} -type input + +# outputs +create_qtm_port { \ + clock_out_n \ + clock_out_p \ + trigg_out_n \ + trigg_out_p \ +} -type output + +set_qtm_port_load { \ + bypass_out_div \ + bypass_trig_div \ + en_outbuff \ + en_trigbuff \ + sel_trigbuff[3:0] \ + bufferend_signals[15:0] \ + Ndiv_trigbuff[2:0] \ + Ndiv_outbuff[2:0] \ + sel_outbuff[3:0] \ +} -value 0.02 + +set_qtm_port_drive { \ + clock_out_n \ + clock_out_p \ + trigg_out_n \ + trigg_out_p \ +} -value 1 + +redirect qtm.rpt report_qtm_model +save_qtm_model -format {lib db} -library_cell + +exit diff --git a/synthesis/scripts/QTM/run.sh b/synthesis/scripts/QTM/run.sh new file mode 100755 index 00000000..7bc84a21 --- /dev/null +++ b/synthesis/scripts/QTM/run.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +module load pts +pt_shell -f analog_core.qtm.tcl diff --git a/synthesis/scripts/QTM/run_lc.tcl b/synthesis/scripts/QTM/run_lc.tcl new file mode 100644 index 00000000..f61272a3 --- /dev/null +++ b/synthesis/scripts/QTM/run_lc.tcl @@ -0,0 +1,6 @@ +# lc_shell -f run_lc.tcl +# + +read_lib analog_core.lib +write_lib analog_core -format db -output analog_core.db +exit diff --git a/synthesis/scripts/QTM/run_pt.tcl b/synthesis/scripts/QTM/run_pt.tcl new file mode 100644 index 00000000..79e923ac --- /dev/null +++ b/synthesis/scripts/QTM/run_pt.tcl @@ -0,0 +1,13 @@ +######################################### +######################################### +# build QTM model for analog_core module +######################################### +######################################### + +source pt_qtm.tcl +#report_qtm_model +#current_design analog_core +#set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA +report_units +save_qtm_model -format lib -library_cell +exit From 5a64d8a4d1ee293500113bbe969ecaa4053cdf28 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 7 May 2020 10:47:57 -0700 Subject: [PATCH 13/16] update digital_core to that of the master branch --- vlog/new_chip_src/digital_core/digital_core.sv | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/vlog/new_chip_src/digital_core/digital_core.sv b/vlog/new_chip_src/digital_core/digital_core.sv index aa8d7094..1e9ee88c 100644 --- a/vlog/new_chip_src/digital_core/digital_core.sv +++ b/vlog/new_chip_src/digital_core/digital_core.sv @@ -31,7 +31,7 @@ module digital_core import const_pack::*; ( prbs_debug_intf pdbg_intf_i (); wme_debug_intf wdbg_intf_i (); - + // internal signals wire logic rstb; @@ -211,7 +211,6 @@ module digital_core import const_pack::*; ( assign dsp_dbg_intf_i.mlsd_shift = ddbg_intf_i.mlsd_shift; assign dsp_dbg_intf_i.thresh = ddbg_intf_i.cmp_thresh; - `ifndef SYNTHESIS_DEBUG weight_manager #(.width(Nti), .depth(10), .bitwidth(10)) wme_ffe_i ( .data (wdbg_intf_i.wme_ffe_data), .inst (wdbg_intf_i.wme_ffe_inst), @@ -231,7 +230,6 @@ module digital_core import const_pack::*; ( .read_reg(wdbg_intf_i.wme_mlsd_read), .weights (dsp_dbg_intf_i.channel_est) ); - `endif dsp_backend dsp_i( .codes(adcout_unfolded[Nti-1:0]), @@ -354,7 +352,7 @@ module digital_core import const_pack::*; ( ); // JTAG - `ifndef SYNTHESIS_DEBUG + jtag jtag_i ( .clk(clk_adc), .rstb(ext_rstb), @@ -367,7 +365,6 @@ module digital_core import const_pack::*; ( .wdbg_intf_i(wdbg_intf_i), .jtag_intf_i(jtag_intf_i) ); - `endif endmodule From c20c3a5a9c03fa5259aea9fdf70e9ca1a59765b2 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 7 May 2020 13:21:52 -0700 Subject: [PATCH 14/16] try re-running tests --- .buildkite/pipeline.yml | 1 + .../construct-commercial-full.py | 18 ++- .../dragonphy_top/mc-gen-sram/configure.yml | 20 +++ .../dragonphy_top/mc-gen-sram/gen_srams.sh | 41 ++++++ .../dragonphy_top/mc-gen-sram/lib2db/Makefile | 10 ++ .../mc-gen-sram/lib2db/generate_db.tcl | 20 +++ .../openram-gen-sram/configure.yml | 48 ++----- .../openram-gen-sram/gen_config.py | 25 ++++ .../openram-gen-sram/gen_constraints.py | 132 ------------------ .../openram-gen-sram/generate_db.tcl | 9 ++ .../openram-gen-sram/myconfig.py | 15 -- designs/dragonphy_top/qtm/configure.yml | 18 ++- .../dragonphy_top/qtm/output_buffer.qtm.tcl | 2 +- designs/dragonphy_top/qtm/run_dc.tcl | 8 -- designs/dragonphy_top/rtl/configure.yml | 1 + designs/dragonphy_top/rtl/gen_rtl.py | 2 +- dragonphy/views.py | 37 +++-- regress.sh | 4 +- tests/test_config/test_config.py | 2 +- vlog/new_chip_src_freepdk45/sram/sram.sv | 21 +++ vlog/new_chip_src_tsmc16/sram/sram.sv | 30 ++++ .../new_chip_stubs/analog_core/analog_core.sv | 4 +- vlog/new_chip_stubs/sram.sv | 12 -- 23 files changed, 247 insertions(+), 233 deletions(-) create mode 100644 designs/dragonphy_top/mc-gen-sram/configure.yml create mode 100644 designs/dragonphy_top/mc-gen-sram/gen_srams.sh create mode 100644 designs/dragonphy_top/mc-gen-sram/lib2db/Makefile create mode 100644 designs/dragonphy_top/mc-gen-sram/lib2db/generate_db.tcl create mode 100644 designs/dragonphy_top/openram-gen-sram/gen_config.py delete mode 100644 designs/dragonphy_top/openram-gen-sram/gen_constraints.py create mode 100644 designs/dragonphy_top/openram-gen-sram/generate_db.tcl delete mode 100644 designs/dragonphy_top/openram-gen-sram/myconfig.py delete mode 100644 designs/dragonphy_top/qtm/run_dc.tcl create mode 100644 vlog/new_chip_src_freepdk45/sram/sram.sv create mode 100644 vlog/new_chip_src_tsmc16/sram/sram.sv delete mode 100644 vlog/new_chip_stubs/sram.sv diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 09e6e310..8ecda5e8 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -29,6 +29,7 @@ steps: source /cad/modules/tcl/init/bash module load base xcelium lc pts syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1 export BUILD_VIEW=asic + export DRAGONPHY_PROCESS=FREEPDK45 export FREEPDK45=/cad/freepdk/FreePDK45 printenv diff --git a/designs/dragonphy_top/construct-commercial-full.py b/designs/dragonphy_top/construct-commercial-full.py index 11089764..30acaf13 100644 --- a/designs/dragonphy_top/construct-commercial-full.py +++ b/designs/dragonphy_top/construct-commercial-full.py @@ -13,7 +13,7 @@ def construct(): if 'DRAGONPHY_PROCESS' in os.environ: DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] else: - DRAGONPHY_PROCESS = 'FREEPDK45' + DRAGONPHY_PROCESS = 'TSMC16' g = Graph() @@ -65,7 +65,7 @@ def construct(): elif DRAGONPHY_PROCESS == 'TSMC16': parameters['adk_name'] = 'tsmc16' parameters['adk_view'] = 'stdview' - # use default timing parameters specified in configure.yml + # default parameters are for TSMC16, so no need to override them here else: raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') @@ -87,6 +87,13 @@ def construct(): dc = Step(this_dir + '/synopsys-dc-synthesis') qtm = Step(this_dir + '/qtm') + if DRAGONPHY_PROCESS == 'FREEPDK45': + sram = Step(this_dir + '/openram-gen-sram') + elif DRAGONPHY_PROCESS == 'TSMC16': + sram = Step(this_dir + '/mc-gen-sram') + else: + raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') + # Default steps info = Step( 'info', default=True ) @@ -108,7 +115,8 @@ def construct(): # Add *.db files to synthesis inputs dc.extend_inputs([ - 'output_buffer.db' + 'output_buffer_lib.db', + 'sram_tt.db' ]) #----------------------------------------------------------------------- @@ -118,8 +126,9 @@ def construct(): g.add_step( info ) g.add_step( rtl ) g.add_step( constraints ) - g.add_step( dc ) g.add_step( qtm ) + g.add_step( sram ) + g.add_step( dc ) g.add_step( iflow ) g.add_step( init ) g.add_step( power ) @@ -160,6 +169,7 @@ def construct(): g.connect_by_name( rtl, dc ) g.connect_by_name( constraints, dc ) g.connect_by_name( qtm, dc ) + g.connect_by_name( sram, dc ) g.connect_by_name( dc, iflow ) g.connect_by_name( dc, init ) diff --git a/designs/dragonphy_top/mc-gen-sram/configure.yml b/designs/dragonphy_top/mc-gen-sram/configure.yml new file mode 100644 index 00000000..fb7b19fa --- /dev/null +++ b/designs/dragonphy_top/mc-gen-sram/configure.yml @@ -0,0 +1,20 @@ +name: mc-gen-sram + +commands: + - bash gen_srams.sh + +outputs: + - sram.v + - sram_pwr.v + - sram.lef + - sram_tt.lib + - sram_tt.db + - sram.gds + - sram.spi + +parameters: + sram_word_size: 144 + sram_num_words: 1024 + sram_mux_size: 4 + sram_corner: "tt0p8v25c" + sram_partial_write: False \ No newline at end of file diff --git a/designs/dragonphy_top/mc-gen-sram/gen_srams.sh b/designs/dragonphy_top/mc-gen-sram/gen_srams.sh new file mode 100644 index 00000000..40dc2751 --- /dev/null +++ b/designs/dragonphy_top/mc-gen-sram/gen_srams.sh @@ -0,0 +1,41 @@ +# Adapted from Garnet + +# Note: you'll need to add a link called "mc" in the mc-sram-sram directory +# in order for this script to work + +# Write config file for the memory compiler +# This specifies the dimensions of the SRAM +echo "${sram_num_words}x${sram_word_size}m${mux_size}s" >> config.txt + +# Set some environment variables +export MC_HOME=mc/tsn16ffcllhdspsbsram_20131200_130a +export PATH="${PATH}:mc/MC2_2013.12.00.f/bin" + +# Determine the name of the SRAM +sram_name="ts1n16ffcllsblvtc${sram_num_words}x${sram_word_size}m${sram_mux_size}s" +if [ $sram_partial_write == True ]; then + sram_name+="w" +fi +sram_name+="_130a" + +# Build up the command to run the memory compiler +cmd="./mc/tsn16ffcllhdspsbsram_130a.pl -file config.txt -NonBIST -NonSLP -NonDSLP -NonSD" +if [ ! $sram_partial_write == True ]; then + cmd+=" -NonBWEB" +fi + +# Actually run the memory compiler +eval $cmd + +# Link output products from the memory compiler into the "outputs" folder +ln -s ../$sram_name/NLDM/${sram_name}_${sram_corner}.lib outputs/sram_tt.lib +ln -s ../$sram_name/GDSII/${sram_name}_m4xdh.gds outputs/sram.gds +ln -s ../$sram_name/LEF/${sram_name}_m4xdh.lef outputs/sram.lef +ln -s ../$sram_name/VERILOG/${sram_name}_pwr.v outputs/sram_pwr.v +ln -s ../$sram_name/VERILOG/${sram_name}.v outputs/sram.v +ln -s ../$sram_name/SPICE/${sram_name}.spi outputs/sram.spi + +# Run a separate script to generate a *.db file for the SRAM +cd lib2db/ +make +cd .. \ No newline at end of file diff --git a/designs/dragonphy_top/mc-gen-sram/lib2db/Makefile b/designs/dragonphy_top/mc-gen-sram/lib2db/Makefile new file mode 100644 index 00000000..3769b58d --- /dev/null +++ b/designs/dragonphy_top/mc-gen-sram/lib2db/Makefile @@ -0,0 +1,10 @@ +# From Garnet + +all: + rm -rf build + mkdir -p build + cd build && dc_shell-xg-t -64bit -output_log_file build.log -f ../generate_db.tcl | tee build.log + ln -sf build/foo.db + +clean: + rm -rf build foo.db \ No newline at end of file diff --git a/designs/dragonphy_top/mc-gen-sram/lib2db/generate_db.tcl b/designs/dragonphy_top/mc-gen-sram/lib2db/generate_db.tcl new file mode 100644 index 00000000..5591669c --- /dev/null +++ b/designs/dragonphy_top/mc-gen-sram/lib2db/generate_db.tcl @@ -0,0 +1,20 @@ +# Adapted from Garnet + +# Determine the name of the SRAM library +set sram_lib_name "ts1n16ffcllsblvtc$::env(num_words)x$::env(word_size)m$::env(mux_size)s" +if {$::env(partial_write)} { + set sram_lib_name "${sram_lib_name}w" +} +set sram_lib_name "${sram_lib_name}_$::env(corner)" + +# Enable library "write" mode -- this must be done before reading a library if +# the user intends to write a library +enable_write_lib_mode + +# Read the SRAM *.lib file (output of memory compiler) +read_lib ../../outputs/sram_tt.lib + +# Write a *.db file for the SRAM +write_lib -format db $sram_lib_name -output ../../outputs/sram_tt.db + +exit \ No newline at end of file diff --git a/designs/dragonphy_top/openram-gen-sram/configure.yml b/designs/dragonphy_top/openram-gen-sram/configure.yml index 9c869605..17a8d352 100644 --- a/designs/dragonphy_top/openram-gen-sram/configure.yml +++ b/designs/dragonphy_top/openram-gen-sram/configure.yml @@ -1,44 +1,18 @@ # Adapted from Garnet -name: constraints +name: openram-gen-sram commands: - - python gen_constraints.py - -outputs: - - constraints.tcl + - | + python gen_config.py + python $OPENRAM_HOME/openram.py myconfig + dc_shell-xg-t -f generate_db.tcl parameters: - # time in ns and capacitance in pF - - # Name of the design - design_name: undefined - - # Main clocks in the design - clk_retimer_period: 0.7 - clk_in_period: 0.7 - clk_jtag_period: 100.0 - - # Retimer clock uncertainty - clk_retimer_setup_uncertainty: 0.03 - clk_retimer_hold_uncertainty: 0.03 + sram_word_size: 144 + sram_num_words: 1024 + sram_tech_name: freepdk45 + sram_output_path: temp - # JTAG clock uncertainty - clk_jtag_setup_uncertainty: 1.0 - clk_jtag_hold_uncertainty: 0.03 - - # Capacitance and transition time - max_capacitance: 0.1 - max_transition: 0.2 - max_clock_transition: 0.1 - - # Clocks that can be monitored from analog_core - clk_hs_period: 0.25 - clk_hs_transition: 0.025 - - # I/O delays and transitions - digital_input_delay: 0.05 - digital_input_transition: 0.5 - input_transition: 0.03 - output_load: 0.02 - output_delay: 0.7 +outputs: + - sram_tt.db diff --git a/designs/dragonphy_top/openram-gen-sram/gen_config.py b/designs/dragonphy_top/openram-gen-sram/gen_config.py new file mode 100644 index 00000000..976fc7bc --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/gen_config.py @@ -0,0 +1,25 @@ +import os +e = os.environ + +OUTPUT = f"""\ +# Data word size +word_size = {e['sram_word_size']} + +# Number of words in the memory +num_words = {e['sram_num_words']} + +# Technology to use in $OPENRAM_TECH +tech_name = "{e['sram_tech_name']}" + +# You can use the technology nominal corner only +nominal_corner_only = True + +# Output directory for the results +output_path = "{e['sram_output_path']}" + +# Output file base name +output_name = "sram_{e['sram_word_size']}_{e['sram_num_words']}_{e['sram_tech_name']}" +""" + +with open('myconfig.py', 'w') as f: + f.write(OUTPUT) \ No newline at end of file diff --git a/designs/dragonphy_top/openram-gen-sram/gen_constraints.py b/designs/dragonphy_top/openram-gen-sram/gen_constraints.py deleted file mode 100644 index dffb48b1..00000000 --- a/designs/dragonphy_top/openram-gen-sram/gen_constraints.py +++ /dev/null @@ -1,132 +0,0 @@ -import os -from pathlib import Path - -OUTPUT_FILE = 'constraints.tcl' - -e = os.environ -output = f'''\ -# Modified from ButterPHY and Garnet constraints - -# Design constraints for synthesis -# time unit : ns -# cap unit: pF - -######### -# Params -######### - -# primary I/Os being treated as don't touch nets - -set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\ - ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\ - ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\ - ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}} - -set analog_net [get_pins ibuf_*/clk] - -set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\ - jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\ - jtag_intf_i.phy_trst_n}} - -######### -# Clocks -######### - -create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}] -create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp] -create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck] -set_dont_touch_network [get_pins {{iacore/clk_adc}}] -set_dont_touch_network [get_port jtag_intf_i.phy_tck] - -set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer -set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer -set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag -set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag - -########### -# Net const -########### - -set_max_capacitance {e["max_capacitance"]} [current_design] -set_max_transition {e["max_transition"]} [current_design] -set_max_transition {e["max_clock_transition"]} [all_clocks] - -set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\ - iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\ - iacore/*del_out_pi*}}] - -foreach x [get_object_name $hs_nets] {{ - create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x] - set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x] -}} - -echo [all_clocks] - -########### -# Analog nets -########### - -set_dont_touch_network [get_ports $analog_io] -set_dont_touch_network $analog_net -set_dont_touch_network [all_outputs] - -########### -# I/O const -########### - -set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs] -set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs] - -set_input_transition {e["input_transition"]} [all_inputs] -set_load {e["output_load"]} [all_outputs] -set_output_delay {e["output_delay"]} [all_outputs] - -############ -# False path -############ - -set_false_path -from clk_retimer -to clk_jtag -set_false_path -from clk_jtag -to clk_retimer - -################ -# DONT USE CELLS -################ - -# foreach lib $mvt_target_libs {{ -# set_dont_use [file rootname [file tail $lib]]/*D0BWP* -# }} - -# Settings from Garnet to consider -# (all commented out at the moment) - -# This constraint sets the input drive strength of the input pins of -# your design. We specifiy a specific standard cell which models what -# would be driving the inputs. This should usually be a small inverter -# which is reasonable if another block of on-chip logic is driving -# your inputs. - -# set_driving_cell -no_design_rule \\ -# -lib_cell $ADK_DRIVING_CELL [all_inputs] - -# Make all signals limit their fanout -# TODO: should this be included? -# set_max_fanout 20 {e["design_name"]} - -# sr 02/2020 -# haha IOPAD cells already have dont_touch property but not ANAIOPAD :( -# Without dont_touch, they disappear during dc-synthesis -# set_dont_touch [ get_cells ANAIOPAD* ] - -# sr 02/2020 -# Arg turns out not all IOPAD cells have dont_touch property I guess -# set_dont_touch [ get_cells IOPAD* ] -''' - -# create output directory -OUTPUT_DIR = Path('outputs') -OUTPUT_DIR.mkdir(exist_ok=True, parents=True) - -# write output text -with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: - f.write(output) - diff --git a/designs/dragonphy_top/openram-gen-sram/generate_db.tcl b/designs/dragonphy_top/openram-gen-sram/generate_db.tcl new file mode 100644 index 00000000..dfc543c0 --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/generate_db.tcl @@ -0,0 +1,9 @@ +# Modified from Garnet + +set sram_lib_name "sram_$::env(sram_word_size)_$::env(sram_num_words)_$::env(sram_tech_name)_TT_1p0V_25C" + +enable_write_lib_mode +read_lib "$::env(sram_output_path)/${sram_lib_name}.lib" +write_lib -format db "${sram_lib_name}_lib" -output outputs/sram_tt.db + +exit \ No newline at end of file diff --git a/designs/dragonphy_top/openram-gen-sram/myconfig.py b/designs/dragonphy_top/openram-gen-sram/myconfig.py deleted file mode 100644 index b700a906..00000000 --- a/designs/dragonphy_top/openram-gen-sram/myconfig.py +++ /dev/null @@ -1,15 +0,0 @@ -# Data word size -word_size = 144 -# Number of words in the memory -num_words = 1024 - -# Technology to use in $OPENRAM_TECH -tech_name = "freepdk45" - -# You can use the technology nominal corner only -nominal_corner_only = True - -# Output directory for the results -output_path = "temp" -# Output file base name -output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) \ No newline at end of file diff --git a/designs/dragonphy_top/qtm/configure.yml b/designs/dragonphy_top/qtm/configure.yml index 3040420a..c28c8c5b 100644 --- a/designs/dragonphy_top/qtm/configure.yml +++ b/designs/dragonphy_top/qtm/configure.yml @@ -1,12 +1,18 @@ -# Adapted from Garnet +# Adapted from Garnet and ButterPHY name: qtm commands: - - mkdir -p build - - mkdir -p outputs - - cd build && pt_shell -f ../output_buffer.qtm.tcl - - cd build && dc_shell-xg-t -f ../run_dc.tcl + - | + mkdir -p build + mkdir -p outputs + cd build + + mkdir -p output_buffer + cd output_buffer + pt_shell -f ../../output_buffer.qtm.tcl + cp output_buffer_lib.db ../../outputs/. + cd .. outputs: - - output_buffer.db + - output_buffer_lib.db diff --git a/designs/dragonphy_top/qtm/output_buffer.qtm.tcl b/designs/dragonphy_top/qtm/output_buffer.qtm.tcl index 683aa3f3..1744af57 100644 --- a/designs/dragonphy_top/qtm/output_buffer.qtm.tcl +++ b/designs/dragonphy_top/qtm/output_buffer.qtm.tcl @@ -41,6 +41,6 @@ set_qtm_port_drive { \ } -value 1 report_qtm_model -save_qtm_model -format lib -library_cell +save_qtm_model -format {lib db} -library_cell exit \ No newline at end of file diff --git a/designs/dragonphy_top/qtm/run_dc.tcl b/designs/dragonphy_top/qtm/run_dc.tcl deleted file mode 100644 index afe4c642..00000000 --- a/designs/dragonphy_top/qtm/run_dc.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# required in order to write libraries -enable_write_lib_mode - -# write the *.db for the output buffer -read_lib output_buffer.lib -write_lib -format db output_buffer -output ../outputs/output_buffer.db - -exit \ No newline at end of file diff --git a/designs/dragonphy_top/rtl/configure.yml b/designs/dragonphy_top/rtl/configure.yml index bba47d90..af45a78b 100644 --- a/designs/dragonphy_top/rtl/configure.yml +++ b/designs/dragonphy_top/rtl/configure.yml @@ -7,4 +7,5 @@ outputs: - design.v parameters: + adk_name: "tsmc16" design_name: None \ No newline at end of file diff --git a/designs/dragonphy_top/rtl/gen_rtl.py b/designs/dragonphy_top/rtl/gen_rtl.py index fffb1efb..471d194a 100644 --- a/designs/dragonphy_top/rtl/gen_rtl.py +++ b/designs/dragonphy_top/rtl/gen_rtl.py @@ -19,7 +19,7 @@ def resolve_include_file(name): # build up a list of source files src_files = [] src_files += [get_file('vlog/new_chip_src/jtag/jtag_intf.sv')] -src_files += get_deps_new_asic(TOP_CELL) +src_files += get_deps_new_asic(TOP_CELL, process=os.environ['adk_name']) # generate the output text output = '' diff --git a/dragonphy/views.py b/dragonphy/views.py index ad7c462b..b0de2fce 100644 --- a/dragonphy/views.py +++ b/dragonphy/views.py @@ -135,32 +135,45 @@ def get_deps(cell_name=None, view_order=None, override=None, return deps -def get_deps_new_asic(cell_name=None, impl_file=None): +def get_deps_new_asic(cell_name=None, impl_file=None, process='tsmc16'): + # List of views to override with stubs + override = { + 'input_buffer': 'new_chip_stubs', + 'analog_core': 'new_chip_stubs' + } + + # List of views to skip and replace with *.db files + skip = { + 'DW_tap', + 'output_buffer' + } + if process == 'freepdk-45nm': + override['sram'] = 'new_chip_src_freepdk45' + skip.add('sram_144_1024_freepdk45') + elif process == 'tsmc16': + raise Exception('The SRAM view for TSMC16 has not been implemented yet.') + else: + raise Exception(f'Unknown process: {process}') + + # Build up the dependency list deps = [] deps += get_deps( cell_name=cell_name, impl_file=impl_file, view_order=['new_pack', 'new_chip_src'], includes=[get_dir('inc/new_asic')], - override={ - # TODO: replace all of these with *.db files - 'sram': 'new_chip_stubs', - 'input_buffer': 'new_chip_stubs', - 'analog_core': 'new_chip_stubs' - }, - skip={ - # these blocks are defined from *.db files - 'DW_tap', - 'output_buffer' - } + override=override, + skip=skip ) + # manual modifications deps.insert(0, Directory.path() + '/build/new_chip_src/adapt_fir/ffe_gpack.sv') deps.insert(0, Directory.path() + '/build/new_chip_src/adapt_fir/cmp_gpack.sv') deps.insert(0, Directory.path() + '/build/new_chip_src/adapt_fir/mlsd_gpack.sv') deps.insert(0, Directory.path() + '/build/new_chip_src/adapt_fir/constant_gpack.sv') deps.insert(0, Directory.path() + '/vlog/new_pack/dsp_pack.sv') + # Return the dependencies return deps def get_deps_cpu_sim_new(cell_name=None, impl_file=None): diff --git a/regress.sh b/regress.sh index d4b0f8f4..29527df4 100644 --- a/regress.sh +++ b/regress.sh @@ -27,5 +27,5 @@ python make.py --view cpu pip install pytest pytest-cov # run tests and upload coverage -# pytest tests -s -v -r s --cov-report=xml --cov=dragonphy --durations=0 -# bash <(curl -s https://codecov.io/bash) \ No newline at end of file +pytest tests -s -v -r s --cov-report=xml --cov=dragonphy --durations=0 +bash <(curl -s https://codecov.io/bash) \ No newline at end of file diff --git a/tests/test_config/test_config.py b/tests/test_config/test_config.py index 23fdfc8d..1aab20b3 100644 --- a/tests/test_config/test_config.py +++ b/tests/test_config/test_config.py @@ -2,7 +2,7 @@ def test_new_asic(): print('Test New ASIC Config') - print(get_deps_new_asic('dragonphy_top')) + print(get_deps_new_asic('dragonphy_top', process='freepdk-45nm')) def test_new_chip_src_config(): print('Test New Chip Source Config') diff --git a/vlog/new_chip_src_freepdk45/sram/sram.sv b/vlog/new_chip_src_freepdk45/sram/sram.sv new file mode 100644 index 00000000..82c7a508 --- /dev/null +++ b/vlog/new_chip_src_freepdk45/sram/sram.sv @@ -0,0 +1,21 @@ +module sram #( + parameter integer ADR_BITS=10, + parameter integer DAT_BITS=144 +) ( + input wire logic CLK, + input wire logic CEB, + input wire logic WEB, + input wire logic [(ADR_BITS-1):0] A, + input wire logic [(DAT_BITS-1):0] D, + output wire logic [(DAT_BITS-1):0] Q +); + // instantiate the FreePDK macro + sram_144_1024_freepdk45 sram_i ( + .clk0(CLK), + .csb0(CEB), + .web0(WEB), + .addr0(A), + .din0(D), + .dout0(Q) + ); +endmodule diff --git a/vlog/new_chip_src_tsmc16/sram/sram.sv b/vlog/new_chip_src_tsmc16/sram/sram.sv new file mode 100644 index 00000000..45950129 --- /dev/null +++ b/vlog/new_chip_src_tsmc16/sram/sram.sv @@ -0,0 +1,30 @@ +module sram #( + parameter integer ADR_BITS=10, + parameter integer DAT_BITS=144 +) ( + input wire logic CLK, + input wire logic CEB, + input wire logic WEB, + input wire logic [(ADR_BITS-1):0] A, + input wire logic [(DAT_BITS-1):0] D, + output wire logic [(DAT_BITS-1):0] Q +); + // enable writing to all bits + logic [(DAT_BITS-1):0] BWEB; + assign BWEB = {(DAT_BITS-1){1'b0}}; + + // instantiate memory + TS1N16FFCLLSBLVTC1024X144M4SW memory ( + // user-provided signals + .CLK(CLK), + .CEB(CEB), + .WEB(WEB), + .A(A), + .D(D), + .Q(Q), + // additional connections + .BWEB(BWEB), + .RTSEL(2'b01), + .WTSEL(2'b00) + ); +endmodule diff --git a/vlog/new_chip_stubs/analog_core/analog_core.sv b/vlog/new_chip_stubs/analog_core/analog_core.sv index e74a4c1b..d2f382bb 100644 --- a/vlog/new_chip_stubs/analog_core/analog_core.sv +++ b/vlog/new_chip_stubs/analog_core/analog_core.sv @@ -16,10 +16,10 @@ module analog_core import const_pack::*; #( input wire logic ext_clk_test0, // (+) 4GHz clock input (from pad) input wire logic ext_clk_test1, // (-) 4GHz clock input (from pad) - input wire logic clk_cdr, // cdr loop filter clock (from DCORE) input wire logic clk_async, // asynchronous clock for phase measurement // (from DCORE) input wire logic [Npi-1:0] ctl_pi[Nout-1:0], // PI control code (from DCORE) + input wire logic ctl_valid, // PI control valid flag (from DCORE) input `real_t Vcal, // bias voltage for V2T (from pad) @@ -33,4 +33,4 @@ module analog_core import const_pack::*; #( acore_debug_intf.acore adbg_intf_i ); -endmodule +endmodule \ No newline at end of file diff --git a/vlog/new_chip_stubs/sram.sv b/vlog/new_chip_stubs/sram.sv deleted file mode 100644 index 917ad586..00000000 --- a/vlog/new_chip_stubs/sram.sv +++ /dev/null @@ -1,12 +0,0 @@ -module sram #( - parameter integer ADR_BITS=10, - parameter integer DAT_BITS=128 -) ( - input CLK, - input CEB, - input WEB, - input [(ADR_BITS-1):0] A, - input [(DAT_BITS-1):0] D, - output [(DAT_BITS-1):0] Q -); -endmodule From 4bd205ddd34b7d0d20425ec6aad525ae9a156deb Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 7 May 2020 13:47:46 -0700 Subject: [PATCH 15/16] speed up openram step --- .../openram-gen-sram/configure.yml | 13 +- .../openram-gen-sram/lib.openram | 321 ++++++++++ designs/jtag/.mflowgen.yml | 1 - designs/jtag/constraints/configure.yml | 23 - designs/jtag/constraints/constraints.tcl | 54 -- .../jtag/constraints/outputs/constraints.tcl | 1 - designs/jtag/construct-commercial-full.py | 177 ------ designs/jtag/rtl/configure.yml | 10 - designs/jtag/rtl/gen_rtl.py | 40 -- .../assertion_helpers.py | 67 -- .../jtag/synopsys-dc-synthesis/configure.yml | 93 --- designs/jtag/synopsys-dc-synthesis/dc.tcl | 598 ------------------ .../designer_interface.tcl | 90 --- .../jtag/synopsys-dc-synthesis/pre_synth.tcl | 49 -- designs/jtag/synopsys-dc-synthesis/run.sh | 114 ---- designs/weight_manager/.mflowgen.yml | 1 - .../weight_manager/constraints/configure.yml | 23 - .../constraints/constraints.tcl | 55 -- .../constraints/outputs/constraints.tcl | 1 - .../construct-commercial-full.py | 179 ------ designs/weight_manager/rtl/configure.yml | 10 - designs/weight_manager/rtl/gen_rtl.py | 34 - .../rtl/weight_manager_insts.sv | 26 - .../assertion_helpers.py | 67 -- .../synopsys-dc-synthesis/configure.yml | 93 --- .../synopsys-dc-synthesis/dc.tcl | 598 ------------------ .../designer_interface.tcl | 90 --- .../synopsys-dc-synthesis/pre_synth.tcl | 49 -- .../synopsys-dc-synthesis/run.sh | 114 ---- dragonphy/views.py | 3 +- tests/test_config/test_config.py | 8 +- 31 files changed, 339 insertions(+), 2663 deletions(-) create mode 100644 designs/dragonphy_top/openram-gen-sram/lib.openram delete mode 100644 designs/jtag/.mflowgen.yml delete mode 100644 designs/jtag/constraints/configure.yml delete mode 100644 designs/jtag/constraints/constraints.tcl delete mode 120000 designs/jtag/constraints/outputs/constraints.tcl delete mode 100644 designs/jtag/construct-commercial-full.py delete mode 100644 designs/jtag/rtl/configure.yml delete mode 100644 designs/jtag/rtl/gen_rtl.py delete mode 100644 designs/jtag/synopsys-dc-synthesis/assertion_helpers.py delete mode 100644 designs/jtag/synopsys-dc-synthesis/configure.yml delete mode 100644 designs/jtag/synopsys-dc-synthesis/dc.tcl delete mode 100644 designs/jtag/synopsys-dc-synthesis/designer_interface.tcl delete mode 100644 designs/jtag/synopsys-dc-synthesis/pre_synth.tcl delete mode 100755 designs/jtag/synopsys-dc-synthesis/run.sh delete mode 100644 designs/weight_manager/.mflowgen.yml delete mode 100644 designs/weight_manager/constraints/configure.yml delete mode 100644 designs/weight_manager/constraints/constraints.tcl delete mode 120000 designs/weight_manager/constraints/outputs/constraints.tcl delete mode 100644 designs/weight_manager/construct-commercial-full.py delete mode 100644 designs/weight_manager/rtl/configure.yml delete mode 100644 designs/weight_manager/rtl/gen_rtl.py delete mode 100644 designs/weight_manager/rtl/weight_manager_insts.sv delete mode 100644 designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py delete mode 100644 designs/weight_manager/synopsys-dc-synthesis/configure.yml delete mode 100644 designs/weight_manager/synopsys-dc-synthesis/dc.tcl delete mode 100644 designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl delete mode 100644 designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl delete mode 100755 designs/weight_manager/synopsys-dc-synthesis/run.sh diff --git a/designs/dragonphy_top/openram-gen-sram/configure.yml b/designs/dragonphy_top/openram-gen-sram/configure.yml index 17a8d352..d2e079c7 100644 --- a/designs/dragonphy_top/openram-gen-sram/configure.yml +++ b/designs/dragonphy_top/openram-gen-sram/configure.yml @@ -4,8 +4,17 @@ name: openram-gen-sram commands: - | - python gen_config.py - python $OPENRAM_HOME/openram.py myconfig + # Option 1 (slow): Run OpenRAM to generate a *.lib file + # python gen_config.py + # python $OPENRAM_HOME/openram.py myconfig + + # Option 2 (fast): Copy over a pre-compiled *.lib file + # Note that if the memory size changes the file will + # have to be recompiled. + mkdir -p temp + cp lib.openram temp/sram_144_1024_freepdk45_TT_1p0V_25C.lib + + # run script to generate a *.db file from the *.lib model dc_shell-xg-t -f generate_db.tcl parameters: diff --git a/designs/dragonphy_top/openram-gen-sram/lib.openram b/designs/dragonphy_top/openram-gen-sram/lib.openram new file mode 100644 index 00000000..98ab121f --- /dev/null +++ b/designs/dragonphy_top/openram-gen-sram/lib.openram @@ -0,0 +1,321 @@ +library (sram_144_1024_freepdk45_TT_1p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1V" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1, pF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 1.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.00125, 0.005, 0.04"); + index_2("5.2275000000000003e-05, 0.00020910000000000001, 0.0016728000000000001"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.00125, 0.005, 0.04"); + index_2("0.00125, 0.005, 0.04"); + } + + default_operating_conditions : OC; + + + type (data){ + base_type : array; + data_type : bit; + bit_width : 144; + bit_from : 0; + bit_to : 143; + } + + type (addr){ + base_type : array; + data_type : bit; + bit_width : 10; + bit_from : 0; + bit_to : 9; + } + +cell (sram_144_1024_freepdk45){ + memory(){ + type : ram; + address_width : 10; + word_width : 144; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 206133.367475; + + leakage_power () { + when : "csb0"; + value : 0.15083; + } + cell_leakage_power : 0; + bus(din0){ + bus_type : data; + direction : input; + capacitance : 0.00020910000000000001; + memory_write(){ + address : addr0; + clocked_on : clk0; + } + pin(din0[143:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + bus(dout0){ + bus_type : data; + direction : output; + max_capacitance : 0.0016728000000000001; + min_capacitance : 5.2275000000000003e-05; + memory_read(){ + address : addr0; + } + pin(dout0[143:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.4, 0.4, 0.402",\ + "0.4, 0.4, 0.402",\ + "0.4, 0.4, 0.402"); + } + cell_fall(CELL_TABLE) { + values("0.4, 0.4, 0.402",\ + "0.4, 0.4, 0.402",\ + "0.4, 0.4, 0.402"); + } + rise_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_transition(CELL_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + bus(addr0){ + bus_type : addr; + direction : input; + capacitance : 0.00020910000000000001; + max_transition : 0.04; + pin(addr0[9:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(csb0){ + direction : input; + capacitance : 0.00020910000000000001; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(web0){ + direction : input; + capacitance : 0.00020910000000000001; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 0.00020910000000000001; + internal_power(){ + when : "!csb0 & clk0 & !web0"; + rise_power(scalar){ + values("17.70635310366173"); + } + fall_power(scalar){ + values("17.70635310366173"); + } + } + internal_power(){ + when : "!csb0 & !clk0 & web0"; + rise_power(scalar){ + values("17.70635310366173"); + } + fall_power(scalar){ + values("17.70635310366173"); + } + } + internal_power(){ + when : "csb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.04"); + } + fall_constraint(scalar) { + values("0.04"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.08"); + } + fall_constraint(scalar) { + values("0.08"); + } + } + } + + } +} diff --git a/designs/jtag/.mflowgen.yml b/designs/jtag/.mflowgen.yml deleted file mode 100644 index 189d498a..00000000 --- a/designs/jtag/.mflowgen.yml +++ /dev/null @@ -1 +0,0 @@ -construct: construct-commercial-full.py diff --git a/designs/jtag/constraints/configure.yml b/designs/jtag/constraints/configure.yml deleted file mode 100644 index e5992188..00000000 --- a/designs/jtag/constraints/configure.yml +++ /dev/null @@ -1,23 +0,0 @@ -#========================================================================= -# Constraints -#========================================================================= -# Author : Alex Carsello -# Date : Nov 1, 2019 -# - -name: constraints - -#------------------------------------------------------------------------- -# Inputs and Outputs -#------------------------------------------------------------------------- - -outputs: - - constraints.tcl - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -parameters: - clock_period: 1.0 - design_name: undefined diff --git a/designs/jtag/constraints/constraints.tcl b/designs/jtag/constraints/constraints.tcl deleted file mode 100644 index e2d2a3f8..00000000 --- a/designs/jtag/constraints/constraints.tcl +++ /dev/null @@ -1,54 +0,0 @@ -#========================================================================= -# Design Constraints File -#========================================================================= - -# This constraint sets the target clock period for the chip in -# nanoseconds. Note that the first parameter is the name of the clock -# signal in your verlog design. If you called it something different than -# clk you will need to change this. You should set this constraint -# carefully. If the period is unrealistically small then the tools will -# spend forever trying to meet timing and ultimately fail. If the period -# is too large the tools will have no trouble but you will get a very -# conservative implementation. - -create_clock -name system_clock -period 10.0 [get_ports clk] -create_clock -name test_clock -period 100.0 [get_ports jtag_intf_i.phy_tck] - -set_false_path -from system_clock -to test_clock -set_false_path -from test_clock -to system_clock - -# This constraint sets the load capacitance in picofarads of the -# output pins of your design. - -set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] - -# This constraint sets the input drive strength of the input pins of -# your design. We specifiy a specific standard cell which models what -# would be driving the inputs. This should usually be a small inverter -# which is reasonable if another block of on-chip logic is driving -# your inputs. - -set_driving_cell -no_design_rule \ - -lib_cell $ADK_DRIVING_CELL [all_inputs] - -# set_input_delay constraints for input ports -# -# - make this non-zero to avoid hold buffers on input-registered designs - -# set_input_delay -clock ${clock_name} [expr ${dc_clock_period}/2.0] [all_inputs] - -# set_output_delay constraints for output ports - -# set_output_delay -clock ${clock_name} 0 [all_outputs] - -# Make all signals limit their fanout - -set_max_fanout 20 $dc_design_name - -# Make all signals meet good slew - -# set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name - -#set_input_transition 1 [all_inputs] -#set_max_transition 10 [all_outputs] - diff --git a/designs/jtag/constraints/outputs/constraints.tcl b/designs/jtag/constraints/outputs/constraints.tcl deleted file mode 120000 index 50630c20..00000000 --- a/designs/jtag/constraints/outputs/constraints.tcl +++ /dev/null @@ -1 +0,0 @@ -../constraints.tcl \ No newline at end of file diff --git a/designs/jtag/construct-commercial-full.py b/designs/jtag/construct-commercial-full.py deleted file mode 100644 index 7134a597..00000000 --- a/designs/jtag/construct-commercial-full.py +++ /dev/null @@ -1,177 +0,0 @@ -# Adapted from mflowgen GcdUnit example - -# To select the process, set the DRAGONPHY_PROCESS environment variable -# to either FREEPDK45 or TSMC16 - -import os - -from mflowgen.components import Graph, Step - -def construct(): - - # Get the name of the process to be used from the environment - if 'DRAGONPHY_PROCESS' in os.environ: - DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] - else: - DRAGONPHY_PROCESS = 'FREEPDK45' - - g = Graph() - - #----------------------------------------------------------------------- - # Parameters - #----------------------------------------------------------------------- - - parameters = { - 'construct_path': __file__, - 'design_name': 'jtag', - 'topographical': True - } - - if DRAGONPHY_PROCESS == 'FREEPDK45': - parameters['adk_name'] = 'freepdk-45nm' - parameters['adk_view'] = 'view-standard' - elif DRAGONPHY_PROCESS == 'TSMC16': - parameters['adk_name'] = 'tsmc16' - parameters['adk_view'] = 'stdview' - else: - raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') - - #----------------------------------------------------------------------- - # Create nodes - #----------------------------------------------------------------------- - - this_dir = os.path.dirname( os.path.abspath( __file__ ) ) - - # ADK step - - g.set_adk(parameters['adk_name']) - adk = g.get_adk_step() - - # Custom steps - - rtl = Step(this_dir + '/rtl') - constraints = Step(this_dir + '/constraints') - dc = Step(this_dir + '/synopsys-dc-synthesis') - - # Default steps - - info = Step( 'info', default=True ) - iflow = Step( 'cadence-innovus-flowsetup', default=True ) - init = Step( 'cadence-innovus-init', default=True ) - power = Step( 'cadence-innovus-power', default=True ) - place = Step( 'cadence-innovus-place', default=True ) - cts = Step( 'cadence-innovus-cts', default=True ) - postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) - route = Step( 'cadence-innovus-route', default=True ) - postroute = Step( 'cadence-innovus-postroute', default=True ) - postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) - signoff = Step( 'cadence-innovus-signoff', default=True ) - genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) - gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) - drc = Step( 'mentor-calibre-drc', default=True ) - lvs = Step( 'mentor-calibre-lvs', default=True ) - debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) - - #----------------------------------------------------------------------- - # Graph -- Add nodes - #----------------------------------------------------------------------- - - g.add_step( info ) - g.add_step( rtl ) - g.add_step( constraints ) - g.add_step( dc ) - g.add_step( iflow ) - g.add_step( init ) - g.add_step( power ) - g.add_step( place ) - g.add_step( cts ) - g.add_step( postcts_hold ) - g.add_step( route ) - g.add_step( postroute ) - g.add_step( postroute_hold ) - g.add_step( signoff ) - g.add_step( genlibdb ) - g.add_step( gdsmerge ) - g.add_step( drc ) - g.add_step( lvs ) - g.add_step( debugcalibre ) - - #----------------------------------------------------------------------- - # Graph -- Add edges - #----------------------------------------------------------------------- - - # Connect by name - - g.connect_by_name( adk, dc ) - g.connect_by_name( adk, iflow ) - g.connect_by_name( adk, init ) - g.connect_by_name( adk, power ) - g.connect_by_name( adk, place ) - g.connect_by_name( adk, cts ) - g.connect_by_name( adk, postcts_hold ) - g.connect_by_name( adk, route ) - g.connect_by_name( adk, postroute ) - g.connect_by_name( adk, postroute_hold ) - g.connect_by_name( adk, signoff ) - g.connect_by_name( adk, gdsmerge ) - g.connect_by_name( adk, drc ) - g.connect_by_name( adk, lvs ) - - g.connect_by_name( rtl, dc ) - g.connect_by_name( constraints, dc ) - - g.connect_by_name( dc, iflow ) - g.connect_by_name( dc, init ) - g.connect_by_name( dc, power ) - g.connect_by_name( dc, place ) - g.connect_by_name( dc, cts ) - - g.connect_by_name( iflow, init ) - g.connect_by_name( iflow, power ) - g.connect_by_name( iflow, place ) - g.connect_by_name( iflow, cts ) - g.connect_by_name( iflow, postcts_hold ) - g.connect_by_name( iflow, route ) - g.connect_by_name( iflow, postroute ) - g.connect_by_name( iflow, postroute_hold ) - g.connect_by_name( iflow, signoff ) - - g.connect_by_name( init, power ) - g.connect_by_name( power, place ) - g.connect_by_name( place, cts ) - g.connect_by_name( cts, postcts_hold ) - g.connect_by_name( postcts_hold, route ) - g.connect_by_name( route, postroute ) - g.connect_by_name( postroute, postroute_hold ) - g.connect_by_name( postroute_hold, signoff ) - - g.connect_by_name( signoff, genlibdb ) - g.connect_by_name( adk, genlibdb ) - - g.connect_by_name( signoff, gdsmerge ) - - g.connect_by_name( signoff, drc ) - g.connect_by_name( gdsmerge, drc ) - g.connect_by_name( signoff, lvs ) - g.connect_by_name( gdsmerge, lvs ) - - g.connect_by_name( adk, debugcalibre ) - g.connect_by_name( dc, debugcalibre ) - g.connect_by_name( iflow, debugcalibre ) - g.connect_by_name( signoff, debugcalibre ) - g.connect_by_name( drc, debugcalibre ) - g.connect_by_name( lvs, debugcalibre ) - - #----------------------------------------------------------------------- - # Parameterize - #----------------------------------------------------------------------- - - g.update_params( parameters ) - - return g - - -if __name__ == '__main__': - g = construct() -# g.plot() - diff --git a/designs/jtag/rtl/configure.yml b/designs/jtag/rtl/configure.yml deleted file mode 100644 index bba47d90..00000000 --- a/designs/jtag/rtl/configure.yml +++ /dev/null @@ -1,10 +0,0 @@ -name: rtl - -commands: - - python gen_rtl.py - -outputs: - - design.v - -parameters: - design_name: None \ No newline at end of file diff --git a/designs/jtag/rtl/gen_rtl.py b/designs/jtag/rtl/gen_rtl.py deleted file mode 100644 index 0828f5f9..00000000 --- a/designs/jtag/rtl/gen_rtl.py +++ /dev/null @@ -1,40 +0,0 @@ -import os -import re -from pathlib import Path -from dragonphy import * - -TOP_CELL = os.environ.get('design_name', 'jtag') -OUTPUT_FILE = 'design.v' - -def remove_dup(seq): - # fast method to remove duplicates from a list while preserving order - # source: Raymond Hettinger (https://twitter.com/raymondh/status/944125570534621185) - return list(dict.fromkeys(seq)) - -# build up a list of source files -src_files = [] -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/jtag/jtag_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/analog_core/acore_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/mm_cdr/cdr_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/digital_core/dcore_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/sram/sram_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/prbs/prbs_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/weight_manager/wme_debug_intf.sv')) -src_files += get_deps_new_asic(TOP_CELL) -src_files = remove_dup(src_files) - -# generate the output text -output = '' - -for src_file in src_files: - output += f'// Content from file: {src_file}\n' - output += open(src_file, 'r').read() - output += '\n' - -# create output directory -OUTPUT_DIR = Path('outputs') -OUTPUT_DIR.mkdir(exist_ok=True, parents=True) - -# write output text -with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: - f.write(output) diff --git a/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py b/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py deleted file mode 100644 index c873bdd0..00000000 --- a/designs/jtag/synopsys-dc-synthesis/assertion_helpers.py +++ /dev/null @@ -1,67 +0,0 @@ -#========================================================================= -# assertion_helpers.py -#========================================================================= -# Helper functions for assertions -# -# Author : Christopher Torng -# Date : March 14, 2020 -# - -from glob import glob - -import re - -# percent_clock_gated -# -# Reads the clock-gating report and returns a float representing the -# percentage of registers that are clock gated. -# - -def percent_clock_gated(): - - # Read the clock-gating report - - with open( glob('reports/*clock_gating.rpt')[0] ) as fd: - lines = fd.readlines() - - # Get the line with the clock-gating percentage, which looks like this: - # - # | Number of Gated registers | 32 (94.12%) | - # - - gate_line = [ l for l in lines if 'Number of Gated registers' in l ][0] - - # Extract the percentage between parentheses - - percentage = float( re.search( r'\((.*?)%\)', gate_line ).group(1) )/100 - - return percentage - -# n_regs -# -# Reads the clock-gating report and returns an integer for the number of -# registers that exist in the design. -# - -def n_regs(): - - # Read the clock-gating report - - with open( glob('reports/*clock_gating.rpt')[0] ) as fd: - lines = fd.readlines() - - # Get the line with the number of registers, which looks like this: - # - # | Total number of registers | 34 | - # - - regs_line = [ l for l in lines if 'Total number of registers' in l ][0] - - # Extract the number - - regs = int( re.search( r'\|\s*(\d*)\s*\|', regs_line ).group(1) ) - - return regs - - - diff --git a/designs/jtag/synopsys-dc-synthesis/configure.yml b/designs/jtag/synopsys-dc-synthesis/configure.yml deleted file mode 100644 index 47a7538e..00000000 --- a/designs/jtag/synopsys-dc-synthesis/configure.yml +++ /dev/null @@ -1,93 +0,0 @@ -#========================================================================= -# Synopsys DC Synthesis -#========================================================================= -# Author : Christopher Torng, Yanghui Ou -# Date : June 7, 2019 -# - -name: synopsys-dc-synthesis - -#------------------------------------------------------------------------- -# Inputs and Outputs -#------------------------------------------------------------------------- - -inputs: - - adk - - design.v - - constraints.tcl - - run.saif - -outputs: - - design.v - - design.sdc - - design.namemap - -#------------------------------------------------------------------------- -# Commands -#------------------------------------------------------------------------- - -commands: - - bash run.sh - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -parameters: - clock_period: 1.0 - design_name: undefined - # Path to the design instance in run.saif (e.g., tb/dut) - saif_instance: undefined - flatten_effort: 0 - topographical: True - nthreads: 16 # multithreading available to the tool - -#------------------------------------------------------------------------- -# Debug -#------------------------------------------------------------------------- - -debug: - - export DC_EXIT_AFTER_SETUP=1 - - ln -sf results/*.mapped.ddc debug.ddc - - design_vision-xg -topographical -x "source dc.tcl; read_ddc debug.ddc" - -#------------------------------------------------------------------------- -# Assertions -#------------------------------------------------------------------------- - -preconditions: - - - assert Tool( 'dc_shell-xg-t' ) # tool check - - assert File( 'inputs/adk' ) # must exist - - assert File( 'inputs/design.v' ) # must exist - - assert File( 'inputs/constraints.tcl' ) # must exist - -postconditions: - - - assert File( 'outputs/design.v' ) # must exist - - assert File( 'outputs/design.sdc' ) # must exist - - # Basic error checking - - - assert 'error' not in File( 'logs/dc.log' ) - - assert 'Unresolved references' not in File( 'logs/dc.log' ) - - assert 'Unable to resolve' not in File( 'logs/dc.log' ) - - # If GTECH is found, that means this design was not mapped to a - # technology library and is still in DC's generic representation - - - assert 'GTECH' not in File( 'outputs/design.v' ) - - # Sanity check that there is a clock in the constraints - - - assert 'create_clock' in File( 'outputs/design.sdc' ) - - # Check that at least N% of registers were clock-gated - # TODO add this check back - -# - | -# from assertion_helpers import percent_clock_gated, n_regs -# if n_regs() > 10: -# assert percent_clock_gated() > 0.50 - - diff --git a/designs/jtag/synopsys-dc-synthesis/dc.tcl b/designs/jtag/synopsys-dc-synthesis/dc.tcl deleted file mode 100644 index 19b255e8..00000000 --- a/designs/jtag/synopsys-dc-synthesis/dc.tcl +++ /dev/null @@ -1,598 +0,0 @@ -#========================================================================= -# dc.tcl -#========================================================================= -# We use Synopsys DC to synthesize a single RTL netlist file into gates. -# -# This script has evolved over time inspired by (1) the Synopsys reference -# methodology scripts that are released year after year on Solvnet, (2) -# synthesis scripts from other research groups, as well as (3) reference -# papers from user groups online. -# -# If you make a major update to this script (e.g., update inspired by the -# latest version of the Synopsys reference methodology), please list the -# changeset in the version history below. -# -# Author : Christopher Torng -# Date : September 30, 2018 -# -#------------------------------------------------------------------------- -# Version History -#------------------------------------------------------------------------- -# -# - 09/30/2018 -- Christopher Torng -# - Clean slate DC scripts -# - We are now independent of the Synopsys Reference Methodology -# - Version of Synopsys DC running "% dc_shell -v": -# dc_shell version - M-2016.12 -# dc_shell build date - Nov 21, 2016 -# -# - 04/08/2018 -- Christopher Torng -# - Our original version was based on the Synopsys reference -# methodology (D-2010.03-SP1) -# - Big update now inspired by the Celerity Synopsys DC scripts, which -# were in turn also based on the Synopsys reference methodology -# (L-2016.03-SP2) -# -#------------------------------------------------------------------------- - -#------------------------------------------------------------------------- -# Designer interface -#------------------------------------------------------------------------- -# Source the designer interface script, which sets up variables from the -# build system, sets up ASIC design kit variables, etc. - -source -echo -verbose designer_interface.tcl - -#------------------------------------------------------------------------- -# Pre-synthesis plugin -#------------------------------------------------------------------------- - -if {[file exists [which $dc_pre_synthesis_plugin]]} { - puts "Info: Reading pre-synth plugin: $dc_pre_synthesis_plugin" - source -echo -verbose $dc_pre_synthesis_plugin -} - -#------------------------------------------------------------------------- -# Setup -#------------------------------------------------------------------------- - -# Set up variables for this specific ASIC design kit - -set SYNOPSYS_TOOL "dc-syn" -source -echo -verbose $dc_adk_tcl - -# Multicore support -- watch how many licenses we have! - -set_host_options -max_cores $dc_num_cores - -# Set up alib caching for faster consecutive runs - -set_app_var alib_library_analysis_path $dc_alib_dir - -# Set up tracking for Synopsys Formality - -set_svf ${dc_results_dir}/${dc_design_name}.mapped.svf - -# Set up search path for libraries and design files - -set_app_var search_path ". $dc_additional_search_path $search_path" - -# Important app vars -# -# - target_library -- DC maps the design to gates in this library (db) -# - synthetic_library -- DesignWare library (sldb) -# - link_library -- Libraries for any other design references (e.g., -# SRAMs, hierarchical blocks, macros, IO libs) (db) - -set_app_var target_library $dc_target_libraries -set_app_var synthetic_library dw_foundation.sldb -set_app_var link_library [join " - * - $target_library - $dc_extra_link_libraries - $synthetic_library - "] - - -# SAIF mapping. - # -saif_map -start - -# Create Milkyway library -# -# By default, Milkyway libraries only have 180 or so layers available to -# use (255 total, but some are reserved). The extend_mw_layers command -# expands the Milkyway library to accommodate up to 4095 layers. - -# Only create new Milkyway design library if it doesn't already exist - -set milkyway_library ${dc_design_name}_lib - -if {![file isdirectory $milkyway_library ]} { - - # Create a new Milkyway library - - extend_mw_layers - create_mw_lib -technology $dc_milkyway_tf \ - -mw_reference_library $dc_milkyway_ref_libraries \ - $milkyway_library - -} else { - - # Reuse existing Milkyway library, but ensure that it is consistent with - # the provided reference Milkyway libraries. - - set_mw_lib_reference $milkyway_library \ - -mw_reference_library $dc_milkyway_ref_libraries - -} - -open_mw_lib $milkyway_library - -# Set up TLU plus (if the files exist) - -if { $dc_topographical == True } { - if {[file exists [which $dc_tluplus_max]]} { - set_tlu_plus_files -max_tluplus $dc_tluplus_max \ - -min_tluplus $dc_tluplus_min \ - -tech2itf_map $dc_tluplus_map - - check_tlu_plus_files - } -} - -# Avoiding X-propagation for synchronous reset DFFs -# -# There are two key variables that help avoid X-propagation for -# synchronous reset DFFs: -# -# - set hdlin_ff_always_sync_set_reset true -# -# - Tells DC to use every constant 0 loaded into a DFF with a clock -# for synchronous reset, and every constant 1 loaded into a DFF with a -# clock for synchronous set -# -# - set compile_seqmap_honor_sync_set_reset true -# -# - Tells DC to preserve synchronous reset or preset logic close to -# the flip-flop -# -# So the hdlin variable first tells DC to treat resets as synchronous, and -# the compile variable tells DC that for all these synchronous reset DFFs, -# keep the logic simple and close to the DFF to avoid X-propagation. The -# hdlin variable applies to the analyze step when we read in the RTL, so -# it must be set before we read in the Verilog. The second variable -# applies to compile and must be set before we run compile_ultra. -# -# Note: Instead of setting the hdlin_ff_always_sync_set_reset variable to -# true, you can specifically tell DC about a particular DFF reset using -# the //synopsys sync_set_reset "reset, int_reset" pragma. -# -# By default, the hdlin_ff_always_async_set_reset variable is set to true, -# and the hdlin_ff_always_sync_set_reset variable is set to false. - -set hdlin_ff_always_sync_set_reset true -set compile_seqmap_honor_sync_set_reset true - -# Remove new variable info messages from the end of the log file - -set_app_var sh_new_variable_message false - -# Corners -# -# If we want to do corners in DC, then we would use this command to set -# the min and max libraries: - -#set_min_library $max_library -min_version $min_library - -# SAIF Name Mapping Database - -#if { ${VINAME} != "NONE" } { -# saif_map -start -#} - -# Hook to drop into interactive Design Compiler shell after setup - -if {[info exists ::env(DC_EXIT_AFTER_SETUP)]} { return } - -#------------------------------------------------------------------------- -# Read design -#------------------------------------------------------------------------- - -# Check libraries - -check_library > $dc_reports_dir/${dc_design_name}.check_library.rpt - -# The first "WORK" is a reserved word for Design Compiler. The value for -# the -path option is customizable. - -define_design_lib WORK -path ${dc_results_dir}/WORK - -# Analyze the RTL source files -# -# Source the read design plugin if it exists. Otherwise, we do a default -# read and elaborate the design. - -if {[file exists [which $dc_read_design_plugin]]} { - puts "Info: Reading read design plugin: $dc_read_design_plugin" - source -echo -verbose $dc_read_design_plugin -} else { - # Since no read design plugin exists, we do a default read - if { ![analyze -format sverilog $dc_rtl_handoff] } { exit 1 } - if {[file exists [which setup-design-params.txt]]} { - elaborate $dc_design_name -file_parameters setup-design-params.txt - rename_design $dc_design_name* $dc_design_name - } else { - elaborate $dc_design_name - } -} - -current_design $dc_design_name -link - -#------------------------------------------------------------------------- -# Write out useful files -#------------------------------------------------------------------------- - -# This ddc can be used as a checkpoint to load up to the current state - -write -hierarchy -format ddc \ - -output ${dc_results_dir}/${dc_design_name}.elab.ddc - -# This Verilog is useful to double-check the netlist that dc will use for -# mapping - -write -hierarchy -format verilog \ - -output ${dc_results_dir}/${dc_design_name}.elab.v - -#------------------------------------------------------------------------- -# Apply design constraints -#------------------------------------------------------------------------- - -# Apply logical design constraints - -puts "Info: Reading constraints file plugin: $dc_constraints_plugin" - -source -echo -verbose $dc_constraints_plugin - -# The check_timing command checks for constraint problems such as -# undefined clocking, undefined input arrival times, and undefined output -# constraints. These constraint problems could cause you to overlook -# timing violations. For this reason, the check_timing command is -# recommended whenever you apply new constraints such as clock -# definitions, I/O delays, or timing exceptions. - -redirect -tee \ - ${dc_reports_dir}/${dc_design_name}.premapped.checktiming.rpt \ - {check_timing} - -# Path groups - -set ports_clock_root [filter_collection \ - [get_attribute [get_clocks] sources] \ - object_class==port] - -group_path -name REGOUT \ - -to [all_outputs] - -group_path -name REGIN \ - -from [remove_from_collection [all_inputs] $ports_clock_root] - -group_path -name FEEDTHROUGH \ - -from [remove_from_collection [all_inputs] $ports_clock_root] \ - -to [all_outputs] - -# Apply physical design constraints -# -# Set the minimum and maximum routing layers used in DC topographical mode - -if { $dc_topographical == True } { - set_ignored_layers -min_routing_layer $ADK_MIN_ROUTING_LAYER_DC - set_ignored_layers -max_routing_layer $ADK_MAX_ROUTING_LAYER_DC - - report_ignored_layers -} - -#------------------------------------------------------------------------- -# Additional options -#------------------------------------------------------------------------- - -# Replace special characters with non-special ones before writing out the -# synthesized netlist (e.g., "\bus[5]" -> "bus_5_") - -set_app_var verilogout_no_tri true - -# Prevent assignment statements in the Verilog netlist. - -set_fix_multiple_port_nets -all -buffer_constants - -# Choose design flattening options - -if {[info exists DC_FLATTEN_EFFORT]} { - set dc_flatten_effort $DC_FLATTEN_EFFORT - if {"$dc_flatten_effort" == ""} { - set dc_flatten_effort 0 - } -} else { - set dc_flatten_effort 0 -} - -puts "Info: Flattening effort (DC_FLATTEN_EFFORT) = $dc_flatten_effort" - -set compile_ultra_options "" -if {$dc_flatten_effort == 0} { - puts "Info: All design hierarchies are preserved unless otherwise specified." - set_app_var compile_ultra_ungroup_dw false - puts "Info: Design Compiler compile_ultra boundary optimization is disabled." - append compile_ultra_options " -no_autoungroup -no_boundary_optimization" - -} elseif {$dc_flatten_effort == 1} { - puts "Info: Unconditionally ungroup the DesignWare cells." - set_app_var compile_ultra_ungroup_dw true - puts "Info: Design Compiler compile_ultra automatic ungrouping is disabled." - puts "Info: Design Compiler compile_ultra boundary optimization is disabled." - append compile_ultra_options " -no_autoungroup -no_boundary_optimization" - -} elseif {$dc_flatten_effort == 2} { - puts "Info: Unconditionally ungroup the DesignWare cells." - set_app_var compile_ultra_ungroup_dw true - puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." - puts "Info: Design Compiler compile_ultra boundary optimization is enabled." - append compile_ultra_options "" - -} elseif {$dc_flatten_effort == 3} { - set ungroup_start_level 2 - ungroup -start_level $ungroup_start_level -all -flatten - puts "Info: All hierarchical cells starting from level $ungroup_start_level are flattened." - puts "Info: Unconditionally ungroup the DesignWare cells." - puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." - puts "Info: Design Compiler compile_ultra boundary optimization is enabled." - set_app_var compile_ultra_ungroup_dw true - append compile_ultra_options "" - -} else { - puts "Info: Unrecognizable DC_FLATTEN_EFFORT value: $dc_flatten_effort" - exit -} - -# Enable or disable clock gating - -if {[info exists DC_GATE_CLOCK]} { - set dc_gate_clock $DC_GATE_CLOCK - if {"$dc_gate_clock" == ""} { - set dc_gate_clock true - } -} else { - set dc_gate_clock true -} - -puts "Info: Clock gating (DC_GATE_CLOCK) = $dc_gate_clock" - -if {$dc_gate_clock == true} { - append compile_ultra_options " -gate_clock" -} - -# Check design for consistency -# -# Most problems with synthesis will be caught in this report - -check_design -summary -check_design \ - > ${dc_reports_dir}/${dc_design_name}.premapped.checkdesign.rpt - -#------------------------------------------------------------------------- -# Compile -#------------------------------------------------------------------------- - -puts "Info: DC compile_ultra options = $compile_ultra_options" - -eval "compile_ultra $compile_ultra_options" - -# High-effort area optimization -# -# This command was introduced in I-2013.12 and performs monotonic -# gate-to-gate optimization on mapped designs. It is supposed to improve -# area without degrading timing or leakage. - -# Skip this step by setting the DC_SKIP_OPTIMIZE_NETLIST variable in the -# pre-synthesis plugin - -if {!([info exists DC_SKIP_OPTIMIZE_NETLIST] && $DC_SKIP_OPTIMIZE_NETLIST)} { - optimize_netlist -area -} - -# Check design - -check_design -summary -check_design > ${dc_reports_dir}/${dc_design_name}.mapped.checkdesign.rpt - -# Write the .namemap file for the Energy analysis - -if {[file exists "inputs/run.saif" ]} { - saif_map \ - -create_map \ - -input "inputs/run.saif" \ - -source_instance ${dc_saif_instance} -} - -#------------------------------------------------------------------------- -# Write out the design -#------------------------------------------------------------------------- - -# Synopsys Formality - -set_svf -off - -# Use naming rules to preserve structs - -define_name_rules verilog -preserve_struct_ports - -report_names \ - -rules verilog \ - > ${dc_reports_dir}/${dc_design_name}.mapped.naming.rpt - -change_names -rules verilog -hierarchy - -# Write out files - -write -format ddc \ - -hierarchy \ - -output ${dc_results_dir}/${dc_design_name}.mapped.ddc - -write -format verilog \ - -hierarchy \ - -output ${dc_results_dir}/${dc_design_name}.mapped.v - -write -format svsim \ - -output ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v - -# Dump the mapped.v and svwrapper.v into one svsim.v file to make it -# easier to include a single file for gate-level simulation. The svwrapper -# matches the interface of the original RTL even if using SystemVerilog -# features (e.g., array of arrays, uses parameters, etc.). - -sh cat ${dc_results_dir}/${dc_design_name}.mapped.v \ - ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v \ - > ${dc_results_dir}/${dc_design_name}.mapped.svsim.v - -# Write top-level verilog view needed for block instantiation - -write \ - -format verilog \ - -output ${dc_results_dir}/${dc_design_name}.mapped.top.v - -# Floorplan - -if { $dc_topographical == True } { - write_floorplan -all ${dc_results_dir}/${dc_design_name}.mapped.fp -} - -# Parasitics - -write_parasitics -output ${dc_results_dir}/${dc_design_name}.mapped.spef - -# SDF for back-annotated gate-level simulation - -write_sdf ${dc_results_dir}/${dc_design_name}.mapped.sdf - -# Do not write out net RC info into SDC - -set_app_var write_sdc_output_lumped_net_capacitance false -set_app_var write_sdc_output_net_resistance false - -# SDC constraints - -write_sdc -nosplit ${dc_results_dir}/${dc_design_name}.mapped.sdc - -#------------------------------------------------------------------------- -# Final reports -#------------------------------------------------------------------------- - -# Report units - -redirect -tee \ - ${dc_reports_dir}/${dc_design_name}.mapped.units.rpt \ - {report_units} - -# Report QOR - -report_qor > ${dc_reports_dir}/${dc_design_name}.mapped.qor.rpt - -# Report timing - -report_clock_timing \ - -type summary \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.clock.rpt - -report_timing \ - -input_pins -capacitance -transition_time \ - -nets -significant_digits 4 -nosplit \ - -path_type full_clock -attributes \ - -nworst 10 -max_paths 30 -delay_type max \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.setup.rpt - -report_timing \ - -input_pins -capacitance -transition_time \ - -nets -significant_digits 4 -nosplit \ - -path_type full_clock -attributes \ - -nworst 10 -max_paths 30 -delay_type min \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.hold.rpt - -# Report constraints - -report_constraint \ - -nosplit \ - -verbose \ - > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.rpt - -report_constraint \ - -nosplit \ - -verbose \ - -all_violators \ - > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.violators.rpt - -report_timing_requirements \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.requirements.rpt - -# Report area - -report_area \ - -hierarchy \ - -physical \ - -nosplit \ - > ${dc_reports_dir}/${dc_design_name}.mapped.area.rpt - -# Report references and resources - -report_reference \ - -nosplit \ - -hierarchy \ - > ${dc_reports_dir}/${dc_design_name}.mapped.reference.rpt - -report_resources \ - -nosplit \ - -hierarchy \ - > ${dc_reports_dir}/${dc_design_name}.mapped.resources.rpt - -# Report power -# -# Use SAIF file for power analysis -if {[file exists "inputs/run.saif" ]} { - read_saif \ - -map_names \ - -input "inputs/run.saif" \ - -instance_name $dc_saif_instance \ - -verbose - - report_saif \ - -hier \ - -annotated_flag \ - -rtl_saif \ - > ${dc_reports_dir}/${dc_design_name}.mapped.saif.rpt - - saif_map \ - -type ptpx \ - -write_map \ - ${dc_reports_dir}/${dc_design_name}.namemap -} - -report_power \ - -nosplit \ - -hier \ - > ${dc_reports_dir}/${dc_design_name}.mapped.power.rpt - -report_clock_gating \ - -nosplit \ - > ${dc_reports_dir}/${dc_design_name}.mapped.clock_gating.rpt - -#------------------------------------------------------------------------- -# Post-synthesis plugin -#------------------------------------------------------------------------- - -if {[file exists [which $dc_post_synthesis_plugin]]} { - puts "Info: Reading post-synthesis plugin: $dc_post_synthesis_plugin" - source -echo -verbose $dc_post_synthesis_plugin -} - -exit - diff --git a/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl b/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl deleted file mode 100644 index 0996d017..00000000 --- a/designs/jtag/synopsys-dc-synthesis/designer_interface.tcl +++ /dev/null @@ -1,90 +0,0 @@ -#========================================================================= -# designer_interface.tcl -#========================================================================= -# The designer_interface.tcl file is the first script run by Design -# Compiler (see the top of dc.tcl). It is the interface that connects the -# dc-synthesis scripts with the following: -# -# - Build system parameters -# - Build system inputs -# - ASIC design kit -# - Plugin scripts -# -# Author : Christopher Torng -# Date : April 8, 2018 - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -set dc_design_name $::env(design_name) -set dc_saif_instance $::env(saif_instance) -set dc_clock_period $::env(clock_period) -set dc_flatten_effort $::env(flatten_effort) -set dc_topographical $::env(topographical) - -#------------------------------------------------------------------------- -# Inputs -#------------------------------------------------------------------------- - -set dc_rtl_handoff inputs/design.v -set adk_dir inputs/adk - -# Extra libraries -# -# The glob below will capture any libraries collected by the build system -# (e.g., SRAM libraries) generated from steps that synthesis depends on. -# -# To add more link libraries (e.g., IO cells, hierarchical blocks), append -# to the "dc_extra_link_libraries" variable in the pre-synthesis plugin -# like this: -# -# set dc_extra_link_libraries [join " -# $dc_extra_link_libraries -# extra1.db -# extra2.db -# extra3.db -# "] - -set dc_extra_link_libraries [join " - [glob -nocomplain inputs/*.db] - [glob -nocomplain inputs/adk/*.db] - "] - -#------------------------------------------------------------------------- -# Interface to the ASIC design kit -#------------------------------------------------------------------------- - -set dc_milkyway_ref_libraries $adk_dir/stdcells.mwlib -set dc_milkyway_tf $adk_dir/rtk-tech.tf -set dc_tluplus_map $adk_dir/rtk-tluplus.map -set dc_tluplus_max $adk_dir/rtk-max.tluplus -set dc_tluplus_min $adk_dir/rtk-min.tluplus -set dc_adk_tcl $adk_dir/adk.tcl -set dc_target_libraries stdcells.db - -# Extra libraries - -set dc_additional_search_path $adk_dir - -#------------------------------------------------------------------------- -# Directories -#------------------------------------------------------------------------- - -set dc_flow_dir . -set dc_plugins_dir . -set dc_logs_dir logs -set dc_reports_dir reports -set dc_results_dir results -set dc_alib_dir alib - -#------------------------------------------------------------------------- -# Interface to plugins -#------------------------------------------------------------------------- - -set dc_pre_synthesis_plugin pre_synth.tcl -set dc_read_design_plugin read_design.tcl -set dc_constraints_plugin inputs/constraints.tcl -set dc_post_synthesis_plugin post_synth.tcl - - diff --git a/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl b/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl deleted file mode 100644 index e5cab31f..00000000 --- a/designs/jtag/synopsys-dc-synthesis/pre_synth.tcl +++ /dev/null @@ -1,49 +0,0 @@ -#========================================================================= -# pre_synth.tcl -#========================================================================= -# This plug-in script is called before synthesis -# -# Author : Christopher Torng -# Date : May 14, 2018 - -# Number of cores for multicore optimization - -set dc_num_cores $env(nthreads) - -# Add more link libraries (e.g., IO cells, hierarchical blocks) - -# set dc_extra_link_libraries [join " -# $dc_extra_link_libraries -# extra1.db -# extra2.db -# extra3.db -# "] - -# Enable additional area optimizations (skip false = enable optimizations) - -set DC_SKIP_OPTIMIZE_NETLIST true - -# Enable clock-gating - -set DC_GATE_CLOCK true - -# DC flatten effort -# -# - Effort 0: No auto-ungrouping / boundary optimizations (strict hierarchy) -# - Effort 1: No auto-ungrouping / boundary optimizations -# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) -# - Effort 2: Enable auto-ungrouping / boundary optimizations -# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) -# - Effort 3: Everything ungrouped + level param for how deep to ungroup -# -# Note that even with boundary optimizations off, DC will still propagate -# constants across the boundary, although this can be disabled with a -# variable if we really wanted to disable it. - -set DC_FLATTEN_EFFORT $env(flatten_effort) - -# When boundary optimizations are off, set this variable to true to still -# allow unconnected registers to be removed. - -set compile_optimize_unloaded_seq_logic_with_no_bound_opt true - diff --git a/designs/jtag/synopsys-dc-synthesis/run.sh b/designs/jtag/synopsys-dc-synthesis/run.sh deleted file mode 100755 index ae57c1f0..00000000 --- a/designs/jtag/synopsys-dc-synthesis/run.sh +++ /dev/null @@ -1,114 +0,0 @@ -#! /usr/bin/env bash -#========================================================================= -# run.sh -#========================================================================= -# Author : Christopher Torng -# Date : June 2, 2019 -# - -# Print commands during execution - -set -x - -# DC shell - -dc_exec='dc_shell-xg-t -64bit' - -# Build directories - -rm -rf ./logs -rm -rf ./reports -rm -rf ./results - -mkdir -p logs -mkdir -p reports -mkdir -p results - -# alib -# -# Design Compiler caches analyzed libraries to improve performance using -# ".alib" directories. The alib takes a while to generate but is reused on -# subsequent runs. It is useful to store a centralized copy of the alib to -# avoid re-generating the alib (usually only several minutes but can be -# annoying) on every new clone of the ASIC repo. -# -# However, if DC sees a .db that does not have an associated .alib it will -# try to automatically create one. This is not usually a problem when -# students just use standard cells, but if a student is trying to use -# SRAMs, then they will be using new .db files that DC has not seen yet. -# The problem is that students do not have write permissions to the -# centralized copy of the alib in the ADK. -# -# The solution we use is to create a local alib directory in the current -# build directory with _per-file_ symlinks to the centralized alib (and -# with the same directory hierarchy). This allows students to reuse the -# centralized copies of the alib files while allowing new alibs (e.g., for -# SRAMs) to be generated locally. -# -# This is possible because the alibs are stored in a directory that holds -# a ".db.alib" file for each db file: -# -# - alib -# - alib-52 -# - iocells.db.alib -# - stdcells.db.alib -# -# This new alib directory just needs to contain symlinks to each saved -# alib in the ADK. This can be done simply by using "cp -srf" of the ADK -# alib to the build directory, which generates symbolic links to each file -# instead of copying. This way, the student can access the master copy of -# the saved alibs in the ADK, and if there are any additional db's -# specified, their alibs will be saved in the local build directory. - -rm -rf alib -mkdir -p alib - -cp -srf $PWD/inputs/adk/alib/* alib || true - -# Run the synthesis script - -if [ "x$topographical" == "xTrue" ]; then - opt_topographical='-topographical_mode' -else - opt_topographical= -fi - -$dc_exec $opt_topographical -f dc.tcl -output_log_file logs/dc.log || exit 1 - -# Compress the spef file - -cd results -gzip *.mapped.spef -cd .. - -# Set up the outputs - -mkdir -p outputs && cd outputs - -ln -sf ../results/*.mapped.v design.v -ln -sf ../results/*.mapped.sdc design.sdc -ln -sf ../results/*.mapped.spef.gz design.spef.gz -ln -sf ../reports/*.namemap design.namemap - -cd .. - -# Grep for failure messages - -grep --color "^Error" logs/dc.log || true -grep --color -B 3 "*** Presto compilation terminated" logs/dc.log || true -grep --color "unresolved references." logs/dc.log || true - -# ELAB-405 -# -# When using a Verilog generation tool, there may be a -# generation/translation mistake that defines a net twice. This will give -# a message like this: -# -# Warning: ./inputs/design.v:2473: Net mul__recv__msg__opd_b[0] or a -# directly connected net may be driven by more than one process or block. -# (ELAB-405) -# -# This is usually a bad sign.. -# - -grep --color "ELAB-405" logs/dc.log || true diff --git a/designs/weight_manager/.mflowgen.yml b/designs/weight_manager/.mflowgen.yml deleted file mode 100644 index 189d498a..00000000 --- a/designs/weight_manager/.mflowgen.yml +++ /dev/null @@ -1 +0,0 @@ -construct: construct-commercial-full.py diff --git a/designs/weight_manager/constraints/configure.yml b/designs/weight_manager/constraints/configure.yml deleted file mode 100644 index e5992188..00000000 --- a/designs/weight_manager/constraints/configure.yml +++ /dev/null @@ -1,23 +0,0 @@ -#========================================================================= -# Constraints -#========================================================================= -# Author : Alex Carsello -# Date : Nov 1, 2019 -# - -name: constraints - -#------------------------------------------------------------------------- -# Inputs and Outputs -#------------------------------------------------------------------------- - -outputs: - - constraints.tcl - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -parameters: - clock_period: 1.0 - design_name: undefined diff --git a/designs/weight_manager/constraints/constraints.tcl b/designs/weight_manager/constraints/constraints.tcl deleted file mode 100644 index 18c009f3..00000000 --- a/designs/weight_manager/constraints/constraints.tcl +++ /dev/null @@ -1,55 +0,0 @@ -#========================================================================= -# Design Constraints File -#========================================================================= - -# This constraint sets the target clock period for the chip in -# nanoseconds. Note that the first parameter is the name of the clock -# signal in your verlog design. If you called it something different than -# clk you will need to change this. You should set this constraint -# carefully. If the period is unrealistically small then the tools will -# spend forever trying to meet timing and ultimately fail. If the period -# is too large the tools will have no trouble but you will get a very -# conservative implementation. - -set clock_net clk -set clock_name ideal_clock - -create_clock -name ${clock_name} \ - -period ${dc_clock_period} \ - [get_ports ${clock_net}] - -# This constraint sets the load capacitance in picofarads of the -# output pins of your design. - -set_load -pin_load $ADK_TYPICAL_ON_CHIP_LOAD [all_outputs] - -# This constraint sets the input drive strength of the input pins of -# your design. We specifiy a specific standard cell which models what -# would be driving the inputs. This should usually be a small inverter -# which is reasonable if another block of on-chip logic is driving -# your inputs. - -set_driving_cell -no_design_rule \ - -lib_cell $ADK_DRIVING_CELL [all_inputs] - -# set_input_delay constraints for input ports -# -# - make this non-zero to avoid hold buffers on input-registered designs - -set_input_delay -clock ${clock_name} [expr ${dc_clock_period}/2.0] [all_inputs] - -# set_output_delay constraints for output ports - -set_output_delay -clock ${clock_name} 0 [all_outputs] - -# Make all signals limit their fanout - -set_max_fanout 20 $dc_design_name - -# Make all signals meet good slew - -set_max_transition [expr 0.25*${dc_clock_period}] $dc_design_name - -#set_input_transition 1 [all_inputs] -#set_max_transition 10 [all_outputs] - diff --git a/designs/weight_manager/constraints/outputs/constraints.tcl b/designs/weight_manager/constraints/outputs/constraints.tcl deleted file mode 120000 index 50630c20..00000000 --- a/designs/weight_manager/constraints/outputs/constraints.tcl +++ /dev/null @@ -1 +0,0 @@ -../constraints.tcl \ No newline at end of file diff --git a/designs/weight_manager/construct-commercial-full.py b/designs/weight_manager/construct-commercial-full.py deleted file mode 100644 index d481881c..00000000 --- a/designs/weight_manager/construct-commercial-full.py +++ /dev/null @@ -1,179 +0,0 @@ -# Adapted from mflowgen GcdUnit example - -# To select the process, set the DRAGONPHY_PROCESS environment variable -# to either FREEPDK45 or TSMC16 - -import os - -from mflowgen.components import Graph, Step - -def construct(): - - # Get the name of the process to be used from the environment - if 'DRAGONPHY_PROCESS' in os.environ: - DRAGONPHY_PROCESS = os.environ['DRAGONPHY_PROCESS'] - else: - DRAGONPHY_PROCESS = 'FREEPDK45' - - g = Graph() - - #----------------------------------------------------------------------- - # Parameters - #----------------------------------------------------------------------- - - parameters = { - 'construct_path': __file__, - 'design_name': 'weight_manager', - 'topographical': True - } - - if DRAGONPHY_PROCESS == 'FREEPDK45': - parameters['adk_name'] = 'freepdk-45nm' - parameters['adk_view'] = 'view-standard' - parameters['clock_period'] = 7.0 - elif DRAGONPHY_PROCESS == 'TSMC16': - parameters['adk_name'] = 'tsmc16' - parameters['adk_view'] = 'stdview' - parameters['clock_period'] = 0.7 - else: - raise Exception(f'Unknown process: {DRAGONPHY_PROCESS}') - - #----------------------------------------------------------------------- - # Create nodes - #----------------------------------------------------------------------- - - this_dir = os.path.dirname( os.path.abspath( __file__ ) ) - - # ADK step - - g.set_adk(parameters['adk_name']) - adk = g.get_adk_step() - - # Custom steps - - rtl = Step(this_dir + '/rtl') - constraints = Step(this_dir + '/constraints') - dc = Step(this_dir + '/synopsys-dc-synthesis') - - # Default steps - - info = Step( 'info', default=True ) - iflow = Step( 'cadence-innovus-flowsetup', default=True ) - init = Step( 'cadence-innovus-init', default=True ) - power = Step( 'cadence-innovus-power', default=True ) - place = Step( 'cadence-innovus-place', default=True ) - cts = Step( 'cadence-innovus-cts', default=True ) - postcts_hold = Step( 'cadence-innovus-postcts_hold', default=True ) - route = Step( 'cadence-innovus-route', default=True ) - postroute = Step( 'cadence-innovus-postroute', default=True ) - postroute_hold = Step( 'cadence-innovus-postroute_hold', default=True ) - signoff = Step( 'cadence-innovus-signoff', default=True ) - genlibdb = Step( 'synopsys-ptpx-genlibdb', default=True ) - gdsmerge = Step( 'mentor-calibre-gdsmerge', default=True ) - drc = Step( 'mentor-calibre-drc', default=True ) - lvs = Step( 'mentor-calibre-lvs', default=True ) - debugcalibre = Step( 'cadence-innovus-debug-calibre', default=True ) - - #----------------------------------------------------------------------- - # Graph -- Add nodes - #----------------------------------------------------------------------- - - g.add_step( info ) - g.add_step( rtl ) - g.add_step( constraints ) - g.add_step( dc ) - g.add_step( iflow ) - g.add_step( init ) - g.add_step( power ) - g.add_step( place ) - g.add_step( cts ) - g.add_step( postcts_hold ) - g.add_step( route ) - g.add_step( postroute ) - g.add_step( postroute_hold ) - g.add_step( signoff ) - g.add_step( genlibdb ) - g.add_step( gdsmerge ) - g.add_step( drc ) - g.add_step( lvs ) - g.add_step( debugcalibre ) - - #----------------------------------------------------------------------- - # Graph -- Add edges - #----------------------------------------------------------------------- - - # Connect by name - - g.connect_by_name( adk, dc ) - g.connect_by_name( adk, iflow ) - g.connect_by_name( adk, init ) - g.connect_by_name( adk, power ) - g.connect_by_name( adk, place ) - g.connect_by_name( adk, cts ) - g.connect_by_name( adk, postcts_hold ) - g.connect_by_name( adk, route ) - g.connect_by_name( adk, postroute ) - g.connect_by_name( adk, postroute_hold ) - g.connect_by_name( adk, signoff ) - g.connect_by_name( adk, gdsmerge ) - g.connect_by_name( adk, drc ) - g.connect_by_name( adk, lvs ) - - g.connect_by_name( rtl, dc ) - g.connect_by_name( constraints, dc ) - - g.connect_by_name( dc, iflow ) - g.connect_by_name( dc, init ) - g.connect_by_name( dc, power ) - g.connect_by_name( dc, place ) - g.connect_by_name( dc, cts ) - - g.connect_by_name( iflow, init ) - g.connect_by_name( iflow, power ) - g.connect_by_name( iflow, place ) - g.connect_by_name( iflow, cts ) - g.connect_by_name( iflow, postcts_hold ) - g.connect_by_name( iflow, route ) - g.connect_by_name( iflow, postroute ) - g.connect_by_name( iflow, postroute_hold ) - g.connect_by_name( iflow, signoff ) - - g.connect_by_name( init, power ) - g.connect_by_name( power, place ) - g.connect_by_name( place, cts ) - g.connect_by_name( cts, postcts_hold ) - g.connect_by_name( postcts_hold, route ) - g.connect_by_name( route, postroute ) - g.connect_by_name( postroute, postroute_hold ) - g.connect_by_name( postroute_hold, signoff ) - - g.connect_by_name( signoff, genlibdb ) - g.connect_by_name( adk, genlibdb ) - - g.connect_by_name( signoff, gdsmerge ) - - g.connect_by_name( signoff, drc ) - g.connect_by_name( gdsmerge, drc ) - g.connect_by_name( signoff, lvs ) - g.connect_by_name( gdsmerge, lvs ) - - g.connect_by_name( adk, debugcalibre ) - g.connect_by_name( dc, debugcalibre ) - g.connect_by_name( iflow, debugcalibre ) - g.connect_by_name( signoff, debugcalibre ) - g.connect_by_name( drc, debugcalibre ) - g.connect_by_name( lvs, debugcalibre ) - - #----------------------------------------------------------------------- - # Parameterize - #----------------------------------------------------------------------- - - g.update_params( parameters ) - - return g - - -if __name__ == '__main__': - g = construct() -# g.plot() - diff --git a/designs/weight_manager/rtl/configure.yml b/designs/weight_manager/rtl/configure.yml deleted file mode 100644 index bba47d90..00000000 --- a/designs/weight_manager/rtl/configure.yml +++ /dev/null @@ -1,10 +0,0 @@ -name: rtl - -commands: - - python gen_rtl.py - -outputs: - - design.v - -parameters: - design_name: None \ No newline at end of file diff --git a/designs/weight_manager/rtl/gen_rtl.py b/designs/weight_manager/rtl/gen_rtl.py deleted file mode 100644 index 5fcfccc5..00000000 --- a/designs/weight_manager/rtl/gen_rtl.py +++ /dev/null @@ -1,34 +0,0 @@ -import os -import re -from pathlib import Path -from dragonphy import * - -OUTPUT_FILE = 'design.v' - -def remove_dup(seq): - # fast method to remove duplicates from a list while preserving order - # source: Raymond Hettinger (https://twitter.com/raymondh/status/944125570534621185) - return list(dict.fromkeys(seq)) - -# build up a list of source files -src_files = [] -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/digital_core/dsp_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file=get_file('vlog/new_chip_src/weight_manager/wme_debug_intf.sv')) -src_files += get_deps_new_asic(impl_file='weight_manager_insts.sv') -src_files = remove_dup(src_files) - -# generate the output text -output = '' - -for src_file in src_files: - output += f'// Content from file: {src_file}\n' - output += open(src_file, 'r').read() - output += '\n' - -# create output directory -OUTPUT_DIR = Path('outputs') -OUTPUT_DIR.mkdir(exist_ok=True, parents=True) - -# write output text -with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f: - f.write(output) diff --git a/designs/weight_manager/rtl/weight_manager_insts.sv b/designs/weight_manager/rtl/weight_manager_insts.sv deleted file mode 100644 index 39a903d2..00000000 --- a/designs/weight_manager/rtl/weight_manager_insts.sv +++ /dev/null @@ -1,26 +0,0 @@ -module weight_manager_insts import const_pack::*; ( - input wire logic clk_adc, - input wire logic rstb, - wme_debug_intf.wme wdbg_intf_i, - dsp_debug_intf.dsp dsp_dbg_intf_i -); - weight_manager #(.width(Nti), .depth(10), .bitwidth(10)) wme_ffe_i ( - .data (wdbg_intf_i.wme_ffe_data), - .inst (wdbg_intf_i.wme_ffe_inst), - .exec (wdbg_intf_i.wme_ffe_exec), - .clk (clk_adc), - .rstb (rstb), - .read_reg(wdbg_intf_i.wme_ffe_read), - .weights (dsp_dbg_intf_i.weights) - ); - - weight_manager #(.width(Nti), .depth(30), .bitwidth(8)) wme_channel_est_i ( - .data (wdbg_intf_i.wme_mlsd_data), - .inst (wdbg_intf_i.wme_mlsd_inst), - .exec (wdbg_intf_i.wme_mlsd_exec), - .clk (clk_adc), - .rstb (rstb), - .read_reg(wdbg_intf_i.wme_mlsd_read), - .weights (dsp_dbg_intf_i.channel_est) - ); -endmodule diff --git a/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py b/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py deleted file mode 100644 index c873bdd0..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/assertion_helpers.py +++ /dev/null @@ -1,67 +0,0 @@ -#========================================================================= -# assertion_helpers.py -#========================================================================= -# Helper functions for assertions -# -# Author : Christopher Torng -# Date : March 14, 2020 -# - -from glob import glob - -import re - -# percent_clock_gated -# -# Reads the clock-gating report and returns a float representing the -# percentage of registers that are clock gated. -# - -def percent_clock_gated(): - - # Read the clock-gating report - - with open( glob('reports/*clock_gating.rpt')[0] ) as fd: - lines = fd.readlines() - - # Get the line with the clock-gating percentage, which looks like this: - # - # | Number of Gated registers | 32 (94.12%) | - # - - gate_line = [ l for l in lines if 'Number of Gated registers' in l ][0] - - # Extract the percentage between parentheses - - percentage = float( re.search( r'\((.*?)%\)', gate_line ).group(1) )/100 - - return percentage - -# n_regs -# -# Reads the clock-gating report and returns an integer for the number of -# registers that exist in the design. -# - -def n_regs(): - - # Read the clock-gating report - - with open( glob('reports/*clock_gating.rpt')[0] ) as fd: - lines = fd.readlines() - - # Get the line with the number of registers, which looks like this: - # - # | Total number of registers | 34 | - # - - regs_line = [ l for l in lines if 'Total number of registers' in l ][0] - - # Extract the number - - regs = int( re.search( r'\|\s*(\d*)\s*\|', regs_line ).group(1) ) - - return regs - - - diff --git a/designs/weight_manager/synopsys-dc-synthesis/configure.yml b/designs/weight_manager/synopsys-dc-synthesis/configure.yml deleted file mode 100644 index 47a7538e..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/configure.yml +++ /dev/null @@ -1,93 +0,0 @@ -#========================================================================= -# Synopsys DC Synthesis -#========================================================================= -# Author : Christopher Torng, Yanghui Ou -# Date : June 7, 2019 -# - -name: synopsys-dc-synthesis - -#------------------------------------------------------------------------- -# Inputs and Outputs -#------------------------------------------------------------------------- - -inputs: - - adk - - design.v - - constraints.tcl - - run.saif - -outputs: - - design.v - - design.sdc - - design.namemap - -#------------------------------------------------------------------------- -# Commands -#------------------------------------------------------------------------- - -commands: - - bash run.sh - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -parameters: - clock_period: 1.0 - design_name: undefined - # Path to the design instance in run.saif (e.g., tb/dut) - saif_instance: undefined - flatten_effort: 0 - topographical: True - nthreads: 16 # multithreading available to the tool - -#------------------------------------------------------------------------- -# Debug -#------------------------------------------------------------------------- - -debug: - - export DC_EXIT_AFTER_SETUP=1 - - ln -sf results/*.mapped.ddc debug.ddc - - design_vision-xg -topographical -x "source dc.tcl; read_ddc debug.ddc" - -#------------------------------------------------------------------------- -# Assertions -#------------------------------------------------------------------------- - -preconditions: - - - assert Tool( 'dc_shell-xg-t' ) # tool check - - assert File( 'inputs/adk' ) # must exist - - assert File( 'inputs/design.v' ) # must exist - - assert File( 'inputs/constraints.tcl' ) # must exist - -postconditions: - - - assert File( 'outputs/design.v' ) # must exist - - assert File( 'outputs/design.sdc' ) # must exist - - # Basic error checking - - - assert 'error' not in File( 'logs/dc.log' ) - - assert 'Unresolved references' not in File( 'logs/dc.log' ) - - assert 'Unable to resolve' not in File( 'logs/dc.log' ) - - # If GTECH is found, that means this design was not mapped to a - # technology library and is still in DC's generic representation - - - assert 'GTECH' not in File( 'outputs/design.v' ) - - # Sanity check that there is a clock in the constraints - - - assert 'create_clock' in File( 'outputs/design.sdc' ) - - # Check that at least N% of registers were clock-gated - # TODO add this check back - -# - | -# from assertion_helpers import percent_clock_gated, n_regs -# if n_regs() > 10: -# assert percent_clock_gated() > 0.50 - - diff --git a/designs/weight_manager/synopsys-dc-synthesis/dc.tcl b/designs/weight_manager/synopsys-dc-synthesis/dc.tcl deleted file mode 100644 index 19b255e8..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/dc.tcl +++ /dev/null @@ -1,598 +0,0 @@ -#========================================================================= -# dc.tcl -#========================================================================= -# We use Synopsys DC to synthesize a single RTL netlist file into gates. -# -# This script has evolved over time inspired by (1) the Synopsys reference -# methodology scripts that are released year after year on Solvnet, (2) -# synthesis scripts from other research groups, as well as (3) reference -# papers from user groups online. -# -# If you make a major update to this script (e.g., update inspired by the -# latest version of the Synopsys reference methodology), please list the -# changeset in the version history below. -# -# Author : Christopher Torng -# Date : September 30, 2018 -# -#------------------------------------------------------------------------- -# Version History -#------------------------------------------------------------------------- -# -# - 09/30/2018 -- Christopher Torng -# - Clean slate DC scripts -# - We are now independent of the Synopsys Reference Methodology -# - Version of Synopsys DC running "% dc_shell -v": -# dc_shell version - M-2016.12 -# dc_shell build date - Nov 21, 2016 -# -# - 04/08/2018 -- Christopher Torng -# - Our original version was based on the Synopsys reference -# methodology (D-2010.03-SP1) -# - Big update now inspired by the Celerity Synopsys DC scripts, which -# were in turn also based on the Synopsys reference methodology -# (L-2016.03-SP2) -# -#------------------------------------------------------------------------- - -#------------------------------------------------------------------------- -# Designer interface -#------------------------------------------------------------------------- -# Source the designer interface script, which sets up variables from the -# build system, sets up ASIC design kit variables, etc. - -source -echo -verbose designer_interface.tcl - -#------------------------------------------------------------------------- -# Pre-synthesis plugin -#------------------------------------------------------------------------- - -if {[file exists [which $dc_pre_synthesis_plugin]]} { - puts "Info: Reading pre-synth plugin: $dc_pre_synthesis_plugin" - source -echo -verbose $dc_pre_synthesis_plugin -} - -#------------------------------------------------------------------------- -# Setup -#------------------------------------------------------------------------- - -# Set up variables for this specific ASIC design kit - -set SYNOPSYS_TOOL "dc-syn" -source -echo -verbose $dc_adk_tcl - -# Multicore support -- watch how many licenses we have! - -set_host_options -max_cores $dc_num_cores - -# Set up alib caching for faster consecutive runs - -set_app_var alib_library_analysis_path $dc_alib_dir - -# Set up tracking for Synopsys Formality - -set_svf ${dc_results_dir}/${dc_design_name}.mapped.svf - -# Set up search path for libraries and design files - -set_app_var search_path ". $dc_additional_search_path $search_path" - -# Important app vars -# -# - target_library -- DC maps the design to gates in this library (db) -# - synthetic_library -- DesignWare library (sldb) -# - link_library -- Libraries for any other design references (e.g., -# SRAMs, hierarchical blocks, macros, IO libs) (db) - -set_app_var target_library $dc_target_libraries -set_app_var synthetic_library dw_foundation.sldb -set_app_var link_library [join " - * - $target_library - $dc_extra_link_libraries - $synthetic_library - "] - - -# SAIF mapping. - # -saif_map -start - -# Create Milkyway library -# -# By default, Milkyway libraries only have 180 or so layers available to -# use (255 total, but some are reserved). The extend_mw_layers command -# expands the Milkyway library to accommodate up to 4095 layers. - -# Only create new Milkyway design library if it doesn't already exist - -set milkyway_library ${dc_design_name}_lib - -if {![file isdirectory $milkyway_library ]} { - - # Create a new Milkyway library - - extend_mw_layers - create_mw_lib -technology $dc_milkyway_tf \ - -mw_reference_library $dc_milkyway_ref_libraries \ - $milkyway_library - -} else { - - # Reuse existing Milkyway library, but ensure that it is consistent with - # the provided reference Milkyway libraries. - - set_mw_lib_reference $milkyway_library \ - -mw_reference_library $dc_milkyway_ref_libraries - -} - -open_mw_lib $milkyway_library - -# Set up TLU plus (if the files exist) - -if { $dc_topographical == True } { - if {[file exists [which $dc_tluplus_max]]} { - set_tlu_plus_files -max_tluplus $dc_tluplus_max \ - -min_tluplus $dc_tluplus_min \ - -tech2itf_map $dc_tluplus_map - - check_tlu_plus_files - } -} - -# Avoiding X-propagation for synchronous reset DFFs -# -# There are two key variables that help avoid X-propagation for -# synchronous reset DFFs: -# -# - set hdlin_ff_always_sync_set_reset true -# -# - Tells DC to use every constant 0 loaded into a DFF with a clock -# for synchronous reset, and every constant 1 loaded into a DFF with a -# clock for synchronous set -# -# - set compile_seqmap_honor_sync_set_reset true -# -# - Tells DC to preserve synchronous reset or preset logic close to -# the flip-flop -# -# So the hdlin variable first tells DC to treat resets as synchronous, and -# the compile variable tells DC that for all these synchronous reset DFFs, -# keep the logic simple and close to the DFF to avoid X-propagation. The -# hdlin variable applies to the analyze step when we read in the RTL, so -# it must be set before we read in the Verilog. The second variable -# applies to compile and must be set before we run compile_ultra. -# -# Note: Instead of setting the hdlin_ff_always_sync_set_reset variable to -# true, you can specifically tell DC about a particular DFF reset using -# the //synopsys sync_set_reset "reset, int_reset" pragma. -# -# By default, the hdlin_ff_always_async_set_reset variable is set to true, -# and the hdlin_ff_always_sync_set_reset variable is set to false. - -set hdlin_ff_always_sync_set_reset true -set compile_seqmap_honor_sync_set_reset true - -# Remove new variable info messages from the end of the log file - -set_app_var sh_new_variable_message false - -# Corners -# -# If we want to do corners in DC, then we would use this command to set -# the min and max libraries: - -#set_min_library $max_library -min_version $min_library - -# SAIF Name Mapping Database - -#if { ${VINAME} != "NONE" } { -# saif_map -start -#} - -# Hook to drop into interactive Design Compiler shell after setup - -if {[info exists ::env(DC_EXIT_AFTER_SETUP)]} { return } - -#------------------------------------------------------------------------- -# Read design -#------------------------------------------------------------------------- - -# Check libraries - -check_library > $dc_reports_dir/${dc_design_name}.check_library.rpt - -# The first "WORK" is a reserved word for Design Compiler. The value for -# the -path option is customizable. - -define_design_lib WORK -path ${dc_results_dir}/WORK - -# Analyze the RTL source files -# -# Source the read design plugin if it exists. Otherwise, we do a default -# read and elaborate the design. - -if {[file exists [which $dc_read_design_plugin]]} { - puts "Info: Reading read design plugin: $dc_read_design_plugin" - source -echo -verbose $dc_read_design_plugin -} else { - # Since no read design plugin exists, we do a default read - if { ![analyze -format sverilog $dc_rtl_handoff] } { exit 1 } - if {[file exists [which setup-design-params.txt]]} { - elaborate $dc_design_name -file_parameters setup-design-params.txt - rename_design $dc_design_name* $dc_design_name - } else { - elaborate $dc_design_name - } -} - -current_design $dc_design_name -link - -#------------------------------------------------------------------------- -# Write out useful files -#------------------------------------------------------------------------- - -# This ddc can be used as a checkpoint to load up to the current state - -write -hierarchy -format ddc \ - -output ${dc_results_dir}/${dc_design_name}.elab.ddc - -# This Verilog is useful to double-check the netlist that dc will use for -# mapping - -write -hierarchy -format verilog \ - -output ${dc_results_dir}/${dc_design_name}.elab.v - -#------------------------------------------------------------------------- -# Apply design constraints -#------------------------------------------------------------------------- - -# Apply logical design constraints - -puts "Info: Reading constraints file plugin: $dc_constraints_plugin" - -source -echo -verbose $dc_constraints_plugin - -# The check_timing command checks for constraint problems such as -# undefined clocking, undefined input arrival times, and undefined output -# constraints. These constraint problems could cause you to overlook -# timing violations. For this reason, the check_timing command is -# recommended whenever you apply new constraints such as clock -# definitions, I/O delays, or timing exceptions. - -redirect -tee \ - ${dc_reports_dir}/${dc_design_name}.premapped.checktiming.rpt \ - {check_timing} - -# Path groups - -set ports_clock_root [filter_collection \ - [get_attribute [get_clocks] sources] \ - object_class==port] - -group_path -name REGOUT \ - -to [all_outputs] - -group_path -name REGIN \ - -from [remove_from_collection [all_inputs] $ports_clock_root] - -group_path -name FEEDTHROUGH \ - -from [remove_from_collection [all_inputs] $ports_clock_root] \ - -to [all_outputs] - -# Apply physical design constraints -# -# Set the minimum and maximum routing layers used in DC topographical mode - -if { $dc_topographical == True } { - set_ignored_layers -min_routing_layer $ADK_MIN_ROUTING_LAYER_DC - set_ignored_layers -max_routing_layer $ADK_MAX_ROUTING_LAYER_DC - - report_ignored_layers -} - -#------------------------------------------------------------------------- -# Additional options -#------------------------------------------------------------------------- - -# Replace special characters with non-special ones before writing out the -# synthesized netlist (e.g., "\bus[5]" -> "bus_5_") - -set_app_var verilogout_no_tri true - -# Prevent assignment statements in the Verilog netlist. - -set_fix_multiple_port_nets -all -buffer_constants - -# Choose design flattening options - -if {[info exists DC_FLATTEN_EFFORT]} { - set dc_flatten_effort $DC_FLATTEN_EFFORT - if {"$dc_flatten_effort" == ""} { - set dc_flatten_effort 0 - } -} else { - set dc_flatten_effort 0 -} - -puts "Info: Flattening effort (DC_FLATTEN_EFFORT) = $dc_flatten_effort" - -set compile_ultra_options "" -if {$dc_flatten_effort == 0} { - puts "Info: All design hierarchies are preserved unless otherwise specified." - set_app_var compile_ultra_ungroup_dw false - puts "Info: Design Compiler compile_ultra boundary optimization is disabled." - append compile_ultra_options " -no_autoungroup -no_boundary_optimization" - -} elseif {$dc_flatten_effort == 1} { - puts "Info: Unconditionally ungroup the DesignWare cells." - set_app_var compile_ultra_ungroup_dw true - puts "Info: Design Compiler compile_ultra automatic ungrouping is disabled." - puts "Info: Design Compiler compile_ultra boundary optimization is disabled." - append compile_ultra_options " -no_autoungroup -no_boundary_optimization" - -} elseif {$dc_flatten_effort == 2} { - puts "Info: Unconditionally ungroup the DesignWare cells." - set_app_var compile_ultra_ungroup_dw true - puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." - puts "Info: Design Compiler compile_ultra boundary optimization is enabled." - append compile_ultra_options "" - -} elseif {$dc_flatten_effort == 3} { - set ungroup_start_level 2 - ungroup -start_level $ungroup_start_level -all -flatten - puts "Info: All hierarchical cells starting from level $ungroup_start_level are flattened." - puts "Info: Unconditionally ungroup the DesignWare cells." - puts "Info: Design Compiler compile_ultra automatic ungrouping is enabled." - puts "Info: Design Compiler compile_ultra boundary optimization is enabled." - set_app_var compile_ultra_ungroup_dw true - append compile_ultra_options "" - -} else { - puts "Info: Unrecognizable DC_FLATTEN_EFFORT value: $dc_flatten_effort" - exit -} - -# Enable or disable clock gating - -if {[info exists DC_GATE_CLOCK]} { - set dc_gate_clock $DC_GATE_CLOCK - if {"$dc_gate_clock" == ""} { - set dc_gate_clock true - } -} else { - set dc_gate_clock true -} - -puts "Info: Clock gating (DC_GATE_CLOCK) = $dc_gate_clock" - -if {$dc_gate_clock == true} { - append compile_ultra_options " -gate_clock" -} - -# Check design for consistency -# -# Most problems with synthesis will be caught in this report - -check_design -summary -check_design \ - > ${dc_reports_dir}/${dc_design_name}.premapped.checkdesign.rpt - -#------------------------------------------------------------------------- -# Compile -#------------------------------------------------------------------------- - -puts "Info: DC compile_ultra options = $compile_ultra_options" - -eval "compile_ultra $compile_ultra_options" - -# High-effort area optimization -# -# This command was introduced in I-2013.12 and performs monotonic -# gate-to-gate optimization on mapped designs. It is supposed to improve -# area without degrading timing or leakage. - -# Skip this step by setting the DC_SKIP_OPTIMIZE_NETLIST variable in the -# pre-synthesis plugin - -if {!([info exists DC_SKIP_OPTIMIZE_NETLIST] && $DC_SKIP_OPTIMIZE_NETLIST)} { - optimize_netlist -area -} - -# Check design - -check_design -summary -check_design > ${dc_reports_dir}/${dc_design_name}.mapped.checkdesign.rpt - -# Write the .namemap file for the Energy analysis - -if {[file exists "inputs/run.saif" ]} { - saif_map \ - -create_map \ - -input "inputs/run.saif" \ - -source_instance ${dc_saif_instance} -} - -#------------------------------------------------------------------------- -# Write out the design -#------------------------------------------------------------------------- - -# Synopsys Formality - -set_svf -off - -# Use naming rules to preserve structs - -define_name_rules verilog -preserve_struct_ports - -report_names \ - -rules verilog \ - > ${dc_reports_dir}/${dc_design_name}.mapped.naming.rpt - -change_names -rules verilog -hierarchy - -# Write out files - -write -format ddc \ - -hierarchy \ - -output ${dc_results_dir}/${dc_design_name}.mapped.ddc - -write -format verilog \ - -hierarchy \ - -output ${dc_results_dir}/${dc_design_name}.mapped.v - -write -format svsim \ - -output ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v - -# Dump the mapped.v and svwrapper.v into one svsim.v file to make it -# easier to include a single file for gate-level simulation. The svwrapper -# matches the interface of the original RTL even if using SystemVerilog -# features (e.g., array of arrays, uses parameters, etc.). - -sh cat ${dc_results_dir}/${dc_design_name}.mapped.v \ - ${dc_results_dir}/${dc_design_name}.mapped.svwrapper.v \ - > ${dc_results_dir}/${dc_design_name}.mapped.svsim.v - -# Write top-level verilog view needed for block instantiation - -write \ - -format verilog \ - -output ${dc_results_dir}/${dc_design_name}.mapped.top.v - -# Floorplan - -if { $dc_topographical == True } { - write_floorplan -all ${dc_results_dir}/${dc_design_name}.mapped.fp -} - -# Parasitics - -write_parasitics -output ${dc_results_dir}/${dc_design_name}.mapped.spef - -# SDF for back-annotated gate-level simulation - -write_sdf ${dc_results_dir}/${dc_design_name}.mapped.sdf - -# Do not write out net RC info into SDC - -set_app_var write_sdc_output_lumped_net_capacitance false -set_app_var write_sdc_output_net_resistance false - -# SDC constraints - -write_sdc -nosplit ${dc_results_dir}/${dc_design_name}.mapped.sdc - -#------------------------------------------------------------------------- -# Final reports -#------------------------------------------------------------------------- - -# Report units - -redirect -tee \ - ${dc_reports_dir}/${dc_design_name}.mapped.units.rpt \ - {report_units} - -# Report QOR - -report_qor > ${dc_reports_dir}/${dc_design_name}.mapped.qor.rpt - -# Report timing - -report_clock_timing \ - -type summary \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.clock.rpt - -report_timing \ - -input_pins -capacitance -transition_time \ - -nets -significant_digits 4 -nosplit \ - -path_type full_clock -attributes \ - -nworst 10 -max_paths 30 -delay_type max \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.setup.rpt - -report_timing \ - -input_pins -capacitance -transition_time \ - -nets -significant_digits 4 -nosplit \ - -path_type full_clock -attributes \ - -nworst 10 -max_paths 30 -delay_type min \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.hold.rpt - -# Report constraints - -report_constraint \ - -nosplit \ - -verbose \ - > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.rpt - -report_constraint \ - -nosplit \ - -verbose \ - -all_violators \ - > ${dc_reports_dir}/${dc_design_name}.mapped.constraints.violators.rpt - -report_timing_requirements \ - > ${dc_reports_dir}/${dc_design_name}.mapped.timing.requirements.rpt - -# Report area - -report_area \ - -hierarchy \ - -physical \ - -nosplit \ - > ${dc_reports_dir}/${dc_design_name}.mapped.area.rpt - -# Report references and resources - -report_reference \ - -nosplit \ - -hierarchy \ - > ${dc_reports_dir}/${dc_design_name}.mapped.reference.rpt - -report_resources \ - -nosplit \ - -hierarchy \ - > ${dc_reports_dir}/${dc_design_name}.mapped.resources.rpt - -# Report power -# -# Use SAIF file for power analysis -if {[file exists "inputs/run.saif" ]} { - read_saif \ - -map_names \ - -input "inputs/run.saif" \ - -instance_name $dc_saif_instance \ - -verbose - - report_saif \ - -hier \ - -annotated_flag \ - -rtl_saif \ - > ${dc_reports_dir}/${dc_design_name}.mapped.saif.rpt - - saif_map \ - -type ptpx \ - -write_map \ - ${dc_reports_dir}/${dc_design_name}.namemap -} - -report_power \ - -nosplit \ - -hier \ - > ${dc_reports_dir}/${dc_design_name}.mapped.power.rpt - -report_clock_gating \ - -nosplit \ - > ${dc_reports_dir}/${dc_design_name}.mapped.clock_gating.rpt - -#------------------------------------------------------------------------- -# Post-synthesis plugin -#------------------------------------------------------------------------- - -if {[file exists [which $dc_post_synthesis_plugin]]} { - puts "Info: Reading post-synthesis plugin: $dc_post_synthesis_plugin" - source -echo -verbose $dc_post_synthesis_plugin -} - -exit - diff --git a/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl b/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl deleted file mode 100644 index 0996d017..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/designer_interface.tcl +++ /dev/null @@ -1,90 +0,0 @@ -#========================================================================= -# designer_interface.tcl -#========================================================================= -# The designer_interface.tcl file is the first script run by Design -# Compiler (see the top of dc.tcl). It is the interface that connects the -# dc-synthesis scripts with the following: -# -# - Build system parameters -# - Build system inputs -# - ASIC design kit -# - Plugin scripts -# -# Author : Christopher Torng -# Date : April 8, 2018 - -#------------------------------------------------------------------------- -# Parameters -#------------------------------------------------------------------------- - -set dc_design_name $::env(design_name) -set dc_saif_instance $::env(saif_instance) -set dc_clock_period $::env(clock_period) -set dc_flatten_effort $::env(flatten_effort) -set dc_topographical $::env(topographical) - -#------------------------------------------------------------------------- -# Inputs -#------------------------------------------------------------------------- - -set dc_rtl_handoff inputs/design.v -set adk_dir inputs/adk - -# Extra libraries -# -# The glob below will capture any libraries collected by the build system -# (e.g., SRAM libraries) generated from steps that synthesis depends on. -# -# To add more link libraries (e.g., IO cells, hierarchical blocks), append -# to the "dc_extra_link_libraries" variable in the pre-synthesis plugin -# like this: -# -# set dc_extra_link_libraries [join " -# $dc_extra_link_libraries -# extra1.db -# extra2.db -# extra3.db -# "] - -set dc_extra_link_libraries [join " - [glob -nocomplain inputs/*.db] - [glob -nocomplain inputs/adk/*.db] - "] - -#------------------------------------------------------------------------- -# Interface to the ASIC design kit -#------------------------------------------------------------------------- - -set dc_milkyway_ref_libraries $adk_dir/stdcells.mwlib -set dc_milkyway_tf $adk_dir/rtk-tech.tf -set dc_tluplus_map $adk_dir/rtk-tluplus.map -set dc_tluplus_max $adk_dir/rtk-max.tluplus -set dc_tluplus_min $adk_dir/rtk-min.tluplus -set dc_adk_tcl $adk_dir/adk.tcl -set dc_target_libraries stdcells.db - -# Extra libraries - -set dc_additional_search_path $adk_dir - -#------------------------------------------------------------------------- -# Directories -#------------------------------------------------------------------------- - -set dc_flow_dir . -set dc_plugins_dir . -set dc_logs_dir logs -set dc_reports_dir reports -set dc_results_dir results -set dc_alib_dir alib - -#------------------------------------------------------------------------- -# Interface to plugins -#------------------------------------------------------------------------- - -set dc_pre_synthesis_plugin pre_synth.tcl -set dc_read_design_plugin read_design.tcl -set dc_constraints_plugin inputs/constraints.tcl -set dc_post_synthesis_plugin post_synth.tcl - - diff --git a/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl b/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl deleted file mode 100644 index e5cab31f..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/pre_synth.tcl +++ /dev/null @@ -1,49 +0,0 @@ -#========================================================================= -# pre_synth.tcl -#========================================================================= -# This plug-in script is called before synthesis -# -# Author : Christopher Torng -# Date : May 14, 2018 - -# Number of cores for multicore optimization - -set dc_num_cores $env(nthreads) - -# Add more link libraries (e.g., IO cells, hierarchical blocks) - -# set dc_extra_link_libraries [join " -# $dc_extra_link_libraries -# extra1.db -# extra2.db -# extra3.db -# "] - -# Enable additional area optimizations (skip false = enable optimizations) - -set DC_SKIP_OPTIMIZE_NETLIST true - -# Enable clock-gating - -set DC_GATE_CLOCK true - -# DC flatten effort -# -# - Effort 0: No auto-ungrouping / boundary optimizations (strict hierarchy) -# - Effort 1: No auto-ungrouping / boundary optimizations -# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) -# - Effort 2: Enable auto-ungrouping / boundary optimizations -# DesignWare cells are ungrouped (var compile_ultra_ungroup_dw) -# - Effort 3: Everything ungrouped + level param for how deep to ungroup -# -# Note that even with boundary optimizations off, DC will still propagate -# constants across the boundary, although this can be disabled with a -# variable if we really wanted to disable it. - -set DC_FLATTEN_EFFORT $env(flatten_effort) - -# When boundary optimizations are off, set this variable to true to still -# allow unconnected registers to be removed. - -set compile_optimize_unloaded_seq_logic_with_no_bound_opt true - diff --git a/designs/weight_manager/synopsys-dc-synthesis/run.sh b/designs/weight_manager/synopsys-dc-synthesis/run.sh deleted file mode 100755 index ae57c1f0..00000000 --- a/designs/weight_manager/synopsys-dc-synthesis/run.sh +++ /dev/null @@ -1,114 +0,0 @@ -#! /usr/bin/env bash -#========================================================================= -# run.sh -#========================================================================= -# Author : Christopher Torng -# Date : June 2, 2019 -# - -# Print commands during execution - -set -x - -# DC shell - -dc_exec='dc_shell-xg-t -64bit' - -# Build directories - -rm -rf ./logs -rm -rf ./reports -rm -rf ./results - -mkdir -p logs -mkdir -p reports -mkdir -p results - -# alib -# -# Design Compiler caches analyzed libraries to improve performance using -# ".alib" directories. The alib takes a while to generate but is reused on -# subsequent runs. It is useful to store a centralized copy of the alib to -# avoid re-generating the alib (usually only several minutes but can be -# annoying) on every new clone of the ASIC repo. -# -# However, if DC sees a .db that does not have an associated .alib it will -# try to automatically create one. This is not usually a problem when -# students just use standard cells, but if a student is trying to use -# SRAMs, then they will be using new .db files that DC has not seen yet. -# The problem is that students do not have write permissions to the -# centralized copy of the alib in the ADK. -# -# The solution we use is to create a local alib directory in the current -# build directory with _per-file_ symlinks to the centralized alib (and -# with the same directory hierarchy). This allows students to reuse the -# centralized copies of the alib files while allowing new alibs (e.g., for -# SRAMs) to be generated locally. -# -# This is possible because the alibs are stored in a directory that holds -# a ".db.alib" file for each db file: -# -# - alib -# - alib-52 -# - iocells.db.alib -# - stdcells.db.alib -# -# This new alib directory just needs to contain symlinks to each saved -# alib in the ADK. This can be done simply by using "cp -srf" of the ADK -# alib to the build directory, which generates symbolic links to each file -# instead of copying. This way, the student can access the master copy of -# the saved alibs in the ADK, and if there are any additional db's -# specified, their alibs will be saved in the local build directory. - -rm -rf alib -mkdir -p alib - -cp -srf $PWD/inputs/adk/alib/* alib || true - -# Run the synthesis script - -if [ "x$topographical" == "xTrue" ]; then - opt_topographical='-topographical_mode' -else - opt_topographical= -fi - -$dc_exec $opt_topographical -f dc.tcl -output_log_file logs/dc.log || exit 1 - -# Compress the spef file - -cd results -gzip *.mapped.spef -cd .. - -# Set up the outputs - -mkdir -p outputs && cd outputs - -ln -sf ../results/*.mapped.v design.v -ln -sf ../results/*.mapped.sdc design.sdc -ln -sf ../results/*.mapped.spef.gz design.spef.gz -ln -sf ../reports/*.namemap design.namemap - -cd .. - -# Grep for failure messages - -grep --color "^Error" logs/dc.log || true -grep --color -B 3 "*** Presto compilation terminated" logs/dc.log || true -grep --color "unresolved references." logs/dc.log || true - -# ELAB-405 -# -# When using a Verilog generation tool, there may be a -# generation/translation mistake that defines a net twice. This will give -# a message like this: -# -# Warning: ./inputs/design.v:2473: Net mul__recv__msg__opd_b[0] or a -# directly connected net may be driven by more than one process or block. -# (ELAB-405) -# -# This is usually a bad sign.. -# - -grep --color "ELAB-405" logs/dc.log || true diff --git a/dragonphy/views.py b/dragonphy/views.py index b0de2fce..764ebcd8 100644 --- a/dragonphy/views.py +++ b/dragonphy/views.py @@ -151,7 +151,8 @@ def get_deps_new_asic(cell_name=None, impl_file=None, process='tsmc16'): override['sram'] = 'new_chip_src_freepdk45' skip.add('sram_144_1024_freepdk45') elif process == 'tsmc16': - raise Exception('The SRAM view for TSMC16 has not been implemented yet.') + override['sram'] = 'new_chip_src_tsmc16' + skip.add('TS1N16FFCLLSBLVTC1024X144M4SW') else: raise Exception(f'Unknown process: {process}') diff --git a/tests/test_config/test_config.py b/tests/test_config/test_config.py index 1aab20b3..f58e5340 100644 --- a/tests/test_config/test_config.py +++ b/tests/test_config/test_config.py @@ -1,8 +1,10 @@ +import pytest from dragonphy import * -def test_new_asic(): - print('Test New ASIC Config') - print(get_deps_new_asic('dragonphy_top', process='freepdk-45nm')) +@pytest.mark.parametrize('process', ['freepdk-45nm', 'tsmc16']) +def test_new_asic_config(process): + print(f'Test New ASIC Config (process={process})') + print(get_deps_new_asic('dragonphy_top', process=process)) def test_new_chip_src_config(): print('Test New Chip Source Config') From 8fdcf63cd74e33a632d14a25cb7ce5a4ed747224 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 7 May 2020 13:52:08 -0700 Subject: [PATCH 16/16] remove SYN test since the synthesis test is covered more thoroughly in test_mflowgen --- .buildkite/pipeline.yml | 2 +- tests/new_tests/SYN/test_syn.py | 73 --------------------------------- 2 files changed, 1 insertion(+), 74 deletions(-) delete mode 100644 tests/new_tests/SYN/test_syn.py diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml index 8ecda5e8..d0f1de72 100644 --- a/.buildkite/pipeline.yml +++ b/.buildkite/pipeline.yml @@ -3,7 +3,7 @@ steps: command: | # set up environment source /cad/modules/tcl/init/bash - module load base xcelium dc_shell + module load base xcelium export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v export BUILD_VIEW=cpu printenv diff --git a/tests/new_tests/SYN/test_syn.py b/tests/new_tests/SYN/test_syn.py deleted file mode 100644 index 7572beca..00000000 --- a/tests/new_tests/SYN/test_syn.py +++ /dev/null @@ -1,73 +0,0 @@ -# general imports -import os -import re -import pytest -from pathlib import Path - -# DragonPHY imports -from dragonphy import * - -THIS_DIR = Path(__file__).parent.resolve() -BUILD_DIR = THIS_DIR / 'build' - -TEMPLATE = '''\ -set search_path {inc_dirs} -set file_list {src_files} - -set status [analyze -format sverilog $file_list] -if {{$status != 1}} {{ - exit 1 -}} - -set status [elaborate {top_name}] -if {{$status != 1}} {{ - exit 1 -}} - -exit 0 -''' - -def tcl_list(vals): - retval = ' '.join(f'{{{val}}}' for val in vals) - retval = f'[list {retval}]' - return retval - -@pytest.mark.skipif('FPGA_SERVER' in os.environ, - reason='This test cannot run on FPGA servers.') -def test_sim(top_cell='dragonphy_top', run_tcl='run.tcl'): - src_files = [] - - # manually add JTAG interface because it is not instantiated - # anywhere (only appears in I/O specifications) - src_files += [get_file('vlog/new_chip_src/jtag/jtag_intf.sv')] - # add the rest of the files - src_files += get_deps_new_asic(top_cell) - - inc_dirs = [get_dir('inc/new_asic')] - top_name = top_cell - - BUILD_DIR.mkdir(exist_ok=True, parents=True) - with open(BUILD_DIR / run_tcl, 'w') as f: - f.write( - TEMPLATE.format( - inc_dirs=tcl_list(inc_dirs), - src_files=tcl_list(src_files), - top_name=top_name - ) - ) - - args = [] - args += ['dc_shell'] - args += ['-f', run_tcl] - args += ['-no_init'] - args += ['-no_home_init'] - args += ['-no_local_init'] - args += ['-no_gui'] - args += ['-no_log'] - - err_str = re.compile('(error)|(^Error:)') - subprocess_run(args, cwd=BUILD_DIR, err_str=err_str) - - -if __name__ == "__main__": - test_sim()