Power sequencing is seemingly incorrect.

[gibsonpil]

Correct me if I'm wrong, but it looks as though VCC-IO and VDD-SYS/VDD-CORE come up at the same time in your design. The datasheet for the F133/D1s states that the VCC-IO rail has to come up at least 2ms before VDD-SYS/VDD-CORE.

It seems as though you may have realized this and added an RC circuit to the enable pins on the buck converters for the +1.8V and +0.9V rails to delay start-up, but in actuality you should only delay enabling the +0.9V rail to achieve the desired sequencing.

Similarly, it looks like the reset pin is required to be held low until at least 64ms after VDD-CORE comes up, but in your design it's always pulled high (unless someone hits the reset button).

Let me know what you think.