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orin.c
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orin.c
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/*MIT License
*
*Copyright (c) 2024 Rubberazer
*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the "Software"), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in all
*copies or substantial portions of the Software.
*
*THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
*AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
*LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
*OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
*SOFTWARE.
*/
/* jetgpio version 2.0 */
/* Orin Nano & NX extension */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <math.h>
#include <sys/fcntl.h>
#include <sys/mman.h>
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <sys/file.h>
#include <sys/types.h>
#include <sys/poll.h>
#include <linux/i2c-dev.h>
#include <linux/i2c.h>
#include <linux/spi/spidev.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <pthread.h>
#include <linux/version.h>
#include "Jetclocks/jetclocks.h"
#include "jetgpio.h"
#define BILLION 1000000000L
static int fd_GPIO;
static volatile GPIO_CNF_Init pin_CNF;
static volatile GPIO_CNF_Init pin_DEB;
static volatile GPIO_CNF_Init pin_IN;
static volatile GPIO_CNF_Init pin_OUT;
static volatile GPIO_CNF_Init pin_OUT_VLE;
static volatile GPIO_CNF_Init pin_INT_CLR;
static volatile GPIO_CNF_Init pin_MUX;
static volatile GPIO_CNF_Init pin_CFG;
PISRFunc ISRFunc_CFG[41];
static volatile uint32_t *PWM1;
static volatile uint32_t *PWM5;
static volatile uint32_t *PWM7;
static volatile uint32_t PWM1_Init;
static volatile uint32_t PWM5_Init;
static volatile uint32_t PWM7_Init;
static i2cInfo_t i2cInfo[8];
#if LINUX_VERSION_CODE < KERNEL_VERSION(5,14,1)
static int i2c_speed[8];
#endif
static SPIInfo_t SpiInfo[3];
static volatile GPIO_CNFO *pin3;
static volatile GPIO_CNFO *pin5;
static volatile GPIO_CNFO *pin7;
static volatile GPIO_CNFO *pin8;
static volatile GPIO_CNFO *pin10;
static volatile GPIO_CNFO *pin11;
static volatile GPIO_CNFO *pin12;
static volatile GPIO_CNFO *pin13;
static volatile GPIO_CNFO *pin15;
static volatile GPIO_CNFO *pin16;
static volatile GPIO_CNFO *pin18;
static volatile GPIO_CNFO *pin19;
static volatile GPIO_CNFO *pin21;
static volatile GPIO_CNFO *pin22;
static volatile GPIO_CNFO *pin23;
static volatile GPIO_CNFO *pin24;
static volatile GPIO_CNFO *pin26;
static volatile GPIO_CNFO *pin27;
static volatile GPIO_CNFO *pin28;
static volatile GPIO_CNFO *pin29;
static volatile GPIO_CNFO *pin31;
static volatile GPIO_CNFO *pin32;
static volatile GPIO_CNFO *pin33;
static volatile GPIO_CNFO *pin35;
static volatile GPIO_CNFO *pin36;
static volatile GPIO_CNFO *pin37;
static volatile GPIO_CNFO *pin38;
static volatile GPIO_CNFO *pin40;
static volatile uint32_t *pinmux3;
static volatile uint32_t *pinmux5;
static volatile uint32_t *pinmux7;
static volatile uint32_t *pinmux8;
static volatile uint32_t *pinmux10;
static volatile uint32_t *pinmux11;
static volatile uint32_t *pinmux12;
static volatile uint32_t *pinmux13;
static volatile uint32_t *pinmux15;
static volatile uint32_t *pinmux16;
static volatile uint32_t *pinmux18;
static volatile uint32_t *pinmux19;
static volatile uint32_t *pinmux21;
static volatile uint32_t *pinmux22;
static volatile uint32_t *pinmux23;
static volatile uint32_t *pinmux24;
static volatile uint32_t *pinmux26;
static volatile uint32_t *pinmux27;
static volatile uint32_t *pinmux28;
static volatile uint32_t *pinmux29;
static volatile uint32_t *pinmux31;
static volatile uint32_t *pinmux32;
static volatile uint32_t *pinmux33;
static volatile uint32_t *pinmux35;
static volatile uint32_t *pinmux36;
static volatile uint32_t *pinmux37;
static volatile uint32_t *pinmux38;
static volatile uint32_t *pinmux40;
static volatile uint32_t *pincfg3;
static volatile uint32_t *pincfg5;
static volatile uint32_t *pincfg7;
static volatile uint32_t *pincfg8;
static volatile uint32_t *pincfg10;
static volatile uint32_t *pincfg11;
static volatile uint32_t *pincfg12;
static volatile uint32_t *pincfg13;
static volatile uint32_t *pincfg15;
static volatile uint32_t *pincfg16;
static volatile uint32_t *pincfg18;
static volatile uint32_t *pincfg19;
static volatile uint32_t *pincfg21;
static volatile uint32_t *pincfg22;
static volatile uint32_t *pincfg23;
static volatile uint32_t *pincfg24;
static volatile uint32_t *pincfg26;
static volatile uint32_t *pincfg27;
static volatile uint32_t *pincfg28;
static volatile uint32_t *pincfg29;
static volatile uint32_t *pincfg31;
static volatile uint32_t *pincfg32;
static volatile uint32_t *pincfg33;
static volatile uint32_t *pincfg35;
static volatile uint32_t *pincfg36;
static volatile uint32_t *pincfg37;
static volatile uint32_t *pincfg38;
static volatile uint32_t *pincfg40;
static void *baseCNF_AON;
static void *baseCNF_NAON;
static void *basePINMUX_AON;
static void *basePINMUX_G7;
static void *basePINMUX_G3;
static void *basePINMUX_EDP;
static void *basePINMUX_G4;
static void *basePINMUX_G2;
static void *basePWM1;
static void *basePWM5;
static void *basePWM7;
static unsigned clk_rate_PWM1 = 408000000;
static unsigned clk_rate_PWM5 = 408000000;
static unsigned clk_rate_PWM7 = 408000000;
static volatile unsigned global_int;
static pthread_t callThd[28];
static pthread_attr_t attr;
static int pth_err;
static void *status_thread;
static int thread_n = 0;
static unsigned long long pin_tracker = 0;
int gpioInitialise(void)
{
int status = 1;
// Getting the page size
int pagesize = sysconf(_SC_PAGESIZE);
// read physical memory (needs root)
fd_GPIO = open("/dev/mem", O_RDWR | O_SYNC);
if (fd_GPIO < 0) {
perror("/dev/mem");
fprintf(stderr, "Please run this program as root (for example with sudo)\n");
return -1;
}
// Mapping GPIO_CNF_AON
baseCNF_AON = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, base_CNF_AON);
if (baseCNF_AON == MAP_FAILED) {
return -2;
}
// Mapping GPIO_CNF_NAON
baseCNF_NAON = mmap(0, 5 * pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, base_CNF_NAON);
if (baseCNF_NAON == MAP_FAILED) {
return -3;
}
// Mapping PINMUX_AON
basePINMUX_AON = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_AON);
if (basePINMUX_AON == MAP_FAILED) {
return -4;
}
// Mapping PINMUX_G7
basePINMUX_G7 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_G7);
if (basePINMUX_G7 == MAP_FAILED) {
return -5;
}
// Mapping PINMUX_G3
basePINMUX_G3 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_G3);
if (basePINMUX_G3 == MAP_FAILED) {
return -6;
}
// Mapping PINMUX_EDP
basePINMUX_EDP = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_EDP);
if (basePINMUX_EDP == MAP_FAILED) {
return -7;
}
// Mapping PINMUX_G4
basePINMUX_G4 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_G4);
if (basePINMUX_G4 == MAP_FAILED) {
return -8;
}
// Mapping PINMUX_G2
basePINMUX_G2 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, Pinmux_G2);
if (basePINMUX_G2 == MAP_FAILED) {
return -9;
}
// Mapping PWM1
basePWM1 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, base_PWM1);
if (basePWM1 == MAP_FAILED) {
return -10;
}
// Mapping PWM5
basePWM5 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, base_PWM5);
if (basePWM5 == MAP_FAILED) {
return -11;
}
// Mapping PWM7
basePWM7 = mmap(0, pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd_GPIO, base_PWM7);
if (basePWM7 == MAP_FAILED) {
return -12;
}
// Pointer to CNFO_3
pin3 = (GPIO_CNFO volatile *)((char *)baseCNF_AON + CNFO_3);
pin_CNF.pin3 = pin3->CNF[0];
pin_DEB.pin3 = pin3->DEB[0];
pin_IN.pin3 = pin3->IN[0];
pin_OUT.pin3 = pin3->OUT[0];
pin_OUT_VLE.pin3 = pin3->OUT_VLE[0];
// Pointer to PINMUX3
pinmux3 = (uint32_t volatile *)((char *)basePINMUX_AON + PINMUXO_3);
pin_MUX.pin3 = *pinmux3;
// Pointer to PINCFG3
pincfg3 = (uint32_t volatile *)((char *)basePINMUX_AON + CFGO_3);
pin_CFG.pin3 = *pincfg3;
// Pointer to CNF5
pin5 = (GPIO_CNFO volatile *)((char *)baseCNF_AON + CNFO_5);
pin_CNF.pin5 = pin5->CNF[0];
pin_DEB.pin5 = pin5->DEB[0];
pin_IN.pin5 = pin5->IN[0];
pin_OUT.pin5 = pin5->OUT[0];
pin_OUT_VLE.pin5 = pin5->OUT_VLE[0];
// Pointer to PINMUX5
pinmux5 = (uint32_t volatile *)((char *)basePINMUX_AON + PINMUXO_5);
pin_MUX.pin5 = *pinmux5;
// Pointer to PINCFG5
pincfg5 = (uint32_t volatile *)((char *)basePINMUX_AON + CFGO_5);
pin_CFG.pin5 = *pincfg5;
// Pointer to CNF7
pin7 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_7);
pin_CNF.pin7 = pin7->CNF[0];
pin_DEB.pin7 = pin7->DEB[0];
pin_IN.pin7 = pin7->IN[0];
pin_OUT.pin7 = pin7->OUT[0];
pin_OUT_VLE.pin7 = pin7->OUT_VLE[0];
// Pointer to PINMUX7
pinmux7 = (uint32_t volatile *)((char *)basePINMUX_G7 + PINMUXO_7);
pin_MUX.pin7 = *pinmux7;
// Pointer to PINCFG7
pincfg7 = (uint32_t volatile *)((char *)basePINMUX_G7 + CFGO_7);
pin_CFG.pin7 = *pincfg7;
// Pointer to CNF8
pin8 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_8);
pin_CNF.pin8 = pin8->CNF[0];
pin_DEB.pin8 = pin8->DEB[0];
pin_IN.pin8 = pin8->IN[0];
pin_OUT.pin8 = pin8->OUT[0];
pin_OUT_VLE.pin8 = pin8->OUT_VLE[0];
// Pointer to PINMUX8
pinmux8 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_8);
pin_MUX.pin8 = *pinmux8;
// Pointer to PINCFG8
pincfg8 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_8);
pin_CFG.pin8 = *pincfg8;
// Pointer to CNF10
pin10 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_10);
pin_CNF.pin10 = pin10->CNF[0];
pin_DEB.pin10 = pin10->DEB[0];
pin_IN.pin10 = pin10->IN[0];
pin_OUT.pin10 = pin10->OUT[0];
pin_OUT_VLE.pin10 = pin10->OUT_VLE[0];
// Pointer to PINMUX10
pinmux10 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_10);
pin_MUX.pin10 = *pinmux10;
// Pointer to PINCFG10
pincfg10 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_10);
pin_CFG.pin10 = *pincfg10;
// Pointer to CNF11
pin11 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_11);
pin_CNF.pin11 = pin11->CNF[0];
pin_DEB.pin11 = pin11->DEB[0];
pin_IN.pin11 = pin11->IN[0];
pin_OUT.pin11 = pin11->OUT[0];
pin_OUT_VLE.pin11 = pin11->OUT_VLE[0];
// Pointer to PINMUX11
pinmux11 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_11);
pin_MUX.pin11 = *pinmux11;
// Pointer to PINCFG11
pincfg11 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_11);
pin_CFG.pin11 = *pincfg11;
// Pointer to CNF12
pin12 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_12);
pin_CNF.pin12 = pin12->CNF[0];
pin_DEB.pin12 = pin12->DEB[0];
pin_IN.pin12 = pin12->IN[0];
pin_OUT.pin12 = pin12->OUT[0];
pin_OUT_VLE.pin12 = pin12->OUT_VLE[0];
// Pointer to PINMUX12
pinmux12 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_12);
pin_MUX.pin12 = *pinmux12;
// Pointer to PINCFG12
pincfg12 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_12);
pin_CFG.pin12 = *pincfg12;
// Pointer to CNF13
pin13 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_13);
pin_CNF.pin13 = pin13->CNF[0];
pin_DEB.pin13 = pin13->DEB[0];
pin_IN.pin13 = pin13->IN[0];
pin_OUT.pin13 = pin13->OUT[0];
pin_OUT_VLE.pin13 = pin13->OUT_VLE[0];
// Pointer to PINMUX13
pinmux13 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_13);
pin_MUX.pin13 = *pinmux13;
// Pointer to PINCFG13
pincfg13 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_13);
pin_CFG.pin13 = *pincfg13;
// Pointer to CNF15
pin15 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_15);
pin_CNF.pin15 = pin15->CNF[0];
pin_DEB.pin15 = pin15->DEB[0];
pin_IN.pin15 = pin15->IN[0];
pin_OUT.pin15 = pin15->OUT[0];
pin_OUT_VLE.pin15 = pin15->OUT_VLE[0];
// Pointer to PINMUX15
pinmux15 = (uint32_t volatile *)((char *)basePINMUX_EDP + PINMUXO_15);
pin_MUX.pin15 = *pinmux15;
// Pointer to PINCFG15
pincfg15 = (uint32_t volatile *)((char *)basePINMUX_EDP + CFGO_15);
pin_CFG.pin15 = *pincfg15;
// Pointer to CNF16
pin16 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_16);
pin_CNF.pin16 = pin16->CNF[0];
pin_DEB.pin16 = pin16->DEB[0];
pin_IN.pin16 = pin16->IN[0];
pin_OUT.pin16 = pin16->OUT[0];
pin_OUT_VLE.pin16 = pin16->OUT_VLE[0];
// Pointer to PINMUX16
pinmux16 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_16);
pin_MUX.pin16 = *pinmux16;
// Pointer to PINCFG16
pincfg16 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_16);
pin_CFG.pin16 = *pincfg16;
// Pointer to CNF18
pin18 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_18);
pin_CNF.pin18 = pin18->CNF[0];
pin_DEB.pin18 = pin18->DEB[0];
pin_IN.pin18 = pin18->IN[0];
pin_OUT.pin18 = pin18->OUT[0];
pin_OUT_VLE.pin18 = pin18->OUT_VLE[0];
// Pointer to PINMUX18
pinmux18 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_18);
pin_MUX.pin18 = *pinmux18;
// Pointer to PINCFG18
pincfg18 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_18);
pin_CFG.pin18 = *pincfg18;
// Pointer to CNF19
pin19 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_19);
pin_CNF.pin19 = pin19->CNF[0];
pin_DEB.pin19 = pin19->DEB[0];
pin_IN.pin19 = pin19->IN[0];
pin_OUT.pin19 = pin19->OUT[0];
pin_OUT_VLE.pin19 = pin19->OUT_VLE[0];
// Pointer to PINMUX19
pinmux19 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_19);
pin_MUX.pin19 = *pinmux19;
// Pointer to PINCFG19
pincfg19 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_19);
pin_CFG.pin19 = *pincfg19;
// Pointer to CNF21
pin21 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_21);
pin_CNF.pin21 = pin21->CNF[0];
pin_DEB.pin21 = pin21->DEB[0];
pin_IN.pin21 = pin21->IN[0];
pin_OUT.pin21 = pin21->OUT[0];
pin_OUT_VLE.pin21 = pin21->OUT_VLE[0];
// Pointer to PINMUX21
pinmux21 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_21);
pin_MUX.pin21 = *pinmux21;
// Pointer to PINCFG21
pincfg21 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_21);
pin_CFG.pin21 = *pincfg21;
// Pointer to CNF22
pin22 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_22);
pin_CNF.pin22 = pin22->CNF[0];
pin_DEB.pin22 = pin22->DEB[0];
pin_IN.pin22 = pin22->IN[0];
pin_OUT.pin22 = pin22->OUT[0];
pin_OUT_VLE.pin22 = pin22->OUT_VLE[0];
// Pointer to PINMUX22
pinmux22 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_22);
pin_MUX.pin22 = *pinmux22;
// Pointer to PINCFG22
pincfg22 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_22);
pin_CFG.pin22 = *pincfg22;
// Pointer to CNF23
pin23 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_23);
pin_CNF.pin23 = pin23->CNF[0];
pin_DEB.pin23 = pin23->DEB[0];
pin_IN.pin23 = pin23->IN[0];
pin_OUT.pin23 = pin23->OUT[0];
pin_OUT_VLE.pin23 = pin23->OUT_VLE[0];
// Pointer to PINMUX23
pinmux23 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_23);
pin_MUX.pin23 = *pinmux23;
// Pointer to PINCFG23
pincfg23 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_23);
pin_CFG.pin23 = *pincfg23;
// Pointer to CNF24
pin24 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_24);
pin_CNF.pin24 = pin24->CNF[0];
pin_DEB.pin24 = pin24->DEB[0];
pin_IN.pin24 = pin24->IN[0];
pin_OUT.pin24 = pin24->OUT[0];
pin_OUT_VLE.pin24 = pin24->OUT_VLE[0];
// Pointer to PINMUX24
pinmux24 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_24);
pin_MUX.pin24 = *pinmux24;
// Pointer to PINCFG24
pincfg24 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_24);
pin_CFG.pin24 = *pincfg24;
// Pointer to CNF26
pin26 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_26);
pin_CNF.pin26 = pin26->CNF[0];
pin_DEB.pin26 = pin26->DEB[0];
pin_IN.pin26 = pin26->IN[0];
pin_OUT.pin26 = pin26->OUT[0];
pin_OUT_VLE.pin26 = pin26->OUT_VLE[0];
// Pointer to PINMUX26
pinmux26 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_26);
pin_MUX.pin26 = *pinmux26;
// Pointer to PINCFG26
pincfg26 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_26);
pin_CFG.pin26 = *pincfg26;
// Pointer to CNF27
pin27 = (GPIO_CNFO volatile *)((char *)baseCNF_AON + CNFO_27);
pin_CNF.pin27 = pin27->CNF[0];
pin_DEB.pin27 = pin27->DEB[0];
pin_IN.pin27 = pin27->IN[0];
pin_OUT.pin27 = pin27->OUT[0];
pin_OUT_VLE.pin27 = pin27->OUT_VLE[0];
// Pointer to PINMUX27
pinmux27 = (uint32_t volatile *)((char *)basePINMUX_AON + PINMUXO_27);
pin_MUX.pin27 = *pinmux27;
// Pointer to PINCFG27
pincfg27 = (uint32_t volatile *)((char *)basePINMUX_AON + CFGO_27);
pin_CFG.pin27 = *pincfg27;
// Pointer to CNF28
pin28 = (GPIO_CNFO volatile *)((char *)baseCNF_AON + CNFO_28);
pin_CNF.pin28 = pin28->CNF[0];
pin_DEB.pin28 = pin28->DEB[0];
pin_IN.pin28 = pin28->IN[0];
pin_OUT.pin28 = pin28->OUT[0];
pin_OUT_VLE.pin28 = pin28->OUT_VLE[0];
// Pointer to PINMUX28
pinmux28 = (uint32_t volatile *)((char *)basePINMUX_AON + PINMUXO_28);
pin_MUX.pin28 = *pinmux28;
// Pointer to PINCFG28
pincfg28 = (uint32_t volatile *)((char *)basePINMUX_AON + CFGO_28);
pin_CFG.pin28 = *pincfg28;
// Pointer to CNF29
pin29 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_29);
pin_CNF.pin29 = pin29->CNF[0];
pin_DEB.pin29 = pin29->DEB[0];
pin_IN.pin29 = pin29->IN[0];
pin_OUT.pin29 = pin29->OUT[0];
pin_OUT_VLE.pin29 = pin29->OUT_VLE[0];
// Pointer to PINMUX29
pinmux29 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_29);
pin_MUX.pin29 = *pinmux29;
// Pointer to PINCFG29
pincfg29 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_29);
pin_CFG.pin29 = *pincfg29;
// Pointer to CNF31
pin31 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_31);
pin_CNF.pin31 = pin31->CNF[0];
pin_DEB.pin31 = pin31->DEB[0];
pin_IN.pin31 = pin31->IN[0];
pin_OUT.pin31 = pin31->OUT[0];
pin_OUT_VLE.pin31 = pin31->OUT_VLE[0];
// Pointer to PINMUX31
pinmux31 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_31);
pin_MUX.pin31 = *pinmux31;
// Pointer to PINCFG31
pincfg31 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_31);
pin_CFG.pin31 = *pincfg31;
// Pointer to CNF32
pin32 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_32);
pin_CNF.pin32 = pin32->CNF[0];
pin_DEB.pin32 = pin32->DEB[0];
pin_IN.pin32 = pin32->IN[0];
pin_OUT.pin32 = pin32->OUT[0];
pin_OUT_VLE.pin32 = pin32->OUT_VLE[0];
// Pointer to PINMUX32
pinmux32 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_32);
pin_MUX.pin32 = *pinmux32;
// Pointer to PINCFG32
pincfg32 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_32);
pin_CFG.pin32 = *pincfg32;
// Pointer to CNF33
pin33 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_33);
pin_CNF.pin33 = pin33->CNF[0];
pin_DEB.pin33 = pin33->DEB[0];
pin_IN.pin33 = pin33->IN[0];
pin_OUT.pin33 = pin33->OUT[0];
pin_OUT_VLE.pin33 = pin33->OUT_VLE[0];
// Pointer to PINMUX33
pinmux33 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_33);
pin_MUX.pin33 = *pinmux33;
// Pointer to PINCFG33
pincfg33 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_33);
pin_CFG.pin33 = *pincfg33;
// Pointer to CNF35
pin35 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_35);
pin_CNF.pin35 = pin35->CNF[0];
pin_DEB.pin35 = pin35->DEB[0];
pin_IN.pin35 = pin35->IN[0];
pin_OUT.pin35 = pin35->OUT[0];
pin_OUT_VLE.pin35 = pin35->OUT_VLE[0];
// Pointer to PINMUX35
pinmux35 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_35);
pin_MUX.pin35 = *pinmux35;
// Pointer to PINCFG35
pincfg35 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_35);
pin_CFG.pin35 = *pincfg35;
// Pointer to CNF36
pin36 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_36);
pin_CNF.pin36 = pin36->CNF[0];
pin_DEB.pin36 = pin36->DEB[0];
pin_IN.pin36 = pin36->IN[0];
pin_OUT.pin36 = pin36->OUT[0];
pin_OUT_VLE.pin36 = pin36->OUT_VLE[0];
// Pointer to PINMUX36
pinmux36 = (uint32_t volatile *)((char *)basePINMUX_G3 + PINMUXO_36);
pin_MUX.pin36 = *pinmux36;
// Pointer to PINCFG36
pincfg36 = (uint32_t volatile *)((char *)basePINMUX_G3 + CFGO_36);
pin_CFG.pin36 = *pincfg36;
// Pointer to CNF37
pin37 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_37);
pin_CNF.pin37 = pin37->CNF[0];
pin_DEB.pin37 = pin37->DEB[0];
pin_IN.pin37 = pin37->IN[0];
pin_OUT.pin37 = pin37->OUT[0];
pin_OUT_VLE.pin37 = pin37->OUT_VLE[0];
// Pointer to PINMUX37
pinmux37 = (uint32_t volatile *)((char *)basePINMUX_G2 + PINMUXO_37);
pin_MUX.pin37 = *pinmux37;
// Pointer to PINCFG37
pincfg37 = (uint32_t volatile *)((char *)basePINMUX_G2 + CFGO_37);
pin_CFG.pin37 = *pincfg37;
// Pointer to CNF38
pin38 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_38);
pin_CNF.pin38 = pin38->CNF[0];
pin_DEB.pin38 = pin38->DEB[0];
pin_IN.pin38 = pin38->IN[0];
pin_OUT.pin38 = pin38->OUT[0];
pin_OUT_VLE.pin38 = pin38->OUT_VLE[0];
// Pointer to PINMUX38
pinmux38 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_38);
pin_MUX.pin38 = *pinmux38;
// Pointer to PINCFG38
pincfg38 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_38);
pin_CFG.pin38 = *pincfg38;
// Pointer to CNF40
pin40 = (GPIO_CNFO volatile *)((char *)baseCNF_NAON + CNFO_40);
pin_CNF.pin40 = pin40->CNF[0];
pin_DEB.pin40 = pin40->DEB[0];
pin_IN.pin40 = pin40->IN[0];
pin_OUT.pin40 = pin40->OUT[0];
pin_OUT_VLE.pin40 = pin40->OUT_VLE[0];
// Pointer to PINMUX40
pinmux40 = (uint32_t volatile *)((char *)basePINMUX_G4 + PINMUXO_40);
pin_MUX.pin40 = *pinmux40;
// Pointer to PINCFG40
pincfg40 = (uint32_t volatile *)((char *)basePINMUX_G4 + CFGO_40);
pin_CFG.pin40 = *pincfg40;
// Pointer to PWM1
PWM1 = (uint32_t volatile *)((char *)basePWM1);
PWM1_Init = *PWM1;
// Pointer to PWM5
PWM5 = (uint32_t volatile *)((char *)basePWM5);
PWM5_Init = *PWM5;
// Pointer to PWM7
PWM7 = (uint32_t volatile *)((char *)basePWM7);
PWM7_Init = *PWM7;
// Initialize i2c
i2cInfo[1].state = I2C_CLOSED;
i2cInfo[7].state = I2C_CLOSED;
// Initialize spi
SpiInfo[0].state = SPI_CLOSED;
SpiInfo[2].state = SPI_CLOSED;
// Global interrupt variable
global_int = 1;
// Allocating memory for the struct
for (int j = 0; j < 41; j++) {
ISRFunc_CFG[j] = calloc (1, sizeof(ISRFunc));
}
return status;
}
void gpioTerminate(void) {
// Stopping threads
global_int = 0;
// Cancelling threads to avoid blocking on read()
for(int i = 0;i < thread_n; i++) {
pthread_cancel(callThd[i]);
//printf("Thread number: %d cancelled\n",i);
}
//Joining threads
for(int j = 0;j < thread_n; j++) {
pthread_join(callThd[j], &status_thread);
//printf("Thread number: %d joined\n",j);
}
// Free allocated memory
for (int k = 0; k < 41; k++) {
free(ISRFunc_CFG[k]);
}
int pagesize = sysconf(_SC_PAGESIZE);
// Restoring registers to their previous state
if ((pin_tracker >> 28) & 1) {
*PWM1 = PWM1_Init;
struct jetclk clock;
memset(&clock, 0, sizeof(clock));
int dev = open("/dev/jetclocks", O_WRONLY);
if(dev < 0) {
printf("Opening /dev/jetclocks not possible\n");
}
clock.clk_set_rate = clk_rate_PWM1;
strncpy(clock.clk, "pwm1", sizeof(clock.clk));
ioctl(dev, CLK_SET_RATE, &clock);
close(dev);
}
if ((pin_tracker >> 29) & 1) {
*PWM5 = PWM5_Init;
struct jetclk clock;
memset(&clock, 0, sizeof(clock));
int dev = open("/dev/jetclocks", O_WRONLY);
if(dev < 0) {
printf("Opening /dev/jetclocks not possible\n");
}
clock.clk_set_rate = clk_rate_PWM5;
strncpy(clock.clk, "pwm5", sizeof(clock.clk));
ioctl(dev, CLK_SET_RATE, &clock);
close(dev);
}
if ((pin_tracker >> 30) & 1) {
*PWM7 = PWM7_Init;
struct jetclk clock;
memset(&clock, 0, sizeof(clock));
int dev = open("/dev/jetclocks", O_WRONLY);
if(dev < 0) {
printf("Opening /dev/jetclocks not possible\n");
}
clock.clk_set_rate = clk_rate_PWM7;
strncpy(clock.clk, "pwm7", sizeof(clock.clk));
ioctl(dev, CLK_SET_RATE, &clock);
close(dev);
}
if (pin_tracker & 1) {
pin3->CNF[0] = pin_CNF.pin3;
pin3->DEB[0] = pin_DEB.pin3;
pin3->IN[0] = pin_IN.pin3;
pin3->OUT[0] = pin_OUT.pin3;
pin3->OUT_VLE[0] = pin_OUT_VLE.pin3;
*pinmux3 = pin_MUX.pin3;
*pincfg3 = pin_CFG.pin3;
}
if ((pin_tracker >> 1) & 1) {
pin5->CNF[0] = pin_CNF.pin5;
pin5->DEB[0] = pin_DEB.pin5;
pin5->IN[0] = pin_IN.pin5;
pin5->OUT[0] = pin_OUT.pin5;
pin5->OUT_VLE[0] = pin_OUT_VLE.pin5;
*pinmux5 = pin_MUX.pin5;
*pincfg5 = pin_CFG.pin5;
}
if ((pin_tracker >> 2) & 1) {
pin7->CNF[0] = pin_CNF.pin7;
pin7->DEB[0] = pin_DEB.pin7;
pin7->IN[0] = pin_IN.pin7;
pin7->OUT[0] = pin_OUT.pin7;
pin7->OUT_VLE[0] = pin_OUT_VLE.pin7;
*pinmux7 = pin_MUX.pin7;
*pincfg7 = pin_CFG.pin7;
}
if ((pin_tracker >> 3) & 1) {
pin8->CNF[0] = pin_CNF.pin8;
pin8->DEB[0] = pin_DEB.pin8;
pin8->IN[0] = pin_IN.pin8;
pin8->OUT[0] = pin_OUT.pin8;
pin8->OUT_VLE[0] = pin_OUT_VLE.pin8;
*pinmux8 = pin_MUX.pin8;
*pincfg8 = pin_CFG.pin8;
}
if ((pin_tracker >> 4) & 1) {
pin10->CNF[0] = pin_CNF.pin10;
pin10->DEB[0] = pin_DEB.pin10;
pin10->IN[0] = pin_IN.pin10;
pin10->OUT[0] = pin_OUT.pin10;
pin10->OUT_VLE[0] = pin_OUT_VLE.pin10;
*pinmux10 = pin_MUX.pin10;
*pincfg10 = pin_CFG.pin10;
}
if ((pin_tracker >> 5) & 1) {
pin11->CNF[0] = pin_CNF.pin11;
pin11->DEB[0] = pin_DEB.pin11;
pin11->IN[0] = pin_IN.pin11;
pin11->OUT[0] = pin_OUT.pin11;
pin11->OUT_VLE[0] = pin_OUT_VLE.pin11;
*pinmux11 = pin_MUX.pin11;
*pincfg11 = pin_CFG.pin11;
}
if ((pin_tracker >> 6) & 1) {
pin12->CNF[0] = pin_CNF.pin12;
pin12->DEB[0] = pin_DEB.pin12;
pin12->IN[0] = pin_IN.pin12;
pin12->OUT[0] = pin_OUT.pin12;
pin12->OUT_VLE[0] = pin_OUT_VLE.pin12;
*pinmux12 = pin_MUX.pin12;
*pincfg12 = pin_CFG.pin12;
}
if (((pin_tracker >> 7) & 1) || ((pin_tracker >> 32) & 1)) {
pin13->CNF[0] = pin_CNF.pin13;
pin13->DEB[0] = pin_DEB.pin13;
pin13->IN[0] = pin_IN.pin13;
pin13->OUT[0] = pin_OUT.pin13;
pin13->OUT_VLE[0] = pin_OUT_VLE.pin13;
*pinmux13 = pin_MUX.pin13;
*pincfg13 = pin_CFG.pin13;
}
if (((pin_tracker >> 8) & 1) || ((pin_tracker >> 28) & 1)) {
pin15->CNF[0] = pin_CNF.pin15;
pin15->DEB[0] = pin_DEB.pin15;
pin15->IN[0] = pin_IN.pin15;
pin15->OUT[0] = pin_OUT.pin15;
pin15->OUT_VLE[0] = pin_OUT_VLE.pin15;
*pinmux15 = pin_MUX.pin15;
*pincfg15 = pin_CFG.pin15;
}
if ((pin_tracker >> 9) & 1) {
pin16->CNF[0] = pin_CNF.pin16;
pin16->DEB[0] = pin_DEB.pin16;
pin16->IN[0] = pin_IN.pin16;
pin16->OUT[0] = pin_OUT.pin16;
pin16->OUT_VLE[0] = pin_OUT_VLE.pin16;
*pinmux16 = pin_MUX.pin16;
*pincfg16 = pin_CFG.pin16;
}
if (((pin_tracker >> 10) & 1) || ((pin_tracker >> 32) & 1)) {
pin18->CNF[0] = pin_CNF.pin18;
pin18->DEB[0] = pin_DEB.pin18;
pin18->IN[0] = pin_IN.pin18;
pin18->OUT[0] = pin_OUT.pin18;
pin18->OUT_VLE[0] = pin_OUT_VLE.pin18;
*pinmux18 = pin_MUX.pin18;
*pincfg18 = pin_CFG.pin18;
}
if (((pin_tracker >> 11) & 1) || ((pin_tracker >> 31) & 1)) {
pin19->CNF[0] = pin_CNF.pin19;
pin19->DEB[0] = pin_DEB.pin19;
pin19->IN[0] = pin_IN.pin19;
pin19->OUT[0] = pin_OUT.pin19;
pin19->OUT_VLE[0] = pin_OUT_VLE.pin19;
*pinmux19 = pin_MUX.pin19;
*pincfg19 = pin_CFG.pin19;
}
if (((pin_tracker >> 12) & 1) || ((pin_tracker >> 31) & 1)) {
pin21->CNF[0] = pin_CNF.pin21;
pin21->DEB[0] = pin_DEB.pin21;
pin21->IN[0] = pin_IN.pin21;
pin21->OUT[0] = pin_OUT.pin21;
pin21->OUT_VLE[0] = pin_OUT_VLE.pin21;
*pinmux21 = pin_MUX.pin21;
*pincfg21 = pin_CFG.pin21;
}
if (((pin_tracker >> 13) & 1) || ((pin_tracker >> 32) & 1)) {
pin22->CNF[0] = pin_CNF.pin22;
pin22->DEB[0] = pin_DEB.pin22;
pin22->IN[0] = pin_IN.pin22;
pin22->OUT[0] = pin_OUT.pin22;
pin22->OUT_VLE[0] = pin_OUT_VLE.pin22;
*pinmux22 = pin_MUX.pin22;
*pincfg22 = pin_CFG.pin22;
}
if (((pin_tracker >> 14) & 1) || ((pin_tracker >> 31) & 1)) {
pin23->CNF[0] = pin_CNF.pin23;
pin23->DEB[0] = pin_DEB.pin23;
pin23->IN[0] = pin_IN.pin23;
pin23->OUT[0] = pin_OUT.pin23;
pin23->OUT_VLE[0] = pin_OUT_VLE.pin23;
*pinmux23 = pin_MUX.pin23;
*pincfg23 = pin_CFG.pin23;
}
if (((pin_tracker >> 15) & 1) || ((pin_tracker >> 31) & 1)) {
pin24->CNF[0] = pin_CNF.pin24;
pin24->DEB[0] = pin_DEB.pin24;
pin24->IN[0] = pin_IN.pin24;
pin24->OUT[0] = pin_OUT.pin24;
pin24->OUT_VLE[0] = pin_OUT_VLE.pin24;
*pinmux24 = pin_MUX.pin24;
*pincfg24 = pin_CFG.pin24;
}
if ((pin_tracker >> 16) & 1) {
pin26->CNF[0] = pin_CNF.pin26;
pin26->DEB[0] = pin_DEB.pin26;
pin26->IN[0] = pin_IN.pin26;
pin26->OUT[0] = pin_OUT.pin26;
pin26->OUT_VLE[0] = pin_OUT_VLE.pin26;
*pinmux26 = pin_MUX.pin26;
*pincfg26 = pin_CFG.pin26;
}
if ((pin_tracker >> 17) & 1) {
pin27->CNF[0] = pin_CNF.pin27;
pin27->DEB[0] = pin_DEB.pin27;
pin27->IN[0] = pin_IN.pin27;
pin27->OUT[0] = pin_OUT.pin27;
pin27->OUT_VLE[0] = pin_OUT_VLE.pin27;
*pinmux27 = pin_MUX.pin27;
*pincfg27 = pin_CFG.pin27;
}