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dyladdylad
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cpu/sam4s: introduce initial support
Signed-off-by: dylad <[email protected]>
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‎cpu/sam4s/Kconfig‎

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# Copyright (c) 2025 Mesotic SAS
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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config CPU_FAM_SAM4S
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bool
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select CPU_CORE_CORTEX_M4
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## CPU Models
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config CPU_MODEL_SAM4SD32C
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bool
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select CPU_FAM_SAM4S
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## Common CPU symbols
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config CPU_FAM
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default "sam4s" if CPU_FAM_SAM4S
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config CPU_MODEL
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default "sam4sd32c" if CPU_MODEL_SAM4SD32C
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config CPU
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default "sam4s" if CPU_FAM_SAM4s
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source "$(RIOTCPU)/cortexm_common/Kconfig"

‎cpu/sam4s/Makefile‎

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# define the module that is build
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MODULE = cpu
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# add a list of subdirectories, that should also be build
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DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/sam_common
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# (file triggers compiler bug. see #5775)
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SRC_NOLTO += vectors.c
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include $(RIOTBASE)/Makefile.base

‎cpu/sam4s/Makefile.dep‎

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include $(RIOTCPU)/sam_common/Makefile.dep

‎cpu/sam4s/Makefile.features‎

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CPU_CORE = cortex-m4
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CPU_FAM = sam4s
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FEATURES_PROVIDED += cortexm_mpu
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include $(RIOTCPU)/cortexm_common/Makefile.features

‎cpu/sam4s/Makefile.include‎

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ROM_START_ADDR ?= 0x400000
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RAM_START_ADDR ?= 0x20000000
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ROM_LEN ?= 0x200000
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RAM_LEN ?= 0x28000
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include $(RIOTCPU)/sam_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk

‎cpu/sam4s/cpu.c‎

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/*
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* Copyright (C) 2025 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam4s
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Dylan Laduranty <[email protected]>
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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#include "kernel_init.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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#define XTAL_STARTUP (8U)
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#define PLL_CNT (64U)
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#if ((CLOCK_PLL_MUL < 7) || (CLOCK_PLL_MUL > 62))
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#error "CLOCK_PLL_MUL has an incorrect value"
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#endif
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* SAM4s MCUs requires WPKEY for enabling peripheral */
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PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
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/* disable the watchdog timer */
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WDT->WDT_MR |= WDT_MR_WDDIS;
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/* initialize the Cortex-M core */
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cortexm_init();
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/* setup the flash wait states */
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EFC0->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(CLOCK_FWS);
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/* enable the Cortex-M Cache Controller */
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CMCC->CMCC_CTRL |= CMCC_CTRL_CEN;
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/* unlock write protect register for PMC module */
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PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
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/* activate the external crystal */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCXTST(XTAL_STARTUP)
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| CKGR_MOR_MOSCXTEN
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| CKGR_MOR_MOSCRCEN;
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/* wait for crystal to be stable */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {}
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/* select crystal to clock the main clock */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCXTST(XTAL_STARTUP)
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| CKGR_MOR_MOSCXTEN
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCSEL;
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/* wait for main oscillator selection to be complete */
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {}
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/* setup PLLA */
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
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| CKGR_PLLAR_PLLACOUNT(PLL_CNT)
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| CKGR_PLLAR_MULA(CLOCK_PLL_MUL)
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| CKGR_PLLAR_DIVA(CLOCK_PLL_DIV);
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/* wait for PLL to lock */
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while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {}
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/* before switching to PLLA, we need to switch to main clock */
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PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
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/* use PLLA as main clock source */
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PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK;
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/* wait for master clock to be ready */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
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/* setup the SCLK: switch to external oscillator if applicable */
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#if CLOCK_SCLK_XTAL
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/* enable external oscillator */
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SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
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while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL_CRYST)) {}
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#endif
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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/* trigger static peripheral initialization */
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periph_init();
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}

‎cpu/sam4s/doc.txt‎

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/**
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* @defgroup cpu_sam4s Atmel SAM4S
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* @ingroup cpu
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* @brief Atmel SAM4S Cortex-M4 MCU specific implementation.
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*
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* This module contains Atmel SAM4S specific code and definition.
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*
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* @see cpu_sam_common
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*/

‎cpu/sam4s/include/periph_cpu.h‎

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/*
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* Copyright (C) 2025 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam4s
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Dylan Laduranty <[email protected]>
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*
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#include "macros/units.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */

‎cpu/sam4s/periph/Makefile‎

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include $(RIOTMAKE)/periph.mk

‎cpu/sam4s/vectors.c‎

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/*
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* Copyright (C) 2025 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam4s
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* @{
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*
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* @file
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* @brief Startup code and interrupt vector definition
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*
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* @author Dylan Laduranty <[email protected]>
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*
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* @}
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*/
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#include <stdint.h>
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* Cortex-M common interrupt vectors */
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WEAK_DEFAULT void isr_svc(void);
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WEAK_DEFAULT void isr_pendsv(void);
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WEAK_DEFAULT void isr_systick(void);
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/* SAM4S specific interrupt vector */
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WEAK_DEFAULT void isr_supc(void);
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WEAK_DEFAULT void isr_rstc(void);
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WEAK_DEFAULT void isr_rtc(void);
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WEAK_DEFAULT void isr_rtt(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_pmc(void);
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WEAK_DEFAULT void isr_eefc0(void);
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WEAK_DEFAULT void isr_eefc1(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_smc(void);
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WEAK_DEFAULT void isr_pioa(void);
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WEAK_DEFAULT void isr_piob(void);
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WEAK_DEFAULT void isr_pioc(void);
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WEAK_DEFAULT void isr_usart0(void);
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WEAK_DEFAULT void isr_usart1(void);
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WEAK_DEFAULT void isr_hsmci(void);
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WEAK_DEFAULT void isr_twi0(void);
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WEAK_DEFAULT void isr_twi1(void);
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WEAK_DEFAULT void isr_spi(void);
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WEAK_DEFAULT void isr_ssc(void);
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WEAK_DEFAULT void isr_tc0(void);
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WEAK_DEFAULT void isr_tc1(void);
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WEAK_DEFAULT void isr_tc2(void);
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WEAK_DEFAULT void isr_tc3(void);
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WEAK_DEFAULT void isr_tc4(void);
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WEAK_DEFAULT void isr_tc5(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_dacc(void);
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WEAK_DEFAULT void isr_pwm(void);
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WEAK_DEFAULT void isr_crccu(void);
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WEAK_DEFAULT void isr_acc(void);
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WEAK_DEFAULT void isr_udp(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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isr_supc, /* 0 Supply Controller */
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isr_rstc, /* 1 Reset Controller */
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isr_rtc, /* 2 Real Time Clock */
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isr_rtt, /* 3 Real Timer Timer */
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isr_wdt, /* 4 Watchdog Timer */
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isr_pmc, /* 5 Power Management Controller */
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isr_eefc0, /* 6 Enhanced Embedded Flash Controller 0 */
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isr_eefc1, /* 7 Enhanced Embedded Flash Controller 1 */
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isr_uart0, /* 8 Universal Asynchronous Receiver Transceiver 0 */
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isr_uart1, /* 9 Universal Asynchronous Receiver Transceiver 1 */
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isr_smc, /* 10 Static Memory Controller */
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isr_pioa, /* 11 GPIO port A */
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isr_piob, /* 12 GPIO port B */
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isr_pioc, /* 13 GPIO port C */
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isr_usart0, /* 14 USART0 */
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isr_usart1, /* 15 USART1 */
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(0UL), /* Reserved */
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(0UL), /* Reserved */
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isr_hsmci, /* 18 Multimedia Card Interface */
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isr_twi0, /* 19 Two-wire Interface 0 */
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isr_twi1, /* 20 Two-wire Interface 1 */
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isr_spi, /* 21 Serial Peripheral Interface */
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isr_ssc, /* 22 Synchronous Serial Controller */
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isr_tc0, /* 23 Timer Counter 0 */
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isr_tc1, /* 24 Timer Counter 1 */
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isr_tc2, /* 25 Timer Counter 2 */
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isr_tc3, /* 26 Timer Counter 3 */
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isr_tc4, /* 27 Timer Counter 4 */
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isr_tc5, /* 28 Timer Counter 5 */
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isr_adc, /* 29 Analog/Digital Converter */
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isr_dacc, /* 30 Digital/Analog Converter Controller */
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isr_pwm, /* 31 Pulse Width Modulation */
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isr_crccu, /* 32 CRC Calculation Unit */
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isr_acc, /* 33 Analog Comparator Controller */
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isr_udp, /* 34 USB Device Port */
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};

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