default.2bc.cfg

# ECE 4100/6100
#
# sim-outorder configuration
#
# Prof. Hsien-Hsin S. Lee
#
# School of Electrical and Computer Engineering
# Georgia Tech, Atlanta, GA 30332
#

# 2bit counter 
# branch predictor type {nottaken|taken|perfect|bimod|2lev}
# -bpred                       bimod 
-bpred                       perfect

# bimod predictor config (<table size>)
-bpred:bimod          16384 

# BTB size (4096 sets, 4 way)
-bpred:btb            4096 4 

# return address stack 
-bpred:ras  8

# extra branch mis-prediction latency
-fetch:mplat                      3
# -fetch:mplat                      9



# l1 inst cache config, 32KB, 64-byte line, 8 way
-cache:il1             il1:64:64:8:l

# l1 instruction cache hit latency (in cycles)
-cache:il1lat                     1 

# l1 data cache config, 32KB, 64-byte line, 8-way
-cache:dl1             dl1:64:64:8:l

# l1 data cache hit latency (in cycles)
-cache:dl1lat                     1 

# l2 data cache config, 1MB, 64-byte line, 8-way
-cache:dl2             ul2:2048:64:8:l

# l2 data cache hit latency (in cycles)
-cache:dl2lat                    14

# l2 instruction cache config, i.e., {<config>|dl2|none}
-cache:il2                      dl2

# memory access latency (<first_chunk> <inter_chunk>, 3GHz core & 1GHz FSB)
-mem:lat               150 3

# memory access bus width (in bytes)
-mem:width              8

# instruction TLB config (4KB page)
-tlb:itlb               itlb:32:4096:4:l

# data TLB config (4KB page)
-tlb:dtlb               dtlb:64:4096:4:l

# inst/data TLB miss latency (in cycles)
-tlb:lat                  30




# instruction fetch queue size (in insts)
-fetch:ifqsize                    256


# instruction decode B/W (insts/cycle)
-decode:width                     8 

# instruction issue B/W (insts/cycle)
-issue:width                      8 

# commit width
-commit:width			  8

# register update unit (RUU) size (this is the instruction window size)
-ruu:size                        256

# load/store queue (LSQ) size
-lsq:size                        64

# run pipeline with in-order issue
-issue:inorder                    false

# total number of integer ALU's available
-res:ialu                         8

# total number of integer multiplier/dividers available
-res:imult                        4 

# total number of memory system ports available (to CPU)
#-res:memport                     8

# total number of floating point ALU's available
-res:fpalu                        4 

# total number of floating point multiplier/dividers available
-res:fpmult                       4