From 5e62d380c54524d8916573aa3397270f457e4901 Mon Sep 17 00:00:00 2001 From: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com> Date: Thu, 13 Jul 2023 17:46:09 +0200 Subject: [PATCH 01/68] Add an exclude list for known failing Hifive1 tests (#485) * Add an exclude list for known failing Hifive1 tests This commit adds a list of known failing tests based on: https://github.com/riscv/riscv-openocd/issues/869#issue-1769176709 * Fix name of the HiFive1 flash target Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com> --------- Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com> --- debug/hifive1_excludes.yaml | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 debug/hifive1_excludes.yaml diff --git a/debug/hifive1_excludes.yaml b/debug/hifive1_excludes.yaml new file mode 100644 index 000000000..f9391ee80 --- /dev/null +++ b/debug/hifive1_excludes.yaml @@ -0,0 +1,28 @@ +# Below are known failing tests on riscv-openocd on HiFive1 board, rev. A01. +# This board uses the legacy debug spec v 0.11. + +# Tested on Jun-26-2023. +# riscv-openocd commit: a45589d60aa6864475fddcded885c8ff47d50be1 +# riscv-tests commit: 7b52ba3b7167acb4d8b38f4d4633112b4699cb26 + +all: + - EtriggerTest + - IcountTest + - InstantHaltTest + - ItriggerTest + - MemorySampleMixed + - MemorySampleSingle + - MemTestReadInvalid + - RepeatReadTest + - Semihosting + - SemihostingFileio + +HiFive1Flash: + - DebugBreakpoint + - DebugExit + - DebugFunctionCall + - Hwbp1 + - Hwbp2 + - Registers + - TooManyHwbp + - UserInterrupt From feddb19b3f780ef8e6a037bcc4ef1d63111d86d4 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 13 Jul 2023 10:22:43 -0700 Subject: [PATCH 02/68] debug: flushregs -> maintenance flush register-cache flushregs is deprecated. --- debug/gdbserver.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 46d65dfea..ea3bb0c5e 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -433,7 +433,7 @@ class InstantHaltTest(GdbTest): def test(self): """Assert that reset is really resetting what it should.""" self.gdb.command("monitor reset halt") - self.gdb.command("flushregs") + self.gdb.command("maintenance flush register-cache") threads = self.gdb.threads() pcs = [] for t in threads: @@ -451,7 +451,7 @@ def test(self): """Change the PC right as we come out of reset.""" # 0x13 is nop self.gdb.command("monitor reset halt") - self.gdb.command("flushregs") + self.gdb.command("maintenance flush register-cache") self.gdb.command(f"p *((int*) 0x{self.hart.ram:x})=0x13") self.gdb.command(f"p *((int*) 0x{self.hart.ram + 4:x})=0x13") self.gdb.command(f"p *((int*) 0x{self.hart.ram + 8:x})=0x13") @@ -1743,10 +1743,10 @@ def test(self): value = self.gdb.p(regname) assertNotEqual(value, 0) self.gdb.p(f"{regname}=0") - self.gdb.command("flushregs") + self.gdb.command("maintenance flush register-cache") assertEqual(self.gdb.p(regname), 0) self.gdb.p(f"{regname}=0x{value:x}") - self.gdb.command("flushregs") + self.gdb.command("maintenance flush register-cache") assertEqual(self.gdb.p(regname), value) assertEqual(self.gdb.p("$a0"), 0) From e989825542c9e1bf84865558f2eb01302f159faa Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Fri, 14 Jul 2023 10:09:52 +0300 Subject: [PATCH 03/68] Remove old warning check in RepeatReadTest --- debug/gdbserver.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index ea3bb0c5e..ff0f7ab8b 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -925,10 +925,6 @@ def is_valid_warning(line): return True for line in itertools.dropwhile(is_valid_warning, output.splitlines()): - # This `if` is to be removed after - # https://github.com/riscv/riscv-openocd/pull/871 is merged. - if line.startswith("Batch memory"): - continue for v in line.split(): values.append(int(v, 16)) From 1754ac49dc90ee99a8452aeca5fe218b54e03f18 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Jun 2023 17:07:09 -0700 Subject: [PATCH 04/68] Move `import random` Just so it's easier to quickly comment out code and hard-code the target to use without pylint complaining. This really should be a command line option. --- debug/testlib.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index 2155e0564..8962ae32b 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1,7 +1,6 @@ import collections import os import os.path -import random import re import shlex import subprocess @@ -1136,7 +1135,9 @@ def __init__(self, target, hart=None): if hart: self.hart = hart else: + import random # pylint: disable=import-outside-toplevel self.hart = random.choice(target.harts) + #self.hart = target.harts[-1] self.server = None self.target_process = None self.binary = None From f6c33d7d1986da701a2d97c179d1b22b462f7e8d Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Jun 2023 17:05:39 -0700 Subject: [PATCH 05/68] Move "monitor targets" calls into a central place. --- debug/gdbserver.py | 3 --- debug/testlib.py | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 46d65dfea..e5d370740 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1989,7 +1989,6 @@ def setup(self): self.gdb.b("handle_trap") def test(self): - self.gdb.command(f"monitor targets {self.hart.id}") # Set trigger on Load access fault self.gdb.command("monitor riscv etrigger set m 0x20") # Set fox to a null pointer so we'll get a load access exception later. @@ -2009,7 +2008,6 @@ def setup(self): DebugTest.setup(self) self.gdb.b("main") self.gdb.c() - self.gdb.command(f"monitor targets {self.hart.id}") def test(self): # Execute 2 instructions. @@ -2039,7 +2037,6 @@ def setup(self): self.gdb.load() def test(self): - self.gdb.command(f"monitor targets {self.hart.id}") output = self.gdb.command("monitor riscv itrigger set 0x80") assertIn("Doesn't make sense", output) output = self.gdb.command("monitor riscv itrigger set m 0") diff --git a/debug/testlib.py b/debug/testlib.py index 8962ae32b..688829df0 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1309,6 +1309,7 @@ def parkOtherHarts(self, symbol=None): self.gdb.p(f"$pc={symbol}") self.gdb.select_hart(self.hart) + self.gdb.command(f"monitor targets {self.hart.id}") def disable_pmp(self): # Disable physical memory protection by allowing U mode access to all From 65e27a9d3851c35687b1d02793b452f598d1f7ae Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Jun 2023 17:03:34 -0700 Subject: [PATCH 06/68] parkOtherHarts() already defaults to cease --- debug/gdbserver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index e5d370740..04180c3b0 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1818,7 +1818,7 @@ def early_applicable(self): def setup(self): ProgramTest.setup(self) - self.parkOtherHarts("precease") + self.parkOtherHarts() def test(self): # Run all the way to the infinite loop in exit From a29522f3e4baec1a50beb01ec70d69a94ac0083c Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Jun 2023 17:06:31 -0700 Subject: [PATCH 07/68] debug: Add support_unavailable_control property. --- debug/targets.py | 3 +++ debug/targets/RISC-V/spike32-2-hwthread.py | 1 + debug/targets/RISC-V/spike32-2.py | 1 + debug/targets/RISC-V/spike32.py | 1 + debug/targets/RISC-V/spike64-2-hwthread.py | 1 + debug/targets/RISC-V/spike64-2-rtos.py | 1 + debug/targets/RISC-V/spike64-2.py | 1 + debug/targets/RISC-V/spike64.py | 1 + 8 files changed, 10 insertions(+) diff --git a/debug/targets.py b/debug/targets.py index 19527497a..3f63e79b9 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -129,6 +129,9 @@ class Target: # in https://github.com/FreeRTOS/FreeRTOS. freertos_binary = None + # Supports controlling hart availability through DMCUSTOM. + support_unavailable_control = False + # Internal variables: directory = None temporary_files = [] diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index 3a2426910..b617be24b 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -10,6 +10,7 @@ class spike32_2(targets.Target): timeout_sec = 5 implements_custom_test = True support_memory_sampling = False # not supported without sba + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV32IMAFDV", support_hasel=True, diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 6a5a83932..1d0cc48f4 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -9,6 +9,7 @@ class spike32_2(targets.Target): openocd_config_path = "spike-2.cfg" timeout_sec = 30 implements_custom_test = True + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4, diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index 0d67ebd28..f0afd88ba 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -17,6 +17,7 @@ class spike32(targets.Target): implements_custom_test = True support_memory_sampling = False # Needs SBA freertos_binary = "bin/RTOSDemo32.axf" + support_unavailable_control = True def create(self): # 64-bit FPRs on 32-bit target diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py index 1ac184add..d1d2bf7dd 100644 --- a/debug/targets/RISC-V/spike64-2-hwthread.py +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -13,6 +13,7 @@ class spike64_2(targets.Target): implements_custom_test = True support_hasel = False support_memory_sampling = False # Needs SBA + support_unavailable_control = True def create(self): return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index 33c1ff242..f4de8b8e8 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -13,6 +13,7 @@ class spike64_2_rtos(targets.Target): test_semihosting = False support_manual_hwbp = False # not supported with `-rtos riscv` support_memory_sampling = False # not supported with `-rtos riscv` + support_unavailable_control = True def create(self): return testlib.Spike(self, abstract_rti=30, support_hasel=False, diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 48326ad7d..e4c7524fa 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -10,6 +10,7 @@ class spike64_2(targets.Target): timeout_sec = 5 implements_custom_test = True support_memory_sampling = False # Needs SBA + support_unavailable_control = True def create(self): return testlib.Spike(self) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 79176c202..8f5ba4f4b 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -17,6 +17,7 @@ class spike64(targets.Target): timeout_sec = 30 implements_custom_test = True freertos_binary = "bin/RTOSDemo64.axf" + support_unavailable_control = True def create(self): # 32-bit FPRs only From e1cb5be2709f461459b07221a15587e388fa90be Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Jun 2023 17:08:28 -0700 Subject: [PATCH 08/68] Interact with OpenOCD CLI over stdin/stdout. It's a bit messy to read the log file to get the output, but it seems to be flushed often so that this works. Also, added the `targets` method for retrieving the list of targets, and `wait_until_running` method to wait until all targets are in a running state. --- debug/testlib.py | 141 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 102 insertions(+), 39 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index 688829df0..5c09f0ac9 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -293,6 +293,7 @@ def __del__(self): pass class Openocd: + # pylint: disable=too-many-instance-attributes # pylint: disable-next=consider-using-with logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log') logname = logfile.name @@ -301,6 +302,7 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, freertos=False, debug_openocd=False): self.timeout = timeout self.debug_openocd = debug_openocd + self.command_count = 0 if server_cmd: cmd = shlex.split(server_cmd) @@ -313,15 +315,13 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, # line, since they are executed in order. cmd += [ # Tell OpenOCD to bind gdb to an unused, ephemeral port. - "--command", - "gdb_port 0", - # Disable tcl and telnet servers, since they are unused and because - # the port numbers will conflict if multiple OpenOCD processes are - # running on the same server. - "--command", - "tcl_port disabled", - "--command", - "telnet_port disabled", + "--command", "gdb_port 0", + # We don't use the TCL server. + "--command", "tcl_port disabled", + # Put the regular command prompt in stdin. Don't listen on a port + # because it will conflict if multiple OpenOCD instances are running + # at the same time. + "--command", "telnet_port pipe", ] if config: @@ -342,6 +342,9 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, # pylint: disable-next=consider-using-with raw_logfile = open(Openocd.logname, "wb") + # pylint: disable-next=consider-using-with + self.read_log_fd = open(Openocd.logname, "rb") + self.log_buf = b"" try: # pylint: disable-next=consider-using-with spike_dasm = subprocess.Popen("spike-dasm", stdin=subprocess.PIPE, @@ -363,12 +366,12 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, logfile.flush() self.gdb_ports = [] - self.process = self.start(cmd, logfile, extra_env) + self.start(cmd, logfile, extra_env) def start(self, cmd, logfile, extra_env): combined_env = {**os.environ, **extra_env} # pylint: disable-next=consider-using-with - process = subprocess.Popen(cmd, stdin=subprocess.PIPE, + self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, stdout=logfile, stderr=logfile, env=combined_env) try: @@ -376,38 +379,21 @@ def start(self, cmd, logfile, extra_env): # using OpenOCD to communicate with a simulator this may take a # long time, and gdb will time out when trying to connect if we # attempt too early. - start = time.time() - messaged = False - with open(Openocd.logname, "r", encoding='utf-8') as fd: - while True: - line = fd.readline() - if not line: - if not process.poll() is None: - raise TestLibError("OpenOCD exited early.") - time.sleep(0.1) - continue - - m = re.search( - r"Listening on port (\d+) for gdb connections", line) - if m: - self.gdb_ports.append(int(m.group(1))) - - if "telnet server disabled" in line: - break - - if not messaged and time.time() - start > 1: - messaged = True - print("Waiting for OpenOCD to start...") - if (time.time() - start) > self.timeout: - raise TestLibError("Timed out waiting for OpenOCD to " - "listen for gdb") + + while True: + m = self.expect( + rb"(Listening on port (\d+) for gdb connections|" + rb"tcl server disabled)", + message="Waiting for OpenOCD to start up...") + if b"gdb" in m.group(1): + self.gdb_ports.append(int(m.group(2))) + else: + break if self.debug_openocd: # pylint: disable=consider-using-with self.debugger = subprocess.Popen(["gnome-terminal", "-e", - f"gdb --pid={process.pid}"]) - return process - + f"gdb --pid={self.process.pid}"]) except Exception: print_log(Openocd.logname) raise @@ -433,6 +419,83 @@ def smp(self): return True return False + def command(self, cmd): + """Write the command to OpenOCD's stdin. Return the output of the + command, minus the prompt.""" + self.process.stdin.write(f"{cmd}\n".encode()) + self.process.stdin.flush() + m = self.expect(re.escape(f"{cmd}\n".encode())) + + # The prompt isn't flushed to the log, so send a unique command that + # lets us find where output of the last command ends. + magic = f"# {self.command_count}x".encode() + self.command_count += 1 + self.process.stdin.write(magic + b"\n") + self.process.stdin.flush() + m = self.expect(rb"(.*)^> " + re.escape(magic)) + return m.group(1) + + def expect(self, regex, message=None): + """Wait for the regex to match the log, and return the match object. If + message is given, print it while waiting. + We read the logfile to tell us what OpenOCD has done.""" + messaged = False + start = time.time() + + while True: + for line in self.read_log_fd.readlines(): + line = line.rstrip() + # Remove nulls, carriage returns, and newlines. + line = re.sub(rb"[\x00\r\n]+", b"", line) + # Remove debug messages. + debug_match = re.search(rb"Debug: \d+ \d+ .*", line) + if debug_match: + line = line[:debug_match.start()] + line[debug_match.end():] + self.log_buf += line + else: + self.log_buf += line + b"\n" + + m = re.search(regex, self.log_buf, re.MULTILINE | re.DOTALL) + if m: + self.log_buf = self.log_buf[m.end():] + return m + + if not self.process.poll() is None: + raise TestLibError("OpenOCD exited early.") + + if message and not messaged and time.time() - start > 1: + messaged = True + print(message) + + if (time.time() - start) > self.timeout: + raise TestLibError(f"Timed out waiting for {regex} in " + f"{Openocd.logname}") + + time.sleep(0.1) + + def targets(self): + """Run `targets` command.""" + result = self.command("targets").decode() + # TargetName Type Endian TapName State + # -- ------------------ ---------- ------ ------------------ -------- + # 0* riscv.cpu riscv little riscv.cpu halted + lines = result.splitlines() + headers = lines[0].split() + data = [] + for line in lines[2:]: + data.append(dict(zip(headers, line.split()[1:]))) + return data + + def wait_until_running(self, harts): + """Wait until the given harts are running.""" + start = time.time() + while True: + targets = self.targets() + if all(targets[hart.id]["State"] == "running" for hart in harts): + return + if time.time() - start > self.timeout: + raise TestLibError("Timed out waiting for targets to run.") + class OpenocdCli: def __init__(self, port=4444): self.child = pexpect.spawn( From ba831d02bdb4249ef744bd04da6c912680c7b66e Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 6 Jul 2023 14:41:02 -0700 Subject: [PATCH 09/68] debug: CeaseMultiTest -> UnavailableMultiTest Use the new spike mechanism to test OpenOCD behavior when a hart becomes unavailable while running. Create CommandException. --- debug/gdbserver.py | 19 +++++++++++++------ debug/testlib.py | 19 +++++++++++++++++-- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 04180c3b0..bf04f2ea4 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -19,7 +19,7 @@ from testlib import GdbTest, GdbSingleHartTest, TestFailed from testlib import TestNotApplicable, CompileError from testlib import UnknownThread -from testlib import CouldNotReadRegisters +from testlib import CouldNotReadRegisters, CommandException MSTATUS_UIE = 0x00000001 MSTATUS_SIE = 0x00000002 @@ -1807,14 +1807,16 @@ def test(self): output = self.gdb.c() assertIn("_exit", output) -class CeaseMultiTest(GdbTest): - """Test that we work correctly when a hart ceases to respond (e.g. because +class UnavailableMultiTest(GdbTest): + """Test that we work correctly when a hart becomes unavailable (e.g. because it's powered down).""" compile_args = ("programs/counting_loop.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE") def early_applicable(self): - return self.hart.support_cease and len(self.target.harts) > 1 + return (self.hart.support_cease or + self.target.support_unavailable_control) \ + and len(self.target.harts) > 1 def setup(self): ProgramTest.setup(self) @@ -1822,7 +1824,12 @@ def setup(self): def test(self): # Run all the way to the infinite loop in exit - self.gdb.c(wait=False) + self.gdb.c_all(wait=False) + # Other hart should have become unavailable. + if self.target.support_unavailable_control: + self.server.wait_until_running(self.target.harts) + self.server.command( + f"riscv dmi_write 0x1f 0x{(1< Date: Thu, 6 Jul 2023 14:41:39 -0700 Subject: [PATCH 10/68] debug: CeaseRunTest -> UnavailableRunTest Use new spike mechanism to test OpenOCD behavior when the current hart becomes unavailable while running. Create ThreadTerminated exception. --- debug/gdbserver.py | 21 ++++++++++++++++++--- debug/testlib.py | 5 +++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index bf04f2ea4..ad85e349c 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -20,6 +20,7 @@ from testlib import TestNotApplicable, CompileError from testlib import UnknownThread from testlib import CouldNotReadRegisters, CommandException +from testlib import ThreadTerminated MSTATUS_UIE = 0x00000001 MSTATUS_SIE = 0x00000002 @@ -1879,11 +1880,12 @@ def test(self): except CouldNotReadRegisters: pass -class CeaseRunTest(ProgramTest): +class UnavailableRunTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" def early_applicable(self): - return self.hart.support_cease + return self.hart.support_cease or \ + self.target.support_unavailable_control def test(self): self.gdb.b("main") @@ -1891,10 +1893,23 @@ def test(self): assertIn("Breakpoint", output) assertIn("main", output) - self.gdb.p("$pc=precease") + if self.target.support_unavailable_control: + self.gdb.p("$pc=loop_forever") + else: + self.gdb.p("$pc=cease") self.gdb.c(wait=False) + if self.target.support_unavailable_control: + self.server.wait_until_running([self.hart]) + self.server.command( + f"riscv dmi_write 0x1f 0x{(~(1< Date: Thu, 6 Jul 2023 14:41:56 -0700 Subject: [PATCH 11/68] debug: Create UnavailableCycleTest Use new spike mechanism to test OpenOCD behavior when a hart becomes unavailable, and then available again. --- debug/gdbserver.py | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index ad85e349c..f8997cc7a 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1917,6 +1917,33 @@ def test(self): except CouldNotReadRegisters: pass +class UnavailableCycleTest(ProgramTest): + """Test that harts can be debugged after becoming temporarily + unavailable.""" + def early_applicable(self): + return self.target.support_unavailable_control + + def test(self): + self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint", output) + assertIn("main", output) + + self.gdb.p("$pc=loop_forever") + self.gdb.c(wait=False) + self.server.wait_until_running([self.hart]) + self.server.command( + f"riscv dmi_write 0x1f 0x{(~(1< Date: Tue, 18 Jul 2023 10:39:29 -0700 Subject: [PATCH 12/68] debug: Disable unavailable tests. They have issues when run in a github workflow. --- debug/gdbserver.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 97e49d890..53eeffafe 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1815,9 +1815,10 @@ class UnavailableMultiTest(GdbTest): "-DDEFINE_FREE") def early_applicable(self): - return (self.hart.support_cease or - self.target.support_unavailable_control) \ - and len(self.target.harts) > 1 + return False # This test fails in github workflows + #return (self.hart.support_cease or + # self.target.support_unavailable_control) \ + # and len(self.target.harts) > 1 def setup(self): ProgramTest.setup(self) @@ -1884,8 +1885,9 @@ class UnavailableRunTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" def early_applicable(self): - return self.hart.support_cease or \ - self.target.support_unavailable_control + return False # This test fails in github workflows + #return self.hart.support_cease or \ + # self.target.support_unavailable_control def test(self): self.gdb.b("main") @@ -1921,7 +1923,8 @@ class UnavailableCycleTest(ProgramTest): """Test that harts can be debugged after becoming temporarily unavailable.""" def early_applicable(self): - return self.target.support_unavailable_control + return False # This test fails in github workflows + #return self.target.support_unavailable_control def test(self): self.gdb.b("main") From e1f88be374e98df1dcc075e17a3d515d7daad6c2 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 19 Jul 2023 13:09:18 -0700 Subject: [PATCH 13/68] debug: Only run pylint if debug files changed. --- .github/workflows/debug.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/debug.yml b/.github/workflows/debug.yml index 29ca5b2aa..7b6beb4ff 100644 --- a/.github/workflows/debug.yml +++ b/.github/workflows/debug.yml @@ -1,6 +1,9 @@ -on: pull_request +on: + pull_request: + paths: + - 'debug/**' -name: Check Code Style (checkpatch) +name: Check Debug Code Style (pylint) jobs: check: From 49ea5933fe54084b2bad4a76637559f087f578c4 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 19 Jul 2023 13:14:33 -0700 Subject: [PATCH 14/68] debug: Better comment the privilege tests. Just doing this to make a change in the debug files, which should now cause the pylint workflow to execute. --- debug/gdbserver.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 53eeffafe..3b9a661ca 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1562,6 +1562,7 @@ def test(self): # assertIn("0xbead", output) class PrivTest(GdbSingleHartTest): + """Base class for a few tests that change privilege levels.""" compile_args = ("programs/priv.S", ) def setup(self): # pylint: disable=attribute-defined-outside-init @@ -1588,8 +1589,8 @@ def setup(self): pass class PrivRw(PrivTest): + """Test reading/writing priv.""" def test(self): - """Test reading/writing priv.""" self.write_nop_program(4) for privilege in range(4): self.gdb.p(f"$priv={privilege}") @@ -1600,9 +1601,9 @@ def test(self): assertEqual(actual, privilege) class PrivChange(PrivTest): + """Test that the core's privilege level actually changes when the debugger + writes it.""" def test(self): - """Test that the core's privilege level actually changes.""" - if 0 not in self.supported: raise TestNotApplicable From 87dc207566d777dfc2bc4c2567879f7bdbe6bd60 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 20 Jul 2023 17:34:27 -0700 Subject: [PATCH 15/68] debug: Actually run tests in github workflow. This should avoid problems like we just had where bad tests can break the OpenOCD workflow. These tests only run if any debug files are changed, so should have no impact at all on non-debug tests in this repo. This file is copied and then slightly changed from riscv-openocd. New changes are that cacheable steps (building spike, OpenOCD) are stored to the cache even if running the tests fails. --- .github/workflows/spike-openocd-tests.yml | 172 ++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 .github/workflows/spike-openocd-tests.yml diff --git a/.github/workflows/spike-openocd-tests.yml b/.github/workflows/spike-openocd-tests.yml new file mode 100644 index 000000000..3f1d93bb4 --- /dev/null +++ b/.github/workflows/spike-openocd-tests.yml @@ -0,0 +1,172 @@ +# Build Spike and run a couple of debug tests. + +name: Test OpenOCD against 2 spike configurations + +env: + SPIKE_REPO: https://github.com/riscv-software-src/riscv-isa-sim.git + SPIKE_REV: master + RISCV_TESTS_REPO: https://github.com/riscv-software-src/riscv-tests.git + RISCV_TESTS_REV: master + OPENOCD_REPO: https://github.com/riscv/riscv-openocd.git + OPENOCD_REV: riscv + TOOLCHAIN_URL: https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.2.0-1/xpack-riscv-none-elf-gcc-12.2.0-1-linux-x64.tar.gz + +on: + # Run on merges to master to populate the cache with entities that are + # accessible by every pull request. + push: + branches: + - riscv + paths: + - 'debug/**' + - '.github/workflows/spike-openocd-tests.yml' + pull_request: + types: [synchronize, opened, reopened] + paths: + - 'debug/**' + - '.github/workflows/spike-openocd-tests.yml' + +# There is some commented out code below that would be useful in adding this +# workflow to other repos. Ideally we can come up with something that would +# leave this file almost identical between repos, so they can all easily run +# this test suite. + +jobs: + test: + name: Test debug (Ubuntu) + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Install packages + run: | + sudo apt-get update + sudo apt-get install -y device-tree-compiler build-essential + + - name: Get revisions of dependencies + run: | + SPIKE_COMMIT=$( git ls-remote "$SPIKE_REPO" $SPIKE_REV | awk '{ print $1; }' ) + OPENOCD_COMMIT=$( git ls-remote "$OPENOCD_REPO" $OPENOCD_REV | awk '{ print $1; }' ) + echo "Revison of Spike: $SPIKE_COMMIT" + echo "Revision of OpenOCD: $OPENOCD_COMMIT" + # Save for later use + echo "SPIKE_COMMIT=$SPIKE_COMMIT" >> $GITHUB_ENV + echo "OPENOCD_COMMIT=$OPENOCD_COMMIT" >> $GITHUB_ENV + + - name: Get the toolchain from cache (if available) + id: cache-restore-toolchain + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/toolchain + key: "toolchain-${{env.TOOLCHAIN_URL}}" + + - if: ${{ steps.cache-restore-toolchain.outputs.cache-hit != 'true' }} + name: Download Toolchain (if not cached) + run: | + mkdir -p /opt/riscv/toolchain + wget --progress=dot:giga $TOOLCHAIN_URL -O /tmp/toolchain.tar.gz + + - if: ${{ steps.cache-restore-toolchain.outputs.cache-hit != 'true' }} + name: Install Toolchain (if not cached) + run: tar zxf /tmp/toolchain.tar.gz --strip-components=1 -C /opt/riscv/toolchain + + - name: Save the toolchain to the cache (if necessary) + id: cache-save-toolchain + uses: actions/cache/save@v3 + with: + path: /opt/riscv/toolchain + key: "toolchain-${{env.TOOLCHAIN_URL}}" + + - name: Get OpenOCD from cache (if available) + id: cache-restore-openocd + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/openocd + key: "openocd-${{env.OPENOCD_COMMIT}}" + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Download OpenOCD source (if not cached) + run: | + git clone "$OPENOCD_REPO" + cd riscv-openocd + git checkout "$OPENOCD_COMMIT" + git submodule update --init --recursive + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Build OpenOCD (if not cached) + run: | + cd riscv-openocd + ./bootstrap + ./configure --prefix=/opt/riscv/openocd + make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" + make install + + - if: ${{ steps.cache-restore-openocd.outputs.cache-hit != 'true' }} + name: Save OpenOCD to cache (if built) + id: cache-save-openocd + uses: actions/cache/save@v3 + with: + path: /opt/riscv/openocd + key: "openocd-${{env.OPENOCD_COMMIT}}" + + - name: Get spike from cache (if available) + id: cache-restore-spike + uses: actions/cache/restore@v3 + with: + path: /opt/riscv/spike + key: "spike-${{env.SPIKE_COMMIT}}" + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Download Spike source (if not cached) + run: | + git clone "$SPIKE_REPO" + cd riscv-isa-sim + git checkout "$SPIKE_COMMIT" + git submodule update --init --recursive + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Build Spike (if not cached) + run: | + cd riscv-isa-sim + mkdir build && cd build + ../configure --prefix=/opt/riscv/spike + make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" + make install + + - if: ${{ steps.cache-restore-spike.outputs.cache-hit != 'true' }} + name: Save spike to cache (if built) + id: cache-save-spike + uses: actions/cache/save@v3 + with: + path: /opt/riscv/spike + key: "spike-${{env.SPIKE_COMMIT}}" + + - name: Run Spike32 Tests + id: spike32-tests + run: | + cd debug + ./gdbserver.py targets/RISC-V/spike32.py --print-failures \ + --gcc /opt/riscv/toolchain/bin/riscv-none-elf-gcc \ + --gdb /opt/riscv/toolchain/bin/riscv-none-elf-gdb \ + --sim_cmd /opt/riscv/spike/bin/spike \ + --server_cmd /opt/riscv/openocd/bin/openocd + + - name: Run Spike64-2 Tests + if: success() || steps.spike32-tests.conclusion == 'failure' + run: | + cd debug + ./gdbserver.py targets/RISC-V/spike64-2.py --print-failures \ + --gcc /opt/riscv/toolchain/bin/riscv-none-elf-gcc \ + --gdb /opt/riscv/toolchain/bin/riscv-none-elf-gdb \ + --sim_cmd /opt/riscv/spike/bin/spike \ + --server_cmd /opt/riscv/openocd/bin/openocd + + - name: Archive test logs + # Proceed even if there was a failed test + if: ${{ success() || failure() }} + uses: actions/upload-artifact@v3 + with: + name: test-logs + path: riscv-tests/debug/logs From e63009ff847638d23dae13dfba1f534ed6ad9473 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 18 Jul 2023 12:55:57 -0700 Subject: [PATCH 16/68] debug: Re-enable unavailable tests. --- debug/gdbserver.py | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 3b9a661ca..5a2ba2abe 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1816,10 +1816,9 @@ class UnavailableMultiTest(GdbTest): "-DDEFINE_FREE") def early_applicable(self): - return False # This test fails in github workflows - #return (self.hart.support_cease or - # self.target.support_unavailable_control) \ - # and len(self.target.harts) > 1 + return (self.hart.support_cease or + self.target.support_unavailable_control) \ + and len(self.target.harts) > 1 def setup(self): ProgramTest.setup(self) @@ -1886,9 +1885,8 @@ class UnavailableRunTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" def early_applicable(self): - return False # This test fails in github workflows - #return self.hart.support_cease or \ - # self.target.support_unavailable_control + return self.hart.support_cease or \ + self.target.support_unavailable_control def test(self): self.gdb.b("main") @@ -1924,8 +1922,7 @@ class UnavailableCycleTest(ProgramTest): """Test that harts can be debugged after becoming temporarily unavailable.""" def early_applicable(self): - return False # This test fails in github workflows - #return self.target.support_unavailable_control + return self.target.support_unavailable_control def test(self): self.gdb.b("main") From 83425c3163dfd5d1a2ecb5b2afc3b3309bfd8762 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 18 Jul 2023 13:26:07 -0700 Subject: [PATCH 17/68] debug: Tolerate more whitespace from OpenOCD CLI During the github workflow this character is \n, while on my computer it's ' '. I'm sure there's a good reason for that, but it doesn't seem worth figuring out what that reason is. --- debug/testlib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index 63cc49c79..435b41b5a 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -432,7 +432,7 @@ def command(self, cmd): self.command_count += 1 self.process.stdin.write(magic + b"\n") self.process.stdin.flush() - m = self.expect(rb"(.*)^> " + re.escape(magic)) + m = self.expect(rb"(.*)^>\s*" + re.escape(magic)) return m.group(1) def expect(self, regex, message=None): From 07a5dda6e5760b35a7f35d7d1f174264031906a3 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 29 Aug 2023 14:07:43 -0700 Subject: [PATCH 18/68] debug: Add --hart command line option to gdbserver.py This lets you reproduce a test running on a specific hart. --- debug/testlib.py | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index 435b41b5a..2c59af20f 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1058,11 +1058,15 @@ def load_excluded_tests(excluded_tests_file, target_name): def run_all_tests(module, target, parsed): todo = [] + if not parsed.hart is None: + target_hart = target.harts[parsed.hart] + else: + target_hart = None for name in dir(module): definition = getattr(module, name) if isinstance(definition, type) and hasattr(definition, 'test') and \ (not parsed.test or any(test in name for test in parsed.test)): - todo.append((name, definition, None)) + todo.append((name, definition, target_hart)) if parsed.list_tests: for name, definition, hart in todo: @@ -1130,7 +1134,10 @@ def run_tests(parsed, target, todo): result = instance.run() log_fd.write(f"Result: {result}\n") log_fd.write(f"Logfile: {log_name}\n") - log_fd.write(f"Reproduce: {sys.argv[0]} {parsed.target} {name}\n") + log_fd.write(f"Reproduce: {sys.argv[0]} {parsed.target} {name}") + if len(target.harts) > 1: + log_fd.write(f" --hart {instance.hart.id}") + log_fd.write("\n") finally: sys.stdout = real_stdout log_fd.write(f"Time elapsed: {time.time() - start:.2f}s\n") @@ -1189,6 +1196,9 @@ def add_test_run_options(parser): help="Specify yaml file listing tests to exclude") parser.add_argument("--target-timeout", help="Override the base target timeout.", default=None, type=int) + parser.add_argument("--hart", + help="Run tests against this hart in multihart tests.", + default=None, type=int) def header(title, dash='-', length=78): if title: @@ -1215,7 +1225,7 @@ class BaseTest: def __init__(self, target, hart=None): self.target = target - if hart: + if not hart is None: self.hart = hart else: import random # pylint: disable=import-outside-toplevel From 3cc4fed6cd0937d5a2b81d22142fc436428a1a95 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 29 Aug 2023 14:06:58 -0700 Subject: [PATCH 19/68] debug: Fix interrupt_all() to restore state. --- debug/testlib.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index 435b41b5a..104b29ee0 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -896,9 +896,10 @@ def interrupt(self, ops=None): return self.active_child.before.strip().decode() def interrupt_all(self): - for child in self.children: - self.select_child(child) - self.interrupt() + with PrivateState(self): + for child in self.children: + self.select_child(child) + self.interrupt() def x(self, address, size='w', count=1): output = self.command(f"x/{count}{size} {address}", ops=count / 16) From e10e446c1c70958b67eab97363f8096f8aa7ae09 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 28 Sep 2023 11:12:04 -0700 Subject: [PATCH 20/68] debug: Make Openocd.targets() tolerate blank lines. --- debug/testlib.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index 435b41b5a..9f048c030 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -483,7 +483,8 @@ def targets(self): headers = lines[0].split() data = [] for line in lines[2:]: - data.append(dict(zip(headers, line.split()[1:]))) + if line.strip(): + data.append(dict(zip(headers, line.split()[1:]))) return data def wait_until_running(self, harts): From 4c8fab6e1c5594e0b2a655a9089622ddd7ca00d5 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 25 Jul 2023 13:41:42 -0700 Subject: [PATCH 21/68] debug: Better interlock when interacting with gdb CLI. Actually wait for the command to be echoed back. This means we won't be confused if there are extra newlines in gdb output. --- debug/testlib.py | 1 + 1 file changed, 1 insertion(+) diff --git a/debug/testlib.py b/debug/testlib.py index 435b41b5a..b665edb6f 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -795,6 +795,7 @@ def command(self, command, ops=1, reset_delays=0): timeout = max(1, ops) * self.timeout self.active_child.sendline(command) try: + self.active_child.expect(re.escape(command), timeout=timeout) self.active_child.expect("\n", timeout=timeout) except pexpect.exceptions.TIMEOUT as exc: raise CommandSendTimeout(command) from exc From 903ec8243fc8af856ac549fcbfbd78835f2c3556 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 28 Sep 2023 11:13:52 -0700 Subject: [PATCH 22/68] debug: Add Openocd.set_available() This helper uses dmi_write commands to mark harts available/unavailable. --- debug/gdbserver.py | 13 ++++++------- debug/testlib.py | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5a2ba2abe..23515a393 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1830,8 +1830,7 @@ def test(self): # Other hart should have become unavailable. if self.target.support_unavailable_control: self.server.wait_until_running(self.target.harts) - self.server.command( - f"riscv dmi_write 0x1f 0x{(1< self.timeout: raise TestLibError("Timed out waiting for targets to run.") + def set_available(self, harts): + """Set the given harts to available, and any others to be unavailable. + This uses a custom DMI register (0x1f) that is only implemented in + spike.""" + available_mask = 0 + for hart in harts: + available_mask |= 1 << hart.id + self.command(f"riscv dmi_write 0x1f 0x{available_mask:x}") + + # Wait until it happened. + start = time.time() + while True: + currently_available = set() + currently_unavailable = set() + for i, target in enumerate(self.targets()): + if target["State"] == "unavailable": + currently_unavailable.add(i) + else: + currently_available.add(i) + if currently_available == set(hart.id for hart in harts): + return + if time.time() - start > self.timeout: + raise TestLibError("Timed out waiting for hart availability.") + class OpenocdCli: def __init__(self, port=4444): self.child = pexpect.spawn( From ecf4fde3b3ddf0fc3e8a8069d96e4d5c64cf54bf Mon Sep 17 00:00:00 2001 From: liangzhen Date: Thu, 14 Sep 2023 10:25:28 +0800 Subject: [PATCH 23/68] Disable timer interrupt to fix some bugs Signed-off-by: liangzhen --- debug/gdbserver.py | 6 ++++++ debug/testlib.py | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5a2ba2abe..31523b168 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1039,8 +1039,10 @@ def test(self): local = self.gdb.p("local") if interrupt_count > 1000 and \ local > 1000: + self.disable_timer() return + self.disable_timer() assertGreater(interrupt_count, 1000) assertGreater(local, 1000) @@ -1191,6 +1193,8 @@ def test(self): time.sleep(1) self.gdb.p("buf", fmt="") + self.disable_timer(interrupt=True) + class MulticoreRtosSwitchActiveHartTest(GdbTest): compile_args = ("programs/multicore.c", "-DMULTICORE") @@ -1220,6 +1224,8 @@ def test(self): assertIn("set_trap_handler", output) assertNotIn("received signal SIGTRAP", output) + self.disable_timer() + class SmpSimultaneousRunHalt(GdbTest): compile_args = ("programs/run_halt_timing.S", "-DMULTICORE") diff --git a/debug/testlib.py b/debug/testlib.py index 435b41b5a..6f470a0a5 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1411,6 +1411,13 @@ def disable_pmp(self): # PMP registers are optional pass + def disable_timer(self, interrupt=False): + for hart in self.target.harts: + self.gdb.select_hart(hart) + if interrupt: + self.gdb.interrupt() + self.gdb.p("$mie=$mie & ~0x80") + def exit(self, expected_result=10): self.gdb.command("delete") self.gdb.b("_exit") From 15d7d67f37f6c3f659977afca47de1f8240e0ae5 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 11 Oct 2023 12:58:01 -0700 Subject: [PATCH 24/68] debug: Document that pexpect is needed. Resolves #510. --- debug/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/debug/README.md b/debug/README.md index b98d8c209..6dc30d76f 100644 --- a/debug/README.md +++ b/debug/README.md @@ -19,6 +19,7 @@ The following should be in the user's path: * openocd (can be overridden with `--server_cmd` when running gdbserver.py manually), which should be the latest from https://github.com/riscv/riscv-openocd.git. +* Python packages that might not be installed: pexpect Usage ===== From 33663712bd8943fb360f4f5b730949ca11f3fc17 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 18 Jul 2023 09:41:35 -0700 Subject: [PATCH 25/68] debug: Add UnavailableHaltedTest Test behavior when a hart becomes unavailable while halted. --- debug/gdbserver.py | 61 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 3a6f93218..cb3ab4329 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1863,6 +1863,7 @@ def test(self): self.gdb.p("$pc=_start") self.exit() + class CeaseStepiTest(ProgramTest): """Test that we work correctly when the hart we're debugging ceases to respond.""" @@ -1950,6 +1951,66 @@ def test(self): self.gdb.interrupt() self.gdb.p("$pc") +class UnavailableHaltedTest(ProgramTest): + """Test behavior when the current hart becomes unavailable while halted.""" + def early_applicable(self): + return self.target.support_unavailable_control + + def test_resume(self, c_expect=None): + # Confirm things don't completely fall apart on `c` + self.gdb.c(wait=False) + if c_expect: + self.gdb.expect(c_expect) + else: + time.sleep(1) + + # Now send a DMI command through OpenOCD to make the hart available + # again. + self.server.set_available(self.target.harts) + + # The hart will show up as halted. That's just how spike behaves when we + # make a hart unavailable while it's halted. + + self.gdb.expect("became available") + self.gdb.p("$minstret") + + def test(self): + self.gdb.b("main") + output = self.gdb.c() + assertIn("Breakpoint", output) + assertIn("main", output) + + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + self.gdb.command(f"# disabled hart {self.hart.id}") + # gdb won't show that the hart became unavailable, because it thinks + # nothing can changed on a halted Linux thread. + try: + # We can't try this with something reasonable like $pc, because gdb + # has cached it, and it assumes the target can't change while it's + # halted. + self.gdb.p("$minstret") + assert False, ("Registers shouldn't be accessible when the hart is " + "unavailable.") + except testlib.CouldNotFetch: + pass + + # There's a breakpoint set, so gdb will single step. You can't single + # step an unavailable target, so gdb should get a message to that + # effect. + self.test_resume(c_expect="unavailable") + + # Delete breakpoints + self.gdb.command("delete") + self.server.set_available( + [h for h in self.target.harts if h != self.hart]) + + # Resume again. With breakpoints cleared, gdb will send vCont;c instead + # of step. There should be no error this time, since there is no + # observable difference between an unavailable thread and a running + # thread. + self.test_resume() + class FreeRtosTest(GdbTest): def early_applicable(self): return self.target.freertos_binary From 4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Mon, 16 Oct 2023 13:47:52 +0800 Subject: [PATCH 26/68] Make CLINT address configurable Signed-off-by: liangzhen --- debug/gdbserver.py | 6 +++--- debug/programs/init.h | 6 ++++-- debug/programs/run_halt_timing.S | 6 +++++- debug/targets.py | 6 +++++- 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 3a6f93218..e48b8889f 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -912,7 +912,7 @@ def early_applicable(self): def test(self): self.gdb.b("main:start") self.gdb.c() - mtime_addr = 0x02000000 + 0xbff8 + mtime_addr = self.target.clint_addr + 0xbff8 count = 1024 output = self.gdb.command( f"monitor riscv repeat_read {count} 0x{mtime_addr:x} 4") @@ -1048,8 +1048,8 @@ def test(self): def postMortem(self): GdbSingleHartTest.postMortem(self) - self.gdb.p("*((long long*) 0x200bff8)") - self.gdb.p("*((long long*) 0x2004000)") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0xbff8:x})") + self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})") self.gdb.p("interrupt_count") self.gdb.p("local") diff --git a/debug/programs/init.h b/debug/programs/init.h index 06d5384fd..e79681d95 100644 --- a/debug/programs/init.h +++ b/debug/programs/init.h @@ -1,8 +1,10 @@ #ifndef INIT_H #define INIT_H -#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8)) -#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000)) +#ifdef CLINT +#define MTIME (*(volatile long long *)(CLINT + 0xbff8)) +#define MTIMECMP ((volatile long long *)(CLINT + 0x4000)) +#endif typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc, void *sp); diff --git a/debug/programs/run_halt_timing.S b/debug/programs/run_halt_timing.S index ce4000afa..dc5d58b51 100644 --- a/debug/programs/run_halt_timing.S +++ b/debug/programs/run_halt_timing.S @@ -6,12 +6,16 @@ # define LREG lw # define SREG sw # define REGBYTES 4 +#endif + +#ifdef CLINT +#define MTIME_ADDR CLINT + 0xbff8 #endif .global main main: li s0, 0 - li s1, 0x0200bff8 + li s1, MTIME_ADDR loop: addi s0, s0, 1 LREG s2, 0(s1) diff --git a/debug/targets.py b/debug/targets.py index 3f63e79b9..081e2c66d 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -93,9 +93,12 @@ class Target: # before starting the test. gdb_setup = [] - # Supports mtime at 0x2004000 + # Supports mtime default at clint_addr + 0x4000 supports_clint_mtime = True + # CLINT register address, set to the default value of spike. + clint_addr = 0x02000000 + # Implements custom debug registers like spike does. It seems unlikely any # hardware will every do that. implements_custom_test = False @@ -189,6 +192,7 @@ def do_compile(self, hart, *sources): Target.temporary_files.append(self.temporary_binary) args = list(sources) + [ + f"-DCLINT={self.clint_addr}", "programs/entry.S", "programs/init.c", f"-DNHARTS={len(self.harts)}", "-I", "../env", From 57544c2c89f720015ca6c25ca1632603ab712901 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Mon, 16 Oct 2023 10:53:02 +0800 Subject: [PATCH 27/68] Make the non-existent csr configurable Signed-off-by: liangzhen --- debug/gdbserver.py | 9 +++++---- debug/targets.py | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 3a6f93218..4b2291c1d 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -221,14 +221,15 @@ def test(self): class SimpleNoExistTest(GdbTest): def test(self): + nonexist_csr = self.hart.nonexist_csr try: - self.gdb.p("$csr2288") - assert False, "Reading csr2288 should have failed" + self.gdb.p(f"${nonexist_csr}") + assert False, f"Reading the ${nonexist_csr} should have failed" except testlib.CouldNotFetch: pass try: - self.gdb.p("$csr2288=5") - assert False, "Writing csr2288 should have failed" + self.gdb.p(f"${nonexist_csr}=5") + assert False, f"Writing the ${nonexist_csr} should have failed" except testlib.CouldNotFetch: pass diff --git a/debug/targets.py b/debug/targets.py index 3f63e79b9..c1633e9ae 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -33,6 +33,9 @@ class Hart: # no device mapped to that location. bad_address = None + # The non-existent register for access test + nonexist_csr = "csr2288" + # Number of instruction triggers the hart supports. instruction_hardware_breakpoint_count = 0 From aa15f70c071a03b428621990142f6c049a656526 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Tue, 24 Oct 2023 09:29:53 +0800 Subject: [PATCH 28/68] Support instruction count limit in IcountTest This is taking into account that the hardware limits count to 1. Signed-off-by: liangzhen --- debug/gdbserver.py | 8 ++++++-- debug/targets.py | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 86359c814..5450adb1e 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -2129,9 +2129,13 @@ def setup(self): def test(self): # Execute 2 instructions. output = self.gdb.command("monitor riscv icount set m 2") - assertNotIn("Failed", output) + if self.target.icount_limit > 1: + assertNotIn("Failed", output) + else: + assertIn("Failed", output) + self.gdb.b("main_post_csrr") output = self.gdb.c() - assertIn("breakpoint", output) + assertIn("main_post_csrr", output) main_post_csrr = self.gdb.p("&main_post_csrr") assertEqual(self.gdb.p("$pc"), main_post_csrr) diff --git a/debug/targets.py b/debug/targets.py index 189d79b5a..bb7a5cf15 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -138,6 +138,9 @@ class Target: # Supports controlling hart availability through DMCUSTOM. support_unavailable_control = False + # Instruction count limit + icount_limit = 4 + # Internal variables: directory = None temporary_files = [] From a4d9f97003c4cca0d32336e10b4f96edcd958750 Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Wed, 8 Nov 2023 20:55:04 +0300 Subject: [PATCH 29/68] debug: use TCL-RPC to fetch results of OpenOCD commands instead of parsing log file Quick and dirty fix for https://github.com/riscv-software-src/riscv-tests/issues/520 --- debug/testlib.py | 67 +++++++++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index f36965f6e..7f28186cb 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -9,6 +9,7 @@ import time import traceback +import tty import pexpect import yaml @@ -308,20 +309,16 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, cmd = shlex.split(server_cmd) else: cmd = ["openocd"] - if debug: - cmd.append("-d") # This command needs to come before any config scripts on the command # line, since they are executed in order. cmd += [ # Tell OpenOCD to bind gdb to an unused, ephemeral port. "--command", "gdb_port 0", - # We don't use the TCL server. - "--command", "tcl_port disabled", - # Put the regular command prompt in stdin. Don't listen on a port - # because it will conflict if multiple OpenOCD instances are running - # at the same time. - "--command", "telnet_port pipe", + # We create a socket for OpenOCD command line (TCL-RPC) + "--command", "tcl_port 0", + # don't use telnet + "--command", "telnet_port disabled", ] if config: @@ -331,6 +328,7 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, sys.exit(1) cmd += ["-f", self.config_file] + if debug: cmd.append("-d") @@ -366,12 +364,18 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, logfile.flush() self.gdb_ports = [] + self.tclrpc_port = None self.start(cmd, logfile, extra_env) + self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}") + # TCL-RPC uses \x1a as a watermark for end of message. We set raw + # pty mode to disable translation of \x1a to EOF + tty.setraw(self.openocd_cli.child_fd) + def start(self, cmd, logfile, extra_env): combined_env = {**os.environ, **extra_env} # pylint: disable-next=consider-using-with - self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, + self.process = subprocess.Popen(cmd, stdin=None, stdout=logfile, stderr=logfile, env=combined_env) try: @@ -379,15 +383,28 @@ def start(self, cmd, logfile, extra_env): # using OpenOCD to communicate with a simulator this may take a # long time, and gdb will time out when trying to connect if we # attempt too early. - while True: m = self.expect( - rb"(Listening on port (\d+) for gdb connections|" - rb"tcl server disabled)", + rb"Listening on port (?P\d+) for " + rb"(?P(?:gdb)|(?:tcl)) connections", message="Waiting for OpenOCD to start up...") - if b"gdb" in m.group(1): - self.gdb_ports.append(int(m.group(2))) - else: + if m["server"] == b"gdb": + self.gdb_ports.append(int(m["port"])) + elif m["server"] == b"tcl": + if self.tclrpc_port: + raise TestLibError( + "unexpected re-definition of TCL-RPC port") + self.tclrpc_port = int(m["port"]) + # WARNING! WARNING! WARNING! + # The condition below works properly only if OpenOCD reports + # gdb/tcl ports in a specific order. Namely, it requires the + # gdb ports to be reported before the tcl one. At the moment + # this comment was written OpenOCD reports these ports in the + # required order if we have a call to `init` statement in + # either target configuration file or command-line parameter. + # All configuration files used in testing include a call to + # `init` + if self.tclrpc_port and (len(self.gdb_ports) > 0): break if self.debug_openocd: @@ -420,20 +437,12 @@ def smp(self): return False def command(self, cmd): - """Write the command to OpenOCD's stdin. Return the output of the - command, minus the prompt.""" - self.process.stdin.write(f"{cmd}\n".encode()) - self.process.stdin.flush() - m = self.expect(re.escape(f"{cmd}\n".encode())) - - # The prompt isn't flushed to the log, so send a unique command that - # lets us find where output of the last command ends. - magic = f"# {self.command_count}x".encode() - self.command_count += 1 - self.process.stdin.write(magic + b"\n") - self.process.stdin.flush() - m = self.expect(rb"(.*)^>\s*" + re.escape(magic)) - return m.group(1) + """Send the command to OpenOCD's TCL-RPC server. Return the output of + the command, minus the prompt.""" + self.openocd_cli.write(f"{cmd}\n\x1a") + self.openocd_cli.expect(rb"(.*)\x1a") + m = self.openocd_cli.match.group(1) + return m def expect(self, regex, message=None): """Wait for the regex to match the log, and return the match object. If From 4a72ca96dcab626a6289ccf035175adb69d8d727 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Fri, 5 Jan 2024 11:30:57 +0800 Subject: [PATCH 30/68] Disable mmu after test translate Signed-off-by: liangzhen --- debug/gdbserver.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5450adb1e..787e5bf69 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1679,6 +1679,10 @@ def test_translation(self): assertEqual(0xdeadbeef, self.gdb.p("virtual[0]")) assertEqual(0x55667788, self.gdb.p("virtual[1]")) + # disable mmu + self.gdb.p("$mstatus=$mstatus & ~0x20000") + self.gdb.p("$satp=0") + SATP_MODE_OFF = 0 SATP_MODE_SV32 = 1 SATP_MODE_SV39 = 8 From a0771484353d273bd6df8389193df9597b105572 Mon Sep 17 00:00:00 2001 From: Lucas Clemente Vella Date: Mon, 29 Jan 2024 19:40:50 +0000 Subject: [PATCH 31/68] Uses appropriate addi instruction in lrsc test. --- isa/rv64ua/lrsc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S index ab0d025a7..39fb156d0 100644 --- a/isa/rv64ua/lrsc.S +++ b/isa/rv64ua/lrsc.S @@ -62,7 +62,7 @@ addi a2, a2, 1 add a4, a4, a2 sc.w a4, a4, (a0) bnez a4, 1b -add a1, a1, -1 +addi a1, a1, -1 bnez a1, 1b # wait for all cores to finish From 9b04ba41669e8f408f89148fb13f41a196f1fd14 Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Wed, 31 Jan 2024 00:14:44 +0300 Subject: [PATCH 32/68] [debug tests] print selected seed for PRNG Previously the seed was not printed and this created problems with reproduction of the issues. It's still not an ideal - meaning interactions between spike/gdb/openocd are inherently non-determistic (since time is involved), but at least we should get the same sources for the same seed now. --- debug/gdbserver.py | 9 +++++++++ debug/testlib.py | 3 +++ 2 files changed, 12 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5450adb1e..f457b866e 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -11,6 +11,7 @@ import re import itertools +from datetime import datetime import targets import testlib from testlib import assertEqual, assertNotEqual @@ -2194,6 +2195,14 @@ def main(): module = sys.modules[__name__] + # initialize PRNG + selected_seed = parsed.seed + if parsed.seed is None: + selected_seed = int(datetime.now().timestamp()) + print(f"PRNG seed for {target.name} is generated automatically") + print(f"PRNG seed for {target.name} is {selected_seed}") + random.seed(selected_seed) + return testlib.run_all_tests(module, target, parsed) # TROUBLESHOOTING TIPS diff --git a/debug/testlib.py b/debug/testlib.py index 7f28186cb..a50a488b5 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1232,6 +1232,9 @@ def add_test_run_options(parser): help="Specify yaml file listing tests to exclude") parser.add_argument("--target-timeout", help="Override the base target timeout.", default=None, type=int) + parser.add_argument("--seed", + help="Use user-specified seed value for PRNG.", default=None, + type=int) parser.add_argument("--hart", help="Run tests against this hart in multihart tests.", default=None, type=int) From b89570c845e21b0dbf94b93a9685542002eda957 Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Thu, 1 Feb 2024 20:52:54 +0300 Subject: [PATCH 33/68] [debug tests] add option to log GDB remote serial protocol introduce a new option to log communications over GDB remote serial protocol which is helpful for debugging some tests. --- debug/testlib.py | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index a50a488b5..79a6a56be 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -708,7 +708,8 @@ class Gdb: 11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139, 97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53) - def __init__(self, target, ports, cmd=None, timeout=60, binaries=None): + def __init__(self, target, ports, cmd=None, timeout=60, binaries=None, + logremote=False): assert ports self.target = target @@ -744,6 +745,16 @@ def __init__(self, target, ports, cmd=None, timeout=60, binaries=None): self.command("set print entry-values no", reset_delays=None) self.command(f"set remotetimeout {self.timeout}", reset_delays=None) self.command(f"set remotetimeout {self.target.timeout_sec}") + if logremote: + # pylint: disable-next=consider-using-with + remotelog = tempfile.NamedTemporaryFile( + prefix=f"remote.gdb@{port}-", suffix=".log") + if print_log_names: + real_stdout.write( + f"Temporary remotelog: {remotelog.name}\n") + self.logfiles.append(remotelog) + self.command(f"set remotelogfile {remotelog.name}", + reset_delays=None) self.active_child = self.children[0] def connect(self): @@ -1124,6 +1135,8 @@ def run_all_tests(module, target, parsed): gcc_cmd = parsed.gcc global target_timeout # pylint: disable=global-statement target_timeout = parsed.target_timeout + global remotelogfile_enable # pylint: disable=global-statement + remotelogfile_enable = parsed.remotelogfile_enable examine_added = False for hart in target.harts: @@ -1235,6 +1248,10 @@ def add_test_run_options(parser): parser.add_argument("--seed", help="Use user-specified seed value for PRNG.", default=None, type=int) + parser.add_argument("--remotelogfile-enable", + help="If specified save GDB will record remote session to a file", + action="store_true", + default=False) parser.add_argument("--hart", help="Run tests against this hart in multihart tests.", default=None, type=int) @@ -1383,6 +1400,7 @@ def run(self): gdb_cmd = None target_timeout = None +remotelogfile_enable = False class GdbTest(BaseTest): def __init__(self, target, hart=None): BaseTest.__init__(self, target, hart=hart) @@ -1399,7 +1417,8 @@ def classSetup(self): self.gdb = Gdb(self.target, self.server.gdb_ports, cmd=gdb_cmd, timeout=target_timeout or self.target.timeout_sec, - binaries=self.binaries) + binaries=self.binaries, + logremote=remotelogfile_enable) self.logs += self.gdb.lognames() self.gdb.connect() From 787829a1b5d796961769a50e4731dd8a4dd6356e Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Wed, 31 Jan 2024 00:14:44 +0300 Subject: [PATCH 34/68] [debug tests] fix setting of remotetimeout fixes setting of `remotetimeout`. It was silently overwritten by default values from platform definition even if user specified one. --- debug/testlib.py | 1 - 1 file changed, 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index 79a6a56be..1d3fd1880 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -744,7 +744,6 @@ def __init__(self, target, ports, cmd=None, timeout=60, binaries=None, # Force consistency. self.command("set print entry-values no", reset_delays=None) self.command(f"set remotetimeout {self.timeout}", reset_delays=None) - self.command(f"set remotetimeout {self.target.timeout_sec}") if logremote: # pylint: disable-next=consider-using-with remotelog = tempfile.NamedTemporaryFile( From 9e18388b744c7cea04483ef1ef21bcd81e5835fb Mon Sep 17 00:00:00 2001 From: liangzhen Date: Fri, 2 Feb 2024 09:56:01 +0800 Subject: [PATCH 35/68] Add virtual memory synchronization after completing the page tables Signed-off-by: liangzhen Change-Id: Ida1490338d204541c5c7f143aec3b8d79d83d7f4 --- debug/programs/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/debug/programs/translate.c b/debug/programs/translate.c index 59dffd60f..e246baf77 100644 --- a/debug/programs/translate.c +++ b/debug/programs/translate.c @@ -163,6 +163,7 @@ int main() virtual = (uint32_t *) ( (reg_t) virtual | ~(((reg_t) 1 << vms->vaddr_bits) - 1)); add_entry(master_table, 0, (reg_t) virtual, (reg_t) physical); + __asm__ __volatile__ ("sfence.vma" ::: "memory"); // Virtual memory synchronization unsigned long satp = set_field(0, SATP_MODE, vms->mode); satp = set_field(satp, SATP_PPN, ((unsigned long) master_table) >> 12); From c45a88f37a5618dd2da4cfb31180d10db1e131f4 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Fri, 2 Feb 2024 10:00:23 +0800 Subject: [PATCH 36/68] Clear breakpoints so that gdb will not single step Signed-off-by: liangzhen Change-Id: I7a4a24972cfa2ddc307a5f06fe3fd5380794719f --- debug/gdbserver.py | 1 + 1 file changed, 1 insertion(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5450adb1e..4bfd408a5 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -2139,6 +2139,7 @@ def test(self): main_post_csrr = self.gdb.p("&main_post_csrr") assertEqual(self.gdb.p("$pc"), main_post_csrr) + self.gdb.command("delete") self.gdb.command("monitor riscv icount clear") # Execute 1 instruction. From 9f053a87bc9ce3afbdaf5e808f98eed5a8229887 Mon Sep 17 00:00:00 2001 From: Eiji Yoshiya Date: Sat, 3 Feb 2024 09:23:09 +0900 Subject: [PATCH 37/68] If Svnapot is not implemented, skip the test. If Svnapot is not implemented, a page fault will occur when accessing a page with napot specified. In this case, let the test pass. --- isa/rv64ssvnapot/napot.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/isa/rv64ssvnapot/napot.S b/isa/rv64ssvnapot/napot.S index 92d2b4990..fbc4014dd 100644 --- a/isa/rv64ssvnapot/napot.S +++ b/isa/rv64ssvnapot/napot.S @@ -121,6 +121,7 @@ RVTEST_CODE_BEGIN # Do a store to MY_VA li a0, MY_VA li a1, 42 +napot_store: sw a1, (a0) # Clear MPRV @@ -153,6 +154,16 @@ RVTEST_CODE_BEGIN .align 2 .global mtvec_handler mtvec_handler: + # Skip if Svnapot is not implemented. + csrr t5, mcause + li t6, CAUSE_STORE_PAGE_FAULT + bne t5, t6, die + csrr t5, mepc + la t6, napot_store + bne t5, t6, die + csrr t5, mtval + li t6, MY_VA + beq t5, t6, pass die: RVTEST_FAIL From f83ba405f167bc906d9e81d8e35a1b70bb105219 Mon Sep 17 00:00:00 2001 From: liangzhen Date: Fri, 2 Feb 2024 10:14:20 +0800 Subject: [PATCH 38/68] Check the mcontrol triggers, no other triggers. Signed-off-by: liangzhen Change-Id: Iac914aef8080411e6acd9039c4bdfa728533103c --- debug/gdbserver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 5450adb1e..ebc591c19 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -1415,7 +1415,7 @@ def check_triggers(self, tdata1_lsbs, tdata2): i = 0 for i in range(16): tdata1 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i}]") - if tdata1 == 0: + if (tdata1 == 0) or (tdata1 >> (self.hart.xlen-4) == 15): break tdata2 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i+1}]") From 45476161d6c42c321458027b70fc03a97f6e4ad7 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 19 Feb 2024 11:17:29 +0800 Subject: [PATCH 39/68] Add zba test cases Signed-off-by: Roger Chang --- isa/Makefile | 8 +++- isa/rv32uzba/Makefrag | 14 +++++++ isa/rv32uzba/sh1add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv32uzba/sh2add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv32uzba/sh3add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/Makefrag | 16 ++++++++ isa/rv64uzba/add_uw.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh1add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh1add_uw.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh2add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh2add_uw.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh3add.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/sh3add_uw.S | 85 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzba/slli_uw.S | 72 ++++++++++++++++++++++++++++++++++ 14 files changed, 958 insertions(+), 2 deletions(-) create mode 100644 isa/rv32uzba/Makefrag create mode 100644 isa/rv32uzba/sh1add.S create mode 100644 isa/rv32uzba/sh2add.S create mode 100644 isa/rv32uzba/sh3add.S create mode 100644 isa/rv64uzba/Makefrag create mode 100644 isa/rv64uzba/add_uw.S create mode 100644 isa/rv64uzba/sh1add.S create mode 100644 isa/rv64uzba/sh1add_uw.S create mode 100644 isa/rv64uzba/sh2add.S create mode 100644 isa/rv64uzba/sh2add_uw.S create mode 100644 isa/rv64uzba/sh3add.S create mode 100644 isa/rv64uzba/sh3add_uw.S create mode 100644 isa/rv64uzba/slli_uw.S diff --git a/isa/Makefile b/isa/Makefile index d66b9017a..ffd82ffa5 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -14,6 +14,7 @@ include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag +include $(src_dir)/rv64uzba/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -26,6 +27,7 @@ include $(src_dir)/rv32ua/Makefrag include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag +include $(src_dir)/rv32uzba/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -50,10 +52,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ define compile_template @@ -86,6 +88,7 @@ $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) +$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -96,6 +99,7 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) +$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzba/Makefrag b/isa/rv32uzba/Makefrag new file mode 100644 index 000000000..39a2c9987 --- /dev/null +++ b/isa/rv32uzba/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzba tests +#----------------------------------------------------------------------- + +rv32uzba_sc_tests = \ + sh1add \ + sh2add \ + sh3add \ + +rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests)) +rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests)) +rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests)) + +spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests) diff --git a/isa/rv32uzba/sh1add.S b/isa/rv32uzba/sh1add.S new file mode 100644 index 000000000..03ae19012 --- /dev/null +++ b/isa/rv32uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh2add.S b/isa/rv32uzba/sh2add.S new file mode 100644 index 000000000..057dba5d5 --- /dev/null +++ b/isa/rv32uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzba/sh3add.S b/isa/rv32uzba/sh3add.S new file mode 100644 index 000000000..530241e5c --- /dev/null +++ b/isa/rv32uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/Makefrag b/isa/rv64uzba/Makefrag new file mode 100644 index 000000000..a2428f391 --- /dev/null +++ b/isa/rv64uzba/Makefrag @@ -0,0 +1,16 @@ +#======================================================================= +# Makefrag for rv64uzba tests +#----------------------------------------------------------------------- + +rv64uzba_sc_tests = \ + add_uw \ + sh1add sh1add_uw \ + sh2add sh2add_uw \ + sh3add sh3add_uw \ + slli_uw \ + +rv64uzba_p_tests = $(addprefix rv64uzba-p-, $(rv64uzba_sc_tests)) +rv64uzba_v_tests = $(addprefix rv64uzba-v-, $(rv64uzba_sc_tests)) +rv64uzba_ps_tests = $(addprefix rv64uzba-ps-, $(rv64uzba_sc_tests)) + +spike_tests += $(rv64uzba_p_tests) $(rv64uzba_v_tests) diff --git a/isa/rv64uzba/add_uw.S b/isa/rv64uzba/add_uw.S new file mode 100644 index 000000000..cd89628f1 --- /dev/null +++ b/isa/rv64uzba/add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add_uw.S +#----------------------------------------------------------------------------- +# +# Test add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add.uw, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add.uw, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add.uw, 0x0000000080000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add.uw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add.uw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add.uw, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add.uw, 0x0000000080007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add.uw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add.uw, 0x0000000100000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add.uw, 0x00000000fffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add.uw, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add.uw, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add.uw, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add.uw, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add.uw, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add.uw, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add.uw, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add.uw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add.uw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add.uw, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add.uw, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add.uw, 0 ); + TEST_RR_ZERODEST( 38, add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh1add.S b/isa/rv64uzba/sh1add.S new file mode 100644 index 000000000..1ccaf774f --- /dev/null +++ b/isa/rv64uzba/sh1add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.S +#----------------------------------------------------------------------------- +# +# Test sh1add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add, 0xffffffff00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add, 0xfffffffeffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add, 0xffffffff00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add, 0xfffffffffffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add, 0 ); + TEST_RR_ZERODEST( 38, sh1add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh1add_uw.S b/isa/rv64uzba/sh1add_uw.S new file mode 100644 index 000000000..78b198dfe --- /dev/null +++ b/isa/rv64uzba/sh1add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh1add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh1add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh1add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh1add.uw, 0x00000003, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh1add.uw, 0x0000000d, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh1add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh1add.uw, 0x0000000100000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh1add.uw, 0x00000000ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh1add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh1add.uw, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh1add.uw, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh1add.uw, 0x0000000100007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh1add.uw, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh1add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh1add.uw, 0x00000001ffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh1add.uw, 0x00000001fffffffd, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh1add.uw, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh1add.uw, 39, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add.uw, 41, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add.uw, 37, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add.uw, 39, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add.uw, 41, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh1add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh1add.uw, 64, 32 ); + TEST_RR_ZEROSRC12( 37, sh1add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh1add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh2add.S b/isa/rv64uzba/sh2add.S new file mode 100644 index 000000000..a8756bbb2 --- /dev/null +++ b/isa/rv64uzba/sh2add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.S +#----------------------------------------------------------------------------- +# +# Test sh2add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add, 0xfffffffe00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add, 0xfffffffdffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add, 0xfffffffe00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add, 0xfffffffffffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add, 0xfffffffffffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add, 0 ); + TEST_RR_ZERODEST( 38, sh2add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh2add_uw.S b/isa/rv64uzba/sh2add_uw.S new file mode 100644 index 000000000..1da3a43af --- /dev/null +++ b/isa/rv64uzba/sh2add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh2add.uw.S +#----------------------------------------------------------------------------- +# +# Test sh2add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh2add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh2add.uw, 0x00000005, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh2add.uw, 0x00000013, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh2add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh2add.uw, 0x0000000200000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh2add.uw, 0x00000001ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh2add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh2add.uw, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh2add.uw, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh2add.uw, 0x0000000200007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh2add.uw, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh2add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh2add.uw, 0x00000003fffffffd, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh2add.uw, 0x00000003fffffffb, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh2add.uw, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh2add.uw, 65, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add.uw, 71, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add.uw, 63, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add.uw, 67, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add.uw, 71, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh2add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh2add.uw, 128, 32 ); + TEST_RR_ZEROSRC12( 37, sh2add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh2add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh3add.S b/isa/rv64uzba/sh3add.S new file mode 100644 index 000000000..086e07a46 --- /dev/null +++ b/isa/rv64uzba/sh3add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add.S +#----------------------------------------------------------------------------- +# +# Test sh3add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add, 0xfffffffc00000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add, 0xfffffffbffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add, 0xfffffffc00007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add, 0xfffffffffffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add, 0xfffffffffffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add, 0 ); + TEST_RR_ZERODEST( 38, sh3add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/sh3add_uw.S b/isa/rv64uzba/sh3add_uw.S new file mode 100644 index 000000000..f07375fca --- /dev/null +++ b/isa/rv64uzba/sh3add_uw.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh3add_uw.S +#----------------------------------------------------------------------------- +# +# Test sh3add.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sh3add.uw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sh3add.uw, 0x00000009, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sh3add.uw, 0x0000001f, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, sh3add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sh3add.uw, 0x0000000400000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, sh3add.uw, 0x00000003ffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sh3add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sh3add.uw, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sh3add.uw, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sh3add.uw, 0x0000000400007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sh3add.uw, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sh3add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sh3add.uw, 0x00000007fffffff9, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sh3add.uw, 0x00000007fffffff7, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, sh3add.uw, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, sh3add.uw, 117, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add.uw, 131, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add.uw, 115, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add.uw, 123, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add.uw, 131, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, sh3add.uw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, sh3add.uw, 256, 32 ); + TEST_RR_ZEROSRC12( 37, sh3add.uw, 0 ); + TEST_RR_ZERODEST( 38, sh3add.uw, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzba/slli_uw.S b/isa/rv64uzba/slli_uw.S new file mode 100644 index 000000000..e60f91279 --- /dev/null +++ b/isa/rv64uzba/slli_uw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli_uw.S +#----------------------------------------------------------------------------- +# +# Test slli.uw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli.uw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli.uw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli.uw, 0x00000000ffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli.uw, 0x00000001fffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli.uw, 0x0000007fffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli.uw, 0x00003fffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli.uw, 0x7fffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli.uw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli.uw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli.uw, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli.uw, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli.uw, 0x1090909080000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 50, slli.uw, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, slli.uw, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, slli.uw, 0x0909080000000000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli.uw, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli.uw, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli.uw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END From a3498c6d2f770af95964a0a7ba46f285cecd1eb3 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 19 Feb 2024 11:29:33 +0800 Subject: [PATCH 40/68] Add zbb test cases Signed-off-by: Roger Chang --- isa/Makefile | 8 +++- isa/rv32uzbb/Makefrag | 26 ++++++++++++ isa/rv32uzbb/andn.S | 7 ++++ isa/rv32uzbb/clz.S | 76 +++++++++++++++++++++++++++++++++ isa/rv32uzbb/cpop.S | 75 +++++++++++++++++++++++++++++++++ isa/rv32uzbb/ctz.S | 75 +++++++++++++++++++++++++++++++++ isa/rv32uzbb/max.S | 7 ++++ isa/rv32uzbb/maxu.S | 7 ++++ isa/rv32uzbb/min.S | 7 ++++ isa/rv32uzbb/minu.S | 7 ++++ isa/rv32uzbb/orc_b.S | 75 +++++++++++++++++++++++++++++++++ isa/rv32uzbb/orn.S | 7 ++++ isa/rv32uzbb/rev8.S | 75 +++++++++++++++++++++++++++++++++ isa/rv32uzbb/rol.S | 97 +++++++++++++++++++++++++++++++++++++++++++ isa/rv32uzbb/ror.S | 91 ++++++++++++++++++++++++++++++++++++++++ isa/rv32uzbb/rori.S | 68 ++++++++++++++++++++++++++++++ isa/rv32uzbb/sext_b.S | 7 ++++ isa/rv32uzbb/sext_h.S | 7 ++++ isa/rv32uzbb/xnor.S | 7 ++++ isa/rv32uzbb/zext_h.S | 7 ++++ isa/rv64uzbb/Makefrag | 26 ++++++++++++ isa/rv64uzbb/andn.S | 76 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/clz.S | 74 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/clzw.S | 76 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/cpop.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/cpopw.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/ctz.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/ctzw.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/max.S | 84 +++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/maxu.S | 84 +++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/min.S | 84 +++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/minu.S | 84 +++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/orc_b.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/orn.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/rev8.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/rol.S | 96 ++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/rolw.S | 97 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/ror.S | 94 +++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/rori.S | 72 ++++++++++++++++++++++++++++++++ isa/rv64uzbb/roriw.S | 68 ++++++++++++++++++++++++++++++ isa/rv64uzbb/rorw.S | 91 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbb/sext_b.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/sext_h.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/xnor.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbb/zext_h.S | 75 +++++++++++++++++++++++++++++++++ 45 files changed, 2665 insertions(+), 2 deletions(-) create mode 100644 isa/rv32uzbb/Makefrag create mode 100644 isa/rv32uzbb/andn.S create mode 100644 isa/rv32uzbb/clz.S create mode 100644 isa/rv32uzbb/cpop.S create mode 100644 isa/rv32uzbb/ctz.S create mode 100644 isa/rv32uzbb/max.S create mode 100644 isa/rv32uzbb/maxu.S create mode 100644 isa/rv32uzbb/min.S create mode 100644 isa/rv32uzbb/minu.S create mode 100644 isa/rv32uzbb/orc_b.S create mode 100644 isa/rv32uzbb/orn.S create mode 100644 isa/rv32uzbb/rev8.S create mode 100644 isa/rv32uzbb/rol.S create mode 100644 isa/rv32uzbb/ror.S create mode 100644 isa/rv32uzbb/rori.S create mode 100644 isa/rv32uzbb/sext_b.S create mode 100644 isa/rv32uzbb/sext_h.S create mode 100644 isa/rv32uzbb/xnor.S create mode 100644 isa/rv32uzbb/zext_h.S create mode 100644 isa/rv64uzbb/Makefrag create mode 100644 isa/rv64uzbb/andn.S create mode 100644 isa/rv64uzbb/clz.S create mode 100644 isa/rv64uzbb/clzw.S create mode 100644 isa/rv64uzbb/cpop.S create mode 100644 isa/rv64uzbb/cpopw.S create mode 100644 isa/rv64uzbb/ctz.S create mode 100644 isa/rv64uzbb/ctzw.S create mode 100644 isa/rv64uzbb/max.S create mode 100644 isa/rv64uzbb/maxu.S create mode 100644 isa/rv64uzbb/min.S create mode 100644 isa/rv64uzbb/minu.S create mode 100644 isa/rv64uzbb/orc_b.S create mode 100644 isa/rv64uzbb/orn.S create mode 100644 isa/rv64uzbb/rev8.S create mode 100644 isa/rv64uzbb/rol.S create mode 100644 isa/rv64uzbb/rolw.S create mode 100644 isa/rv64uzbb/ror.S create mode 100644 isa/rv64uzbb/rori.S create mode 100644 isa/rv64uzbb/roriw.S create mode 100644 isa/rv64uzbb/rorw.S create mode 100644 isa/rv64uzbb/sext_b.S create mode 100644 isa/rv64uzbb/sext_h.S create mode 100644 isa/rv64uzbb/xnor.S create mode 100644 isa/rv64uzbb/zext_h.S diff --git a/isa/Makefile b/isa/Makefile index ffd82ffa5..28ae6a668 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -15,6 +15,7 @@ include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag +include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -28,6 +29,7 @@ include $(src_dir)/rv32uf/Makefrag include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag +include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -52,10 +54,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ define compile_template @@ -89,6 +91,7 @@ $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -100,6 +103,7 @@ $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) +$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzbb/Makefrag b/isa/rv32uzbb/Makefrag new file mode 100644 index 000000000..752f8d036 --- /dev/null +++ b/isa/rv32uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv32uzbb tests +#----------------------------------------------------------------------- + +rv32uzbb_sc_tests = \ + andn \ + clz \ + cpop \ + ctz \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol \ + ror \ + rori \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests)) +rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests)) +rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests)) + +spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests) diff --git a/isa/rv32uzbb/andn.S b/isa/rv32uzbb/andn.S new file mode 100644 index 000000000..f54aa1aba --- /dev/null +++ b/isa/rv32uzbb/andn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/andn.S" diff --git a/isa/rv32uzbb/clz.S b/isa/rv32uzbb/clz.S new file mode 100644 index 000000000..4b349ad87 --- /dev/null +++ b/isa/rv32uzbb/clz.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 32, 0x00000000); + TEST_R_OP( 3, clz, 31, 0x00000001); + TEST_R_OP( 4, clz, 30, 0x00000003); + + TEST_R_OP( 5, clz, 0, 0xffff8000 ); + TEST_R_OP( 6, clz, 8, 0x00800000 ); + TEST_R_OP( 7, clz, 0, 0xffff8000 ); + + TEST_R_OP( 8, clz, 17, 0x00007fff); + TEST_R_OP( 9, clz, 1, 0x7fffffff); + TEST_R_OP( 10, clz, 13, 0x0007ffff ); + + TEST_R_OP( 11, clz, 0, 0x80000000); + TEST_R_OP( 12, clz, 3, 0x121f5000); + + TEST_R_OP( 13, clz, 5, 0x04000000); + TEST_R_OP( 14, clz, 28, 0x0000000e); + TEST_R_OP( 15, clz, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clz, 5, 0x070f8000 ); + TEST_R_OP( 22, clz, 4, 0x08008000 ); + TEST_R_OP( 23, clz, 3, 0x18008000 ); + + TEST_R_OP( 24, clz, 17, 0x00007fff); + TEST_R_OP( 25, clz, 1, 0x7fffffff); + TEST_R_OP( 26, clz, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/cpop.S b/isa/rv32uzbb/cpop.S new file mode 100644 index 000000000..4d9775891 --- /dev/null +++ b/isa/rv32uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x00000000); + TEST_R_OP( 3, cpop, 1, 0x00000001); + TEST_R_OP( 4, cpop, 2, 0x00000003); + + TEST_R_OP( 5, cpop, 17, 0xffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x00800000 ); + TEST_R_OP( 7, cpop, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpop, 15, 0x00007fff); + TEST_R_OP( 9, cpop, 31, 0x7fffffff); + TEST_R_OP( 10, cpop, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpop, 1, 0x80000000); + TEST_R_OP( 12, cpop, 9, 0x121f5000); + + TEST_R_OP( 13, cpop, 0, 0x00000000); + TEST_R_OP( 14, cpop, 3, 0x0000000e); + TEST_R_OP( 15, cpop, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x00808000 ); + TEST_R_OP( 23, cpop, 3, 0x01808000 ); + + TEST_R_OP( 24, cpop, 17, 0x30007fff); + TEST_R_OP( 25, cpop, 30, 0x77ffffff); + TEST_R_OP( 26, cpop, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ctz.S b/isa/rv32uzbb/ctz.S new file mode 100644 index 000000000..58bf2f1f4 --- /dev/null +++ b/isa/rv32uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 32, 0x00000000); + TEST_R_OP( 3, ctz, 0, 0x00000001); + TEST_R_OP( 4, ctz, 0, 0x00000003); + + TEST_R_OP( 5, ctz, 15, 0xffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x00800000 ); + TEST_R_OP( 7, ctz, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x00007fff); + TEST_R_OP( 9, ctz, 0, 0x7fffffff); + TEST_R_OP( 10, ctz, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctz, 31, 0x80000000); + TEST_R_OP( 12, ctz, 12, 0x121f5000); + + TEST_R_OP( 13, ctz, 30, 0xc0000000); + TEST_R_OP( 14, ctz, 1, 0x0000000e); + TEST_R_OP( 15, ctz, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x00808000 ); + TEST_R_OP( 23, ctz, 12, 0x01809000 ); + + TEST_R_OP( 24, ctz, 0, 0x00007fff); + TEST_R_OP( 25, ctz, 0, 0x7fffffff); + TEST_R_OP( 26, ctz, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/max.S b/isa/rv32uzbb/max.S new file mode 100644 index 000000000..ecd713cab --- /dev/null +++ b/isa/rv32uzbb/max.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/max.S" diff --git a/isa/rv32uzbb/maxu.S b/isa/rv32uzbb/maxu.S new file mode 100644 index 000000000..27cfc2950 --- /dev/null +++ b/isa/rv32uzbb/maxu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/maxu.S" diff --git a/isa/rv32uzbb/min.S b/isa/rv32uzbb/min.S new file mode 100644 index 000000000..c24a51448 --- /dev/null +++ b/isa/rv32uzbb/min.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/min.S" diff --git a/isa/rv32uzbb/minu.S b/isa/rv32uzbb/minu.S new file mode 100644 index 000000000..4b2549d19 --- /dev/null +++ b/isa/rv32uzbb/minu.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/minu.S" diff --git a/isa/rv32uzbb/orc_b.S b/isa/rv32uzbb/orc_b.S new file mode 100644 index 000000000..7fb844154 --- /dev/null +++ b/isa/rv32uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001); + TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003); + + TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 ); + TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 ); + TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 ); + + TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff ); + + TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000); + TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000); + + TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000); + TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e); + TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 ); + TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 ); + TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 ); + + TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff); + TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff); + TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/orn.S b/isa/rv32uzbb/orn.S new file mode 100644 index 000000000..cdfafccfa --- /dev/null +++ b/isa/rv32uzbb/orn.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/orn.S" diff --git a/isa/rv32uzbb/rev8.S b/isa/rv32uzbb/rev8.S new file mode 100644 index 000000000..2828f27c2 --- /dev/null +++ b/isa/rv32uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 3, rev8, 0x01000000, 0x00000001); + TEST_R_OP( 4, rev8, 0x03000000, 0x00000003); + + TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 ); + TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 ); + TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080, 0x80000000); + TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000); + + TEST_R_OP( 13, rev8, 0x00000000, 0x00000000); + TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e); + TEST_R_OP( 15, rev8, 0x41134020, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 ); + TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 ); + TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 ); + + TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff); + TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff); + TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rol.S b/isa/rv32uzbb/rol.S new file mode 100644 index 000000000..a7c04feca --- /dev/null +++ b/isa/rv32uzbb/rol.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 ); + TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 ); + TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 ); + TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 ); + TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 ); + TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 ); + TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 ); + TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee ); + TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 ); + TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 ); + TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 ); + TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/ror.S b/isa/rv32uzbb/ror.S new file mode 100644 index 000000000..5b5774081 --- /dev/null +++ b/isa/rv32uzbb/ror.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 ); + TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 ); + TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 ); + TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 ); + TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 ); + TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 ); + TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 ); + TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 ); + TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce ); + + TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/rori.S b/isa/rv32uzbb/rori.S new file mode 100644 index 000000000..c98ed8591 --- /dev/null +++ b/isa/rv32uzbb/rori.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 ); + TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 ); + TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 ); + TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 ); + TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 ); + TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbb/sext_b.S b/isa/rv32uzbb/sext_b.S new file mode 100644 index 000000000..f73e10767 --- /dev/null +++ b/isa/rv32uzbb/sext_b.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_b.S" diff --git a/isa/rv32uzbb/sext_h.S b/isa/rv32uzbb/sext_h.S new file mode 100644 index 000000000..d4b4206c9 --- /dev/null +++ b/isa/rv32uzbb/sext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/sext_h.S" diff --git a/isa/rv32uzbb/xnor.S b/isa/rv32uzbb/xnor.S new file mode 100644 index 000000000..c5e453a5a --- /dev/null +++ b/isa/rv32uzbb/xnor.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/xnor.S" diff --git a/isa/rv32uzbb/zext_h.S b/isa/rv32uzbb/zext_h.S new file mode 100644 index 000000000..d339ccc16 --- /dev/null +++ b/isa/rv32uzbb/zext_h.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbb/zext_h.S" diff --git a/isa/rv64uzbb/Makefrag b/isa/rv64uzbb/Makefrag new file mode 100644 index 000000000..2e93897c4 --- /dev/null +++ b/isa/rv64uzbb/Makefrag @@ -0,0 +1,26 @@ +#======================================================================= +# Makefrag for rv64uzbb tests +#----------------------------------------------------------------------- + +rv64uzbb_sc_tests = \ + andn \ + clz clzw \ + cpop cpopw \ + ctz ctzw \ + max maxu \ + min minu \ + orc_b \ + orn \ + rev8 \ + rol rolw \ + ror rorw \ + rori roriw \ + sext_b sext_h \ + xnor \ + zext_h \ + +rv64uzbb_p_tests = $(addprefix rv64uzbb-p-, $(rv64uzbb_sc_tests)) +rv64uzbb_v_tests = $(addprefix rv64uzbb-v-, $(rv64uzbb_sc_tests)) +rv64uzbb_ps_tests = $(addprefix rv64uzbb-ps-, $(rv64uzbb_sc_tests)) + +spike_tests += $(rv64uzbb_p_tests) $(rv64uzbb_v_tests) diff --git a/isa/rv64uzbb/andn.S b/isa/rv64uzbb/andn.S new file mode 100644 index 000000000..be7f032e8 --- /dev/null +++ b/isa/rv64uzbb/andn.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andn.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# This test is forked from and.S +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, andn, 0x00000000000f000f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, andn, 0x0f000f000f000f00, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, andn, 0x00f000f000f000f0, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, andn, 0x000f000f000f000f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, andn, 0x0000000000000000, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, andn, 0, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, andn, 0x0000000000ff00ff, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, andn, 0 ); + TEST_RR_ZERODEST( 27, andn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clz.S b/isa/rv64uzbb/clz.S new file mode 100644 index 000000000..9df653174 --- /dev/null +++ b/isa/rv64uzbb/clz.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clz.S +#----------------------------------------------------------------------------- +# +# Test clz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clz, 64, 0x0000000000000000); + TEST_R_OP( 3, clz, 63, 0x0000000000000001); + TEST_R_OP( 4, clz, 62, 0x0000000000000003); + + TEST_R_OP( 5, clz, 0, 0xffffffffffff8000 ); + TEST_R_OP( 6, clz, 40, 0x0000000000800000 ); + TEST_R_OP( 7, clz, 13, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, clz, 49, 0x0000000000007fff); + TEST_R_OP( 9, clz, 33, 0x000000007fffffff); + TEST_R_OP( 10, clz, 45, 0x000000000007ffff ); + + TEST_R_OP( 11, clz, 0, 0xffffffff80000000); + TEST_R_OP( 12, clz, 8, 0x00ff578f121f5000); + + TEST_R_OP( 13, clz, 0, 0x8000000000000000); + TEST_R_OP( 14, clz, 60, 0x000000000000000e); + TEST_R_OP( 15, clz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clz, 60, 13); + TEST_R_SRC1_EQ_DEST( 17, clz, 60, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clz, 60, 13); + TEST_R_DEST_BYPASS( 29, 1, clz, 59, 19); + TEST_R_DEST_BYPASS( 20, 2, clz, 58, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, clz, 37, 0x00000000070f8000 ); + TEST_R_OP( 22, clz, 36, 0x0000000008008000 ); + TEST_R_OP( 23, clz, 35, 0x0000000018008000 ); + + TEST_R_OP( 24, clz, 30, 0x0000000300007fff); + TEST_R_OP( 25, clz, 29, 0x000000077fffffff); + TEST_R_OP( 26, clz, 28, 0x0000000f0007ffff); + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/clzw.S b/isa/rv64uzbb/clzw.S new file mode 100644 index 000000000..24b659d7d --- /dev/null +++ b/isa/rv64uzbb/clzw.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clzw.S +#----------------------------------------------------------------------------- +# +# Test clzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, clzw, 32, 0x00000000); + TEST_R_OP( 3, clzw, 31, 0x00000001); + TEST_R_OP( 4, clzw, 30, 0x00000003); + + TEST_R_OP( 5, clzw, 0, 0xffff8000 ); + TEST_R_OP( 6, clzw, 8, 0x00800000 ); + TEST_R_OP( 7, clzw, 0, 0xffff8000 ); + + TEST_R_OP( 8, clzw, 17, 0x00007fff); + TEST_R_OP( 9, clzw, 1, 0x7fffffff); + TEST_R_OP( 10, clzw, 13, 0x0007ffff ); + + TEST_R_OP( 11, clzw, 0, 0x80000000); + TEST_R_OP( 12, clzw, 3, 0x121f5000); + + TEST_R_OP( 13, clzw, 5, 0x04000000); + TEST_R_OP( 14, clzw, 28, 0x0000000e); + TEST_R_OP( 15, clzw, 2, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, clzw, 28, 13); + TEST_R_SRC1_EQ_DEST( 17, clzw, 28, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, clzw, 28, 13); + TEST_R_DEST_BYPASS( 29, 1, clzw, 27, 19); + TEST_R_DEST_BYPASS( 20, 2, clzw, 26, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + + TEST_R_OP( 21, clzw, 5, 0x070f8000 ); + TEST_R_OP( 22, clzw, 4, 0x08008000 ); + TEST_R_OP( 23, clzw, 3, 0x18008000 ); + + TEST_R_OP( 24, clzw, 17, 0x00007fff); + TEST_R_OP( 25, clzw, 1, 0x7fffffff); + TEST_R_OP( 26, clzw, 13, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpop.S b/isa/rv64uzbb/cpop.S new file mode 100644 index 000000000..0083a1ad4 --- /dev/null +++ b/isa/rv64uzbb/cpop.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpop.S +#----------------------------------------------------------------------------- +# +# Test cpop instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpop, 0, 0x0000000000000000); + TEST_R_OP( 3, cpop, 1, 0x0000000000000001); + TEST_R_OP( 4, cpop, 2, 0x0000000000000003); + + TEST_R_OP( 5, cpop, 49, 0xffffffffffff8000 ); + TEST_R_OP( 6, cpop, 1, 0x0000000000800000 ); + TEST_R_OP( 7, cpop, 34, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, cpop, 15, 0x0000000000007fff); + TEST_R_OP( 9, cpop, 31, 0x000000007fffffff); + TEST_R_OP( 10, cpop, 19, 0x000000000007ffff ); + + TEST_R_OP( 11, cpop, 33, 0xffffffff80000000); + TEST_R_OP( 12, cpop, 27, 0x00ff578f121f5000); + + TEST_R_OP( 13, cpop, 1, 0x8000000000000000); + TEST_R_OP( 14, cpop, 3, 0x000000000000000e); + TEST_R_OP( 15, cpop, 11, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpop, 8, 0x00000000007f8000 ); + TEST_R_OP( 22, cpop, 2, 0x0000000000808000 ); + TEST_R_OP( 23, cpop, 3, 0x0000000001808000 ); + + TEST_R_OP( 24, cpop, 17, 0x0000000300007fff); + TEST_R_OP( 25, cpop, 34, 0x000000077fffffff); + TEST_R_OP( 26, cpop, 23, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/cpopw.S b/isa/rv64uzbb/cpopw.S new file mode 100644 index 000000000..7b73882d7 --- /dev/null +++ b/isa/rv64uzbb/cpopw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# cpopw.S +#----------------------------------------------------------------------------- +# +# Test cpopw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, cpopw, 0, 0x00000000); + TEST_R_OP( 3, cpopw, 1, 0x00000001); + TEST_R_OP( 4, cpopw, 2, 0x00000003); + + TEST_R_OP( 5, cpopw, 17, 0xffff8000 ); + TEST_R_OP( 6, cpopw, 1, 0x00800000 ); + TEST_R_OP( 7, cpopw, 18, 0xffff6000 ); + + TEST_R_OP( 8, cpopw, 15, 0x00007fff); + TEST_R_OP( 9, cpopw, 31, 0x7fffffff); + TEST_R_OP( 10, cpopw, 19, 0x0007ffff ); + + TEST_R_OP( 11, cpopw, 1, 0x80000000); + TEST_R_OP( 12, cpopw, 9, 0x121f5000); + + TEST_R_OP( 13, cpopw, 0, 0x00000000); + TEST_R_OP( 14, cpopw, 3, 0x0000000e); + TEST_R_OP( 15, cpopw, 7, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, cpopw, 3, 13); + TEST_R_SRC1_EQ_DEST( 17, cpopw, 3, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, cpopw, 3, 13); + TEST_R_DEST_BYPASS( 29, 1, cpopw, 3, 19); + TEST_R_DEST_BYPASS( 20, 2, cpopw, 2, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, cpopw, 8, 0x007f8000 ); + TEST_R_OP( 22, cpopw, 2, 0x00808000 ); + TEST_R_OP( 23, cpopw, 3, 0x01808000 ); + + TEST_R_OP( 24, cpopw, 17, 0x30007fff); + TEST_R_OP( 25, cpopw, 30, 0x77ffffff); + TEST_R_OP( 26, cpopw, 19, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctz.S b/isa/rv64uzbb/ctz.S new file mode 100644 index 000000000..21b2426ee --- /dev/null +++ b/isa/rv64uzbb/ctz.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctz.S +#----------------------------------------------------------------------------- +# +# Test ctz instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctz, 64, 0x0000000000000000); + TEST_R_OP( 3, ctz, 0, 0x0000000000000001); + TEST_R_OP( 4, ctz, 0, 0x0000000000000003); + + TEST_R_OP( 5, ctz, 15, 0xffffffffffff8000 ); + TEST_R_OP( 6, ctz, 23, 0x0000000000800000 ); + TEST_R_OP( 7, ctz, 15, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, ctz, 0, 0x0000000000007fff); + TEST_R_OP( 9, ctz, 0, 0x000000007fffffff); + TEST_R_OP( 10, ctz, 0, 0x000000000007ffff ); + + TEST_R_OP( 11, ctz, 31, 0xffffffff80000000); + TEST_R_OP( 12, ctz, 12, 0x00ff578f121f5000); + + TEST_R_OP( 13, ctz, 63, 0x8000000000000000); + TEST_R_OP( 14, ctz, 1, 0x000000000000000e); + TEST_R_OP( 15, ctz, 0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctz, 15, 0x00000000007f8000 ); + TEST_R_OP( 22, ctz, 15, 0x0000000000808000 ); + TEST_R_OP( 23, ctz, 12, 0x0000000001809000 ); + + TEST_R_OP( 24, ctz, 0, 0x0000000300007fff); + TEST_R_OP( 25, ctz, 0, 0x000000077fffffff); + TEST_R_OP( 26, ctz, 0, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ctzw.S b/isa/rv64uzbb/ctzw.S new file mode 100644 index 000000000..9915bf13b --- /dev/null +++ b/isa/rv64uzbb/ctzw.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ctzw.S +#----------------------------------------------------------------------------- +# +# Test ctzw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, ctzw, 32, 0x00000000); + TEST_R_OP( 3, ctzw, 0, 0x00000001); + TEST_R_OP( 4, ctzw, 0, 0x00000003); + + TEST_R_OP( 5, ctzw, 15, 0xffff8000 ); + TEST_R_OP( 6, ctzw, 23, 0x00800000 ); + TEST_R_OP( 7, ctzw, 15, 0xffff8000 ); + + TEST_R_OP( 8, ctzw, 0, 0x00007fff); + TEST_R_OP( 9, ctzw, 0, 0x7fffffff); + TEST_R_OP( 10, ctzw, 0, 0x0007ffff ); + + TEST_R_OP( 11, ctzw, 31, 0x80000000); + TEST_R_OP( 12, ctzw, 12, 0x121f5000); + + TEST_R_OP( 13, ctzw, 30, 0xc0000000); + TEST_R_OP( 14, ctzw, 1, 0x0000000e); + TEST_R_OP( 15, ctzw, 0, 0x20401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, ctzw, 0, 13); + TEST_R_SRC1_EQ_DEST( 17, ctzw, 0, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, ctzw, 0, 13); + TEST_R_DEST_BYPASS( 29, 1, ctzw, 0, 19); + TEST_R_DEST_BYPASS( 20, 2, ctzw, 1, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, ctzw, 15, 0x007f8000 ); + TEST_R_OP( 22, ctzw, 15, 0x00808000 ); + TEST_R_OP( 23, ctzw, 12, 0x01809000 ); + + TEST_R_OP( 24, ctzw, 0, 0x00007fff); + TEST_R_OP( 25, ctzw, 0, 0x7fffffff); + TEST_R_OP( 26, ctzw, 0, 0x0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/max.S b/isa/rv64uzbb/max.S new file mode 100644 index 000000000..92eb9ade8 --- /dev/null +++ b/isa/rv64uzbb/max.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# max.S +#----------------------------------------------------------------------------- +# +# Test max instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, max, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, max, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, max, 0x0000000000000007, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, max, 0x0000000000000007, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, max, 0x0000000000000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, max, 0xffffffffffff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, max, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, max, 0x0000000000007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, max, 0x000000007fffffff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, max, 0x0000000000000001, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, max, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, max, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, max, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, max, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, max, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, max, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, max, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, max, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, max, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, max, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, max, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, max, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, max, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, max, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, max, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, max, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, max, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, max, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, max, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, max, 0, -1 ); + TEST_RR_ZEROSRC2( 36, max, 0, -1 ); + TEST_RR_ZEROSRC12( 37, max, 0 ); + TEST_RR_ZERODEST( 38, max, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/maxu.S b/isa/rv64uzbb/maxu.S new file mode 100644 index 000000000..78c20555d --- /dev/null +++ b/isa/rv64uzbb/maxu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# maxu.S +#----------------------------------------------------------------------------- +# +# Test maxu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, maxu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, maxu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, maxu, 0x00000007, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, maxu, 0x00000007, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, maxu, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, maxu, 0x80000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, maxu, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, maxu, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, maxu, 0x7fffffff, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, maxu, 0x7fffffff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, maxu, 0x80000000, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, maxu, 0xffff8000, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, maxu, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, maxu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, maxu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, maxu, 14, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, maxu, 13, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, maxu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, maxu, 13, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, maxu, 14, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, maxu, 13, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, maxu, 14, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, maxu, 13, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, maxu, 15, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, maxu, 13, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, maxu, 16, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, maxu, 13, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, maxu, 17, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, maxu, 13, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, maxu, 18, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, maxu, 13, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, maxu, 19, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, maxu, 13, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, maxu, -1, -1 ); + TEST_RR_ZEROSRC2( 36, maxu, -1, -1 ); + TEST_RR_ZEROSRC12( 37, maxu, 0 ); + TEST_RR_ZERODEST( 38, maxu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/min.S b/isa/rv64uzbb/min.S new file mode 100644 index 000000000..d2e3e29a8 --- /dev/null +++ b/isa/rv64uzbb/min.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# min.S +#----------------------------------------------------------------------------- +# +# Test min instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, min, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, min, 0x0000000000000003, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, min, 0x0000000000000003, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, min, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, min, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, min, 0x0000000000000000, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, min, 0x0000000000007fff, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, min, 0xffffffffffff8000, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, min, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, min, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, min, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, min, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, min, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, min, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, min, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, min, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, min, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, min, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, min, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, min, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, min, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, min, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, min, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, min, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, min, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, min, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, min, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, min, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, min, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, min, -1, -1 ); + TEST_RR_ZEROSRC2( 36, min, -1, -1 ); + TEST_RR_ZEROSRC12( 37, min, 0 ); + TEST_RR_ZERODEST( 38, min, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/minu.S b/isa/rv64uzbb/minu.S new file mode 100644 index 000000000..f92859a6e --- /dev/null +++ b/isa/rv64uzbb/minu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# minu.S +#----------------------------------------------------------------------------- +# +# Test minu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, minu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, minu, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, minu, 0x00000003, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, minu, 0x00000003, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, minu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, minu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, minu, 0x80000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, minu, 0x00000000, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, minu, 0x00000000, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, minu, 0x00007fff, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, minu, 0x00007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, minu, 0x7fffffff, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, minu, 0x00000000, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, minu, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, minu, 0xffffffff, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, minu, 13, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, minu, 11, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, minu, 13, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, minu, 11, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, minu, 13, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, minu, 12, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, minu, 13, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, minu, 11, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, minu, 13, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, minu, 10, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, minu, 13, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, minu, 9, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, minu, 13, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, minu, 8, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, minu, 13, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, minu, 7, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, minu, 13, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, minu, 6, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, minu, 0, -1 ); + TEST_RR_ZEROSRC2( 36, minu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, minu, 0 ); + TEST_RR_ZERODEST( 38, minu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orc_b.S b/isa/rv64uzbb/orc_b.S new file mode 100644 index 000000000..b236bd38b --- /dev/null +++ b/isa/rv64uzbb/orc_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orc.b.S +#----------------------------------------------------------------------------- +# +# Test orc.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, orc.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, orc.b, 0x00000000000000ff, 0x0000000000000001); + TEST_R_OP( 4, orc.b, 0x00000000000000ff, 0x0000000000000003); + + TEST_R_OP( 5, orc.b, 0xffffffffffffff00, 0xffffffffffff8000 ); + TEST_R_OP( 6, orc.b, 0x0000000000ff0000, 0x0000000000800000 ); + TEST_R_OP( 7, orc.b, 0x00ffffffffffff00, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, orc.b, 0x000000000000ffff, 0x0000000000007fff); + TEST_R_OP( 9, orc.b, 0x00000000ffffffff, 0x000000007fffffff); + TEST_R_OP( 10, orc.b, 0x0000000000ffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, orc.b, 0xffffffffff000000, 0xffffffff80000000); + TEST_R_OP( 12, orc.b, 0x00ffffffffffff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, orc.b, 0xff00000000000000, 0x8000000000000000); + TEST_R_OP( 14, orc.b, 0x00000000000000ff, 0x000000000000000e); + TEST_R_OP( 15, orc.b, 0xff0000ffffffffff, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13); + TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13); + TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19); + TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, orc.b, 0x0000000000ffff00, 0x00000000007f8000 ); + TEST_R_OP( 22, orc.b, 0x0000000000ffff00, 0x0000000000808000 ); + TEST_R_OP( 23, orc.b, 0x00000000ffffff00, 0x0000000001808000 ); + + TEST_R_OP( 24, orc.b, 0x000000ff0000ffff, 0x0000000300007fff); + TEST_R_OP( 25, orc.b, 0x000000ffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, orc.b, 0x000000ff00ffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/orn.S b/isa/rv64uzbb/orn.S new file mode 100644 index 000000000..b61000782 --- /dev/null +++ b/isa/rv64uzbb/orn.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# orn.S +#----------------------------------------------------------------------------- +# +# Test orn instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, orn, 0xffffffffff0fff0f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, orn, 0x0fff0fff0fff0fff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, orn, 0xf0fff0fff0fff0ff, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, orn, 0xff0fff0fff0fff0f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, orn, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, orn, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, orn, -1, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, orn, -1 ); + TEST_RR_ZERODEST( 27, orn, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rev8.S b/isa/rv64uzbb/rev8.S new file mode 100644 index 000000000..5e65f37aa --- /dev/null +++ b/isa/rv64uzbb/rev8.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rev8.S +#----------------------------------------------------------------------------- +# +# Test rev8 instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, rev8, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, rev8, 0x0100000000000000, 0x0000000000000001); + TEST_R_OP( 4, rev8, 0x0300000000000000, 0x0000000000000003); + + TEST_R_OP( 5, rev8, 0x0080ffffffffffff, 0xffffffffffff8000 ); + TEST_R_OP( 6, rev8, 0x0000800000000000, 0x0000000000800000 ); + TEST_R_OP( 7, rev8, 0x0080ffffffff0400, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, rev8, 0xff7f000000000000, 0x0000000000007fff); + TEST_R_OP( 9, rev8, 0xffffff7f00000000, 0x000000007fffffff); + TEST_R_OP( 10, rev8, 0xffff070000000000, 0x000000000007ffff ); + + TEST_R_OP( 11, rev8, 0x00000080ffffffff, 0xffffffff80000000); + TEST_R_OP( 12, rev8, 0x00501f128f57ff00, 0x00ff578f121f5000); + + TEST_R_OP( 13, rev8, 0x0000000000000080, 0x8000000000000000); + TEST_R_OP( 14, rev8, 0x0e00000000000000, 0x000000000000000e); + TEST_R_OP( 15, rev8, 0x41134020030000a0, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d00000000000000, 13); + TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b00000000000000, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d00000000000000, 13); + TEST_R_DEST_BYPASS( 29, 1, rev8, 0x1300000000000000, 19); + TEST_R_DEST_BYPASS( 20, 2, rev8, 0x2200000000000000, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, rev8, 0x00807f0000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, rev8, 0x0080800000000000, 0x0000000000808000 ); + TEST_R_OP( 23, rev8, 0x0080800100000000, 0x0000000001808000 ); + + TEST_R_OP( 24, rev8, 0xff7f000003000000, 0x0000000300007fff); + TEST_R_OP( 25, rev8, 0xffffff7f07000000, 0x000000077fffffff); + TEST_R_OP( 26, rev8, 0xffff07000f000000, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rol.S b/isa/rv64uzbb/rol.S new file mode 100644 index 000000000..a69bc05d6 --- /dev/null +++ b/isa/rv64uzbb/rol.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rol.S +#----------------------------------------------------------------------------- +# +# Test rol instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rol, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rol, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rol, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rol, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rol, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rol, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rol, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rol, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rol, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rol, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rol, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rol, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rol, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rol, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rol, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rol, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, rol, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, rol, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, rol, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, rol, 0x0909080000000109, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rol, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rol, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rol, 0 ); + TEST_RR_ZERODEST( 43, rol, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rolw.S b/isa/rv64uzbb/rolw.S new file mode 100644 index 000000000..fdf467463 --- /dev/null +++ b/isa/rv64uzbb/rolw.S @@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rolw.S +#----------------------------------------------------------------------------- +# +# Test rolw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rolw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rolw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rolw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rolw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rolw, 0xffffffff90909090, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rolw, 0x0000000048484848, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rolw, 0xffffffff90909090, 0x0000000021212121, 31 ); + + # Verify that rotates only use bottom five bits + + TEST_RR_OP( 17, rolw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, rolw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, rolw, 0x0000000048484848, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that rotates ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, rolw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, rolw, 0x0000000023456781, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, rolw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, rolw, 0xffffffff93456789, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rolw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rolw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rolw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rolw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rolw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rolw, 0 ); + TEST_RR_ZERODEST( 43, rolw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/ror.S b/isa/rv64uzbb/ror.S new file mode 100644 index 000000000..163333d97 --- /dev/null +++ b/isa/rv64uzbb/ror.S @@ -0,0 +1,94 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test ror instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, ror, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, ror, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, ror, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, ror, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, ror, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, ror, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, ror, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, ror, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, ror, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, ror, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, ror, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, ror, 0x4242424200000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, ror, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, ror, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, ror, 0x4200000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, ror, 0x8484000000008484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, ror, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, ror, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, ror, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, ror, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, ror, 0x0200000000000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, ror, 0x0004000000000000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, ror, 0x6000000000000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, ror, 0, 15 ); + TEST_RR_ZEROSRC2( 41, ror, 32, 32 ); + TEST_RR_ZEROSRC12( 42, ror, 0 ); + TEST_RR_ZERODEST( 43, ror, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rori.S b/isa/rv64uzbb/rori.S new file mode 100644 index 000000000..153f8e6a2 --- /dev/null +++ b/isa/rv64uzbb/rori.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, rori, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, rori, 0x8000000000000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, rori, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, rori, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, rori, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, rori, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, rori, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, rori, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, rori, 0x8000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, rori, 0x4200000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, rori, 0x8484000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, rori, 0x4242424200000000, 0x0000000021212121, 31 ); + + TEST_IMM_OP( 17, rori, 0x0000000000000002, 0x0000000000000001, 63 ); + TEST_IMM_OP( 18, rori, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 19, rori, 0x0004242424200000, 0x0000000021212121, 43 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x0200000000000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, rori, 0, 31 ); + TEST_IMM_ZERODEST( 28, rori, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/roriw.S b/isa/rv64uzbb/roriw.S new file mode 100644 index 000000000..44f381991 --- /dev/null +++ b/isa/rv64uzbb/roriw.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rori.S +#----------------------------------------------------------------------------- +# +# Test rori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, roriw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, roriw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, roriw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, roriw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, roriw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, roriw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, roriw, 0x0000000042424242, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 20, roriw, 0x0000000002000000, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 21, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 22, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 23, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 24, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 25, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 26, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 27, roriw, 0, 31 ); + TEST_IMM_ZERODEST( 28, roriw, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/rorw.S b/isa/rv64uzbb/rorw.S new file mode 100644 index 000000000..de11c3cb3 --- /dev/null +++ b/isa/rv64uzbb/rorw.S @@ -0,0 +1,91 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rorw.S +#----------------------------------------------------------------------------- +# +# Test rorw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rorw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, rorw, 0xffffffff80000000, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, rorw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, rorw, 0xffffffff90909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, rorw, 0x0000000042424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, rorw, 0xffffffff84848484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, rorw, 0x0000000042424242, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, rorw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, rorw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, rorw, 0xffffffff84848484, 0x0000000021212121, 0xffffffffffffffce ); + + TEST_RR_OP( 21, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, rorw, 0x0000000002000000, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, rorw, 0x0000000000040000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, rorw, 0x0000000060000000, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, rorw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, rorw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, rorw, 0 ); + TEST_RR_ZERODEST( 43, rorw, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_b.S b/isa/rv64uzbb/sext_b.S new file mode 100644 index 000000000..8acf86a0d --- /dev/null +++ b/isa/rv64uzbb/sext_b.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_b.S +#----------------------------------------------------------------------------- +# +# Test sext.b instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.b, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.b, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.b, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.b, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.b, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.b, 0x0000000000000000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.b, 0xffffffffffffffff, 0x0000000000007fff); + TEST_R_OP( 9, sext.b, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.b, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.b, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.b, 0x0000000000000000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.b, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.b, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.b, 0x0000000000000041, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.b, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.b, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.b, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.b, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.b, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.b, 0x0000000000000000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.b, 0x0000000000000000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.b, 0x0000000000000000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.b, 0xffffffffffffffff, 0x0000000300007fff); + TEST_R_OP( 25, sext.b, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.b, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/sext_h.S b/isa/rv64uzbb/sext_h.S new file mode 100644 index 000000000..59cf386a3 --- /dev/null +++ b/isa/rv64uzbb/sext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test sext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, sext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, sext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, sext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, sext.h, 0xffffffffffff8000, 0xffffffffffff8000 ); + TEST_R_OP( 6, sext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, sext.h, 0xffffffffffff8000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, sext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, sext.h, 0xffffffffffffffff, 0x000000007fffffff); + TEST_R_OP( 10, sext.h, 0xffffffffffffffff, 0x000000000007ffff ); + + TEST_R_OP( 11, sext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, sext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, sext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, sext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, sext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, sext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, sext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, sext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, sext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, sext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, sext.h, 0xffffffffffff8000, 0x00000000007f8000 ); + TEST_R_OP( 22, sext.h, 0xffffffffffff8000, 0x0000000000808000 ); + TEST_R_OP( 23, sext.h, 0xffffffffffff8000, 0x0000000001808000 ); + + TEST_R_OP( 24, sext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, sext.h, 0xffffffffffffffff, 0x000000077fffffff); + TEST_R_OP( 26, sext.h, 0xffffffffffffffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/xnor.S b/isa/rv64uzbb/xnor.S new file mode 100644 index 000000000..5a74f8639 --- /dev/null +++ b/isa/rv64uzbb/xnor.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xnor.S +#----------------------------------------------------------------------------- +# +# Test xnor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_OP( 3, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_OP( 4, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_OP( 5, xnor, 0xffffffffff00ff00, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, xnor, 0x00ff00ff00ff00ff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 ); + TEST_RR_OP( 51, xnor, 0xf00ff00ff00ff00f, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f ); + TEST_RR_OP( 52, xnor, 0xff00ff00ff00ff00, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xnor, 0xffffffffffffffff, 0xffffffffff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xnor, 0x0000000000ff00ff, 0xffffffffff00ff00 ); + TEST_RR_ZEROSRC2( 25, xnor, 0xffffffffff00ff00, 0x0000000000ff00ff ); + TEST_RR_ZEROSRC12( 26, xnor, -1 ); + TEST_RR_ZERODEST( 27, xnor, 0x0000000011111111, 0x0000000022222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbb/zext_h.S b/isa/rv64uzbb/zext_h.S new file mode 100644 index 000000000..baa0b7afa --- /dev/null +++ b/isa/rv64uzbb/zext_h.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sext_h.S +#----------------------------------------------------------------------------- +# +# Test zext.h instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_R_OP( 2, zext.h, 0x0000000000000000, 0x0000000000000000); + TEST_R_OP( 3, zext.h, 0x0000000000000001, 0x0000000000000001); + TEST_R_OP( 4, zext.h, 0x0000000000000003, 0x0000000000000003); + + TEST_R_OP( 5, zext.h, 0x0000000000008000, 0xffffffffffff8000 ); + TEST_R_OP( 6, zext.h, 0x0000000000000000, 0x0000000000800000 ); + TEST_R_OP( 7, zext.h, 0x0000000000008000, 0x0004ffffffff8000 ); + + TEST_R_OP( 8, zext.h, 0x0000000000007fff, 0x0000000000007fff); + TEST_R_OP( 9, zext.h, 0x000000000000ffff, 0x000000007fffffff); + TEST_R_OP( 10, zext.h, 0x000000000000ffff, 0x000000000007ffff ); + + TEST_R_OP( 11, zext.h, 0x0000000000000000, 0xffffffff80000000); + TEST_R_OP( 12, zext.h, 0x0000000000005000, 0x00ff578f121f5000); + + TEST_R_OP( 13, zext.h, 0x0000000000000000, 0x8000000000000000); + TEST_R_OP( 14, zext.h, 0x000000000000000e, 0x000000000000000e); + TEST_R_OP( 15, zext.h, 0x0000000000001341, 0xa000000320401341); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_R_SRC1_EQ_DEST( 16, zext.h, 0x000000000000000d, 13); + TEST_R_SRC1_EQ_DEST( 17, zext.h, 0x000000000000000b, 11); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_R_DEST_BYPASS( 18, 0, zext.h, 0x000000000000000d, 13); + TEST_R_DEST_BYPASS( 29, 1, zext.h, 0x0000000000000013, 19); + TEST_R_DEST_BYPASS( 20, 2, zext.h, 0x0000000000000022, 34); + + #------------------------------------------------------------- + # Other tests + #------------------------------------------------------------- + + TEST_R_OP( 21, zext.h, 0x0000000000008000, 0x00000000007f8000 ); + TEST_R_OP( 22, zext.h, 0x0000000000008000, 0x0000000000808000 ); + TEST_R_OP( 23, zext.h, 0x0000000000008000, 0x0000000001808000 ); + + TEST_R_OP( 24, zext.h, 0x0000000000007fff, 0x0000000300007fff); + TEST_R_OP( 25, zext.h, 0x000000000000ffff, 0x000000077fffffff); + TEST_R_OP( 26, zext.h, 0x000000000000ffff, 0x0000000f0007ffff); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END From 879cb3ccf7672f537cefece890c85e8cc913c0ea Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 19 Feb 2024 11:32:24 +0800 Subject: [PATCH 41/68] Add zbc test cases Signed-off-by: Roger Chang --- isa/Makefile | 8 +++-- isa/rv32uzbc/Makefrag | 14 ++++++++ isa/rv32uzbc/clmul.S | 84 +++++++++++++++++++++++++++++++++++++++++++ isa/rv32uzbc/clmulh.S | 84 +++++++++++++++++++++++++++++++++++++++++++ isa/rv32uzbc/clmulr.S | 84 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbc/Makefrag | 14 ++++++++ isa/rv64uzbc/clmul.S | 78 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbc/clmulh.S | 78 ++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbc/clmulr.S | 78 ++++++++++++++++++++++++++++++++++++++++ 9 files changed, 520 insertions(+), 2 deletions(-) create mode 100644 isa/rv32uzbc/Makefrag create mode 100644 isa/rv32uzbc/clmul.S create mode 100644 isa/rv32uzbc/clmulh.S create mode 100644 isa/rv32uzbc/clmulr.S create mode 100644 isa/rv64uzbc/Makefrag create mode 100644 isa/rv64uzbc/clmul.S create mode 100644 isa/rv64uzbc/clmulh.S create mode 100644 isa/rv64uzbc/clmulr.S diff --git a/isa/Makefile b/isa/Makefile index 28ae6a668..cb790a005 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -16,6 +16,7 @@ include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag include $(src_dir)/rv64uzbb/Makefrag +include $(src_dir)/rv64uzbc/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -30,6 +31,7 @@ include $(src_dir)/rv32ud/Makefrag include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag include $(src_dir)/rv32uzbb/Makefrag +include $(src_dir)/rv32uzbc/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -54,10 +56,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ define compile_template @@ -92,6 +94,7 @@ $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) $(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -104,6 +107,7 @@ $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) $(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) +$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzbc/Makefrag b/isa/rv32uzbc/Makefrag new file mode 100644 index 000000000..7dcf6d549 --- /dev/null +++ b/isa/rv32uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv32uzbc tests +#----------------------------------------------------------------------- + +rv32uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv32uzbc_p_tests = $(addprefix rv32uzbc-p-, $(rv32uzbc_sc_tests)) +rv32uzbc_v_tests = $(addprefix rv32uzbc-v-, $(rv32uzbc_sc_tests)) +rv32uzbc_ps_tests = $(addprefix rv32uzbc-ps-, $(rv32uzbc_sc_tests)) + +spike_tests += $(rv32uzbc_p_tests) $(rv32uzbc_v_tests) diff --git a/isa/rv32uzbc/clmul.S b/isa/rv32uzbc/clmul.S new file mode 100644 index 000000000..8a5030066 --- /dev/null +++ b/isa/rv32uzbc/clmul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x00005a00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmul, 0x00005b40, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffc324f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmul, 0xfffc324f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmul, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbc/clmulh.S b/isa/rv32uzbc/clmulh.S new file mode 100644 index 000000000..b5fde88c9 --- /dev/null +++ b/isa/rv32uzbc/clmulh.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x00003600, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulh, 0x000036c0, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulh, 0x000133cd, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulh, 0x000133cd, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulh, 0x55550000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulh, 0x55555555, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulh, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulh, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32uzbc/clmulr.S b/isa/rv32uzbc/clmulr.S new file mode 100644 index 000000000..dc255ec49 --- /dev/null +++ b/isa/rv32uzbc/clmulr.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x00006c00, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, clmulr, 0x00006d80, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, clmulr, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xffff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, clmulr, 0x0002679b, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, clmulr, 0x0002679b, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, clmulr, 0xaaaa0000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, clmulr, 0xaaaaaaaa, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, clmulr, 0x00000001, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, clmulr, 0x00000001, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/Makefrag b/isa/rv64uzbc/Makefrag new file mode 100644 index 000000000..01ce4e211 --- /dev/null +++ b/isa/rv64uzbc/Makefrag @@ -0,0 +1,14 @@ +#======================================================================= +# Makefrag for rv64uzbc tests +#----------------------------------------------------------------------- + +rv64uzbc_sc_tests = \ + clmul \ + clmulh \ + clmulr \ + +rv64uzbc_p_tests = $(addprefix rv64uzbc-p-, $(rv64uzbc_sc_tests)) +rv64uzbc_v_tests = $(addprefix rv64uzbc-v-, $(rv64uzbc_sc_tests)) +rv64uzbc_ps_tests = $(addprefix rv64uzbc-ps-, $(rv64uzbc_sc_tests)) + +spike_tests += $(rv64uzbc_p_tests) $(rv64uzbc_v_tests) diff --git a/isa/rv64uzbc/clmul.S b/isa/rv64uzbc/clmul.S new file mode 100644 index 000000000..c14779141 --- /dev/null +++ b/isa/rv64uzbc/clmul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmul.S +#----------------------------------------------------------------------------- +# +# Test clmul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmul, 0x0000000000005a00, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmul, 0x0000000000005b40, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmul, 0x5555400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmul, 0xfffffffffffc324f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmul, 0xfffffffffffc324f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmul, 0 ); + TEST_RR_ZERODEST( 29, clmul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/clmulh.S b/isa/rv64uzbc/clmulh.S new file mode 100644 index 000000000..c5eaf65f7 --- /dev/null +++ b/isa/rv64uzbc/clmulh.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulh.S +#----------------------------------------------------------------------------- +# +# Test clmulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulh, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulh, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulh, 0x555555557fffd555, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulh, 0x00000000000133cd, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulh, 0x00000000000133cd, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulh, 0 ); + TEST_RR_ZERODEST( 29, clmulh, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbc/clmulr.S b/isa/rv64uzbc/clmulr.S new file mode 100644 index 000000000..d2f86df59 --- /dev/null +++ b/isa/rv64uzbc/clmulr.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# clmulr.S +#----------------------------------------------------------------------------- +# +# Test clmulr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, clmulr, 0x0000000000002400, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, clmulr, 0x0000000000002480, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, clmulr, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, clmulr, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, clmulr, 0xaaaaaaaaffffaaaa, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, clmulr, 0x000000000002679b, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, clmulr, 0x000000000002679b, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 ); + TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 ); + TEST_RR_ZEROSRC12( 28, clmulr, 0 ); + TEST_RR_ZERODEST( 29, clmulr, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END From 9c06101326cdd451a051bc3e6469b3c76f24d101 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Mon, 19 Feb 2024 11:35:22 +0800 Subject: [PATCH 42/68] Add zbs test cases Signed-off-by: Roger Chang --- isa/Makefile | 8 +++- isa/rv32uzbs/Makefrag | 15 +++++++ isa/rv32uzbs/bclr.S | 7 ++++ isa/rv32uzbs/bclri.S | 7 ++++ isa/rv32uzbs/bext.S | 7 ++++ isa/rv32uzbs/bexti.S | 7 ++++ isa/rv32uzbs/binv.S | 7 ++++ isa/rv32uzbs/binvi.S | 7 ++++ isa/rv32uzbs/bset.S | 7 ++++ isa/rv32uzbs/bseti.S | 7 ++++ isa/rv64uzbs/Makefrag | 15 +++++++ isa/rv64uzbs/bclr.S | 96 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbs/bclri.S | 74 +++++++++++++++++++++++++++++++++ isa/rv64uzbs/bext.S | 96 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbs/bexti.S | 74 +++++++++++++++++++++++++++++++++ isa/rv64uzbs/binv.S | 96 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbs/binvi.S | 75 +++++++++++++++++++++++++++++++++ isa/rv64uzbs/bset.S | 96 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64uzbs/bseti.S | 74 +++++++++++++++++++++++++++++++++ 19 files changed, 773 insertions(+), 2 deletions(-) create mode 100644 isa/rv32uzbs/Makefrag create mode 100644 isa/rv32uzbs/bclr.S create mode 100644 isa/rv32uzbs/bclri.S create mode 100644 isa/rv32uzbs/bext.S create mode 100644 isa/rv32uzbs/bexti.S create mode 100644 isa/rv32uzbs/binv.S create mode 100644 isa/rv32uzbs/binvi.S create mode 100644 isa/rv32uzbs/bset.S create mode 100644 isa/rv32uzbs/bseti.S create mode 100644 isa/rv64uzbs/Makefrag create mode 100644 isa/rv64uzbs/bclr.S create mode 100644 isa/rv64uzbs/bclri.S create mode 100644 isa/rv64uzbs/bext.S create mode 100644 isa/rv64uzbs/bexti.S create mode 100644 isa/rv64uzbs/binv.S create mode 100644 isa/rv64uzbs/binvi.S create mode 100644 isa/rv64uzbs/bset.S create mode 100644 isa/rv64uzbs/bseti.S diff --git a/isa/Makefile b/isa/Makefile index cb790a005..bf85e1f8b 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -17,6 +17,7 @@ include $(src_dir)/rv64uzfh/Makefrag include $(src_dir)/rv64uzba/Makefrag include $(src_dir)/rv64uzbb/Makefrag include $(src_dir)/rv64uzbc/Makefrag +include $(src_dir)/rv64uzbs/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64ssvnapot/Makefrag include $(src_dir)/rv64mi/Makefrag @@ -32,6 +33,7 @@ include $(src_dir)/rv32uzfh/Makefrag include $(src_dir)/rv32uzba/Makefrag include $(src_dir)/rv32uzbb/Makefrag include $(src_dir)/rv32uzbc/Makefrag +include $(src_dir)/rv32uzbs/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -56,10 +58,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@ define compile_template @@ -95,6 +97,7 @@ $(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32)) $(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32)) $(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32)) $(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32)) +$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32)) $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) @@ -108,6 +111,7 @@ $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64)) $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64)) $(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64)) $(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64)) +$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64)) $(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64)) $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64)) diff --git a/isa/rv32uzbs/Makefrag b/isa/rv32uzbs/Makefrag new file mode 100644 index 000000000..7af7c42c3 --- /dev/null +++ b/isa/rv32uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32uzbs tests +#----------------------------------------------------------------------- + +rv32uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv32uzbs_p_tests = $(addprefix rv32uzbs-p-, $(rv32uzbs_sc_tests)) +rv32uzbs_v_tests = $(addprefix rv32uzbs-v-, $(rv32uzbs_sc_tests)) +rv32uzbs_ps_tests = $(addprefix rv32uzbs-ps-, $(rv32uzbs_sc_tests)) + +spike_tests += $(rv32uzbs_p_tests) $(rv32uzbs_v_tests) diff --git a/isa/rv32uzbs/bclr.S b/isa/rv32uzbs/bclr.S new file mode 100644 index 000000000..10f7e50d7 --- /dev/null +++ b/isa/rv32uzbs/bclr.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclr.S" diff --git a/isa/rv32uzbs/bclri.S b/isa/rv32uzbs/bclri.S new file mode 100644 index 000000000..2f709d8a1 --- /dev/null +++ b/isa/rv32uzbs/bclri.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bclri.S" diff --git a/isa/rv32uzbs/bext.S b/isa/rv32uzbs/bext.S new file mode 100644 index 000000000..0f838e5e7 --- /dev/null +++ b/isa/rv32uzbs/bext.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bext.S" diff --git a/isa/rv32uzbs/bexti.S b/isa/rv32uzbs/bexti.S new file mode 100644 index 000000000..91ee2d66a --- /dev/null +++ b/isa/rv32uzbs/bexti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bexti.S" diff --git a/isa/rv32uzbs/binv.S b/isa/rv32uzbs/binv.S new file mode 100644 index 000000000..55ea39b08 --- /dev/null +++ b/isa/rv32uzbs/binv.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binv.S" diff --git a/isa/rv32uzbs/binvi.S b/isa/rv32uzbs/binvi.S new file mode 100644 index 000000000..587436349 --- /dev/null +++ b/isa/rv32uzbs/binvi.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/binvi.S" diff --git a/isa/rv32uzbs/bset.S b/isa/rv32uzbs/bset.S new file mode 100644 index 000000000..4220823c7 --- /dev/null +++ b/isa/rv32uzbs/bset.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bset.S" diff --git a/isa/rv32uzbs/bseti.S b/isa/rv32uzbs/bseti.S new file mode 100644 index 000000000..4a6179e27 --- /dev/null +++ b/isa/rv32uzbs/bseti.S @@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uzbs/bseti.S" diff --git a/isa/rv64uzbs/Makefrag b/isa/rv64uzbs/Makefrag new file mode 100644 index 000000000..3264b4ddf --- /dev/null +++ b/isa/rv64uzbs/Makefrag @@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64uzbs tests +#----------------------------------------------------------------------- + +rv64uzbs_sc_tests = \ + bclr bclri \ + bext bexti \ + binv binvi \ + bset bseti \ + +rv64uzbs_p_tests = $(addprefix rv64uzbs-p-, $(rv64uzbs_sc_tests)) +rv64uzbs_v_tests = $(addprefix rv64uzbs-v-, $(rv64uzbs_sc_tests)) +rv64uzbs_ps_tests = $(addprefix rv64uzbs-ps-, $(rv64uzbs_sc_tests)) + +spike_tests += $(rv64uzbs_p_tests) $(rv64uzbs_v_tests) diff --git a/isa/rv64uzbs/bclr.S b/isa/rv64uzbs/bclr.S new file mode 100644 index 000000000..75d48de14 --- /dev/null +++ b/isa/rv64uzbs/bclr.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclr.S +#----------------------------------------------------------------------------- +# +# Test bclr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bclr, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bclr, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bclr, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bclr, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bclr, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bclr, 0x21212120, 0x21212121, 0 ); + TEST_RR_OP( 13, bclr, 0x21212121, 0x21212121, 1 ); + TEST_RR_OP( 14, bclr, 0x21212121, 0x21212121, 7 ); + TEST_RR_OP( 15, bclr, 0x21210121, 0x21212121, 13 ); + TEST_RR_OP( 16, bclr, 0x04848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bclr, 0x21212120, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bclr, 0x84848484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bclr, 0x4484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bclr, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bclr, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bclr, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bclr, 0x00000001, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bclr, 0x00001551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bclr, 3, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bclr, 0xff00ff00, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bclr, 0xff00fe00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bclr, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bclr, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bclr, 32, 32 ); + TEST_RR_ZEROSRC12( 42, bclr, 0 ); + TEST_RR_ZERODEST( 43, bclr, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bclri.S b/isa/rv64uzbs/bclri.S new file mode 100644 index 000000000..3d4fdf9b8 --- /dev/null +++ b/isa/rv64uzbs/bclri.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bclri.S +#----------------------------------------------------------------------------- +# +# Test bclri instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bclri, 0xff00ff00, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bclri, 0x00ff00fd, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bclri, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bclri, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bclri, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bclri, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bclri, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bclri, 0x21212120, 0x21212121, 0 ); + TEST_IMM_OP( 13, bclri, 0x21212121, 0x21212121, 1 ); + TEST_IMM_OP( 14, bclri, 0x21212121, 0x21212121, 7 ); + TEST_IMM_OP( 15, bclri, 0x21210121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bclri, 0x04848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bclri, 0x0000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bclri, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bclri, 0xfffff7ff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bclri, 0x00000001, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bclri, 0xff00fe00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bclri, 0, 31 ); + TEST_IMM_ZERODEST( 25, bclri, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bext.S b/isa/rv64uzbs/bext.S new file mode 100644 index 000000000..044074150 --- /dev/null +++ b/isa/rv64uzbs/bext.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bext.S +#----------------------------------------------------------------------------- +# +# Test bext instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bext, 0, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bext, 1, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bext, 1, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, bext, 1, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, bext, 1, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, bext, 1, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, bext, 1, 0xffffffffffffffff, 27 ); + + TEST_RR_OP( 12, bext, 1, 0x21212121, 0 ); + TEST_RR_OP( 13, bext, 0, 0x21212121, 1 ); + TEST_RR_OP( 14, bext, 0, 0x21212121, 7 ); + TEST_RR_OP( 15, bext, 1, 0x21212121, 13 ); + TEST_RR_OP( 16, bext, 1, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bext, 1, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bext, 0, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bext, 0, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bext, 0, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bext, 1, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bext, 0, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bext, 1, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bext, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bext, 0, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bext, 1, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bext, 0, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bext, 0, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bext, 1, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bext, 1, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bext, 1, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bext, 1, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bext, 0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bext, 1, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bext, 0, 15 ); + TEST_RR_ZEROSRC2( 41, bext, 0, 32 ); + TEST_RR_ZEROSRC12( 42, bext, 0 ); + TEST_RR_ZERODEST( 43, bext, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bexti.S b/isa/rv64uzbs/bexti.S new file mode 100644 index 000000000..19c9ed501 --- /dev/null +++ b/isa/rv64uzbs/bexti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bexti.S +#----------------------------------------------------------------------------- +# +# Test bexti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bexti, 0, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bexti, 1, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bexti, 1, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, bexti, 1, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, bexti, 1, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, bexti, 1, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, bexti, 1, 0xffffffffffffffff, 27 ); + + TEST_IMM_OP( 12, bexti, 1, 0x21212121, 0 ); + TEST_IMM_OP( 13, bexti, 0, 0x21212121, 1 ); + TEST_IMM_OP( 14, bexti, 0, 0x21212121, 7 ); + TEST_IMM_OP( 15, bexti, 1, 0x21212121, 13 ); + TEST_IMM_OP( 16, bexti, 1, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bexti, 0, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bexti, 1, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bexti, 1, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bexti, 0, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_DEST_BYPASS( 19, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bexti, 1, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bexti, 0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bexti, 1, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bexti, 0, 31 ); + TEST_IMM_ZERODEST( 25, bexti, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binv.S b/isa/rv64uzbs/binv.S new file mode 100644 index 000000000..853b39828 --- /dev/null +++ b/isa/rv64uzbs/binv.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binv.S +#----------------------------------------------------------------------------- +# +# Test binv instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, binv, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, binv, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, binv, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, binv, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, binv, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, binv, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, binv, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, binv, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, binv, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, binv, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, binv, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, binv, 0x00000000a1212121, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, binv, 0x0000000021212120, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, binv, 0x0000000021212123, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, binv, 0x00000000212121a1, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, binv, 0x0000000021216121, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, binv, 0x8000000021212121, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, binv, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, binv, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, binv, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, binv, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, binv, 0x00004001, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, binv, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, binv, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, binv, 33, 32 ); + TEST_RR_ZEROSRC12( 42, binv, 1 ); + TEST_RR_ZERODEST( 43, binv, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/binvi.S b/isa/rv64uzbs/binvi.S new file mode 100644 index 000000000..07af1f4fe --- /dev/null +++ b/isa/rv64uzbs/binvi.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# binvi.S +#----------------------------------------------------------------------------- +# +# Test binvi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, binvi, 0x0000000000000000, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, binvi, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, binvi, 0xfffffffffffffffe, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, binvi, 0xfffffffffffffffd, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, binvi, 0xffffffffffffff7f, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, binvi, 0xffffffffffffbfff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, binvi, 0xffffffff7fffffff, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, binvi, 0x0000000021212120, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, binvi, 0x0000000021212123, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, binvi, 0x00000000212121a1, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, binvi, 0x0000000021216121, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, binvi, 0x00000000a1212121, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, binvi, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, binvi, 0xffffff7fffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, binvi, 0x0000080021212121, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, binvi, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 ); + + + TEST_IMM_ZEROSRC1( 24, binvi, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, binvi, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bset.S b/isa/rv64uzbs/bset.S new file mode 100644 index 000000000..ee80b60e7 --- /dev/null +++ b/isa/rv64uzbs/bset.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_RR_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_RR_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_RR_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_RR_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_RR_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_RR_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_RR_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_RR_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + + # Verify that shifts only use bottom six(rv64) or five(rv32) bits + + TEST_RR_OP( 17, bset, 0x21212121, 0x21212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, bset, 0x21212123, 0x21212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, bset, 0x212121a1, 0x21212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, bset, 0x8484c484, 0x84848484, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, bset, 0xc484848421212121, 0xc484848421212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, bset, 0x00000081, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, bset, 0x00005551, 0x00005551, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, bset, 11, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_DEST_BYPASS( 26, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_DEST_BYPASS( 27, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_RR_ZEROSRC1( 40, bset, 0x00008000, 15 ); + TEST_RR_ZEROSRC2( 41, bset, 33, 32 ); + TEST_RR_ZEROSRC12( 42, bset, 1 ); + TEST_RR_ZERODEST( 43, bset, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uzbs/bseti.S b/isa/rv64uzbs/bseti.S new file mode 100644 index 000000000..35a55017e --- /dev/null +++ b/isa/rv64uzbs/bseti.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bset.S +#----------------------------------------------------------------------------- +# +# Test bset instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 ); + TEST_IMM_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 ); + TEST_IMM_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 ); + TEST_IMM_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 12, bset, 0x21212121, 0x21212121, 0 ); + TEST_IMM_OP( 13, bset, 0x21212123, 0x21212121, 1 ); + TEST_IMM_OP( 14, bset, 0x212121a1, 0x21212121, 7 ); + TEST_IMM_OP( 15, bset, 0x21212121, 0x21212121, 13 ); + TEST_IMM_OP( 16, bset, 0x84848484, 0x84848484, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, bset, 0x00000081, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, bset, 0xff00ff01, 0xff00ff00, 0 ); + TEST_IMM_DEST_BYPASS( 19, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 ); + TEST_IMM_DEST_BYPASS( 20, 2, bset, 0xff00ff00, 0xff00ff00, 8 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, bset, 0xff00ff00, 0xff00ff00, 8 ); + TEST_IMM_SRC1_BYPASS( 22, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 ); + + TEST_IMM_ZEROSRC1( 24, bset, 0x00008000, 15 ); + TEST_IMM_ZERODEST( 25, bset, 1024, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END From 36b18c8e4ea7bdcd30aed03c5d6235fbb0f8213c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 18 Feb 2024 20:16:38 -0800 Subject: [PATCH 43/68] Fix breakpoint test See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 --- isa/rv64mi/breakpoint.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 1223f7105..153963a71 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -26,6 +26,9 @@ RVTEST_CODE_BEGIN 1: csrw mtvec, a0 + # Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214 + csrsi mstatus, MSTATUS_MIE + # Skip tselect if hard-wired. csrw tselect, x0 csrr a1, tselect From fafa5bb5f12521d8e964465b54fa0d261c05ce3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=A2=81=E9=95=87?= Date: Tue, 5 Mar 2024 11:22:42 +0800 Subject: [PATCH 44/68] Fix CI debug test using ubuntu-20.04 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: 梁镇 Change-Id: I4657a0417b79d515655f6ad4a5ba4465ca58061f --- .github/workflows/spike-openocd-tests.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/spike-openocd-tests.yml b/.github/workflows/spike-openocd-tests.yml index 3f1d93bb4..577bd9511 100644 --- a/.github/workflows/spike-openocd-tests.yml +++ b/.github/workflows/spike-openocd-tests.yml @@ -34,7 +34,7 @@ on: jobs: test: name: Test debug (Ubuntu) - runs-on: ubuntu-latest + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v3 with: From fd01e46314636666b5bed1f08465f734751a4cda Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 19 Mar 2024 14:14:31 -0700 Subject: [PATCH 45/68] ma_addr: permit access faults in lieu of misaligned exceptions --- isa/rv64mi/ma_addr.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index f02a1afc3..8579c016a 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -20,6 +20,7 @@ RVTEST_CODE_BEGIN # indicate it's a load test li s1, CAUSE_MISALIGNED_LOAD + li s2, CAUSE_LOAD_ACCESS #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) @@ -56,6 +57,7 @@ RVTEST_CODE_BEGIN # indicate it's a store test li s1, CAUSE_MISALIGNED_STORE + li s2, CAUSE_STORE_ACCESS /* Check that a misaligned store has some effect and takes no exception, or takes no effect and generates an exception. This is not very @@ -96,7 +98,10 @@ RVTEST_CODE_BEGIN .global mtvec_handler mtvec_handler: csrr t0, mcause - bne t0, s1, fail + beq t0, s1, 1f + beq t0, s2, 1f + j fail +1: csrr t0, mbadaddr beqz t0, 1f From 7f454c3d8aefb1d90727a3db7f13ac691640a575 Mon Sep 17 00:00:00 2001 From: zilong Date: Wed, 17 Apr 2024 11:25:09 +0800 Subject: [PATCH 46/68] debug: Fix nonexistent trigger registers trap handle in entry.S --- debug/programs/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 09cad53d6..5c281a6d4 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -84,8 +84,9 @@ handle_reset: beq t0, t1, 1b .p2align 2 2: - # Restore mtvec + # Restore mtvec and mstatus csrw mtvec, t2 + csrwi mstatus, 0 #ifdef MULTICORE csrr t0, CSR_MHARTID From 1dde0ef3bee0d3f86c6f41796f28625924dc6ba0 Mon Sep 17 00:00:00 2001 From: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Date: Wed, 1 May 2024 23:09:09 +0300 Subject: [PATCH 47/68] [debug tests] increase remotetimeout for all spike-based targets (#553) Spike simulator is very demanding to CPU resources. This causes debug tests to sporadically fail on slower machines. Increasing of gdb's `remotetimeout` should get rid of such failures, unless we run the testsuite on a potato. The only downside is that if OpenOCD is broken, tests can run longer. However, I think this is the sacrifice we can make, since execution time is not affected if everything works as expected. --- debug/targets/RISC-V/spike-multi.py | 2 +- debug/targets/RISC-V/spike32-2-hwthread.py | 2 +- debug/targets/RISC-V/spike32-2.py | 2 +- debug/targets/RISC-V/spike32.py | 2 +- debug/targets/RISC-V/spike64-2-hwthread.py | 4 +--- debug/targets/RISC-V/spike64-2-rtos.py | 2 +- debug/targets/RISC-V/spike64-2.py | 2 +- debug/targets/RISC-V/spike64.py | 2 +- 8 files changed, 8 insertions(+), 10 deletions(-) diff --git a/debug/targets/RISC-V/spike-multi.py b/debug/targets/RISC-V/spike-multi.py index 02be76373..19f8d6cb8 100644 --- a/debug/targets/RISC-V/spike-multi.py +++ b/debug/targets/RISC-V/spike-multi.py @@ -11,7 +11,7 @@ class multispike(targets.Target): spike64.spike64_hart(misa=0x8000000000341129, system=1), spike64.spike64_hart(misa=0x8000000000341129, system=1)] openocd_config_path = "spike-multi.cfg" - timeout_sec = 30 + timeout_sec = 180 server_timeout_sec = 120 implements_custom_test = True support_hasel = False diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py index b617be24b..3be3332d4 100644 --- a/debug/targets/RISC-V/spike32-2-hwthread.py +++ b/debug/targets/RISC-V/spike32-2-hwthread.py @@ -7,7 +7,7 @@ class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40341129), spike32.spike32_hart(misa=0x40341129)] openocd_config_path = "spike-2-hwthread.cfg" - timeout_sec = 5 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # not supported without sba support_unavailable_control = True diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index 1d0cc48f4..0d5f19e8e 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -7,7 +7,7 @@ class spike32_2(targets.Target): harts = [spike32.spike32_hart(misa=0x40141125), spike32.spike32_hart(misa=0x40141125)] openocd_config_path = "spike-2.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True support_unavailable_control = True diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py index f0afd88ba..a196792ff 100644 --- a/debug/targets/RISC-V/spike32.py +++ b/debug/targets/RISC-V/spike32.py @@ -13,7 +13,7 @@ class spike32_hart(targets.Hart): class spike32(targets.Target): harts = [spike32_hart(misa=0x4034112d)] openocd_config_path = "spike-1.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # Needs SBA freertos_binary = "bin/RTOSDemo32.axf" diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py index d1d2bf7dd..4d6e4ba60 100644 --- a/debug/targets/RISC-V/spike64-2-hwthread.py +++ b/debug/targets/RISC-V/spike64-2-hwthread.py @@ -7,9 +7,7 @@ class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000341129), spike64.spike64_hart(misa=0x8000000000341129)] openocd_config_path = "spike-2-hwthread.cfg" - # Increased timeout because we use abstract_rti to artificially slow things - # down. - timeout_sec = 20 + timeout_sec = 180 implements_custom_test = True support_hasel = False support_memory_sampling = False # Needs SBA diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py index f4de8b8e8..0b8739103 100644 --- a/debug/targets/RISC-V/spike64-2-rtos.py +++ b/debug/targets/RISC-V/spike64-2-rtos.py @@ -7,7 +7,7 @@ class spike64_2_rtos(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] openocd_config_path = "spike-rtos.cfg" - timeout_sec = 60 + timeout_sec = 180 implements_custom_test = True support_hasel = False test_semihosting = False diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index e4c7524fa..ea31636ab 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -7,7 +7,7 @@ class spike64_2(targets.Target): harts = [spike64.spike64_hart(misa=0x8000000000141129), spike64.spike64_hart(misa=0x8000000000141129)] openocd_config_path = "spike-2.cfg" - timeout_sec = 5 + timeout_sec = 180 implements_custom_test = True support_memory_sampling = False # Needs SBA support_unavailable_control = True diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 8f5ba4f4b..5616977bf 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -14,7 +14,7 @@ class spike64_hart(targets.Hart): class spike64(targets.Target): harts = [spike64_hart()] openocd_config_path = "spike-1.cfg" - timeout_sec = 30 + timeout_sec = 180 implements_custom_test = True freertos_binary = "bin/RTOSDemo64.axf" support_unavailable_control = True From 203362f8719d0eb24ea64b7cf4a7a2ae4ab8796b Mon Sep 17 00:00:00 2001 From: Marek Vrbka Date: Thu, 2 May 2024 15:14:09 +0200 Subject: [PATCH 48/68] debug: Fix loading of empty exclude lists with comments This patch fixes the case when we are using an empty exception list (for example just a YAML file with comments but without any test items to skip). --- debug/testlib.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index 1d3fd1880..d4826bbdc 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1076,12 +1076,16 @@ def __exit__(self, _type, _value, _traceback): def load_excluded_tests(excluded_tests_file, target_name): result = [] - if excluded_tests_file is None or len(excluded_tests_file) == 0: + if excluded_tests_file is None: + # No list of excluded tests was specified return result target_excludes = {} with open(excluded_tests_file, encoding="utf-8") as file: raw_data = yaml.safe_load(file) + if raw_data is None: + # File contains no targets + return result for (target, test_list) in raw_data.items(): if not isinstance(test_list, list): raise ValueError( From db7e451c49fc8a3d45929c832a9b606f5deb7899 Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Tue, 14 May 2024 15:34:31 +0300 Subject: [PATCH 49/68] debug: workaround for sporadic failures of some tests due to unexpected data present in pexpect match Problem was observed on UnavailableMultiTest - this test was sporadically failing. When the failure was observed the log of the failing test looked as follows: ``` File "/whatever/RISCVTests/debug/testlib.py", line 504, in if all(targets[hart.id]["State"] == "running" for hart in harts): ~~~~~~~~~~~~~~~~^^^^^^^^^ KeyError: 'State' ``` Adding this modification to testlib.py ``` --- a/debug/testlib.py +++ b/debug/testlib.py @@ -498,6 +498,10 @@ class Openocd: for line in lines[2:]: if line.strip(): data.append(dict(zip(headers, line.split()[1:]))) + str_data = str(data) + sys.stdout.flush() + sys.stdout.write(f"parsed targets:\n{result}\n===\n{str_data}\n---\n") + sys.stdout.flush() return data ``` Allowed me to root cause the issue. Namely we have the following situation: ``` parsed targets: Exception ignored in: Traceback (most recent call last): File "/usr/local/lib/python3.11/tempfile.py", line 450, in __del__ self.close() File "/usr/local/lib/python3.11/tempfile.py", line 446, in close unlink(self.name) FileNotFoundError: [Errno 2] No such file or directory: '/tmp/gdb@38873-8s6ud03x.log' ... TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0 riscv.cpu0 riscv little riscv.cpu running 1* riscv.cpu1 riscv little riscv.cpu running === [{'Exception': '"/usr/local/lib/python3.11/tempfile.py",', 'ignored': 'line', 'in:': '450,', ... ``` The only reasonable (to me) explanation for the observed behavior is below. Here is how we connect to TCL-RPC server: ``` self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}") tty.setraw(self.openocd_cli.child_fd) ``` Later we request target list by issuing "targets" command: ``` self.command("targets") ``` Internally, pexpect.spawn implemented as follows: - we fork the process - set up pty and then call execve - all these steps are written in python "Exception ignored" messages are result of exceptions thrown from finalizers of NamedTemporaryFile objects. When exception is thrown from the finalizer - python unconditionally prints a "warning" to stderr. It seems that these messages are polluting our output from "nc" since python GC can be invoked before the execve syscall. The workaround is just to make sure that execve was executed before we rely on the format of command output. To have such a guarantee we just issue a dummy "echo" command and check that we have a proper reply in the output stream. While this explanation looks convincing, the behavior above still looks strange, given that we have https://bugs.python.org/issue14548 which was resolved long ago. However, the proposed workaround fixes the issue. --- debug/testlib.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/debug/testlib.py b/debug/testlib.py index d4826bbdc..1f107be3f 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -367,10 +367,15 @@ def __init__(self, server_cmd=None, config=None, debug=False, timeout=60, self.tclrpc_port = None self.start(cmd, logfile, extra_env) - self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}") + self.openocd_cli = pexpect.spawn(f"nc localhost {self.tclrpc_port}", + echo=False) # TCL-RPC uses \x1a as a watermark for end of message. We set raw # pty mode to disable translation of \x1a to EOF tty.setraw(self.openocd_cli.child_fd) + hello_string = self.command( + "capture { echo \"Hello TCL-RPC!\" }").decode() + if not "Hello TCL-RPC!" in hello_string: + raise RuntimeError(f"TCL-RPC - unexpected reply:\n{hello_string}") def start(self, cmd, logfile, extra_env): combined_env = {**os.environ, **extra_env} From cb357771eb44d9bee4a6ce2925c235a80789a327 Mon Sep 17 00:00:00 2001 From: Parshintsev Anatoly Date: Tue, 14 May 2024 23:46:22 +0300 Subject: [PATCH 50/68] debug: fix sporadic failures of memory sampling tests Memory sampling tests fail sporadically for spike targets. A typical failure looks as follows (ROI from test log): ``` ---------------------------------[ Message ]---------------------------------- 139670831 not less than 124104544 --------------------------------[ Traceback ]--------------------------------- ... SECTION IS SKIPPED FOR READABILITY ... raise TestFailed(f"{a!r} not less than {b!r}", comment) testlib.TestFailed ``` Few observations: - 139670831 is 0x0853352f in hex, while 124104544 is 0x0765af60 - Now, the assert which is failing corresponds to the following expression: ``` assertLess(value, previous_value + tolerance) ``` - tolerance is `0x500000`. (124104544 - 0x500000) is 0x0715af60 If we look at the sampling output for such failing test, we'll see: ``` ... 0x1212340c5c: 0x0715af60 timestamp after: 878087500 timestamp before: 878088133 0x1212340c5c: 0x0853352f ... ``` The log above demonstrates the reason for the failure. Since memory sampling occures every poll (which by default happens approximately every 100ms) a value of the counter may exceed the threshold if the time between subsequent polls is increased (for whatever reason). In my opinion the failing assert can be safely removed, since the checks it perform are quite brittle and cannot be generalized. The assert violation is affected by CPU performance and sporadic delays between polls. For now, instead of assert removal we just avoid checks in-between memory sample bursts. This way we still can be certain that memory samples are frequent enough and hopefully this will avoid sporadic failures. --- debug/gdbserver.py | 1 + 1 file changed, 1 insertion(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index f00dcc973..2cc6c8e9c 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -833,6 +833,7 @@ def check_incrementing_samples(raw_samples, check_addr, first_timestamp = timestamp else: end = (timestamp, total_samples) + previous_value = None else: assertRegex(line, r"^0x[0-f]+: 0x[0-f]+$") address, value = line.split(': ') From 4193bb2998d86e3c46ac957e5186aaaa42be0ff2 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Thu, 23 May 2024 19:05:30 +0300 Subject: [PATCH 51/68] debug: fix HwbpManual test HwbpManual test was broken: * Value read back from `tselect` was compared with `tdata1` value. https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/gdbserver.py#L701-L703 This resulted in the test being reported as not supported, after all the triggers were checked. * `tdata1.type` field was not set to `mcontrol`. * `tselect` value used to be changed by `handle_reset` and not restored. https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/programs/entry.S#L79-L84 * Manual breakpoint used to be left behind. Signed-off-by: Evgeniy Naydanov --- debug/gdbserver.py | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 2cc6c8e9c..ba30b9b4b 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -687,6 +687,8 @@ def test(self): self.gdb.command("delete") #self.gdb.hbreak("rot13") tdata1 = MCONTROL_DMODE(self.hart.xlen) + tdata1 = set_field(tdata1, MCONTROL_TYPE(self.hart.xlen), + MCONTROL_TYPE_MATCH) tdata1 = set_field(tdata1, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE) tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL) tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE @@ -697,20 +699,30 @@ def test(self): value = self.gdb.p("$tselect") if value != tselect: raise TestNotApplicable + # Need to disable the trigger before writing tdata2 + self.gdb.p("$tdata1=0") + # Need to write a valid value to tdata2 before writing tdata1 + self.gdb.p("$tdata2=&rot13") self.gdb.p(f"$tdata1=0x{tdata1:x}") - value = self.gdb.p("$tselect") + value = self.gdb.p("$tdata1") if value == tdata1: break + if value & MCONTROL_TYPE(self.hart.xlen) == MCONTROL_TYPE_NONE: + raise TestNotApplicable self.gdb.p("$tdata1=0") tselect += 1 - self.gdb.p("$tdata2=&rot13") # The breakpoint should be hit exactly 2 times. for _ in range(2): output = self.gdb.c(ops=2) - self.gdb.p("$pc") + assertEqual(self.gdb.p("$pc"), self.gdb.p("&rot13")) assertRegex(output, r"[bB]reakpoint") assertIn("rot13 ", output) + + # Hardware breakpoint are removed by the binary in handle_reset. + # This changes tselect. Therefore GDB needs to restore it. + self.gdb.p(f"$tselect={tselect}") + self.gdb.p("$tdata2=&crc32a") self.gdb.c() before = self.gdb.p("$pc") @@ -719,6 +731,10 @@ def test(self): after = self.gdb.p("$pc") assertNotEqual(before, after) + # Remove the manual HW breakpoint. + assertEqual(tselect, self.gdb.p("$tselect")) + self.gdb.p("$tdata1=0") + self.gdb.b("_exit") self.exit() From fee361fd89edd4ac031a570affde16f4f84414e9 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 30 May 2024 13:21:04 -0700 Subject: [PATCH 52/68] Support basic testing of more Zca instructions By using Zca-friendly registers, we can reuse the existing tests to get quick-and-dirty coverage of Zca, when the assembler is told to use Zca. (This doesn't break non-Zca targets.) --- isa/macros/scalar/test_macros.h | 152 ++++++++++++++++---------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 6c901d0cd..88049eab8 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -45,14 +45,14 @@ test_ ## testnum: \ #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ TEST_CASE( testnum, x14, result, \ - li x1, MASK_XLEN(val1); \ - inst x14, x1, SEXT_IMM(imm); \ + li x13, MASK_XLEN(val1); \ + inst x14, x13, SEXT_IMM(imm); \ ) #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, SEXT_IMM(imm); \ + TEST_CASE( testnum, x11, result, \ + li x11, MASK_XLEN(val1); \ + inst x11, x11, SEXT_IMM(imm); \ ) #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ @@ -123,29 +123,29 @@ test_ ## testnum: \ #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ TEST_CASE( testnum, x14, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x14, x1, x2; \ + li x11, MASK_XLEN(val1); \ + li x12, MASK_XLEN(val2); \ + inst x14, x11, x12; \ ) #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x1, x1, x2; \ + TEST_CASE( testnum, x11, result, \ + li x11, MASK_XLEN(val1); \ + li x12, MASK_XLEN(val2); \ + inst x11, x11, x12; \ ) #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x2, x1, x2; \ + TEST_CASE( testnum, x12, result, \ + li x11, MASK_XLEN(val1); \ + li x12, MASK_XLEN(val2); \ + inst x12, x11, x12; \ ) #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, x1; \ + TEST_CASE( testnum, x11, result, \ + li x11, MASK_XLEN(val1); \ + inst x11, x11, x11; \ ) #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ @@ -218,8 +218,8 @@ test_ ## testnum: \ #define TEST_LD_OP( testnum, inst, result, offset, base ) \ TEST_CASE( testnum, x14, result, \ li x15, result; /* Tell the exception handler the expected result. */ \ - la x1, base; \ - inst x14, offset(x1); \ + la x2, base; \ + inst x14, offset(x2); \ ) #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ @@ -392,9 +392,9 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ la a0, test_ ## testnum ## _data ;\ - flh f0, 0(a0); \ - flh f1, 2(a0); \ - flh f2, 4(a0); \ + flh f10, 0(a0); \ + flh f11, 2(a0); \ + flh f12, 4(a0); \ lh a3, 6(a0); \ code; \ fsflags a1, x0; \ @@ -414,9 +414,9 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ la a0, test_ ## testnum ## _data ;\ - flw f0, 0(a0); \ - flw f1, 4(a0); \ - flw f2, 8(a0); \ + flw f10, 0(a0); \ + flw f11, 4(a0); \ + flw f12, 8(a0); \ lw a3, 12(a0); \ code; \ fsflags a1, x0; \ @@ -436,9 +436,9 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ + fld f10, 0(a0); \ + fld f11, 8(a0); \ + fld f12, 16(a0); \ ld a3, 24(a0); \ code; \ fsflags a1, x0; \ @@ -459,9 +459,9 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ + fld f10, 0(a0); \ + fld f11, 8(a0); \ + fld f12, 16(a0); \ lw a3, 24(a0); \ lw t1, 28(a0); \ code; \ @@ -481,134 +481,134 @@ test_ ## testnum: \ #define TEST_FCVT_S_D32( testnum, result, val1 ) \ TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + fcvt.s.d f13, f10; fcvt.d.s f13, f13; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) #define TEST_FCVT_S_D( testnum, result, val1 ) \ TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) + fcvt.s.d f13, f10; fcvt.d.s f13, f13; fmv.x.d a0, f13) #define TEST_FCVT_D_S( testnum, result, val1 ) \ TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ - fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) + fcvt.d.s f13, f10; fcvt.s.d f13, f13; fmv.x.s a0, f13) #define TEST_FCVT_H_S( testnum, result, val1 ) \ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ - fcvt.s.h f3, f0; fcvt.h.s f3, f3; fmv.x.h a0, f3) + fcvt.s.h f13, f10; fcvt.h.s f13, f13; fmv.x.h a0, f13) #define TEST_FCVT_H_D( testnum, result, val1 ) \ TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, val1, 0.0, 0.0, \ - fcvt.d.h f3, f0; fcvt.h.d f3, f3; fmv.x.h a0, f3) + fcvt.d.h f13, f10; fcvt.h.d f13, f13; fmv.x.h a0, f13) #define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.h a0, f3;) + inst f13, f10; fmv.x.h a0, f13;) #define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) + inst f13, f10; fmv.x.s a0, f13) #define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) // ^: store computation result in address from a0, load high-word into t2 #define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) + inst f13, f10; fmv.x.d a0, f13) #define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) + inst f13, f10; fmv.x.s a0, f13) #define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.h a0, f3) + inst f13, f10; fmv.x.h a0, f13) #define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) // ^: store computation result in address from a0, load high-word into t2 #define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) + inst f13, f10; fmv.x.d a0, f13) #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.s a0, f3) + inst f13, f10, f11; fmv.x.s a0, f13) #define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.h a0, f3) + inst f13, f10, f11; fmv.x.h a0, f13) #define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + inst f13, f10, f11; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) // ^: store computation result in address from a0, load high-word into t2 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.d a0, f3) + inst f13, f10, f11; fmv.x.d a0, f13) #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.s a0, f3) + inst f13, f10, f11, f12; fmv.x.s a0, f13) #define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.h a0, f3) + inst f13, f10, f11, f12; fmv.x.h a0, f13) #define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) + inst f13, f10, f11, f12; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) // ^: store computation result in address from a0, load high-word into t2 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.d a0, f3) + inst f13, f10, f11, f12; fmv.x.d a0, f13) #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) + inst a0, f10, rm) #define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) + inst a0, f10, rm) #define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, f1; li t2, 0) + inst a0, f10, f11; li t2, 0) #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, rm) + inst a0, f10, rm) #define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ - inst a0, f0, f1) + inst a0, f10, f11) #define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, val1, val2, 0.0, \ - inst a0, f0, f1) + inst a0, f10, f11) #define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1; li t2, 0) + inst a0, f10, f11; li t2, 0) #define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1) + inst a0, f10, f11) #define TEST_FCLASS_S(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ - fclass.s a0, fa0) + TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x f10, a0; \ + fclass.s a0, f10) #define TEST_FCLASS_D32(testnum, correct, input) \ TEST_CASE(testnum, a0, correct, \ la a0, test_ ## testnum ## _data ;\ - fld fa0, 0(a0); \ - fclass.d a0, fa0) \ + fld f10, 0(a0); \ + fclass.d a0, f10) \ .pushsection .data; \ .align 3; \ test_ ## testnum ## _data: \ @@ -616,8 +616,8 @@ test_ ## testnum: \ .popsection #define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) + TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x f10, a0; \ + fclass.d a0, f10) #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ test_ ## testnum: \ @@ -625,9 +625,9 @@ test_ ## testnum: \ la a0, test_ ## testnum ## _data ;\ lw a3, 0(a0); \ li a0, val1; \ - inst f0, a0; \ + inst f10, a0; \ fsflags x0; \ - fmv.x.s a0, f0; \ + fmv.x.s a0, f10; \ bne a0, a3, fail; \ .pushsection .data; \ .align 2; \ @@ -641,9 +641,9 @@ test_ ## testnum: \ la a0, test_ ## testnum ## _data ;\ lh a3, 0(a0); \ li a0, val1; \ - inst f0, a0; \ + inst f10, a0; \ fsflags x0; \ - fmv.x.h a0, f0; \ + fmv.x.h a0, f10; \ bne a0, a3, fail; \ .pushsection .data; \ .align 1; \ @@ -658,9 +658,9 @@ test_ ## testnum: \ lw a3, 0(a0); \ lw a4, 4(a0); \ li a1, val1; \ - inst f0, a1; \ + inst f10, a1; \ \ - fsd f0, 0(a0); \ + fsd f10, 0(a0); \ lw a1, 4(a0); \ lw a0, 0(a0); \ \ @@ -679,9 +679,9 @@ test_ ## testnum: \ la a0, test_ ## testnum ## _data ;\ ld a3, 0(a0); \ li a0, val1; \ - inst f0, a0; \ + inst f10, a0; \ fsflags x0; \ - fmv.x.d a0, f0; \ + fmv.x.d a0, f10; \ bne a0, a3, fail; \ .pushsection .data; \ .align 3; \ From 0eb7121a0a07af0e10ecd688609ea4906ae5dbf4 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 30 May 2024 13:38:21 -0700 Subject: [PATCH 53/68] Support more basic testing of Zca instructions Continuation of fee361fd89edd4ac031a570affde16f4f84414e9 --- isa/macros/scalar/test_macros.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 88049eab8..518476cae 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -224,15 +224,15 @@ test_ ## testnum: \ #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ TEST_CASE( testnum, x14, result, \ - la x1, base; \ - li x2, result; \ + la x2, base; \ + li x1, result; \ la x15, 7f; /* Tell the exception handler how to skip this test. */ \ - store_inst x2, offset(x1); \ - load_inst x14, offset(x1); \ + store_inst x1, offset(x2); \ + load_inst x14, offset(x2); \ j 8f; \ 7: \ /* Set up the correct result for TEST_CASE(). */ \ - mv x14, x2; \ + mv x14, x1; \ 8: \ ) @@ -240,8 +240,8 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ -1: la x1, base; \ - inst x14, offset(x1); \ +1: la x13, base; \ + inst x14, offset(x13); \ TEST_INSERT_NOPS_ ## nop_cycles \ addi x6, x14, 0; \ li x7, result; \ @@ -254,9 +254,9 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ -1: la x1, base; \ +1: la x13, base; \ TEST_INSERT_NOPS_ ## nop_cycles \ - inst x14, offset(x1); \ + inst x14, offset(x13); \ li x7, result; \ bne x14, x7, fail; \ addi x4, x4, 1; \ @@ -267,12 +267,12 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ -1: li x1, result; \ +1: li x13, result; \ TEST_INSERT_NOPS_ ## src1_nops \ - la x2, base; \ + la x12, base; \ TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x14, offset(x2); \ + store_inst x13, offset(x12); \ + load_inst x14, offset(x12); \ li x7, result; \ bne x14, x7, fail; \ addi x4, x4, 1; \ From 8853c545d0a44430c8a714d11f18ebad6af7d3fa Mon Sep 17 00:00:00 2001 From: Tommy Murphy Date: Thu, 6 Jun 2024 11:15:36 +0100 Subject: [PATCH 54/68] Suppress 'PRNG seed ...' log messages when --list-tests is specified; see https://github.com/riscv-software-src/riscv-tests/pull/531#issuecomment-2151081139 --- debug/gdbserver.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index ba30b9b4b..16c2b80cf 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -2217,8 +2217,10 @@ def main(): selected_seed = parsed.seed if parsed.seed is None: selected_seed = int(datetime.now().timestamp()) - print(f"PRNG seed for {target.name} is generated automatically") - print(f"PRNG seed for {target.name} is {selected_seed}") + if parsed.list_tests is None: + print(f"PRNG seed for {target.name} is generated automatically") + if parsed.list_tests is None: + print(f"PRNG seed for {target.name} is {selected_seed}") random.seed(selected_seed) return testlib.run_all_tests(module, target, parsed) From d3c0ecaf8629c889726a8deff1f00c4c1405101f Mon Sep 17 00:00:00 2001 From: Tommy Murphy Date: Thu, 6 Jun 2024 19:44:24 +0100 Subject: [PATCH 55/68] Move PRNG seed generation/logging from gdbserver.py:main() into testlib.py:run_all_tests() --- debug/gdbserver.py | 11 ----------- debug/testlib.py | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 16c2b80cf..235814a10 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -11,7 +11,6 @@ import re import itertools -from datetime import datetime import targets import testlib from testlib import assertEqual, assertNotEqual @@ -2213,16 +2212,6 @@ def main(): module = sys.modules[__name__] - # initialize PRNG - selected_seed = parsed.seed - if parsed.seed is None: - selected_seed = int(datetime.now().timestamp()) - if parsed.list_tests is None: - print(f"PRNG seed for {target.name} is generated automatically") - if parsed.list_tests is None: - print(f"PRNG seed for {target.name} is {selected_seed}") - random.seed(selected_seed) - return testlib.run_all_tests(module, target, parsed) # TROUBLESHOOTING TIPS diff --git a/debug/testlib.py b/debug/testlib.py index 1f107be3f..010620340 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -1,6 +1,7 @@ import collections import os import os.path +import random import re import shlex import subprocess @@ -13,6 +14,8 @@ import pexpect import yaml +from datetime import datetime + print_log_names = False real_stdout = sys.stdout @@ -1160,6 +1163,14 @@ def run_all_tests(module, target, parsed): excluded_tests = load_excluded_tests(parsed.exclude_tests, target.name) target.skip_tests += excluded_tests + # initialize PRNG + selected_seed = parsed.seed + if parsed.seed is None: + selected_seed = int(datetime.now().timestamp()) + print(f"PRNG seed for {target.name} is generated automatically") + print(f"PRNG seed for {target.name} is {selected_seed}") + random.seed(selected_seed) + results, count = run_tests(parsed, target, todo) header(f"ran {count} tests in {time.time() - overall_start:.0f}s", dash=':') From 6c1ab378660efe0b7559425df995fb7df39befd3 Mon Sep 17 00:00:00 2001 From: Tommy Murphy Date: Thu, 6 Jun 2024 19:51:06 +0100 Subject: [PATCH 56/68] Fix pylint issues with previous commit changes --- debug/testlib.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/debug/testlib.py b/debug/testlib.py index 010620340..64c70550d 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -10,12 +10,12 @@ import time import traceback +from datetime import datetime + import tty import pexpect import yaml -from datetime import datetime - print_log_names = False real_stdout = sys.stdout @@ -1303,7 +1303,6 @@ def __init__(self, target, hart=None): if not hart is None: self.hart = hart else: - import random # pylint: disable=import-outside-toplevel self.hart = random.choice(target.harts) #self.hart = target.harts[-1] self.server = None From 1d3c10c06e5258711041fde95adefcb1b069aaf6 Mon Sep 17 00:00:00 2001 From: Tommy Murphy Date: Fri, 14 Jun 2024 00:20:57 +0100 Subject: [PATCH 57/68] If ABI not already passed in then parameterize it based on selected XLEN (#566) --- benchmarks/Makefile | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/benchmarks/Makefile b/benchmarks/Makefile index fde4f2316..d38f8aff1 100644 --- a/benchmarks/Makefile +++ b/benchmarks/Makefile @@ -6,6 +6,13 @@ XLEN ?= 64 +ifeq ($(XLEN),32) +ABI ?= ilp32d +endif +ifeq ($(XLEN),64) +ABI ?= lp64d +endif + default: all src_dir = . @@ -43,7 +50,7 @@ bmarks = \ RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- RISCV_GCC ?= $(RISCV_PREFIX)gcc -RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gcv -mabi=lp64d +RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -fno-tree-loop-distribute-patterns -march=rv$(XLEN)gcv -mabi=$(ABI) RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs) RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data From e06a435c1e545def71e833031356372f0828f165 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 24 Jun 2024 15:19:59 -0700 Subject: [PATCH 58/68] Use Zvl/Zve to communicate VLEN/ELEN to target in debug tests (#567) --- debug/test | Bin 0 -> 17704 bytes debug/testlib.py | 5 +++-- 2 files changed, 3 insertions(+), 2 deletions(-) create mode 100755 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changed, 5 insertions(+), 5 deletions(-) diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg index c6c7d2d88..3fdae973e 100644 --- a/debug/targets/RISC-V/spike-1.cfg +++ b/debug/targets/RISC-V/spike-1.cfg @@ -5,7 +5,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME $_CHIPNAME.cpu if {$::env(USE_FREERTOS)} { diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index c10ad8fdd..5a08ece66 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME_0 $_CHIPNAME.cpu0 set _TARGETNAME_1 $_CHIPNAME.cpu1 diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index ebf3c5aef..2de425607 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -6,7 +6,7 @@ remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef set _TARGETNAME_0 $_CHIPNAME.cpu0 set _TARGETNAME_1 $_CHIPNAME.cpu1 diff --git a/debug/targets/RISC-V/spike-multi.cfg b/debug/targets/RISC-V/spike-multi.cfg index 36d43286f..dff325e6d 100644 --- a/debug/targets/RISC-V/spike-multi.cfg +++ b/debug/targets/RISC-V/spike-multi.cfg @@ -5,8 +5,8 @@ adapter driver remote_bitbang remote_bitbang host $::env(REMOTE_BITBANG_HOST) remote_bitbang port $::env(REMOTE_BITBANG_PORT) -jtag newtap riscv.0 cpu -irlen 5 -expected-id 0x10e31913 -jtag newtap riscv.1 cpu -irlen 5 -expected-id 0x10e31913 +jtag newtap riscv.0 cpu -irlen 5 -expected-id 0xdeadbeef +jtag newtap riscv.1 cpu -irlen 5 -expected-id 0xdeadbeef target create riscv.0.cpu0 riscv -chain-position riscv.0.cpu -coreid 0 target create riscv.0.cpu1 riscv -chain-position riscv.0.cpu -coreid 1 From 8cd31446a695882167571f0016e39f3f1110d989 Mon Sep 17 00:00:00 2001 From: Daniel Maslowski Date: Tue, 2 Jul 2024 23:09:51 +0200 Subject: [PATCH 60/68] README: add link to toolchain (#569) Signed-off-by: Daniel Maslowski --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index b20b69206..d07f13863 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,8 @@ Building from repository ----------------------------- We assume that the RISCV environment variable is set to the RISC-V tools -install path, and that the riscv-gnu-toolchain package is installed. +install path, and that the [riscv-gnu-toolchain]( +https://github.com/riscv-collab/riscv-gnu-toolchain) package is installed. $ git clone https://github.com/riscv/riscv-tests $ cd riscv-tests From 7878085d2546af0eb7af72a1df00996d5d8c43fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?B=C3=BC=C5=9Fra=20=C3=96zdemir?= <92295780+busraozdmir@users.noreply.github.com> Date: Thu, 18 Jul 2024 00:19:38 +0300 Subject: [PATCH 61/68] rsort.c description updated to Radix Sort instead of Quicksort (#572) --- benchmarks/rsort/rsort.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/benchmarks/rsort/rsort.c b/benchmarks/rsort/rsort.c index 7ffc12a41..c2788ca48 100644 --- a/benchmarks/rsort/rsort.c +++ b/benchmarks/rsort/rsort.c @@ -1,10 +1,10 @@ // See LICENSE for license details. //************************************************************************** -// Quicksort benchmark +// Radix Sort benchmark //-------------------------------------------------------------------------- // -// This benchmark uses quicksort to sort an array of integers. The +// This benchmark uses radix sort to sort an array of integers. The // implementation is largely adapted from Numerical Recipes for C. The // input data (and reference data) should be generated using the // qsort_gendata.pl perl script and dumped to a file named From 68c70f52115267097bc1381f3e85a18df15bbad4 Mon Sep 17 00:00:00 2001 From: Mark Zhuang Date: Wed, 31 Jul 2024 10:20:49 +0800 Subject: [PATCH 62/68] debug: update lds to merge more section (#573) merge .bss.* to .bss then entry.S can clear it. --- debug/targets/RISC-V/spike32.lds | 9 ++++++--- debug/targets/RISC-V/spike64.lds | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/debug/targets/RISC-V/spike32.lds b/debug/targets/RISC-V/spike32.lds index 77bb1bad7..1e3f34f46 100755 --- a/debug/targets/RISC-V/spike32.lds +++ b/debug/targets/RISC-V/spike32.lds @@ -5,14 +5,17 @@ SECTIONS /* Leave some space for pk's data structures, which includes tohost/fromhost * which are special addresses we ought to leave alone. */ . = 0x10110000; - .text : + .text : { *(.text.entry) *(.text) + *(.text.*) } /* data segment */ - .data : { *(.data) } + .rodata : { *(.rodata .rodata.*) } + + .data : { *(.data .data.*) } .sdata : { __global_pointer$ = . + 0x800; @@ -27,7 +30,7 @@ SECTIONS *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } - .bss : { *(.bss) } + .bss : { *(.bss .bss.*) } __bss_end = .; __malloc_start = .; diff --git a/debug/targets/RISC-V/spike64.lds b/debug/targets/RISC-V/spike64.lds index 2e7d65d17..9cbf36f97 100755 --- a/debug/targets/RISC-V/spike64.lds +++ b/debug/targets/RISC-V/spike64.lds @@ -3,14 +3,17 @@ OUTPUT_ARCH( "riscv" ) SECTIONS { . = 0x1212340000; - .text : + .text : { *(.text.entry) *(.text) + *(.text.*) } /* data segment */ - .data : { *(.data) } + .rodata : { *(.rodata .rodata.*) } + + .data : { *(.data .data.*) } .sdata : { __global_pointer$ = . + 0x800; @@ -25,7 +28,7 @@ SECTIONS *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } - .bss : { *(.bss) } + .bss : { *(.bss .bss.*) } __bss_end = .; __malloc_start = .; From f2f748ebb9cf8ea049103f85c4cbf7e8a2927b16 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov <109669442+en-sc@users.noreply.github.com> Date: Wed, 7 Aug 2024 22:14:00 +0300 Subject: [PATCH 63/68] Remove `debug/test` binary file (#574) The file was added by 00ab5f0dd4cf56b5a0551bc5adedf60c765d0c66 in #567. Seems like a mistake. ``` > readelf -h debug/test ELF Header: Magic: 7f 45 4c 46 02 01 01 00 00 00 00 00 00 00 00 00 Class: ELF64 Data: 2's complement, little endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: EXEC (Executable file) Machine: RISC-V Version: 0x1 Entry point address: 0x1212340000 Start of program headers: 64 (bytes into file) Start of section headers: 16552 (bytes into file) Flags: 0x0 Size of this header: 64 (bytes) Size of program headers: 56 (bytes) Number of program headers: 2 Size of section headers: 64 (bytes) Number of section headers: 18 Section header string table index: 17 ``` --- debug/test | Bin 17704 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100755 debug/test diff --git a/debug/test b/debug/test deleted file mode 100755 index 9b7273772ddc91a39c8b7ddba96e73b2a86155d8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 17704 zcmeHP3v650c|PZ!%adaq(V;|^ zq~ZrM#59%2&C(?vvpHzIB>`GA$c7<9$UO|t3;Y+t#oHKJ->=IK@ti2t`0X^`N=}25Z zvoO-m+L&N0X9M@_c1`GLZgs#$6SW>13mO8Yk1^GTTNFO3+ZvsrUuu^kuoQu%2rNZl zDFRCoSc1ePMO6oI7(EJa``0!tD2O(T$HudytMv+Q{DX^XMSiO<`Gr|*dthFG)^ z2}Ua-$SRe6{A{7XlB;q|!4U;_GrM%C&RJk`=v1YE)c;RX5SRoiZR*0};7fue( z7oNUX+EqDGIvy&QO38PIS>(6{8SN}P6Tg~ePj`ekpNYiUSfqa~i|pRUBGFr{NbJj2 zq(5Orc7M%^L`!xgcFK2^X|Cu|o`$Kmm%6;JXf!_yyANc*? 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This is the case in `HwbpManual`. The test still works with older OpenOCD versions, since no exception is generated when a command (`riscv reserve_trigger` in this case) is not found. --- debug/gdbserver.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 235814a10..78fde22db 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -711,6 +711,8 @@ def test(self): self.gdb.p("$tdata1=0") tselect += 1 + self.gdb.command(f"monitor riscv reserve_trigger {tselect}") + # The breakpoint should be hit exactly 2 times. for _ in range(2): output = self.gdb.c(ops=2) From e2cdf460d248925b43b9085a3470102ce8a0a83b Mon Sep 17 00:00:00 2001 From: HUJIYONG <107032865+HUJIYONG@users.noreply.github.com> Date: Thu, 15 Aug 2024 09:24:55 +0800 Subject: [PATCH 65/68] Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578) issue#577 In the newest riscv spec(2021 or later), two csr register "sptbr"(0x180) "s/mbadaddr"(0x243) were removed, and upgraded to "satp" "s/mtval". Together with more functions. This commit rename them to pass compile. --- isa/rv64mi/illegal.S | 12 ++++++------ isa/rv64mi/ma_addr.S | 2 +- isa/rv64si/dirty.S | 2 +- isa/rv64si/icache-alias.S | 2 +- isa/rv64si/ma_fetch.S | 6 +++--- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index fb6643bd1..ca8830745 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -72,19 +72,19 @@ msip: beqz t2, bare_s_1 csrc sstatus, t0 - # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. + # Make sure SFENCE.VMA and satp don't trap when TVM=0. sfence.vma - csrr t0, sptbr + csrr t0, satp bad5: .word 0 j fail bad6: - # Make sure SFENCE.VMA and sptbr do trap when TVM=1. + # Make sure SFENCE.VMA and satp do trap when TVM=1. sfence.vma j fail bad7: - csrr t0, sptbr + csrr t0, satp j fail test_tsr: @@ -120,7 +120,7 @@ bare_s_2: j fail # And access to satp should not trap - csrr t0, sptbr + csrr t0, satp bare_s_3: .word 0 j fail @@ -156,7 +156,7 @@ synchronous_exception: csrr t0, mepc # Make sure mtval contains either 0 or the instruction word. - csrr t2, mbadaddr + csrr t2, mtval beqz t2, 1f lhu t1, 0(t0) xor t2, t2, t1 diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index 8579c016a..0f7dc2eef 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -103,7 +103,7 @@ mtvec_handler: j fail 1: - csrr t0, mbadaddr + csrr t0, mtval beqz t0, 1f bne t0, t1, fail diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S index 15f31632a..8a64e2552 100644 --- a/isa/rv64si/dirty.S +++ b/isa/rv64si/dirty.S @@ -22,7 +22,7 @@ RVTEST_CODE_BEGIN la a1, page_table_1 srl a1, a1, RISCV_PGSHIFT or a1, a1, a0 - csrw sptbr, a1 + csrw satp, a1 sfence.vma # Set up MPRV with MPP=S, so loads and stores use S-mode diff --git a/isa/rv64si/icache-alias.S b/isa/rv64si/icache-alias.S index dbc934e91..d2468eb30 100644 --- a/isa/rv64si/icache-alias.S +++ b/isa/rv64si/icache-alias.S @@ -48,7 +48,7 @@ RVTEST_CODE_BEGIN la a1, page_table_1 srl a1, a1, RISCV_PGSHIFT or a1, a1, a0 - csrw sptbr, a1 + csrw satp, a1 sfence.vma # Enter supervisor mode and make sure correct page is accessed diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index b683b6f0c..31c7a23db 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN #define sscratch mscratch #define sstatus mstatus #define scause mcause - #define sbadaddr mbadaddr + #define stval mtval #define sepc mepc #define sret mret #define stvec_handler mtvec_handler @@ -205,8 +205,8 @@ stvec_handler: addi a1, a1, 4 bne t0, a1, fail - # verify that badaddr == 0 or badaddr == t0+2. - csrr a0, sbadaddr + # verify that tval == 0 or tval == t0+2. + csrr a0, stval beqz a0, 1f addi a0, a0, -2 bne a0, t0, fail From 2f97bab8be351402781fa3517b44811fd0c527f6 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Tue, 27 Aug 2024 09:06:44 +0100 Subject: [PATCH 66/68] Fix EtriggerTest assuming that NULL causes a trap (#579) There is already a mechanism for the test target to supply a known-bad address, so use that address if it is provided. --- debug/gdbserver.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 235814a10..177d33000 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -2125,8 +2125,10 @@ def setup(self): def test(self): # Set trigger on Load access fault self.gdb.command("monitor riscv etrigger set m 0x20") - # Set fox to a null pointer so we'll get a load access exception later. - self.gdb.p("fox=(char*)0") + # Set fox to a bad pointer so we'll get a load access exception later. + # Use NULL if a known-bad address is not provided. + bad_address = self.hart.bad_address or 0 + self.gdb.p(f"fox=(char*)0x{bad_address:08x}") output = self.gdb.c() # We should not be at handle_trap assertNotIn("handle_trap", output) From 76ff703d9161945354e334afa45c5dfe7680da60 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Thu, 5 Sep 2024 23:19:20 +0300 Subject: [PATCH 67/68] [debug] Fix trigger reservation in HwbpManual Syntax of the command was changed: (on/off) became compulsory. --- debug/gdbserver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index c8328a086..1280878d3 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -711,7 +711,7 @@ def test(self): self.gdb.p("$tdata1=0") tselect += 1 - self.gdb.command(f"monitor riscv reserve_trigger {tselect}") + self.gdb.command(f"monitor riscv reserve_trigger {tselect} on") # The breakpoint should be hit exactly 2 times. for _ in range(2): From 183969629284d85da86c9efc16bc50a3537b1031 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Fri, 6 Sep 2024 12:12:26 +0300 Subject: [PATCH 68/68] [debug] Reserve triggers propperly in HwbpManual https://github.com/riscv-collab/riscv-openocd/pull/1111 introduces a change in OpenOCD behavior: a manual trigger should be manually removed to step/resume from it. This was not concidered in previous stop-gap solutions (76ff703d9161945354e334afa45c5dfe7680da60 and 8cc4918e904ca009cd85350fadf6f44e91eca13c) This commit: 1. Determines if `reserve trigger` is supported by the target. This can be removed once https://github.com/riscv-collab/riscv-openocd/pull/1111 is merged. 2. Marks `HwbpManual` test as not applicable in case `reserve trigger` is not supported. 3. Accounts for the change in OpenOCD's behavior when stepping from a manual BP. 4. Cleans up some minor mistakes in `HwbpManual` --- debug/gdbserver.py | 80 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 21 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 1280878d3..2fd14a8e9 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -676,6 +676,47 @@ def early_applicable(self): return self.target.support_manual_hwbp and \ self.hart.instruction_hardware_breakpoint_count >= 1 + # TODO: This can be removed once + # https://github.com/riscv-collab/riscv-openocd/pull/1111 + # is merged. + def check_reserve_trigger_support(self): + not_supp_msg = "RESERVE_TRIGGER_NOT_SUPPORTED" + if not_supp_msg in self.gdb.command( + "monitor if [catch {riscv reserve_trigger 0 on} e] {echo " + + not_supp_msg + "}").splitlines(): + raise TestNotApplicable + + def set_manual_trigger(self, tdata1, tdata2): + for tselect in itertools.count(0): + self.gdb.p(f"$tselect={tselect}") + if self.gdb.p("$tselect") != tselect: + raise TestNotApplicable + + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} on") + + # Need to disable the trigger before writing tdata2 + self.gdb.p("$tdata1=0") + # Need to write a valid value to tdata2 before writing tdata1 + self.gdb.p(f"$tdata2=0x{tdata2:x}") + self.gdb.p(f"$tdata1=0x{tdata1:x}") + + tdata2_rb = self.gdb.p("$tdata2") + tdata1_rb = self.gdb.p("$tdata1") + if tdata1_rb == tdata1 and tdata2_rb == tdata2: + return tselect + + type_rb = tdata1_rb & MCONTROL_TYPE(self.hart.xlen) + type_none = set_field(0, MCONTROL_TYPE(self.hart.xlen), + MCONTROL_TYPE_NONE) + if type_rb == type_none: + raise TestNotApplicable + + self.gdb.p("$tdata1=0") + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} off") + assert False + def test(self): if not self.hart.honors_tdata1_hmode: # Run to main before setting the breakpoint, because startup code @@ -684,6 +725,12 @@ def test(self): self.gdb.c() self.gdb.command("delete") + + # TODO: This can be removed once + # https://github.com/riscv-collab/riscv-openocd/pull/1111 + # is merged. + self.check_reserve_trigger_support() + #self.gdb.hbreak("rot13") tdata1 = MCONTROL_DMODE(self.hart.xlen) tdata1 = set_field(tdata1, MCONTROL_TYPE(self.hart.xlen), @@ -692,26 +739,9 @@ def test(self): tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL) tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE - tselect = 0 - while True: - self.gdb.p(f"$tselect={tselect}") - value = self.gdb.p("$tselect") - if value != tselect: - raise TestNotApplicable - # Need to disable the trigger before writing tdata2 - self.gdb.p("$tdata1=0") - # Need to write a valid value to tdata2 before writing tdata1 - self.gdb.p("$tdata2=&rot13") - self.gdb.p(f"$tdata1=0x{tdata1:x}") - value = self.gdb.p("$tdata1") - if value == tdata1: - break - if value & MCONTROL_TYPE(self.hart.xlen) == MCONTROL_TYPE_NONE: - raise TestNotApplicable - self.gdb.p("$tdata1=0") - tselect += 1 + tdata2 = self.gdb.p("&rot13") - self.gdb.command(f"monitor riscv reserve_trigger {tselect} on") + tselect = self.set_manual_trigger(tdata1, tdata2) # The breakpoint should be hit exactly 2 times. for _ in range(2): @@ -728,14 +758,22 @@ def test(self): self.gdb.c() before = self.gdb.p("$pc") assertEqual(before, self.gdb.p("&crc32a")) + self.gdb.stepi() - after = self.gdb.p("$pc") - assertNotEqual(before, after) + assertEqual(before, self.gdb.p("$pc"), + "OpenOCD shouldn't disable a reserved trigger.") # Remove the manual HW breakpoint. assertEqual(tselect, self.gdb.p("$tselect")) self.gdb.p("$tdata1=0") + self.gdb.stepi() + assertNotEqual(before, self.gdb.p("$pc"), + "OpenOCD should be able to step from a removed BP.") + + self.gdb.command( + f"monitor riscv reserve_trigger {tselect} off") + self.gdb.b("_exit") self.exit()