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make verilog error #3765
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你可以检查一下你的mill有没有安装成功,输入命令 [Translation] You can check if Mill is installed successfully by entering the command mill --version. |
谢谢,从新git clone后,安装步骤配置,发现xs-env里面的XiangShan文件夹是空的。 [Translation] Thank you. After re-cloning and configuring the installation steps, I found that the XiangShan folder inside xs-env is empty. When running make init in /xs-env/XiangShan, it shows the error: make: *** No rule to make target 'init'. Stop. Could you please explain the reason for this? |
可能是你子模块没有clone完整 [Translation] It’s possible that the submodules weren’t fully cloned. |
感谢您的提问。初次部署XiangShan时,请完全按照XiangShan官网文档https://docs.xiangshan.cc/zh-cn/latest/tools/xsenv/中TLDR一节中脚本运行:
您的问题应该在于没有执行source setup.sh导致环境没有配置完全(XiangShan文件夹内为空) Thank you for your question. When deploying XiangShan for the first time, please follow the steps in the TLDR section of the official XiangShan documentation at https://docs.xiangshan.cc/zh-cn/latest/tools/xsenv/ exactly:
The issue you encountered is likely due to not running source setup.sh, which caused the environment to be improperly configured (the XiangShan folder is empty). |
Before start
Describe you problem
make init后make verilog后,如下,出现了错误,请问是什么原因?
mkdir -p build/rtl
time -avp -0 ./build/time.log mill -i xiangshan.runMain top.TopMain
seq-mem --repl-seq-mem-file=XSTop.sv.conf"
--target-dir build/rtl --config DefaultConfig --issue B--firtool-opt "--repl
--num-cores 1 --dump-fir --target systemverilog--split-verilog - firtool-opt
"-O=release - - disable-annotation-unknown - lowering-options=explicitBitcast,disallowLo
calVariables,disallowPortDeclSharing,locationInfoStyle=none" --fpga-platform --disable
-all --remove-assert --reset-gen --disable-always-basic-diff
/scripts/gen_sep_mem.sh "./scripts/vlsi_mem_gen" "buuild/rtl/XSTop.sv.conf" build/rtl
cat: build/rtl/XSTop.sv.conf: No such file or directory
rm: cannot remove 'build/rtl/XSTop.sv.conf.tmp': No such file or directory
make: *** [Makefile:155: build/rtl/XSTop.sv] Erгог 1
What did you do before
环境已正确配置
Environment
Additional context
make init后make verilog后,如下,出现了错误,请问是什么原因?
mkdir -p build/rtl
time -avp -0 ./build/time.log mill -i xiangshan.runMain top.TopMain
seq-mem --repl-seq-mem-file=XSTop.sv.conf"
--target-dir build/rtl --config DefaultConfig --issue B--firtool-opt "--repl
--num-cores 1 --dump-fir --target systemverilog--split-verilog - firtool-opt
"-O=release - - disable-annotation-unknown - lowering-options=explicitBitcast,disallowLo
calVariables,disallowPortDeclSharing,locationInfoStyle=none" --fpga-platform --disable
-all --remove-assert --reset-gen --disable-always-basic-diff
/scripts/gen_sep_mem.sh "./scripts/vlsi_mem_gen" "buuild/rtl/XSTop.sv.conf" build/rtl
cat: build/rtl/XSTop.sv.conf: No such file or directory
rm: cannot remove 'build/rtl/XSTop.sv.conf.tmp': No such file or directory
make: *** [Makefile:155: build/rtl/XSTop.sv] Erгог 1
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