make verilog error

[yaoyuexiaogege]

Before start

• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。

Describe you problem

make init后make verilog后，如下，出现了错误，请问是什么原因？
mkdir -p build/rtl
time -avp -0 ./build/time.log mill -i xiangshan.runMain top.TopMain
seq-mem --repl-seq-mem-file=XSTop.sv.conf"
--target-dir build/rtl --config DefaultConfig --issue B--firtool-opt "--repl
--num-cores 1 --dump-fir --target systemverilog--split-verilog - firtool-opt
"-O=release - - disable-annotation-unknown - lowering-options=explicitBitcast,disallowLo
calVariables,disallowPortDeclSharing,locationInfoStyle=none" --fpga-platform --disable
-all --remove-assert --reset-gen --disable-always-basic-diff
/scripts/gen_sep_mem.sh "./scripts/vlsi_mem_gen" "buuild/rtl/XSTop.sv.conf" build/rtl
cat: build/rtl/XSTop.sv.conf: No such file or directory
rm: cannot remove 'build/rtl/XSTop.sv.conf.tmp': No such file or directory
make: *** [Makefile:155: build/rtl/XSTop.sv] Erгог 1

What did you do before

环境已正确配置

Environment

• XiangShan branch:
• XiangShan commit id:
• NEMU commit id:
• SPIKE commit id:
• Operating System:
• gcc version:
• mill version:
• java version:

Additional context

make init后make verilog后，如下，出现了错误，请问是什么原因？
mkdir -p build/rtl
time -avp -0 ./build/time.log mill -i xiangshan.runMain top.TopMain
seq-mem --repl-seq-mem-file=XSTop.sv.conf"
--target-dir build/rtl --config DefaultConfig --issue B--firtool-opt "--repl
--num-cores 1 --dump-fir --target systemverilog--split-verilog - firtool-opt
"-O=release - - disable-annotation-unknown - lowering-options=explicitBitcast,disallowLo
calVariables,disallowPortDeclSharing,locationInfoStyle=none" --fpga-platform --disable
-all --remove-assert --reset-gen --disable-always-basic-diff
/scripts/gen_sep_mem.sh "./scripts/vlsi_mem_gen" "buuild/rtl/XSTop.sv.conf" build/rtl
cat: build/rtl/XSTop.sv.conf: No such file or directory
rm: cannot remove 'build/rtl/XSTop.sv.conf.tmp': No such file or directory
make: *** [Makefile:155: build/rtl/XSTop.sv] Erгог 1

[hanyjie]

你可以检查一下你的mill有没有安装成功，输入命令mill --version

[Translation] You can check if Mill is installed successfully by entering the command mill --version.

[yaoyuexiaogege]

你可以检查一下你的mill有没有安装成功，输入命令mill --version

谢谢，从新git clone后，安装步骤配置，发现xs-env里面的XiangShan文件夹是空的。
在/xs-env/XiangShan执行make init后，提示：make: *** No rule to make target 'init'. Stop.
请问是什么原因？

[Translation] Thank you. After re-cloning and configuring the installation steps, I found that the XiangShan folder inside xs-env is empty. When running make init in /xs-env/XiangShan, it shows the error: make: *** No rule to make target 'init'. Stop.

Could you please explain the reason for this?

[hanyjie]

可能是你子模块没有clone完整

[Translation] It’s possible that the submodules weren’t fully cloned.

[Ma-YX]

感谢您的提问。初次部署XiangShan时，请完全按照XiangShan官网文档https://docs.xiangshan.cc/zh-cn/latest/tools/xsenv/中TLDR一节中脚本运行：

git clone https://github.com/OpenXiangShan/xs-env
cd xs-env
sudo -s ./setup-tools.sh # use apt to install dependencies, you may modify it to use different pkg manager
source setup.sh # prepare tools, test develop env using a small project

您的问题应该在于没有执行source setup.sh导致环境没有配置完全（XiangShan文件夹内为空）

Thank you for your question. When deploying XiangShan for the first time, please follow the steps in the TLDR section of the official XiangShan documentation at https://docs.xiangshan.cc/zh-cn/latest/tools/xsenv/ exactly:

git clone https://github.com/OpenXiangShan/xs-env
cd xs-env
sudo -s ./setup-tools.sh # use apt to install dependencies, you may modify it to use different pkg manager
source setup.sh # prepare tools, test develop env using a small project

The issue you encountered is likely due to not running source setup.sh, which caused the environment to be improperly configured (the XiangShan folder is empty).