From c51df1bd0ccbee415ed69d7ff80a98149ee00e06 Mon Sep 17 00:00:00 2001 From: Cai Luoshan Date: Sun, 8 Oct 2023 16:14:15 +0800 Subject: [PATCH] mergeA: fix 2 bugs about merge permission_check and pftrain vaddr --- src/main/scala/coupledL2/Common.scala | 2 ++ src/main/scala/coupledL2/MSHR.scala | 2 ++ src/main/scala/coupledL2/MainPipe.scala | 2 +- src/main/scala/coupledL2/RequestBuffer.scala | 3 ++- 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coupledL2/Common.scala b/src/main/scala/coupledL2/Common.scala index c69be83c..a9aac2de 100644 --- a/src/main/scala/coupledL2/Common.scala +++ b/src/main/scala/coupledL2/Common.scala @@ -42,6 +42,7 @@ trait HasChannelBits { this: Bundle => class MergeTaskBundle(implicit p: Parameters) extends L2Bundle { val off = UInt(offsetBits.W) val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W)) // color bits in cache-alias issue + val vaddr = vaddrBitsOpt.map(_ => UInt(vaddrBitsOpt.get.W)) // vaddr passed by client cache, for prefetcher train val opcode = UInt(3.W) // type of the task operation val param = UInt(3.W) val sourceId = UInt(sourceIdBits.W) // tilelink sourceID @@ -179,6 +180,7 @@ class MSHRInfo(implicit p: Parameters) extends L2Bundle { // whether the mshr_task already in mainpipe val s_refill = Bool() + val param = UInt(3.W) val mergeA = Bool() // whether the mshr already merge an acquire(avoid alias merge) } diff --git a/src/main/scala/coupledL2/MSHR.scala b/src/main/scala/coupledL2/MSHR.scala index 2ce6549b..93d2153e 100644 --- a/src/main/scala/coupledL2/MSHR.scala +++ b/src/main/scala/coupledL2/MSHR.scala @@ -399,6 +399,7 @@ class MSHR(implicit p: Parameters) extends L2Module { val merge_task = Mux(io.aMergeTask.valid, io.aMergeTask.bits, merge_task_r) mp_grant.aMergeTask.off := merge_task.off mp_grant.aMergeTask.alias.foreach(_ := merge_task.alias.getOrElse(0.U)) + mp_grant.aMergeTask.vaddr.foreach(_ := merge_task.vaddr.getOrElse(0.U)) mp_grant.aMergeTask.opcode := odOpGen(merge_task.opcode) mp_grant.aMergeTask.param := MuxLookup( // Acquire -> Grant merge_task.param, @@ -585,6 +586,7 @@ class MSHR(implicit p: Parameters) extends L2Module { io.msInfo.bits.isAcqOrPrefetch := req_acquire || req_prefetch io.msInfo.bits.isPrefetch := req_prefetch io.msInfo.bits.s_refill := state.s_refill + io.msInfo.bits.param := req.param io.msInfo.bits.mergeA := mergeA assert(!(c_resp.valid && !io.status.bits.w_c_resp)) diff --git a/src/main/scala/coupledL2/MainPipe.scala b/src/main/scala/coupledL2/MainPipe.scala index 6d044770..f0bd611b 100644 --- a/src/main/scala/coupledL2/MainPipe.scala +++ b/src/main/scala/coupledL2/MainPipe.scala @@ -416,7 +416,7 @@ class MainPipe(implicit p: Parameters) extends L2Module { train.bits.set := req_s3.set train.bits.needT := Mux(req_s3.mergeA, needT(req_s3.aMergeTask.opcode, req_s3.aMergeTask.param),req_needT_s3) train.bits.source := Mux(req_s3.mergeA, req_s3.aMergeTask.sourceId, req_s3.sourceId) - train.bits.vaddr.foreach(_ := req_s3.vaddr.getOrElse(0.U)) + train.bits.vaddr.foreach(_ := Mux(req_s3.mergeA, req_s3.aMergeTask.vaddr.getOrElse(0.U), req_s3.vaddr.getOrElse(0.U))) } /* ======== Stage 4 ======== */ diff --git a/src/main/scala/coupledL2/RequestBuffer.scala b/src/main/scala/coupledL2/RequestBuffer.scala index 77df5cc5..a8f58162 100644 --- a/src/main/scala/coupledL2/RequestBuffer.scala +++ b/src/main/scala/coupledL2/RequestBuffer.scala @@ -2,6 +2,7 @@ package coupledL2 import chipsalliance.rocketchip.config.Parameters import freechips.rocketchip.tilelink.TLMessages._ +import freechips.rocketchip.tilelink.TLPermissions._ import chisel3._ import chisel3.util._ import coupledL2.utils._ @@ -120,7 +121,7 @@ class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Paramete // incoming Acquire can be merged with late_pf MSHR block val mergeAMask = VecInit(io.mshrInfo.map(s => s.valid && s.bits.isPrefetch && sameAddr(in, s.bits) && !s.bits.willFree && !s.bits.dirHit && !s.bits.s_refill && - in.fromA && (in.opcode === AcquireBlock || in.opcode === AcquirePerm) && !s.bits.mergeA + in.fromA && (in.opcode === AcquireBlock || in.opcode === AcquirePerm) && !s.bits.mergeA && !(in.param === toT && s.bits.param === toB) )).asUInt val mergeA = mergeAMask.orR val mergeAId = OHToUInt(mergeAMask)