From 6556172a30bb244577f74e209385b2fdac8d67f6 Mon Sep 17 00:00:00 2001 From: Cai Luoshan Date: Sun, 2 Jun 2024 18:39:01 +0800 Subject: [PATCH] Directory: fix rrip_touch_way bug for not consider invalid ways --- src/main/scala/coupledL2/Directory.scala | 26 +++++++++++------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/src/main/scala/coupledL2/Directory.scala b/src/main/scala/coupledL2/Directory.scala index 6838f96f..aad708b3 100644 --- a/src/main/scala/coupledL2/Directory.scala +++ b/src/main/scala/coupledL2/Directory.scala @@ -277,9 +277,7 @@ class Directory(implicit p: Parameters) extends L2Module { // update replacer when A/C hit or refill replacerWen := updateHit || updateRefill - // hit-Promotion, miss-Insertion for RRIP, so refill should hit = false.B - val touch_way_s3 = Mux(refillReqValid_s3, replaceWay, way_s3) - val rrip_hit_s3 = Mux(refillReqValid_s3, false.B, hit_s3) + // hit-Promotion, miss-Insertion for RRIP // origin-bit marks whether the data_block is reused val origin_bit_opt = if(random_repl) None else Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true, shouldReset = true))) @@ -288,22 +286,22 @@ class Directory(implicit p: Parameters) extends L2Module { origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire, false.B)) origin_bit_opt.get.io.w( !resetFinish || replacerWen, - Mux(resetFinish, rrip_hit_s3, false.B), + Mux(resetFinish, hit_s3, false.B), Mux(resetFinish, req_s3.set, resetIdx), - UIntToOH(touch_way_s3) + UIntToOH(way_s3) ) if(cacheParams.replacement == "srrip"){ // req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release; // req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill val req_type = WireInit(0.U(4.W)) - req_type := Cat(origin_bits_hold(touch_way_s3), + req_type := Cat(origin_bits_hold(way_s3), req_s3.replacerInfo.channel(2), - (req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch, + (req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch, req_s3.refill ) - val next_state_s3 = repl.get_next_state(repl_state_s3, touch_way_s3, rrip_hit_s3, inv, req_type) + val next_state_s3 = repl.get_next_state(repl_state_s3, way_s3, hit_s3, inv, req_type) val repl_init = Wire(Vec(ways, UInt(2.W))) repl_init.foreach(_ := 2.U(2.W)) replacer_sram_opt.get.io.w( @@ -317,9 +315,9 @@ class Directory(implicit p: Parameters) extends L2Module { // req_type[3]: 0-firstuse, 1-reuse; req_type[2]: 0-acquire, 1-release; // req_type[1]: 0-non-prefetch, 1-prefetch; req_type[0]: 0-not-refill, 1-refill val req_type = WireInit(0.U(4.W)) - req_type := Cat(origin_bits_hold(touch_way_s3), + req_type := Cat(origin_bits_hold(way_s3), req_s3.replacerInfo.channel(2), - (req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(touch_way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch, + (req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(way_s3).prefetch.getOrElse(false.B)) || req_s3.replacerInfo.refill_prefetch, req_s3.refill ) @@ -331,9 +329,9 @@ class Directory(implicit p: Parameters) extends L2Module { val half_setBits = setBits >> 1 val match_a = set_s3(setBits-1,setBits-half_setBits-1)===set_s3(setBits-half_setBits-1,0) // 512 sets [8:4][4:0] val match_b = set_s3(setBits-1,setBits-half_setBits-1)===(~set_s3(setBits-half_setBits-1,0)) - when(refillReqValid_s3 && match_a && !rrip_hit_s3 && (PSEL=/=1023.U)){ //SDMs_srrip miss + when(refillReqValid_s3 && match_a && !hit_s3 && (PSEL=/=1023.U)){ //SDMs_srrip miss PSEL := PSEL + 1.U - } .elsewhen(refillReqValid_s3 && match_b && !rrip_hit_s3 && (PSEL=/=0.U)){ //SDMs_brrip miss + } .elsewhen(refillReqValid_s3 && match_b && !hit_s3 && (PSEL=/=0.U)){ //SDMs_brrip miss PSEL := PSEL - 1.U } // decide use which policy by policy selection counter, for insertion @@ -345,7 +343,7 @@ class Directory(implicit p: Parameters) extends L2Module { Mux(match_b, true.B, Mux(PSEL(9)===0.U, false.B, true.B))) // false.B - srrip, true.B - brrip - val next_state_s3 = repl.get_next_state(repl_state_s3, touch_way_s3, rrip_hit_s3, inv, repl_type, req_type) + val next_state_s3 = repl.get_next_state(repl_state_s3, way_s3, hit_s3, inv, repl_type, req_type) val repl_init = Wire(Vec(ways, UInt(2.W))) repl_init.foreach(_ := 2.U(2.W)) @@ -356,7 +354,7 @@ class Directory(implicit p: Parameters) extends L2Module { 1.U ) } else { - val next_state_s3 = repl.get_next_state(repl_state_s3, touch_way_s3) + val next_state_s3 = repl.get_next_state(repl_state_s3, way_s3) replacer_sram_opt.get.io.w( !resetFinish || replacerWen, Mux(resetFinish, next_state_s3, 0.U),