diff --git a/src/main/scala/coupledL2/tl2chi/MSHR.scala b/src/main/scala/coupledL2/tl2chi/MSHR.scala
index 98bd8510..7dd9157c 100644
--- a/src/main/scala/coupledL2/tl2chi/MSHR.scala
+++ b/src/main/scala/coupledL2/tl2chi/MSHR.scala
@@ -78,6 +78,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
   val probeDirty = RegInit(false.B)
   val probeGotN = RegInit(false.B)
   val timer = RegInit(0.U(64.W)) // for performance analysis
+  val beatCnt = RegInit(0.U(log2Ceil(beatSize).W))
 
   val req_valid = RegInit(false.B)
   val req       = RegInit(0.U.asTypeOf(new TaskBundle()))
@@ -132,6 +133,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
     probeDirty  := false.B
     probeGotN   := false.B
     timer       := 1.U
+    beatCnt     := 0.U
 
     gotRetryAck := false.B
     gotPCrdGrant := false.B
@@ -831,8 +833,9 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
   when (rxdat.valid) {
     when (rxdat.bits.chiOpcode.get === DataSepResp) {
       require(beatSize == 2) // TODO: This is ugly
+      beatCnt := beatCnt + 1.U
       state.w_grantfirst := true.B
-      state.w_grantlast := state.w_grantfirst
+      state.w_grantlast := state.w_grantfirst && beatCnt === (beatSize - 1).U
       state.w_grant := req.off === 0.U || state.w_grantfirst  // TODO? why offset?
       gotT := rxdatIsU || rxdatIsU_PD
       gotDirty := gotDirty || rxdatIsU_PD
@@ -855,6 +858,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module {
   // RXRSP for dataless
   when (rxrsp.valid) {
     when (rxrsp.bits.chiOpcode.get === RespSepData) {
+      state.w_grantfirst := true.B
       srcid := rxrsp.bits.srcID.getOrElse(0.U)
       homenid := rxrsp.bits.srcID.getOrElse(0.U)
       dbid := rxrsp.bits.dbID.getOrElse(0.U)
diff --git a/src/main/scala/coupledL2/tl2chi/chi/Opcode.scala b/src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
index 73d00ed7..1c57d9af 100644
--- a/src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
+++ b/src/main/scala/coupledL2/tl2chi/chi/Opcode.scala
@@ -235,12 +235,6 @@ object CHIOpcode {
 
     def width(implicit p: Parameters) = width_map(p(CHIIssue))
 
-    def DataL2RdData(implicit p: Parameters)        = 0x0.U(width.W)
-    def DataL2RdDataFwded(implicit p: Parameters)  = 0x1.U(width.W)
-    def DataL2RdDataCancel(implicit p: Parameters) = 0x2.U(width.W)
-    def DataL2RdDataFwdedCancel(implicit p: Parameters) = 0x3.U(width.W)
-    def DataL2RdDataFwdedCancel2(implicit p: Parameters) = 0x4.U(width.W)
-
     def DataLCrdReturn(implicit p: Parameters)    = 0x0.U(width.W)
     def SnpRespData(implicit p: Parameters)       = 0x1.U(width.W)
     def CopyBackWrData(implicit p: Parameters)    = 0x2.U(width.W)