diff --git a/src/main/scala/coupledL2/Common.scala b/src/main/scala/coupledL2/Common.scala
index 7572bee4..7dd4114e 100644
--- a/src/main/scala/coupledL2/Common.scala
+++ b/src/main/scala/coupledL2/Common.scala
@@ -138,6 +138,7 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle
 
   def toCHIREQBundle(): CHIREQ = {
     val req = WireInit(0.U.asTypeOf(new CHIREQ()))
+    req.qos := Fill(QOS_WIDTH, 1.U(1.W)) // TODO
     req.tgtID := tgtID.getOrElse(0.U)
     req.srcID := srcID.getOrElse(0.U)
     req.txnID := txnID.getOrElse(0.U)
diff --git a/src/main/scala/coupledL2/tl2chi/MSHR.scala b/src/main/scala/coupledL2/tl2chi/MSHR.scala
index fb12c11f..dedd8c8a 100644
--- a/src/main/scala/coupledL2/tl2chi/MSHR.scala
+++ b/src/main/scala/coupledL2/tl2chi/MSHR.scala
@@ -291,7 +291,7 @@ class MSHR(implicit p: Parameters) extends TL2CHIL2Module with HasCHIOpcodes {
   val a_task = {
     val oa = io.tasks.txreq.bits
     oa := 0.U.asTypeOf(io.tasks.txreq.bits.cloneType)
-//    oa.qos := Mux(!state.s_reissue, 3.U, 0.U) //TODO increase qos when retry
+    oa.qos := Fill(QOS_WIDTH, 1.U(1.W)) // TODO
     oa.tgtID := Mux(!state.s_reissue.getOrElse(false.B), srcid, 0.U)
     oa.srcID := 0.U
     oa.txnID := io.id