diff --git a/src/main/scala/coupledL2/AcquireUnit.scala b/src/main/scala/coupledL2/AcquireUnit.scala
index 56512e61..c391c003 100644
--- a/src/main/scala/coupledL2/AcquireUnit.scala
+++ b/src/main/scala/coupledL2/AcquireUnit.scala
@@ -23,7 +23,7 @@ import utility._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import org.chipsalliance.cde.config.Parameters
-import huancun.{PreferCacheKey}
+import huancun.{DirtyKey, PreferCacheKey}
 
 class AcquireUnit(implicit p: Parameters) extends L2Module {
   val io = IO(new Bundle() {
diff --git a/src/main/scala/coupledL2/L2Param.scala b/src/main/scala/coupledL2/L2Param.scala
index b167dcde..e4b9c440 100644
--- a/src/main/scala/coupledL2/L2Param.scala
+++ b/src/main/scala/coupledL2/L2Param.scala
@@ -23,7 +23,7 @@ import freechips.rocketchip.diplomacy.BufferParams
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import org.chipsalliance.cde.config.Field
-import huancun.CacheParameters
+import huancun.{AliasKey, CacheParameters, IsHitKey, PrefetchKey}
 import coupledL2.prefetch._
 import utility.{MemReqSource, ReqSourceKey}
 
@@ -46,15 +46,6 @@ case class L1Param
   val needResolveAlias = aliasBitsOpt.nonEmpty
 }
 
-// Indicate alias bit of upper level cache
-case object AliasKey extends ControlKey[UInt]("alias")
-case class AliasField(width: Int) extends BundleField(AliasKey) {
-  override def data: UInt = Output(UInt(width.W))
-  override def default(x: UInt): Unit = {
-    x := 0.U(width.W)
-  }
-}
-
 // Pass virtual address of upper level cache
 case object VaddrKey extends ControlKey[UInt]("vaddr")
 case class VaddrField(width: Int) extends BundleField(VaddrKey) {
@@ -64,36 +55,6 @@ case class VaddrField(width: Int) extends BundleField(VaddrKey) {
   }
 }
 
-// Indicate whether Hint is needed by upper level cache
-case object PrefetchKey extends ControlKey[Bool](name = "needHint")
-case class PrefetchField() extends BundleField(PrefetchKey) {
-  override def data: Bool = Output(Bool())
-  override def default(x: Bool): Unit = {
-    x := false.B
-  }
-}
-
-case object IsHitKey extends ControlKey[Bool](name = "isHitInL3")
-
-case class IsHitField() extends BundleField(IsHitKey) {
-  override def data: Bool = Output(Bool())
-
-  override def default(x: Bool): Unit = {
-    x := true.B
-  }
-}
-
-// Indicate whether this block is dirty or not (only used in handle Release/ReleaseData)
-// Now it only works for non-inclusive cache (ignored in inclusive cache)
-case object DirtyKey extends ControlKey[Bool](name = "blockisdirty")
-
-case class DirtyField() extends BundleField(DirtyKey) {
-  override def data: Bool = Output(Bool())
-  override def default(x: Bool): Unit = {
-    x := true.B
-  }
-}
-
 case class L2Param
 (
   name: String = "L2",
diff --git a/src/main/scala/coupledL2/RefillUnit.scala b/src/main/scala/coupledL2/RefillUnit.scala
index 95293817..531f1fb9 100644
--- a/src/main/scala/coupledL2/RefillUnit.scala
+++ b/src/main/scala/coupledL2/RefillUnit.scala
@@ -23,6 +23,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils.XSPerfAccumulate
+import huancun.{DirtyKey, IsHitKey}
 
 class grantAckQEntry(implicit p: Parameters) extends L2Bundle {
   val source = UInt(sourceIdBits.W)
diff --git a/src/main/scala/coupledL2/SinkA.scala b/src/main/scala/coupledL2/SinkA.scala
index a2709327..3214d9e1 100644
--- a/src/main/scala/coupledL2/SinkA.scala
+++ b/src/main/scala/coupledL2/SinkA.scala
@@ -25,6 +25,7 @@ import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLHints._
 import coupledL2.prefetch.PrefetchReq
 import coupledL2.utils.XSPerfAccumulate
+import huancun.{AliasKey, PrefetchKey}
 import utility.MemReqSource
 
 class SinkA(implicit p: Parameters) extends L2Module {
diff --git a/src/main/scala/coupledL2/SourceC.scala b/src/main/scala/coupledL2/SourceC.scala
index 9327746e..2bd0f0aa 100644
--- a/src/main/scala/coupledL2/SourceC.scala
+++ b/src/main/scala/coupledL2/SourceC.scala
@@ -23,6 +23,7 @@ import utility._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import coupledL2.utils.XSPerfAccumulate
+import huancun.DirtyKey
 
 //class SourceC(implicit p: Parameters) extends L2Module {
 //  val io = IO(new Bundle() {
diff --git a/src/test/scala/TestProbeQueue.scala b/src/test/scala/TestProbeQueue.scala
index 0c20b065..719925d2 100644
--- a/src/test/scala/TestProbeQueue.scala
+++ b/src/test/scala/TestProbeQueue.scala
@@ -11,7 +11,7 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import scala.collection.mutable.ArrayBuffer
-
+import huancun.DirtyField