From 42f765a48dde6d4e35b352f271ba73dc7ace079a Mon Sep 17 00:00:00 2001 From: Ding Haonan Date: Mon, 28 Oct 2024 18:24:42 +0800 Subject: [PATCH] chore(TestTop): expand TileLink ID Ranges of CHI TestTop (#274) --- src/test/scala/chi/TestTop.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/test/scala/chi/TestTop.scala b/src/test/scala/chi/TestTop.scala index 513c0a34..7f4e717a 100644 --- a/src/test/scala/chi/TestTop.scala +++ b/src/test/scala/chi/TestTop.scala @@ -48,14 +48,14 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, iss masterNode } - val l1d_nodes = (0 until numCores).map(i => createClientNode(s"l1d$i", 32)) + val l1d_nodes = (0 until numCores).map(i => createClientNode(s"l1d$i", 64)) val l1i_nodes = (0 until numCores).map {i => (0 until numULAgents).map { j => TLClientNode(Seq( TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = s"l1i${i}_${j}", - sourceId = IdRange(0, 32) + sourceId = IdRange(0, 64) )) ) )) @@ -109,7 +109,8 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, iss val mmioClientNode = TLClientNode(Seq( TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( - "uncache" + name = "uncache", + sourceId = IdRange(0, 16) )) ) ))