Incorrect Exception Priority for Misaligned Address and Illegal Instruction

[youzi27]

Describe the bug

In the Nutshell design, when executing a load instruction with the destination register set to zero (e.g., c.ldsp zero, x(sp)) and the address is misaligned, a Load Address Misaligned exception is raised instead of an Illegal Instruction exception. This behavior appears to conflict with the RISC-V specifications, which state that the Illegal Instruction exception should be prioritized over the Load Address Misaligned exception when both conditions are met.

About RISC-V spec 16.3:

C.LDSP is only valid when rd=x0; the code points with rd=x0 are reserved.

About RISC-V priviledged spec 3.1.15:

To Reproduce

1. Assemble a program with a load instruction where the destination register is zero and ensure the load address is misaligned (
   It can be implemented using hardcoding.).
2. Load and execute the program on the NutShell.
3. Observe the type of exception raised.

Expected behavior
Based on the RISC-V specifications, when an Illegal Instruction exception and a Load Address Misaligned exception occur simultaneously, the mcause register should prioritize and process the Illegal Instruction exception over the Load Address Misaligned exception. This ensures consistency with the defined exception handling priorities in the RISC-V specifications.

Screenshots

Environment (optional, if necessary):
OS: Ubuntu 22.04.3 LTS
Compiler: gcc 11.4.0

Additional context
None

[youzi27]

Correction information, regarding RISC-V specification 16.3:

C.LDSP is only valid when rd != x0; the code points with rd=x0 are reserved.