AXI_QUAD_SPI connection problem

[Kgfu]

Hi author, thanks for your sharing about the design and python code.
I want to implement a SPI flash IP, and use the axi_quad_spi_o to test it.
From you vivado project, you use the following constrain file to point out the SPI pin connectoin:
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports spi_rtl_io1_io]
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports spi_rtl_io0_io]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_rtl_sck_o]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_rtl_ss_o]

My question : if I just want to connect my IP's (SPI slave) 4 pins (sclk, cs, mosi, miso) to the axi_quad_spi_o, which pins in SPI_0 I should connect them?

[EnricoGiordano1992]

Hi! You can just connect the single pins of the AXI Quad SPI. In particular, you can see the IO in this way:

• ends with _i: it is an input
• ends with _o: it is an output
• ends with _t: it is an input/output selector

So, you can just connect the io1_i (MISO, Master Input), io0_o (MOSI, Master Output), sck_o (clock output), ss_o (slave selector)