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neorv32.svd
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neorv32.svd
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<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
<vendor>litex</vendor>
<name>SOC</name>
<description><![CDATA[Litex SoC 2023-01-05 16:17:26]]></description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>CTRL</name>
<baseAddress>0x82000000</baseAddress>
<groupName>CTRL</groupName>
<registers>
<register>
<name>RESET</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>soc_rst</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write `1` to this register to reset the full SoC (Pulse Reset)]]></description>
</field>
<field>
<name>cpu_rst</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)]]></description>
</field>
</fields>
</register>
<register>
<name>SCRATCH</name>
<description><![CDATA[Use this register as a scratch space to verify that software read/write accesses
to the Wishbone/CSR bus are working correctly. The initial reset value of
0x1234578 can be used to verify endianness.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x12345678</resetValue>
<size>32</size>
<fields>
<field>
<name>scratch</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>BUS_ERRORS</name>
<description><![CDATA[Total number of Wishbone bus errors (timeouts) since start.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>bus_errors</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0xc</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>IDENTIFIER_MEM</name>
<baseAddress>0x82000800</baseAddress>
<groupName>IDENTIFIER_MEM</groupName>
<registers>
<register>
<name>IDENTIFIER_MEM</name>
<description><![CDATA[8 x 39-bit memory]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>identifier_mem</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>LEDS</name>
<baseAddress>0x82001000</baseAddress>
<groupName>LEDS</groupName>
<registers>
<register>
<name>OUT</name>
<description><![CDATA[Led Output(s) Control.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>out</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>SDRAM</name>
<baseAddress>0x82001800</baseAddress>
<groupName>SDRAM</groupName>
<registers>
<register>
<name>DFII_CONTROL</name>
<description><![CDATA[Control DFI signals common to all phases]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x01</resetValue>
<size>32</size>
<fields>
<field>
<name>sel</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[None]]></description>
</field>
<field>
<name>cke</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[DFI clock enable bus]]></description>
</field>
<field>
<name>odt</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[DFI on-die termination bus]]></description>
</field>
<field>
<name>reset_n</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[DFI clock reset bus]]></description>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_COMMAND</name>
<description><![CDATA[Control DFI signals on a single phase]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>cs</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[DFI chip select bus]]></description>
</field>
<field>
<name>we</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[DFI write enable bus]]></description>
</field>
<field>
<name>cas</name>
<msb>2</msb>
<bitRange>[2:2]</bitRange>
<lsb>2</lsb>
<description><![CDATA[DFI column address strobe bus]]></description>
</field>
<field>
<name>ras</name>
<msb>3</msb>
<bitRange>[3:3]</bitRange>
<lsb>3</lsb>
<description><![CDATA[DFI row address strobe bus]]></description>
</field>
<field>
<name>wren</name>
<msb>4</msb>
<bitRange>[4:4]</bitRange>
<lsb>4</lsb>
<description><![CDATA[DFI write data enable bus]]></description>
</field>
<field>
<name>rden</name>
<msb>5</msb>
<bitRange>[5:5]</bitRange>
<lsb>5</lsb>
<description><![CDATA[DFI read data enable bus]]></description>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_COMMAND_ISSUE</name>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dfii_pi0_command_issue</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_ADDRESS</name>
<description><![CDATA[DFI address bus]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dfii_pi0_address</name>
<msb>12</msb>
<bitRange>[12:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_BADDRESS</name>
<description><![CDATA[DFI bank address bus]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dfii_pi0_baddress</name>
<msb>1</msb>
<bitRange>[1:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_WRDATA</name>
<description><![CDATA[DFI write data bus]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dfii_pi0_wrdata</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>DFII_PI0_RDDATA</name>
<description><![CDATA[DFI read data bus]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>dfii_pi0_rddata</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x1c</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>SPISDCARD</name>
<baseAddress>0x82002000</baseAddress>
<groupName>SPISDCARD</groupName>
<registers>
<register>
<name>CONTROL</name>
<description><![CDATA[SPI Control.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>start</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[SPI Xfer Start (Write ``1`` to start Xfer).]]></description>
</field>
<field>
<name>length</name>
<msb>15</msb>
<bitRange>[15:8]</bitRange>
<lsb>8</lsb>
<description><![CDATA[SPI Xfer Length (in bits).]]></description>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description><![CDATA[SPI Status.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>done</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[SPI Xfer Done (when read as ``1``).]]></description>
</field>
</fields>
</register>
<register>
<name>MOSI</name>
<description><![CDATA[SPI MOSI data (MSB-first serialization).]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mosi</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>MISO</name>
<description><![CDATA[SPI MISO data (MSB-first de-serialization).]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>miso</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>CS</name>
<description><![CDATA[SPI CS Chip-Select and Mode.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x01</resetValue>
<size>32</size>
<fields>
<field>
<name>sel</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[None]]></description>
</field>
<field>
<name>mode</name>
<msb>16</msb>
<bitRange>[16:16]</bitRange>
<lsb>16</lsb>
<description><![CDATA[None]]></description>
</field>
</fields>
</register>
<register>
<name>LOOPBACK</name>
<description><![CDATA[SPI Loopback Mode.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>mode</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[None]]></description>
</field>
</fields>
</register>
<register>
<name>CLK_DIVIDER</name>
<description><![CDATA[SPI Clk Divider.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x7d</resetValue>
<size>32</size>
<fields>
<field>
<name>clk_divider</name>
<msb>15</msb>
<bitRange>[15:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x1c</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>TIMER0</name>
<baseAddress>0x82002800</baseAddress>
<groupName>TIMER0</groupName>
<registers>
<register>
<name>LOAD</name>
<description><![CDATA[Load value when Timer is (re-)enabled. In One-Shot mode, the value written to
this register specifies the Timer's duration in clock cycles.]]></description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>load</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RELOAD</name>
<description><![CDATA[Reload value when Timer reaches ``0``. In Periodic mode, the value written to
this register specify the Timer's period in clock cycles.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>reload</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EN</name>
<description><![CDATA[Enable flag of the Timer. Set this flag to ``1`` to enable/start the Timer. Set
to ``0`` to disable the Timer.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>en</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>UPDATE_VALUE</name>
<description><![CDATA[Update trigger for the current countdown value. A write to this register latches
the current countdown value to ``value`` register.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>update_value</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>VALUE</name>
<description><![CDATA[Latched countdown value. This value is updated by writing to ``update_value``.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>value</name>
<msb>31</msb>
<bitRange>[31:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the zero event trigger. Writes
to this register have no effect.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``zero`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a zero event occurs, the corresponding bit will be set in this register.
To clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `zero` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding zero events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>zero</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``zero`` Event]]></description>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
<peripheral>
<name>UART</name>
<baseAddress>0x82003000</baseAddress>
<groupName>UART</groupName>
<registers>
<register>
<name>RXTX</name>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxtx</name>
<msb>7</msb>
<bitRange>[7:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>TXFULL</name>
<description><![CDATA[TX FIFO Full.]]></description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXEMPTY</name>
<description><![CDATA[RX FIFO Empty.]]></description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>EV_STATUS</name>
<description><![CDATA[This register contains the current raw level of the rx event trigger. Writes to
this register have no effect.]]></description>
<addressOffset>0x000c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Level of the ``tx`` event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Level of the ``rx`` event]]></description>
</field>
</fields>
</register>
<register>
<name>EV_PENDING</name>
<description><![CDATA[When a rx event occurs, the corresponding bit will be set in this register. To
clear the Event, set the corresponding bit in this register.]]></description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[`1` if a `tx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[`1` if a `rx` event occurred. This Event is triggered on a **falling** edge.]]></description>
</field>
</fields>
</register>
<register>
<name>EV_ENABLE</name>
<description><![CDATA[This register enables the corresponding rx events. Write a ``0`` to this
register to disable individual events.]]></description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>tx</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
<description><![CDATA[Write a ``1`` to enable the ``tx`` Event]]></description>
</field>
<field>
<name>rx</name>
<msb>1</msb>
<bitRange>[1:1]</bitRange>
<lsb>1</lsb>
<description><![CDATA[Write a ``1`` to enable the ``rx`` Event]]></description>
</field>
</fields>
</register>
<register>
<name>TXEMPTY</name>
<description><![CDATA[TX FIFO Empty.]]></description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>txempty</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
<register>
<name>RXFULL</name>
<description><![CDATA[RX FIFO Full.]]></description>
<addressOffset>0x001c</addressOffset>
<resetValue>0x00</resetValue>
<size>32</size>
<fields>
<field>
<name>rxfull</name>
<msb>0</msb>
<bitRange>[0:0]</bitRange>
<lsb>0</lsb>
</field>
</fields>
</register>
</registers>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
</peripheral>
</peripherals>
<vendorExtensions>
<memoryRegions>
<memoryRegion>
<name>ROM</name>
<baseAddress>0x00000000</baseAddress>
<size>0x00020000</size>
</memoryRegion>
<memoryRegion>
<name>SRAM</name>
<baseAddress>0x01000000</baseAddress>
<size>0x00002000</size>
</memoryRegion>
<memoryRegion>
<name>MAIN_RAM</name>
<baseAddress>0x40000000</baseAddress>
<size>0x02000000</size>
</memoryRegion>
<memoryRegion>
<name>CSR</name>
<baseAddress>0x82000000</baseAddress>
<size>0x00010000</size>
</memoryRegion>
</memoryRegions>
<constants>
<constant name="CONFIG_CLOCK_FREQUENCY" value="50000000" />
<constant name="CONFIG_CPU_RESET_ADDR" value="0" />
<constant name="CONFIG_CPU_TYPE_NEORV32" value="None" />
<constant name="CONFIG_CPU_VARIANT_FULL" value="None" />
<constant name="CONFIG_CPU_HUMAN_NAME" value="NEORV32-full" />
<constant name="CONFIG_CPU_NOP" value="nop" />
<constant name="UART_POLLING" value="None" />
<constant name="CONFIG_L2_SIZE" value="8192" />
<constant name="CONFIG_CSR_DATA_WIDTH" value="32" />
<constant name="CONFIG_CSR_ALIGNMENT" value="32" />
<constant name="CONFIG_BUS_STANDARD" value="WISHBONE" />
<constant name="CONFIG_BUS_DATA_WIDTH" value="32" />
<constant name="CONFIG_BUS_ADDRESS_WIDTH" value="32" />
<constant name="CONFIG_BUS_BURSTING" value="0" />
</constants>
</vendorExtensions>
</device>