forked from micropython/micropython
-
Notifications
You must be signed in to change notification settings - Fork 3
/
powerctrl.c
1128 lines (987 loc) · 37.5 KB
/
powerctrl.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2013-2018 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "py/mperrno.h"
#include "py/mphal.h"
#include "powerctrl.h"
#include "rtc.h"
#include "genhdr/pllfreqtable.h"
#include "extmod/modbluetooth.h"
#if defined(STM32H5) || defined(STM32H7)
#define RCC_SR RSR
#if defined(STM32H747xx)
#define RCC_SR_SFTRSTF RCC_RSR_SFT2RSTF
#else
#define RCC_SR_SFTRSTF RCC_RSR_SFTRSTF
#endif
#define RCC_SR_RMVF RCC_RSR_RMVF
// This macro returns the actual voltage scaling level factoring in the power overdrive bit.
// If the current voltage scale is VOLTAGE_SCALE1 and PWER_ODEN bit is set return VOLTAGE_SCALE0
// otherwise the current voltage scaling (level VOS1 to VOS3) set in PWER_CSR is returned instead.
#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
// TODO
#define POWERCTRL_GET_VOLTAGE_SCALING() PWR_REGULATOR_VOLTAGE_SCALE0
#elif defined(STM32H723xx)
#define POWERCTRL_GET_VOLTAGE_SCALING() LL_PWR_GetRegulVoltageScaling()
#elif defined(STM32H5)
#define POWERCTRL_GET_VOLTAGE_SCALING() LL_PWR_GetRegulVoltageScaling()
#else
#define POWERCTRL_GET_VOLTAGE_SCALING() \
(((PWR->CSR1 & PWR_CSR1_ACTVOS) && (SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN)) ? \
PWR_REGULATOR_VOLTAGE_SCALE0 : (PWR->CSR1 & PWR_CSR1_ACTVOS))
#endif
#else
#define RCC_SR CSR
#define RCC_SR_SFTRSTF RCC_CSR_SFTRSTF
#define RCC_SR_RMVF RCC_CSR_RMVF
#endif
// Whether this MCU has an independent PLL which can generate 48MHz for USB.
#if defined(STM32F413xx)
// STM32F413 uses PLLI2S as secondary PLL.
#define HAVE_PLL48 1
#define RCC_CR_PLL48_ON RCC_CR_PLLI2SON
#define RCC_CR_PLL48_RDY RCC_CR_PLLI2SRDY
#elif defined(STM32F7)
// STM32F7 uses PLLSAI as secondary PLL.
#define HAVE_PLL48 1
#define RCC_CR_PLL48_ON RCC_CR_PLLSAION
#define RCC_CR_PLL48_RDY RCC_CR_PLLSAIRDY
#else
// MCU does not have a secondary PLL.
#define HAVE_PLL48 0
#endif
#if MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET
// Location in RAM of bootloader state (just after the top of the stack).
// STM32H7 has ECC and writes to RAM must be 64-bit so they are fully committed
// to actual SRAM before a system reset occurs.
#define BL_STATE_PTR ((uint64_t *)&_bl_state)
#define BL_STATE_KEY (0x5a5)
#define BL_STATE_KEY_MASK (0xfff)
#define BL_STATE_KEY_SHIFT (32)
#define BL_STATE_INVALID (0)
#define BL_STATE_VALID(reg, addr) ((uint64_t)(reg) | ((uint64_t)((addr) | BL_STATE_KEY)) << BL_STATE_KEY_SHIFT)
#define BL_STATE_GET_REG(s) ((s) & 0xffffffff)
#define BL_STATE_GET_KEY(s) (((s) >> BL_STATE_KEY_SHIFT) & BL_STATE_KEY_MASK)
#define BL_STATE_GET_ADDR(s) (((s) >> BL_STATE_KEY_SHIFT) & ~BL_STATE_KEY_MASK)
extern uint64_t _bl_state[];
#endif
static inline void powerctrl_disable_hsi_if_unused(void) {
#if !MICROPY_HW_CLK_USE_HSI && (defined(STM32F4) || defined(STM32F7) || defined(STM32H7))
// Disable HSI if it's not used to save a little bit of power
__HAL_RCC_HSI_DISABLE();
#endif
}
NORETURN void powerctrl_mcu_reset(void) {
#if MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET
*BL_STATE_PTR = BL_STATE_INVALID;
#if __DCACHE_PRESENT == 1
SCB_CleanDCache();
#endif
#endif
NVIC_SystemReset();
}
NORETURN static __attribute__((naked)) void branch_to_bootloader(uint32_t r0, uint32_t bl_addr) {
__asm volatile (
"ldr r2, [r1, #0]\n" // get address of stack pointer
"msr msp, r2\n" // get stack pointer
"ldr r2, [r1, #4]\n" // get address of destination
"bx r2\n" // branch to bootloader
);
MP_UNREACHABLE;
}
NORETURN void powerctrl_enter_bootloader(uint32_t r0, uint32_t bl_addr) {
#if MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET
// Enter the bootloader via a reset, so everything is reset (including WDT).
// Upon reset powerctrl_check_enter_bootloader() will jump to the bootloader.
*BL_STATE_PTR = BL_STATE_VALID(r0, bl_addr);
#if __DCACHE_PRESENT == 1
SCB_CleanDCache();
#endif
NVIC_SystemReset();
#else
// Enter the bootloader via a direct jump.
branch_to_bootloader(r0, bl_addr);
#endif
}
void powerctrl_check_enter_bootloader(void) {
#if MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET
uint64_t bl_state = *BL_STATE_PTR;
*BL_STATE_PTR = BL_STATE_INVALID;
if (BL_STATE_GET_KEY(bl_state) == BL_STATE_KEY && (RCC->RCC_SR & RCC_SR_SFTRSTF)) {
// Reset by NVIC_SystemReset with bootloader data set -> branch to bootloader
RCC->RCC_SR = RCC_SR_RMVF;
#if defined(STM32F0) || defined(STM32F4) || defined(STM32G0) || defined(STM32G4) || defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32WB)
__HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH();
#endif
branch_to_bootloader(BL_STATE_GET_REG(bl_state), BL_STATE_GET_ADDR(bl_state));
}
#endif
}
#if !defined(STM32F0) && !defined(STM32L0) && !defined(STM32WB) && !defined(STM32WL)
typedef struct _sysclk_scaling_table_entry_t {
uint16_t mhz;
uint16_t value;
} sysclk_scaling_table_entry_t;
#if defined(STM32F7)
static const sysclk_scaling_table_entry_t volt_scale_table[] = {
{ 151, PWR_REGULATOR_VOLTAGE_SCALE3 },
{ 180, PWR_REGULATOR_VOLTAGE_SCALE2 },
// Above 180MHz uses default PWR_REGULATOR_VOLTAGE_SCALE1
};
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \
defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
static const sysclk_scaling_table_entry_t volt_scale_table[] = {
// See table 15 "FLASH recommended number of wait states and programming delay" of RM0455.
{88, PWR_REGULATOR_VOLTAGE_SCALE3},
{160, PWR_REGULATOR_VOLTAGE_SCALE2},
{225, PWR_REGULATOR_VOLTAGE_SCALE1},
{280, PWR_REGULATOR_VOLTAGE_SCALE0},
};
#elif defined(STM32H7)
static const sysclk_scaling_table_entry_t volt_scale_table[] = {
// See table 55 "Kernel clock distribution overview" of RM0433.
{200, PWR_REGULATOR_VOLTAGE_SCALE3},
{300, PWR_REGULATOR_VOLTAGE_SCALE2},
// Above 300MHz uses default PWR_REGULATOR_VOLTAGE_SCALE1
// (above 400MHz needs special handling for overdrive, currently unsupported)
};
#endif
static int powerctrl_config_vos(uint32_t sysclk_mhz) {
#if defined(STM32F7) || defined(STM32H7)
uint32_t volt_scale = PWR_REGULATOR_VOLTAGE_SCALE1;
for (int i = 0; i < MP_ARRAY_SIZE(volt_scale_table); ++i) {
if (sysclk_mhz <= volt_scale_table[i].mhz) {
volt_scale = volt_scale_table[i].value;
break;
}
}
if (HAL_PWREx_ControlVoltageScaling(volt_scale) != HAL_OK) {
return -MP_EIO;
}
#endif
return 0;
}
// Assumes that PLL is used as the SYSCLK source
int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk_mhz, bool need_pll48) {
uint32_t flash_latency;
#if HAVE_PLL48
if (need_pll48) {
// Configure secondary PLL at 48MHz for those peripherals that need this freq
// (the calculation assumes it can get an integral value of PLL-N).
#if defined(STM32F413xx)
const uint32_t plli2sm = HSE_VALUE / 1000000;
const uint32_t plli2sq = 2;
const uint32_t plli2sr = 2;
const uint32_t plli2sn = 48 * plli2sq;
RCC->PLLI2SCFGR = plli2sr << RCC_PLLI2SCFGR_PLLI2SR_Pos
| plli2sq << RCC_PLLI2SCFGR_PLLI2SQ_Pos
| plli2sn << RCC_PLLI2SCFGR_PLLI2SN_Pos
| plli2sm << RCC_PLLI2SCFGR_PLLI2SM_Pos;
#else
const uint32_t pllm = (RCC->PLLCFGR >> RCC_PLLCFGR_PLLM_Pos) & 0x3f;
const uint32_t pllsaip = 4;
const uint32_t pllsaiq = 2;
const uint32_t pllsain = 48 * pllsaip * pllm / (HSE_VALUE / 1000000);
RCC->PLLSAICFGR = pllsaiq << RCC_PLLSAICFGR_PLLSAIQ_Pos
| (pllsaip / 2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos
| pllsain << RCC_PLLSAICFGR_PLLSAIN_Pos;
#endif
// Turn on the PLL and wait for it to be ready.
RCC->CR |= RCC_CR_PLL48_ON;
uint32_t ticks = mp_hal_ticks_ms();
while (!(RCC->CR & RCC_CR_PLL48_RDY)) {
if (mp_hal_ticks_ms() - ticks > 200) {
return -MP_ETIMEDOUT;
}
}
// Select the alternate 48MHz source.
RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
}
#endif
// If possible, scale down the internal voltage regulator to save power
int ret = powerctrl_config_vos(sysclk_mhz);
if (ret) {
return ret;
}
#if defined(STM32F7)
// These flash_latency values assume a supply voltage between 2.7V and 3.6V
if (sysclk_mhz <= 30) {
flash_latency = FLASH_LATENCY_0;
} else if (sysclk_mhz <= 60) {
flash_latency = FLASH_LATENCY_1;
} else if (sysclk_mhz <= 90) {
flash_latency = FLASH_LATENCY_2;
} else if (sysclk_mhz <= 120) {
flash_latency = FLASH_LATENCY_3;
} else if (sysclk_mhz <= 150) {
flash_latency = FLASH_LATENCY_4;
} else if (sysclk_mhz <= 180) {
flash_latency = FLASH_LATENCY_5;
} else if (sysclk_mhz <= 210) {
flash_latency = FLASH_LATENCY_6;
} else {
flash_latency = FLASH_LATENCY_7;
}
#elif defined(MICROPY_HW_FLASH_LATENCY)
flash_latency = MICROPY_HW_FLASH_LATENCY;
#else
flash_latency = FLASH_LATENCY_5;
#endif
rcc_init->SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
if (HAL_RCC_ClockConfig(rcc_init, flash_latency) != HAL_OK) {
return -MP_EIO;
}
powerctrl_disable_hsi_if_unused();
return 0;
}
#endif
#if !defined(STM32F0) && !defined(STM32G0) && !defined(STM32L0) && !defined(STM32L1) && !defined(STM32L4)
static uint32_t calc_ahb_div(uint32_t wanted_div) {
#if defined(STM32H7)
if (wanted_div <= 1) {
return RCC_HCLK_DIV1;
} else if (wanted_div <= 2) {
return RCC_HCLK_DIV2;
} else if (wanted_div <= 4) {
return RCC_HCLK_DIV4;
} else if (wanted_div <= 8) {
return RCC_HCLK_DIV8;
} else if (wanted_div <= 16) {
return RCC_HCLK_DIV16;
} else if (wanted_div <= 64) {
return RCC_HCLK_DIV64;
} else if (wanted_div <= 128) {
return RCC_HCLK_DIV128;
} else if (wanted_div <= 256) {
return RCC_HCLK_DIV256;
} else {
return RCC_HCLK_DIV512;
}
#else
if (wanted_div <= 1) {
return RCC_SYSCLK_DIV1;
} else if (wanted_div <= 2) {
return RCC_SYSCLK_DIV2;
} else if (wanted_div <= 4) {
return RCC_SYSCLK_DIV4;
} else if (wanted_div <= 8) {
return RCC_SYSCLK_DIV8;
} else if (wanted_div <= 16) {
return RCC_SYSCLK_DIV16;
} else if (wanted_div <= 64) {
return RCC_SYSCLK_DIV64;
} else if (wanted_div <= 128) {
return RCC_SYSCLK_DIV128;
} else if (wanted_div <= 256) {
return RCC_SYSCLK_DIV256;
} else {
return RCC_SYSCLK_DIV512;
}
#endif
}
static uint32_t calc_apb1_div(uint32_t wanted_div) {
#if defined(STM32H7)
if (wanted_div <= 1) {
return RCC_APB1_DIV1;
} else if (wanted_div <= 2) {
return RCC_APB1_DIV2;
} else if (wanted_div <= 4) {
return RCC_APB1_DIV4;
} else if (wanted_div <= 8) {
return RCC_APB1_DIV8;
} else {
return RCC_APB1_DIV16;
}
#else
if (wanted_div <= 1) {
return RCC_HCLK_DIV1;
} else if (wanted_div <= 2) {
return RCC_HCLK_DIV2;
} else if (wanted_div <= 4) {
return RCC_HCLK_DIV4;
} else if (wanted_div <= 8) {
return RCC_HCLK_DIV8;
} else {
return RCC_HCLK_DIV16;
}
#endif
}
static uint32_t calc_apb2_div(uint32_t wanted_div) {
#if defined(STM32H7)
if (wanted_div <= 1) {
return RCC_APB2_DIV1;
} else if (wanted_div <= 2) {
return RCC_APB2_DIV2;
} else if (wanted_div <= 4) {
return RCC_APB2_DIV4;
} else if (wanted_div <= 8) {
return RCC_APB2_DIV8;
} else {
return RCC_APB2_DIV16;
}
#else
return calc_apb1_div(wanted_div);
#endif
}
#if defined(STM32F4) || defined(STM32F7) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7)
int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2) {
// Return straight away if the clocks are already at the desired frequency
if (sysclk == HAL_RCC_GetSysClockFreq()
&& ahb == HAL_RCC_GetHCLKFreq()
&& apb1 == HAL_RCC_GetPCLK1Freq()
#if !defined(STM32G0)
&& apb2 == HAL_RCC_GetPCLK2Freq()
#endif
) {
return 0;
}
// Default PLL parameters that give 48MHz on PLL48CK
uint32_t m = MICROPY_HW_CLK_VALUE / 1000000, n = 336, p = 2, q = 7;
uint32_t sysclk_source;
bool need_pll48 = false;
// Search for a valid PLL configuration that keeps USB at 48MHz
uint32_t sysclk_mhz = sysclk / 1000000;
for (const pll_freq_table_t *pll = &pll_freq_table[MP_ARRAY_SIZE(pll_freq_table) - 1]; pll >= &pll_freq_table[0]; --pll) {
uint32_t sys = PLL_FREQ_TABLE_SYS(*pll);
if (sys <= sysclk_mhz) {
m = PLL_FREQ_TABLE_M(*pll);
p = PLL_FREQ_TABLE_P(*pll);
if (m == 0) {
// special entry for using HSI directly
sysclk_source = RCC_SYSCLKSOURCE_HSI;
} else if (m == 1) {
// special entry for using HSE directly
sysclk_source = RCC_SYSCLKSOURCE_HSE;
} else {
// use PLL
sysclk_source = RCC_SYSCLKSOURCE_PLLCLK;
uint32_t vco_out = sys * p;
n = vco_out * m / (MICROPY_HW_CLK_VALUE / 1000000);
q = vco_out / 48;
#if HAVE_PLL48
need_pll48 = vco_out % 48 != 0;
#endif
}
goto set_clk;
}
}
return -MP_EINVAL;
set_clk:
// Let the USB CDC have a chance to process before we change the clock
mp_hal_delay_ms(5);
// Desired system clock source is in sysclk_source
RCC_ClkInitTypeDef RCC_ClkInitStruct;
#if defined(STM32G0) || defined(STM32G4)
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_ALL;
#else
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
#endif
if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
// Set HSE as system clock source to allow modification of the PLL configuration
// We then change to PLL after re-configuring PLL
#if MICROPY_HW_CLK_USE_HSI
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
#else
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
#endif
} else {
// Directly set the system clock source as desired
RCC_ClkInitStruct.SYSCLKSource = sysclk_source;
}
// Determine the bus clock dividers
// Note: AHB freq required to be >= 14.2MHz for USB operation
RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb);
#if defined(STM32H5)
ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR2_HPRE_Pos];
#elif defined(STM32H7)
// Do nothing.
#else
ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos];
#endif
RCC_ClkInitStruct.APB1CLKDivider = calc_apb1_div(ahb / apb1);
#if !defined(STM32G0)
RCC_ClkInitStruct.APB2CLKDivider = calc_apb2_div(ahb / apb2);
#endif
#if defined(STM32H5)
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
#endif
#if defined(STM32H7)
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = MICROPY_HW_CLK_APB3_DIV;
RCC_ClkInitStruct.APB4CLKDivider = MICROPY_HW_CLK_APB4_DIV;
#endif
#if MICROPY_HW_CLK_LAST_FREQ
// Save the bus dividers for use later
uint32_t h = RCC_ClkInitStruct.AHBCLKDivider >> 4;
uint32_t b1 = RCC_ClkInitStruct.APB1CLKDivider >> 10;
uint32_t b2 = RCC_ClkInitStruct.APB2CLKDivider >> 10;
#endif
// Configure clock
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return -MP_EIO;
}
#if HAVE_PLL48
// Deselect PLLSAI as 48MHz source if we were using it
RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_CK48MSEL;
// Turn PLLSAI off because we are changing PLLM (which drives PLLSAI)
RCC->CR &= ~RCC_CR_PLL48_ON;
#endif
// Re-configure PLL
// Even if we don't use the PLL for the system clock, we still need it for USB, RNG and SDIO
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_OscInitStruct.OscillatorType = MICROPY_HW_RCC_OSCILLATOR_TYPE;
RCC_OscInitStruct.HSEState = MICROPY_HW_RCC_HSE_STATE;
RCC_OscInitStruct.HSIState = MICROPY_HW_RCC_HSI_STATE;
#if defined(STM32G0) || defined(STM32H5)
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
#endif
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = MICROPY_HW_RCC_PLL_SRC;
RCC_OscInitStruct.PLL.PLLM = m;
RCC_OscInitStruct.PLL.PLLN = n;
RCC_OscInitStruct.PLL.PLLP = p;
RCC_OscInitStruct.PLL.PLLQ = q;
#if defined(STM32H5)
RCC_OscInitStruct.PLL.PLLR = 0;
if (MICROPY_HW_CLK_VALUE / 1000000 <= 2 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_0; // 1-2MHz
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 4 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; // 2-4MHz
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 8 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; // 4-8MHz
} else {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; // 8-16MHz
}
if (MICROPY_HW_CLK_VALUE / 1000000 * n <= 420 * m) {
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_MEDIUM; // 150-420MHz
} else {
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; // 192-836MHz
}
RCC_OscInitStruct.PLL.PLLFRACN = 0;
#elif defined(STM32H7)
RCC_OscInitStruct.PLL.PLLR = 0;
if (MICROPY_HW_CLK_VALUE / 1000000 <= 2 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; // 1-2MHz
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 4 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; // 2-4MHz
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 8 * m) {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; // 4-8MHz
} else {
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; // 8-16MHz
}
if (MICROPY_HW_CLK_VALUE / 1000000 * n <= 420 * m) {
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; // 150-420MHz
} else {
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; // 192-960MHz
}
RCC_OscInitStruct.PLL.PLLFRACN = 0;
#endif
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return -MP_EIO;
}
// Set PLL as system clock source if wanted
if (sysclk_source == RCC_SYSCLKSOURCE_PLLCLK) {
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
int ret = powerctrl_rcc_clock_config_pll(&RCC_ClkInitStruct, sysclk_mhz, need_pll48);
if (ret != 0) {
return ret;
}
}
#if MICROPY_HW_CLK_LAST_FREQ
// Save settings in RTC backup register to reconfigure clocks on hard-reset
#if defined(STM32F7)
#define FREQ_BKP BKP31R
#else
#define FREQ_BKP BKP19R
#endif
// qqqqqqqq pppppppp nnnnnnnn nnmmmmmm
// qqqqQQQQ ppppppPP nNNNNNNN NNMMMMMM
// 222111HH HHQQQQPP nNNNNNNN NNMMMMMM
p = (p / 2) - 1;
RTC->FREQ_BKP = m
| (n << 6) | (p << 16) | (q << 18)
| (h << 22)
| (b1 << 26)
| (b2 << 29);
#endif
return 0;
}
#elif defined(STM32WB) || defined(STM32WL)
#if defined(STM32WB)
#include "stm32wbxx_ll_utils.h"
#define FLASH_LATENCY_MAX LL_FLASH_LATENCY_3
#else
#include "stm32wlxx_ll_utils.h"
#define FLASH_LATENCY_MAX LL_FLASH_LATENCY_2
#endif
#define LPR_THRESHOLD (2000000)
#define VOS2_THRESHOLD (16000000)
enum {
SYSCLK_MODE_NONE,
SYSCLK_MODE_MSI,
SYSCLK_MODE_HSE_64M,
};
int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2) {
int sysclk_mode = SYSCLK_MODE_NONE;
uint32_t msirange = 0;
uint32_t sysclk_cur = HAL_RCC_GetSysClockFreq();
if (sysclk == sysclk_cur) {
// SYSCLK does not need changing.
} else if (sysclk == 64000000) {
sysclk_mode = SYSCLK_MODE_HSE_64M;
} else {
for (msirange = 0; msirange < MP_ARRAY_SIZE(MSIRangeTable); ++msirange) {
if (MSIRangeTable[msirange] != 0 && sysclk == MSIRangeTable[msirange]) {
sysclk_mode = SYSCLK_MODE_MSI;
break;
}
}
if (sysclk_mode == SYSCLK_MODE_NONE) {
// Unsupported SYSCLK value.
return -MP_EINVAL;
}
}
// Exit LPR if SYSCLK will increase beyond threshold.
if (LL_PWR_IsEnabledLowPowerRunMode()) {
if (sysclk > LPR_THRESHOLD) {
if (sysclk_cur < LPR_THRESHOLD) {
// Must select MSI=LPR_THRESHOLD=2MHz to exit LPR.
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
}
// Exit LPR and wait for the regulator to be ready.
LL_PWR_ExitLowPowerRunMode();
while (!LL_PWR_IsActiveFlag_REGLPF()) {
}
}
}
// Select VOS1 if SYSCLK will increase beyond threshold.
if (sysclk > VOS2_THRESHOLD) {
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
while (LL_PWR_IsActiveFlag_VOS()) {
}
}
if (sysclk_mode == SYSCLK_MODE_HSE_64M) {
SystemClock_Config();
} else if (sysclk_mode == SYSCLK_MODE_MSI) {
// Set flash latency to maximum to ensure the latency is large enough for
// both the current SYSCLK and the SYSCLK that will be selected below.
LL_FLASH_SetLatency(FLASH_LATENCY_MAX);
while (LL_FLASH_GetLatency() != FLASH_LATENCY_MAX) {
}
// Before changing the MSIRANGE value, if MSI is on then it must also be ready.
while ((RCC->CR & (RCC_CR_MSIRDY | RCC_CR_MSION)) == RCC_CR_MSION) {
}
LL_RCC_MSI_SetRange(msirange << RCC_CR_MSIRANGE_Pos);
// Clock SYSCLK from MSI.
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) {
}
// Disable PLL to decrease power consumption.
LL_RCC_PLL_Disable();
while (LL_RCC_PLL_IsReady() != 0) {
}
LL_RCC_PLL_DisableDomain_SYS();
// Select VOS2 if possible.
if (sysclk <= VOS2_THRESHOLD) {
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
}
// Enter LPR if possible.
if (sysclk <= LPR_THRESHOLD) {
LL_PWR_EnterLowPowerRunMode();
}
// Configure flash latency for the new SYSCLK.
LL_SetFlashLatency(sysclk);
// Update HAL state and SysTick.
SystemCoreClockUpdate();
powerctrl_config_systick();
}
// Return straight away if the clocks are already at the desired frequency.
if (ahb == HAL_RCC_GetHCLKFreq()
&& apb1 == HAL_RCC_GetPCLK1Freq()
&& apb2 == HAL_RCC_GetPCLK2Freq()) {
return 0;
}
// Calculate and configure the bus clock dividers.
uint32_t cfgr = RCC->CFGR;
cfgr &= ~(7 << RCC_CFGR_PPRE2_Pos | 7 << RCC_CFGR_PPRE1_Pos | 0xf << RCC_CFGR_HPRE_Pos);
cfgr |= calc_ahb_div(sysclk / ahb);
cfgr |= calc_apb1_div(ahb / apb1);
cfgr |= calc_apb2_div(ahb / apb2) << (RCC_CFGR_PPRE2_Pos - RCC_CFGR_PPRE1_Pos);
RCC->CFGR = cfgr;
return 0;
}
#if defined(STM32WB)
static void powerctrl_switch_on_HSI(void) {
LL_RCC_HSI_Enable();
while (!LL_RCC_HSI_IsReady()) {
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
}
return;
}
static void powerctrl_low_power_prep_wb55() {
// See WB55 specific documentation in AN5289 Rev 6, and in particular, Figure 6.
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
if (!LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID)) {
if (LL_PWR_IsActiveFlag_C2DS() || LL_PWR_IsActiveFlag_C2SB()) {
// Release ENTRY_STOP_MODE semaphore
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
powerctrl_switch_on_HSI();
}
} else {
powerctrl_switch_on_HSI();
}
// Release RCC semaphore
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
static void powerctrl_low_power_exit_wb55() {
// Ensure the HSE/HSI clock configuration is correct so core2 can wake properly again.
// See WB55 specific documentation in AN5289 Rev 6, and in particular, Figure 7.
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
// Acquire RCC semaphore before adjusting clocks.
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
// Restore the clock configuration of the application
LL_RCC_HSE_Enable();
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
while (!LL_RCC_HSE_IsReady()) {
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
}
}
// Release RCC semaphore
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
#endif // defined(STM32WB)
#endif // defined(STM32WB) || defined(STM32WL)
#endif // !defined(STM32F0) && !defined(STM32G0) && !defined(STM32L0) && !defined(STM32L1) && !defined(STM32L4)
void powerctrl_enter_stop_mode(void) {
// Disable IRQs so that the IRQ that wakes the device from stop mode is not
// executed until after the clocks are reconfigured
uint32_t irq_state = disable_irq();
#if defined(STM32H7) || \
defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32WB55xx) || defined(STM32WB35xx)
// Disable SysTick Interrupt
// Note: This seems to be required at least on the H7 REV Y,
// otherwise the MCU will leave stop mode immediately on entry.
// Note: According to ST Errata ES0206 Rev 18, Section 2.2.1 this is needed
// for STM32F427xx, STM32F437xx, STM32F429xx and STM32F439xx
// Note: According to ST Errata ES0394 Rev 11, Section 2.2.17 this is needed
// for STM32WB55xx and STM32WB35xx
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
#endif
#if defined(MICROPY_BOARD_ENTER_STOP)
MICROPY_BOARD_ENTER_STOP
#endif
#if defined(STM32L4)
// Configure the MSI as the clock source after waking up
__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI);
#endif
#if !defined(STM32F0) && !defined(STM32G0) && !defined(STM32G4) && !defined(STM32L0) && !defined(STM32L1) && !defined(STM32L4) && !defined(STM32WB) && !defined(STM32WL)
// takes longer to wake but reduces stop current
HAL_PWREx_EnableFlashPowerDown();
#endif
#if defined(STM32H5)
// Save RCC CR to re-enable OSCs and PLLs after wake up from low power mode.
uint32_t rcc_cr = RCC->CR;
// Save the current voltage scaling level to restore after exiting low power mode.
uint32_t vscaling = POWERCTRL_GET_VOLTAGE_SCALING();
#endif
#if defined(STM32H7)
// Save RCC CR to re-enable OSCs and PLLs after wake up from low power mode.
uint32_t rcc_cr = RCC->CR;
// Save the current voltage scaling level to restore after exiting low power mode.
uint32_t vscaling = POWERCTRL_GET_VOLTAGE_SCALING();
// If the current voltage scaling level is 0, switch to level 1 before entering low power mode.
if (vscaling == PWR_REGULATOR_VOLTAGE_SCALE0) {
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
// Wait for PWR_FLAG_VOSRDY
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
}
}
#endif
#if defined(STM32WB)
powerctrl_low_power_prep_wb55();
#endif
#if defined(MICROPY_BOARD_PRE_STOP)
MICROPY_BOARD_PRE_STOP
#endif
#if defined(STM32F7)
HAL_PWR_EnterSTOPMode((PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS | PWR_CR1_UDEN), PWR_STOPENTRY_WFI);
#else
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
#endif
#if defined(MICROPY_BOARD_POST_STOP)
MICROPY_BOARD_POST_STOP
#endif
// reconfigure the system clock after waking up
#if defined(STM32F0)
// Enable HSI48
__HAL_RCC_HSI48_ENABLE();
while (!__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY)) {
}
// Select HSI48 as system clock source
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_HSI48);
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI48) {
}
#else // defined(STM32F0)
#if defined(STM32H5) || defined(STM32H7)
// When exiting from Stop or Standby modes, the Run mode voltage scaling is reset to
// the default VOS3 value. Restore the voltage scaling to the previous voltage scale.
if (vscaling != POWERCTRL_GET_VOLTAGE_SCALING()) {
__HAL_PWR_VOLTAGESCALING_CONFIG(vscaling);
// Wait for PWR_FLAG_VOSRDY
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
}
}
#endif
#if defined(STM32WB)
powerctrl_low_power_exit_wb55();
#endif
#if !defined(STM32L4)
// enable clock
__HAL_RCC_HSE_CONFIG(MICROPY_HW_RCC_HSE_STATE);
#if MICROPY_HW_CLK_USE_HSI
__HAL_RCC_HSI_ENABLE();
#endif
while (!__HAL_RCC_GET_FLAG(MICROPY_HW_RCC_FLAG_HSxRDY)) {
}
#endif
#if defined(STM32F7)
// Enable overdrive to reach 216MHz (if needed)
HAL_PWREx_EnableOverDrive();
#endif
#if defined(STM32H5)
// Enable PLL1, and switch the system clock source to PLL1P.
LL_RCC_PLL1_Enable();
while (!LL_RCC_PLL1_IsReady()) {
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
}
#else // defined(STM32H5)
// enable PLL
__HAL_RCC_PLL_ENABLE();
while (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)) {
}
// select PLL as system clock source
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
#if defined(STM32H7)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) {
}
#elif defined(STM32G0) || defined(STM32WB) || defined(STM32WL)
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) {
}
#else
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) {
}
#endif
#endif // defined(STM32H5)
powerctrl_disable_hsi_if_unused();
#if HAVE_PLL48
if (RCC->DCKCFGR2 & RCC_DCKCFGR2_CK48MSEL) {
// Enable PLLSAI if it is selected as 48MHz source
RCC->CR |= RCC_CR_PLL48_ON;
while (!(RCC->CR & RCC_CR_PLL48_RDY)) {
}
}
#endif
#if defined(STM32H5)
if (rcc_cr & RCC_CR_HSI48ON) {
// Enable HSI48.
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady()) {
}
}
#endif
#if defined(STM32H7)
// Enable HSI
if (rcc_cr & RCC_CR_HSION) {
RCC->CR |= RCC_CR_HSION;
while (!(RCC->CR & RCC_CR_HSIRDY)) {
}
}
// Enable CSI
if (rcc_cr & RCC_CR_CSION) {
RCC->CR |= RCC_CR_CSION;
while (!(RCC->CR & RCC_CR_CSIRDY)) {
}
}
// Enable HSI48
if (rcc_cr & RCC_CR_HSI48ON) {
RCC->CR |= RCC_CR_HSI48ON;
while (!(RCC->CR & RCC_CR_HSI48RDY)) {
}
}
// Enable PLL2
if (rcc_cr & RCC_CR_PLL2ON) {
RCC->CR |= RCC_CR_PLL2ON;
while (!(RCC->CR & RCC_CR_PLL2RDY)) {
}
}
// Enable PLL3
if (rcc_cr & RCC_CR_PLL3ON) {
RCC->CR |= RCC_CR_PLL3ON;
while (!(RCC->CR & RCC_CR_PLL3RDY)) {
}
}
#endif
#if defined(STM32L4)
// Enable PLLSAI1 for peripherals that use it
RCC->CR |= RCC_CR_PLLSAI1ON;
while (!(RCC->CR & RCC_CR_PLLSAI1RDY)) {
}
#endif
#endif
#if defined(MICROPY_BOARD_LEAVE_STOP)
MICROPY_BOARD_LEAVE_STOP
#endif
#if defined(STM32H7) || \
defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32WB55xx) || defined(STM32WB35xx)
// Enable SysTick Interrupt
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
#endif
// Enable IRQs now that all clocks are reconfigured