Enable PCIe gen 2 - patch for imx6qdl.dtsi for fixed ventana revisions available?

[sebastian-muesch]

Hi there,

I know this is not an real issue ... but it looks like this might be a good place to ask. I have some REV F ventana boards laying around, which I want to integrate as simulated network clients in an automated testing pod. Therefor I took OpenWRT 21.02 modified/patched it for my special needs. I already managed to generate a stable build, based on kernel 5.4.168.
I needed to make changes like removing the nomsi from the kernel command line and patching some legacy drivercode to enable MSI, because I want to use Intel AX200 (as MPCIE from Alfa Networks) and the AX200 TX performance is extremely bad without MSI (30%+ packet drops). Another use-case is limited by the pcie-bandwidth on a GW5404. From what I read within the gateworks wiki, I should be able to enable Gen2 as a clock generator with the needed accuracy is integrated in all rev-f boards.
When I take a look at the needed code in pcie-imx6.c I see that it will enable gen2 if fsl,max-link-speed = <2>; is set in the devicetree. As the definition in the device-tree in imx6qdl.dtsi does not contain the external clock source in the block pcie: pcie@1ffc000 { I think it is not a wise idea to enable it.

So that leads me to the question: Is there a changed dts definition for the external clock generator available, or maybe a dts with already enabled gen2?

I hope I did not bother you
Thanks in advance
Sebastian

[Gateworks]

Sebastian, I apologize for the late reply as I did not see this message. With regards to Gen2 PCI on Ventana you would need to modify the device-tree and possibly code as well to configure for an external clock such that the internal PCI host uses the external clock. We have not supported this and do not have any code or dt changes for this. Best regards, Tim Tim Harvey Software Engineer Gateworks Corporation (805)781-2000 x18 3026 S. Higuera, San Luis Obispo, CA 93401 www.gateworks.com

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On Wed, Jan 5, 2022 at 2:44 PM sebastian-muesch ***@***.***> wrote: Hi there, I know this is not an real issue ... but it looks like this might be a good place to ask. I have some REV F ventana boards laying around, which I want to integrate as simulated network clients in an automated testing pod. Therefor I took OpenWRT 21.02 modified/patched it for my special needs. I already managed to generate a stable build, based on kernel 5.4.168. I needed to make changes like removing the nomsi from the kernel command line and patching some legacy drivercode to enable MSI, because I want to use Intel AX200 (as MPCIE from Alfa Networks) and the AX200 TX performance is extremely bad without MSI (30%+ packet drops). Another use-case is limited by the pcie-bandwidth on a GW5404. From what I read within the gateworks wiki, I should be able to enable Gen2 as a clock generator with the needed accuracy is integrated in all rev-f boards. When I take a look at the needed code in pcie-imx6.c I see that it will enable gen2 if fsl,max-link-speed = <2>; is set in the devicetree. As the definition in the device-tree in imx6qdl.dtsi does not contain the external clock source in the block pcie: ***@***.*** { I think it is not a wise idea to enable it. So that leads me to the question: Is there a changed dts definition for the external clock generator available, or maybe a dts with already enabled gen2? I hope I did not bother you Thanks in advance Sebastian — Reply to this email directly, view it on GitHub, or unsubscribe. Triage notifications on the go with GitHub Mobile for iOS or Android. You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>