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instcountci: testing multiple 80bit stores using SVE
In preparation for #4166 which should improve on these results.
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‎unittests/InstructionCountCI/X87store-SVE.json‎

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{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"SVE128",
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"SVE256"
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],
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"DisabledHostFeatures": [
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"AFP",
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"FLAGM",
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"FLAGM2",
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"RPRES"
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]
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},
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"Instructions": {
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"fstp tword [rax]": {
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"ExpectedInstructionCount": 15,
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"Comment": "Single 80-bit store.",
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"ExpectedArm64ASM": [
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x4]",
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"mov x21, v2.d[1]",
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"add x22, x4, #0x8 (8)",
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"strh w21, [x22]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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"lsl w22, w22, w20",
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"bic w21, w21, w22",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]"
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]
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},
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"2-store 80bit": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 29,
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"x86Insts": [
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"fstp tword [rax]",
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"fstp tword [rax+10]"
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],
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"ExpectedArm64ASM": [
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x4]",
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"mov x21, v2.d[1]",
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"add x22, x4, #0x8 (8)",
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"strh w21, [x22]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0xa (10)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w22, w22, w20",
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"bic w21, w21, w22",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]"
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]
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},
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"8-store 80bit": {
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"x86InstructionCount": 8,
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"ExpectedInstructionCount": 113,
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"x86Insts": [
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"fstp tword [rax]",
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"fstp tword [rax+10]",
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"fstp tword [rax+20]",
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"fstp tword [rax+30]",
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"fstp tword [rax+40]",
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"fstp tword [rax+50]",
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"fstp tword [rax+60]",
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"fstp tword [rax+70]"
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],
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"ExpectedArm64ASM": [
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"ldrb w20, [x28, #1019]",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x4]",
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"mov x21, v2.d[1]",
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"add x22, x4, #0x8 (8)",
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"strh w21, [x22]",
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"ldrb w21, [x28, #1298]",
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"mov w22, #0x1",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0xa (10)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x14 (20)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x1e (30)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x28 (40)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x32 (50)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x3c (60)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w23, w22, w20",
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"bic w21, w21, w23",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]",
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"add x21, x4, #0x46 (70)",
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"add x0, x28, x20, lsl #4",
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"ldr q2, [x0, #1040]",
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"str d2, [x21]",
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"mov x23, v2.d[1]",
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"add x21, x21, #0x8 (8)",
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"strh w23, [x21]",
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"ldrb w21, [x28, #1298]",
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"lsl w22, w22, w20",
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"bic w21, w21, w22",
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"strb w21, [x28, #1298]",
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"add w20, w20, #0x1 (1)",
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"and w20, w20, #0x7",
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"strb w20, [x28, #1019]"
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]
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}
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}
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}

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