RFNoC "addsub" Block YAML Parameter

[sumdudelr]

Issue Description

The included "addsub" block's YAML definition contains a string parameter. The quotation marks do not carry forward to the generated rfnoc_image_core.sv. Building FPGA image will fail.

Setup Details

• Git commit 8208bad
• Using X310

Expected Behavior

FPGA image builds successfully

Actual Behaviour

Synthesis fails with:

ERROR: [Synth 8-1031] Verilog is not declared [repo/icores/build-x310_rfnoc_image_core/rfnoc_image_core.sv:1591]

Steps to reproduce the problem

Just add an "addsub" block to your RFNoC image.

Additional Information

Can be fixed by adding a few lines to addsub.yml to use hdl_parameters as is done in OOT example gain.yml.

[mbr0wn]

Thanks for reporting. Can confirm.

[joergho]

We fixed the issue and will update master shortly.