diff --git a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v b/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
index 58d44b8e..de871757 100644
--- a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
+++ b/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
@@ -98,6 +98,7 @@ module FemtoRV32 #(
    reg [31:0] rs2;
    reg [31:0] registerFile [31:0];
 
+   // write access
    always @(posedge clk) begin
      if (writeBack)
        if (rdId != 0)
@@ -213,8 +214,8 @@ module FemtoRV32 #(
    // branch->PC+Bimm    AUIPC->PC+Uimm    JAL->PC+Jimm
    // Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
    wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] :
-					    instr[4] ? Uimm[ADDR_WIDTH-1:0] :
-					               Bimm[ADDR_WIDTH-1:0] );
+                                            instr[4] ? Uimm[ADDR_WIDTH-1:0] :
+                                                       Bimm[ADDR_WIDTH-1:0] );
 
    // A separate adder to compute the destination of load/store.
    // testing instr[5] is equivalent to testing isStore in this context.