From b468492d7375d0fc76a5fc3ced9d45ef49d05187 Mon Sep 17 00:00:00 2001 From: Balestrino Date: Wed, 28 Aug 2013 09:51:03 +0200 Subject: [PATCH] big code update --- ComponentUpdateLog.txt | 21 + .../Generated_Source/PSoC5/Cm3RealView.scat | 15 +- .../Generated_Source/PSoC5/Cm3Start.c | 117 +- .../Generated_Source/PSoC5/CyBootAsmGnu.s | 8 +- .../Generated_Source/PSoC5/CyBootAsmRv.s | 8 +- .../Generated_Source/PSoC5/CyDmac.c | 43 +- .../Generated_Source/PSoC5/CyDmac.h | 12 +- .../Generated_Source/PSoC5/CyFlash.c | 18 +- .../Generated_Source/PSoC5/CyFlash.h | 7 +- .../Generated_Source/PSoC5/CyLib.c | 4 +- .../Generated_Source/PSoC5/CyLib.h | 6 +- .../Generated_Source/PSoC5/CySpc.c | 4 +- .../Generated_Source/PSoC5/CySpc.h | 4 +- .../Generated_Source/PSoC5/LCD.c | 15 +- .../Generated_Source/PSoC5/LCD.h | 62 +- .../Generated_Source/PSoC5/LCD_LCDPort.c | 2 +- .../Generated_Source/PSoC5/LCD_LCDPort.h | 4 +- .../PSoC5/LCD_LCDPort_aliases.h | 2 +- .../Generated_Source/PSoC5/LCD_PM.c | 2 +- .../Generated_Source/PSoC5/Pin_1.c | 2 +- .../Generated_Source/PSoC5/Pin_1.h | 4 +- .../Generated_Source/PSoC5/Pin_1_aliases.h | 2 +- .../Generated_Source/PSoC5/Pin_2.c | 2 +- .../Generated_Source/PSoC5/Pin_2.h | 4 +- .../Generated_Source/PSoC5/Pin_2_aliases.h | 2 +- .../Generated_Source/PSoC5/Pin_3.c | 2 +- .../Generated_Source/PSoC5/Pin_3.h | 4 +- .../Generated_Source/PSoC5/Pin_3_aliases.h | 2 +- .../Generated_Source/PSoC5/Pin_4.c | 2 +- .../Generated_Source/PSoC5/Pin_4.h | 4 +- .../Generated_Source/PSoC5/Pin_4_aliases.h | 2 +- .../Generated_Source/PSoC5/Pin_5.c | 2 +- .../Generated_Source/PSoC5/Pin_5.h | 4 +- .../Generated_Source/PSoC5/Pin_5_aliases.h | 2 +- .../Generated_Source/PSoC5/Timer_1.c | 754 +++ .../Generated_Source/PSoC5/Timer_1.h | 439 ++ .../Generated_Source/PSoC5/Timer_1_PM.c | 194 + .../Generated_Source/PSoC5/cm3gcc.ld | 26 +- .../Generated_Source/PSoC5/config.hex | 208 +- .../Generated_Source/PSoC5/core_cm3_psoc5.h | 4 +- .../Generated_Source/PSoC5/cyPm.c | 134 +- .../Generated_Source/PSoC5/cyPm.h | 31 +- .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 256 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 228 +- .../Generated_Source/PSoC5/cyfitter_cfg.h | 2 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 256 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 256 +- .../Generated_Source/PSoC5/cypins.h | 4 +- .../Generated_Source/PSoC5/cytypes.h | 33 +- .../Generated_Source/PSoC5/cyutils.c | 4 +- .../Generated_Source/PSoC5/m_miso_pin.c | 2 +- .../Generated_Source/PSoC5/m_miso_pin.h | 4 +- .../PSoC5/m_miso_pin_aliases.h | 2 +- .../Generated_Source/PSoC5/m_mosi_pin.c | 2 +- .../Generated_Source/PSoC5/m_mosi_pin.h | 4 +- .../PSoC5/m_mosi_pin_aliases.h | 2 +- .../Generated_Source/PSoC5/m_sclk_pin.c | 2 +- .../Generated_Source/PSoC5/m_sclk_pin.h | 4 +- .../PSoC5/m_sclk_pin_aliases.h | 2 +- .../Generated_Source/PSoC5/post_link.bat | 2 +- .../Generated_Source/PSoC5/project.h | 9 +- .../PSOC5_SPI_LSM303D.cycdx | 87 +- .../PSOC5_SPI_LSM303D.cydwr | Bin 30321 -> 30560 bytes .../PSOC5_SPI_LSM303D.cyfit | Bin 182214 -> 192850 bytes .../PSOC5_SPI_LSM303D.cyprj | 55 +- .../PSOC5_SPI_LSM303D.cyprj.SB | 1300 +++++ PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.rpt | 1524 ++++-- PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.svd | 256 +- .../PSOC5_SPI_LSM303D_PSoC5lib.uvproj | 60 + .../PSOC5_SPI_LSM303D_timing.html | 3513 ++++++++++---- .../TopDesign/TopDesign.cysch | Bin 103058 -> 112880 bytes .../codegentemp/Cm3RealView.scat | 15 +- .../codegentemp/Cm3Start.c | 117 +- .../codegentemp/CyBootAsmGnu.s | 8 +- .../codegentemp/CyBootAsmRv.s | 8 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.c | 43 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.h | 12 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.c | 18 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.h | 7 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.c | 4 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.h | 6 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.c | 4 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.h | 4 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.c | 15 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.h | 62 +- .../codegentemp/LCD_LCDPort.c | 2 +- .../codegentemp/LCD_LCDPort.h | 4 +- .../codegentemp/LCD_LCDPort_aliases.h | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_PM.c | 2 +- .../codegentemp/PSOC5_SPI_LSM303D.bvf | 459 +- .../codegentemp/PSOC5_SPI_LSM303D.ctl | 2 +- .../codegentemp/PSOC5_SPI_LSM303D.cycdx | 87 +- .../codegentemp/PSOC5_SPI_LSM303D.cyfit | Bin 182214 -> 192850 bytes .../codegentemp/PSOC5_SPI_LSM303D.dsf | 56 +- .../codegentemp/PSOC5_SPI_LSM303D.pci | 3 +- .../codegentemp/PSOC5_SPI_LSM303D.pco | 77 +- .../codegentemp/PSOC5_SPI_LSM303D.plc_log | 2 +- .../codegentemp/PSOC5_SPI_LSM303D.route | 2410 +++++---- .../codegentemp/PSOC5_SPI_LSM303D.rpt | 1524 ++++-- .../codegentemp/PSOC5_SPI_LSM303D.rt_log | 20 +- .../codegentemp/PSOC5_SPI_LSM303D.sdc | 10 +- .../codegentemp/PSOC5_SPI_LSM303D.svd | 256 +- .../codegentemp/PSOC5_SPI_LSM303D.tr | 4294 ++++++++++------- .../codegentemp/PSOC5_SPI_LSM303D.v | 358 +- .../codegentemp/PSOC5_SPI_LSM303D.vh2 | 538 ++- .../codegentemp/PSOC5_SPI_LSM303D.wde | 2 + .../codegentemp/PSOC5_SPI_LSM303D_p.lib | 2035 +++++++- .../codegentemp/PSOC5_SPI_LSM303D_p.pco | 79 +- .../codegentemp/PSOC5_SPI_LSM303D_p.vh2 | 440 +- .../codegentemp/PSOC5_SPI_LSM303D_r.lib | 2035 +++++++- .../codegentemp/PSOC5_SPI_LSM303D_r.vh2 | 555 ++- .../codegentemp/PSOC5_SPI_LSM303D_t.lib | 2035 +++++++- .../codegentemp/PSOC5_SPI_LSM303D_t.vh2 | 557 ++- .../codegentemp/PSOC5_SPI_LSM303D_timing.html | 3513 ++++++++++---- .../codegentemp/PSOC5_SPI_LSM303D_u.sdc | 6 +- .../codegentemp/PSoC5_Panther_100-TQFP.xml | 3 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.c | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.h | 4 +- .../codegentemp/Pin_1_aliases.h | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.c | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.h | 4 +- .../codegentemp/Pin_2_aliases.h | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.c | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.h | 4 +- .../codegentemp/Pin_3_aliases.h | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.c | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.h | 4 +- .../codegentemp/Pin_4_aliases.h | 2 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.c | 137 + PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.h | 130 + .../codegentemp/Pin_5_aliases.h | 32 + PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.c | 754 +++ PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.h | 439 ++ .../codegentemp/Timer_1_PM.c | 194 + .../codegentemp/bitstream.txt | 298 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cm3gcc.ld | 26 +- .../codegentemp/config.hex | 208 +- .../codegentemp/core_cm3_psoc5.h | 4 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.c | 134 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.h | 31 +- .../codegentemp/cydevice.h | 4 +- .../codegentemp/cydevice_trm.h | 4 +- .../codegentemp/cydevicegnu.inc | 4 +- .../codegentemp/cydevicegnu_trm.inc | 4 +- .../codegentemp/cydevicerv.inc | 4 +- .../codegentemp/cydevicerv_trm.inc | 4 +- .../codegentemp/cyfitter.h | 256 +- .../codegentemp/cyfitter_cfg.c | 228 +- .../codegentemp/cyfitter_cfg.h | 2 +- .../codegentemp/cyfittergnu.inc | 256 +- .../codegentemp/cyfitterrv.inc | 256 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cypins.h | 4 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cytypes.h | 33 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/cyutils.c | 4 +- .../codegentemp/elab_dependencies.txt | 850 ++-- .../codegentemp/generated_files.txt | 164 +- .../codegentemp/lcpsoc3/index | Bin 1792 -> 1792 bytes .../codegentemp/m_miso_pin.c | 2 +- .../codegentemp/m_miso_pin.h | 4 +- .../codegentemp/m_miso_pin_aliases.h | 2 +- .../codegentemp/m_mosi_pin.c | 2 +- .../codegentemp/m_mosi_pin.h | 4 +- .../codegentemp/m_mosi_pin_aliases.h | 2 +- .../codegentemp/m_sclk_pin.c | 2 +- .../codegentemp/m_sclk_pin.h | 4 +- .../codegentemp/m_sclk_pin_aliases.h | 2 +- .../codegentemp/placer.log | 58 +- PSOC5_SPI_LSM303D.cydsn/codegentemp/project.h | 9 +- .../codegentemp/warp_dependencies.txt | 4 + PSOC5_SPI_LSM303D.cydsn/main.c | 549 +-- PSOC5_SPI_LSM303D.cywrk.SB | 337 ++ PSOC5_SPI_LSM303D.cywrk.Tore | 2 +- 178 files changed, 28314 insertions(+), 8931 deletions(-) create mode 100644 PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.c create mode 100644 PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.h create mode 100644 PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1_PM.c create mode 100644 PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj.SB create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.c create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.h create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5_aliases.h create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.c create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.h create mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1_PM.c create mode 100644 PSOC5_SPI_LSM303D.cywrk.SB diff --git a/ComponentUpdateLog.txt b/ComponentUpdateLog.txt index 62bc11c..c511ae3 100644 --- a/ComponentUpdateLog.txt +++ b/ComponentUpdateLog.txt @@ -22,3 +22,24 @@ Project : PSOC5_SPI_LSM303D cy_boot v 3.20 v 3.30 +Last Modified Date & Time: 07/04/2013 18:18:39 + +Project : PSOC5_SPI_LSM303D + Schematic : TopDesign/TopDesign.cysch + + m_miso_pin v 1.80 v 1.90 + m_mosi_pin v 1.80 v 1.90 + m_sclk_pin v 1.80 v 1.90 + Tx_1 v 1.80 v 1.90 + Pin_1 v 1.80 v 1.90 + Pin_2 v 1.80 v 1.90 + Pin_3 v 1.80 v 1.90 + Pin_4 v 1.80 v 1.90 + LCD v 1.80 v 1.90 + +Project : PSOC5_SPI_LSM303D + Design Wide APIs + + cy_boot v 3.30 v 3.40 + + diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3RealView.scat index 716fd4c..968bf68 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -1,6 +1,6 @@ ;******************************************************************************** -;* File Name: Cm3RealView.scat -;* Version 3.30 +;* File Name: Cm3RealView.scat +;* Version 3.40 ;* ;* Description: ;* This Linker Descriptor file describes the memory layout of the PSoC5 @@ -21,9 +21,9 @@ ;* ;* ;******************************************************************************** -;* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -;* You may use this file only in accordance with the license, terms, conditions, -;* disclaimers, and limitations in the end user license agreement accompanying +;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying ;* the software package with which this file was provided. ;********************************************************************************/ @@ -50,6 +50,11 @@ LOAD_ROM 0 (262144 - 0) * (.ramvectors) } + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + DATA +0 { * (+RW, +ZI) diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3Start.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3Start.c index db78216..f7d4c9e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,12 +1,12 @@ /******************************************************************************* * File Name: Cm3Start.c -* Version 3.30 +* Version 3.40 * * Description: * Startup code for the ARM CM3. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,9 +19,9 @@ #include "CyDmac.h" #include "cyfitter.h" - #define NUM_INTERRUPTS 32u #define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS) +#define NUM_ROM_VECTORS 4u #define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR) #define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL) #define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */ @@ -37,10 +37,20 @@ CY_ISR(IntDefaultHandler); void Reset(void); CY_ISR(IntDefaultHandler); +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER __cs3_stack +#endif /* (__ARMCC_VERSION) */ + +/* Global variables */ +CY_NOINIT static uint32 cySysNoInitDataValid; + /******************************************************************************* * Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. *******************************************************************************/ + __attribute__ ((section(".ramvectors"))) #if defined(__ARMCC_VERSION) __align(256) @@ -53,6 +63,7 @@ cyisraddress CyRamVectors[NUM_VECTORS]; /******************************************************************************* * Function Name: IntDefaultHandler ******************************************************************************** +* * Summary: * This function is called for all interrupts, other than reset, that get * called before the system is setup. @@ -79,6 +90,7 @@ CY_ISR(IntDefaultHandler) } } + #if defined(__ARMCC_VERSION) /* Local function for the device reset. */ @@ -93,69 +105,11 @@ extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; /* RealView C Library initialization. */ extern int __main(void); -/******************************************************************************* -* -* Default Rom Interrupt Vector table. -* -*******************************************************************************/ -#pragma diag_suppress 1296 -__attribute__ ((section(".romvectors"))) -const cyisraddress RomVectors[NUM_VECTORS] = -{ - (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit, /* The initial stack pointer 0 */ - (cyisraddress)Reset, /* The reset handler 1 */ - IntDefaultHandler, /* The NMI handler 2 */ - IntDefaultHandler, /* The hard fault handler 3 */ - IntDefaultHandler, /* The MPU fault handler 4 */ - IntDefaultHandler, /* The bus fault handler 5 */ - IntDefaultHandler, /* The usage fault handler 6 */ - IntDefaultHandler, /* Reserved 7 */ - IntDefaultHandler, /* Reserved 8 */ - IntDefaultHandler, /* Reserved 9 */ - IntDefaultHandler, /* Reserved 10 */ - IntDefaultHandler, /* SVCall handler 11 */ - IntDefaultHandler, /* Debug monitor handler 12 */ - IntDefaultHandler, /* Reserved 13 */ - IntDefaultHandler, /* The PendSV handler 14 */ - IntDefaultHandler, /* The SysTick handler 15 */ - IntDefaultHandler, /* External Interrupt(0) 16 */ - IntDefaultHandler, /* External Interrupt(1) 17 */ - IntDefaultHandler, /* External Interrupt(2) 18 */ - IntDefaultHandler, /* External Interrupt(3) 19 */ - IntDefaultHandler, /* External Interrupt(4) 20 */ - IntDefaultHandler, /* External Interrupt(5) 21 */ - IntDefaultHandler, /* External Interrupt(6) 22 */ - IntDefaultHandler, /* External Interrupt(7) 23 */ - IntDefaultHandler, /* External Interrupt(8) 24 */ - IntDefaultHandler, /* External Interrupt(9) 25 */ - IntDefaultHandler, /* External Interrupt(A) 26 */ - IntDefaultHandler, /* External Interrupt(B) 27 */ - IntDefaultHandler, /* External Interrupt(C) 28 */ - IntDefaultHandler, /* External Interrupt(D) 29 */ - IntDefaultHandler, /* External Interrupt(E) 30 */ - IntDefaultHandler, /* External Interrupt(F) 31 */ - IntDefaultHandler, /* External Interrupt(10) 32 */ - IntDefaultHandler, /* External Interrupt(11) 33 */ - IntDefaultHandler, /* External Interrupt(12) 34 */ - IntDefaultHandler, /* External Interrupt(13) 35 */ - IntDefaultHandler, /* External Interrupt(14) 36 */ - IntDefaultHandler, /* External Interrupt(15) 37 */ - IntDefaultHandler, /* External Interrupt(16) 38 */ - IntDefaultHandler, /* External Interrupt(17) 39 */ - IntDefaultHandler, /* External Interrupt(18) 40 */ - IntDefaultHandler, /* External Interrupt(19) 41 */ - IntDefaultHandler, /* External Interrupt(1A) 42 */ - IntDefaultHandler, /* External Interrupt(1B) 43 */ - IntDefaultHandler, /* External Interrupt(1C) 44 */ - IntDefaultHandler, /* External Interrupt(1D) 45 */ - IntDefaultHandler, /* External Interrupt(1E) 46 */ - IntDefaultHandler /* External Interrupt(1F) 47 */ -}; - /******************************************************************************* * Function Name: Reset ******************************************************************************** +* * Summary: * This function handles the reset interrupt for the RVDS/MDK toolchains. * This is the first bit of code that is executed at startup. @@ -180,14 +134,14 @@ __asm void Reset(void) #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) #if(CYDEV_DEBUGGING_ENABLE) - ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */ + ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */ ldrb r4, [r3, #0] orr r4, r4, #01 strb r4, [r3, #0] debugEnabled #endif /* (CYDEV_DEBUGGING_ENABLE) */ - ldr r3, =0x400046f8 /* CYREG_RESET_SR0 */ + ldr r3, =0x400046fa /* CYREG_RESET_SR0 */ ldrb r2, [r3, #0] #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ @@ -209,6 +163,7 @@ debugEnabled /******************************************************************************* * Function Name: $Sub$$main ******************************************************************************** +* * Summary: * This function is called imediatly before the users main * @@ -232,15 +187,14 @@ void $Sub$$main(void) #elif defined(__GNUC__) -extern uint32 __cs3_interrupt_vector; +extern void __cs3_stack(void); extern void __cs3_start_c(void); -#define RomVectors (cyisraddress)(&__cs3_interrupt_vector) - /******************************************************************************* * Function Name: Reset ******************************************************************************** +* * Summary: * This function handles the reset interrupt for the GCC toolchain. This is the * first bit of code that is executed at startup. @@ -284,9 +238,33 @@ void Reset(void) #endif /* __GNUC__ */ + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 1296 +#endif +__attribute__ ((section(".romvectors"))) +const cyisraddress RomVectors[NUM_ROM_VECTORS] = +{ + #if defined(__ARMCC_VERSION) + INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #elif defined (__GNUC__) + &INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #endif /* (__ARMCC_VERSION) */ + (cyisraddress)&Reset, /* The reset handler 1 */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + + /******************************************************************************* * Function Name: initialize_psoc ******************************************************************************** +* * Summary: * This function used to initialize the PSoC chip before calling main. * @@ -314,7 +292,7 @@ void initialize_psoc(void) /* Set Ram interrupt vectors to default functions. */ for(i = 0u; i < NUM_VECTORS; i++) { - CyRamVectors[i] = RomVectors[i]; + CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; } /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ @@ -332,6 +310,9 @@ void initialize_psoc(void) CyDmacConfigure(); #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; } diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s index 64404e9..062dba4 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: CyBootAsmGnu.s -* Version 3.30 +* Version 3.40 * * Description: * Assembly routines for GNU as. * ******************************************************************************** -* Copyright 2010-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying +* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s index 1109303..3b362bc 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,14 +1,14 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 3.30 +; Version 3.40 ; ; DESCRIPTION: ; Assembly routines for RealView. ; ;------------------------------------------------------------------------------- -; Copyright 2010-2012, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying +; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. ;------------------------------------------------------------------------------- diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.c index 763431b..1ed276f 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyDmac.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the DMAC component. The API includes functions for the @@ -21,7 +21,7 @@ * The user can over write this once the TD is allocated. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -570,7 +570,8 @@ cystatus CyDmaChGetRequest(uint8 chHandle) if(chHandle < CY_DMA_NUMBEROF_CHANNELS) { - status = (cystatus) (CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & (CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); } return(status); @@ -818,32 +819,36 @@ uint8 CyDmaTdFreeCount(void) * uint8 nextTd: * Zero based index of the next Transfer Descriptor in the TD chain. Zero is a * valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. * * uint8 configuration: * Stores the Bit field of configuration bits. * -* TD_SWAP_EN - Perform endian swap +* CY_DMA_TD_SWAP_EN - Perform endian swap * -* TD_SWAP_SIZE4 - Swap size = 4 bytes +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes * -* TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger automatically -* when the current TD completes. +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. * -* TD_TERMIN_EN - Terminate this TD if a positive edge on the trq input -* line occurs. The positive edge must occur during a -* burst. That is the only time the DMAC will listen for -* it. +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. * -* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will -* generate a pulse. Note that this option is instance -* specific with the instance name followed by two -* underscores. In this example, the instance name is DMA. +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. * -* TD_INC_DST_ADR - Increment DST_ADR according to the size of each data -* transaction in the burst. +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. * -* TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each data -* transaction in the burst. +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. * * Return: * CYRET_SUCCESS if successful. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.h index 0f42fdf..b7aaef1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyDmac.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the DMA Controller. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -109,9 +109,9 @@ typedef struct dmac_tdmem2_struct #define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ #define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ -#if(CY_PSOC3) +#if(CY_PSOC3 || CY_PSOC5LP) #define CY_DMA_DISABLE_TD 0xFEu -#endif /* (CY_PSOC3) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ #define CY_DMA_TD_SIZE 0x08u @@ -195,9 +195,9 @@ typedef struct dmac_tdmem2_struct #define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) #define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) #define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) -#if(CY_PSOC3) +#if(CY_PSOC3 || CY_PSOC5LP) #define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) -#endif /* (CY_PSOC3) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ #define DMAC_CFG (CY_DMA_CFG_PTR) #define DMAC_ERR (CY_DMA_ERR_PTR) diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.c index e216c45..939ff7c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyFlash.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the FLASH/EEPROM. @@ -13,7 +13,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -364,7 +364,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) /* Copy the rowdata to the temporary buffer. */ #if(CY_PSOC3) - (void) memcpy((void *) rowBuffer, (const void *) rowData, (int16) CYDEV_FLS_ROW_SIZE); + (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); #else (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); #endif /* (CY_PSOC3) */ @@ -403,15 +403,19 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) * CYRET_UNKNOWN if there was an SPC error. * *******************************************************************************/ - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, uint8 * rowECC) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) { uint32 offset; uint16 i; cystatus status; /* Read the existing flash data. */ - offset = CYDEV_FLS_BASE + ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) + + offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) + ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE); + + #if (CYDEV_FLS_BASE != 0u) + offset += CYDEV_FLS_BASE; + #endif for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) { @@ -419,9 +423,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) } #if(CY_PSOC3) - (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *) rowECC, (int16) CYDEV_ECC_ROW_SIZE); + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE); #else - (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *) rowECC, CYDEV_ECC_ROW_SIZE); + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE); #endif /* (CY_PSOC3) */ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.h index ee767ef..18c5d4a 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyFlash.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the FLASH/EEPROM. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -68,7 +68,8 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, uint8 * rowECC) ; + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ void CyFlash_SetWaitCycles(uint8 freq) ; diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.c index 0f59206..0c52ec9 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyLib.c -* Version 3.30 +* Version 3.40 * * Description: * Provides system API for the clocking, interrupts and watchdog timer. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.h index fd2d94a..b036110 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyLib.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the system, clocking, interrupts and @@ -11,7 +11,7 @@ * Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -803,7 +803,7 @@ uint8 CyVdRealTimeStatus(void) ; #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} - #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR &= (uint8)(~DISABLE_IRQ_SET);} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} #endif /* (CY_PSOC3) */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.c index 1baf598..6824a20 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CySpc.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the System Performance Component. @@ -8,7 +8,7 @@ * application. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.h index f2c0c02..afdf79d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CySpc.c -* Version 3.30 +* Version 3.40 * * Description: * Provides definitions for the System Performance Component API. @@ -8,7 +8,7 @@ * application. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.c index 0c7c2ce..a88cd76 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD.c -* Version 1.80 +* Version 1.90 * * Description: * This file provides source code for the Character LCD component's API. @@ -56,13 +56,13 @@ void LCD_Init(void) { /* INIT CODE */ CyDelay(40u); /* Delay 40 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(5u); /* Delay 5 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(15u); /* Delay 15 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(1u); /* Delay 1 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_4_BIT_INIT); /* Selects 4-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_4_BIT_INIT); /* Selects 4-bit mode */ CyDelay(5u); /* Delay 5 ms */ LCD_WriteControl(LCD_CURSOR_AUTO_INCR_ON); /* Incr Cursor After Writes */ @@ -358,7 +358,7 @@ void LCD_IsReady(void) #if (CY_PSOC4) /* Mask off data pins to clear old values out */ - value = LCD_PORT_PC_REG & ((uint8)(~ LCD_DM_DATA_MASK)); + value = LCD_PORT_PC_REG & ((uint32) (~ LCD_DM_DATA_MASK)); /* Load in high Z values for data pins, others unchanged */ LCD_PORT_PC_REG = value | LCD_HIGH_Z_DATA_DM; @@ -406,6 +406,9 @@ void LCD_IsReady(void) /* Set enable low */ LCD_PORT_DR_REG &= ((uint8)(~LCD_E)); + /* This gives a true delay between disably Enable bit and poling Ready bit */ + CyDelayUs(0u); + /* Extract ready bit */ value &= LCD_READY_BIT; diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.h index 0b0bda9..261343e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD.h -* Version 1.80 +* Version 1.90 * * Description: * This header file contains registers and constants associated with the @@ -185,26 +185,30 @@ extern uint8 const CYCODE LCD_customFonts[64u]; * Registers ***************************************/ -/* Port Register Definitions */ -#define LCD_PORT_DR_REG (*(reg8 *) LCD_LCDPort__DR) /* Data Output Register */ -#define LCD_PORT_DR_PTR ( (reg8 *) LCD_LCDPort__DR) -#define LCD_PORT_PS_REG (*(reg8 *) LCD_LCDPort__PS) /* Pin State Register */ -#define LCD_PORT_PS_PTR ( (reg8 *) LCD_LCDPort__PS) - /* Device specific registers */ #if (CY_PSOC4) - #define LCD_PORT_PC_REG (*(reg32 *) LCD_LCDPort__PC) - #define LCD_PORT_PC_PTR (*(reg32 *) LCD_LCDPort__PC) + #define LCD_PORT_DR_REG (*(reg32 *) LCD_LCDPort__DR) /* Data Output Register */ + #define LCD_PORT_DR_PTR ( (reg32 *) LCD_LCDPort__DR) + #define LCD_PORT_PS_REG (*(reg32 *) LCD_LCDPort__PS) /* Pin State Register */ + #define LCD_PORT_PS_PTR ( (reg32 *) LCD_LCDPort__PS) + + #define LCD_PORT_PC_REG (*(reg32 *) LCD_LCDPort__PC) + #define LCD_PORT_PC_PTR (*(reg32 *) LCD_LCDPort__PC) #else - #define LCD_PORT_DM0_REG (*(reg8 *) LCD_LCDPort__DM0) /* Port Drive Mode 0 */ - #define LCD_PORT_DM0_PTR ( (reg8 *) LCD_LCDPort__DM0) - #define LCD_PORT_DM1_REG (*(reg8 *) LCD_LCDPort__DM1) /* Port Drive Mode 1 */ - #define LCD_PORT_DM1_PTR ( (reg8 *) LCD_LCDPort__DM1) - #define LCD_PORT_DM2_REG (*(reg8 *) LCD_LCDPort__DM2) /* Port Drive Mode 2 */ - #define LCD_PORT_DM2_PTR ( (reg8 *) LCD_LCDPort__DM2) + #define LCD_PORT_DR_REG (*(reg8 *) LCD_LCDPort__DR) /* Data Output Register */ + #define LCD_PORT_DR_PTR ( (reg8 *) LCD_LCDPort__DR) + #define LCD_PORT_PS_REG (*(reg8 *) LCD_LCDPort__PS) /* Pin State Register */ + #define LCD_PORT_PS_PTR ( (reg8 *) LCD_LCDPort__PS) + + #define LCD_PORT_DM0_REG (*(reg8 *) LCD_LCDPort__DM0) /* Port Drive Mode 0 */ + #define LCD_PORT_DM0_PTR ( (reg8 *) LCD_LCDPort__DM0) + #define LCD_PORT_DM1_REG (*(reg8 *) LCD_LCDPort__DM1) /* Port Drive Mode 1 */ + #define LCD_PORT_DM1_PTR ( (reg8 *) LCD_LCDPort__DM1) + #define LCD_PORT_DM2_REG (*(reg8 *) LCD_LCDPort__DM2) /* Port Drive Mode 2 */ + #define LCD_PORT_DM2_PTR ( (reg8 *) LCD_LCDPort__DM2) #endif /* CY_PSOC4 */ @@ -214,8 +218,13 @@ extern uint8 const CYCODE LCD_customFonts[64u]; ***************************************/ /* SHIFT must be 1 or 0 */ -#define LCD_PORT_SHIFT (LCD_LCDPort__SHIFT) -#define LCD_PORT_MASK (LCD_LCDPort__MASK) +#if (0 == LCD_LCDPort__SHIFT) + #define LCD_PORT_SHIFT (0x00u) +#else + #define LCD_PORT_SHIFT (0x01u) +#endif /* (0 == LCD_LCDPort__SHIFT) */ + +#define LCD_PORT_MASK ((uint8) (LCD_LCDPort__MASK)) #if (CY_PSOC4) @@ -225,7 +234,9 @@ extern uint8 const CYCODE LCD_customFonts[64u]; */ #define LCD_HIGH_Z_DATA_DM (0x00000249ul) #define LCD_STRONG_DATA_DM (0x00000DB6ul) - #define LCD_DM_DATA_MASK (0xFFFul << (LCD_PORT_SHIFT * 3u)) + #define LCD_DATA_PINS_MASK (0x00000FFFul) + #define LCD_DM_DATA_MASK ((uint32)(LCD_DATA_PINS_MASK << \ + (LCD_PORT_SHIFT * 3u))) #else @@ -247,11 +258,16 @@ extern uint8 const CYCODE LCD_customFonts[64u]; #endif /* CY_PSOC4 */ /* Pin Masks */ -#define LCD_RS ((uint8) (((uint8) 0x20u) << LCD_LCDPort__SHIFT)) -#define LCD_RW ((uint8) (((uint8) 0x40u) << LCD_LCDPort__SHIFT)) -#define LCD_E ((uint8) (((uint8) 0x10u) << LCD_LCDPort__SHIFT)) -#define LCD_READY_BIT ((uint8) (((uint8) 0x08u) << LCD_LCDPort__SHIFT)) -#define LCD_DATA_MASK ((uint8) (((uint8) 0x0Fu) << LCD_LCDPort__SHIFT)) +#define LCD_RS ((uint8) \ + (((uint8) 0x20u) << LCD_LCDPort__SHIFT)) +#define LCD_RW ((uint8) \ + (((uint8) 0x40u) << LCD_LCDPort__SHIFT)) +#define LCD_E ((uint8) \ + (((uint8) 0x10u) << LCD_LCDPort__SHIFT)) +#define LCD_READY_BIT ((uint8) \ + (((uint8) 0x08u) << LCD_LCDPort__SHIFT)) +#define LCD_DATA_MASK ((uint8) \ + (((uint8) 0x0Fu) << LCD_LCDPort__SHIFT)) /* These names are obsolete and will be removed in future revisions */ #define LCD_PORT_DR LCD_PORT_DR_REG diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.c index 7d5cdb8..3fa29b2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.h index 6f77bc0..4417263 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort_aliases.h index bfba954..15c22c8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_LCDPort_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_PM.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_PM.c index b34c396..855f7f2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_PM.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/LCD_PM.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_PM.c -* Version 1.80 +* Version 1.90 * * Description: * This file provides the API source code for the Static Segment LCD component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.c index 6b2c354..2754a77 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.h index d8a146a..4170174 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1_aliases.h index b404d4a..13cc3b1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_1_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.c index 1f4385a..e8c68c4 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.h index b74bf90..4e73fa8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2_aliases.h index d6d8eba..ef19a3a 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_2_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.c index 4237a34..412803c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.h index 5268493..6b112e5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3_aliases.h index d3dcdea..fb8bc2d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_3_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.c index 3bb6dd5..702a703 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.h index 3387667..cded03b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4_aliases.h index 08f796a..4f0894e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_4_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.c index b184643..ee180d0 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_5.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.h index 70589a8..8bc2e01 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_5.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5_aliases.h index 429caab..1f8e49d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Pin_5_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_5.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.c new file mode 100644 index 0000000..66ba383 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.c @@ -0,0 +1,754 @@ +/******************************************************************************* +* File Name: Timer_1.c +* Version 2.50 +* +* Description: +* The Timer component consists of a 8, 16, 24 or 32-bit timer with +* a selectable period between 2 and 2^Width - 1. The timer may free run +* or be used as a capture timer as well. The capture can be initiated +* by a positive or negative edge signal as well as via software. +* A trigger input can be programmed to enable the timer on rising edge +* falling edge, either edge or continous run. +* Interrupts may be generated due to a terminal count condition +* or a capture event. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Timer_1.h" + +uint8 Timer_1_initVar = 0u; + + +/******************************************************************************* +* Function Name: Timer_1_Init +******************************************************************************** +* +* Summary: +* Initialize to the schematic state +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_Init(void) +{ + #if(!Timer_1_UsingFixedFunction) + /* Interrupt State Backup for Critical Region*/ + uint8 Timer_1_interruptState; + #endif /* Interrupt state back up for Fixed Function only */ + + #if (Timer_1_UsingFixedFunction) + /* Clear all bits but the enable bit (if it's already set) for Timer operation */ + Timer_1_CONTROL &= Timer_1_CTRL_ENABLE; + + /* Clear the mode bits for continuous run mode */ + #if (CY_PSOC5A) + Timer_1_CONTROL2 &= ((uint8)(~Timer_1_CTRL_MODE_MASK)); + #endif /* Clear bits in CONTROL2 only in PSOC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_MODE_MASK)); + #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */ + + /* Check if One Shot mode is enabled i.e. RunMode !=0*/ + #if (Timer_1_RunModeUsed != 0x0u) + /* Set 3rd bit of Control register to enable one shot mode */ + Timer_1_CONTROL |= 0x04u; + #endif /* One Shot enabled only when RunModeUsed is not Continuous*/ + + #if (Timer_1_RunModeUsed == 2) + #if (CY_PSOC5A) + /* Set last 2 bits of control2 register if one shot(halt on + interrupt) is enabled*/ + Timer_1_CONTROL2 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Set last 2 bits of control3 register if one shot(halt on + interrupt) is enabled*/ + Timer_1_CONTROL3 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */ + + #endif /* Remove section if One Shot Halt on Interrupt is not enabled */ + + #if (Timer_1_UsingHWEnable != 0) + #if (CY_PSOC5A) + /* Set the default Run Mode of the Timer to Continuous */ + Timer_1_CONTROL2 |= Timer_1_CTRL_MODE_PULSEWIDTH; + #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Clear and Set ROD and COD bits of CFG2 register */ + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_RCOD_MASK)); + Timer_1_CONTROL3 |= Timer_1_CTRL_RCOD; + + /* Clear and Enable the HW enable bit in CFG2 register */ + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_ENBL_MASK)); + Timer_1_CONTROL3 |= Timer_1_CTRL_ENBL; + + /* Set the default Run Mode of the Timer to Continuous */ + Timer_1_CONTROL3 |= Timer_1_CTRL_MODE_CONTINUOUS; + #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */ + + #endif /* Configure Run Mode with hardware enable */ + + /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */ + Timer_1_RT1 &= ((uint8)(~Timer_1_RT1_MASK)); + Timer_1_RT1 |= Timer_1_SYNC; + + /*Enable DSI Sync all all inputs of the Timer*/ + Timer_1_RT1 &= ((uint8)(~Timer_1_SYNCDSI_MASK)); + Timer_1_RT1 |= Timer_1_SYNCDSI_EN; + + /* Set the IRQ to use the status register interrupts */ + Timer_1_CONTROL2 |= Timer_1_CTRL2_IRQ_SEL; + #endif /* Configuring registers of fixed function implementation */ + + /* Set Initial values from Configuration */ + Timer_1_WritePeriod(Timer_1_INIT_PERIOD); + Timer_1_WriteCounter(Timer_1_INIT_PERIOD); + + #if (Timer_1_UsingHWCaptureCounter)/* Capture counter is enabled */ + Timer_1_CAPTURE_COUNT_CTRL |= Timer_1_CNTR_ENABLE; + Timer_1_SetCaptureCount(Timer_1_INIT_CAPTURE_COUNT); + #endif /* Configure capture counter value */ + + #if (!Timer_1_UsingFixedFunction) + #if (Timer_1_SoftwareCaptureMode) + Timer_1_SetCaptureMode(Timer_1_INIT_CAPTURE_MODE); + #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */ + + #if (Timer_1_SoftwareTriggerMode) + if (0u == (Timer_1_CONTROL & Timer_1__B_TIMER__TM_SOFTWARE)) + { + Timer_1_SetTriggerMode(Timer_1_INIT_TRIGGER_MODE); + } + #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */ + + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Timer_1_interruptState = CyEnterCriticalSection(); + + /* Use the interrupt output of the status register for IRQ output */ + Timer_1_STATUS_AUX_CTRL |= Timer_1_STATUS_ACTL_INT_EN_MASK; + + /* Exit Critical Region*/ + CyExitCriticalSection(Timer_1_interruptState); + + #if (Timer_1_EnableTriggerMode) + Timer_1_EnableTrigger(); + #endif /* Set Trigger enable bit for UDB implementation in the control register*/ + + #if (Timer_1_InterruptOnCaptureCount) + #if (!Timer_1_ControlRegRemoved) + Timer_1_SetInterruptCount(Timer_1_INIT_INT_CAPTURE_COUNT); + #endif /* Set interrupt count in control register if control register is not removed */ + #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/ + + Timer_1_ClearFIFO(); + #endif /* Configure additional features of UDB implementation */ + + Timer_1_SetInterruptMode(Timer_1_INIT_INTERRUPT_MODE); +} + + +/******************************************************************************* +* Function Name: Timer_1_Enable +******************************************************************************** +* +* Summary: +* Enable the Timer +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_Enable(void) +{ + /* Globally Enable the Fixed Function Block chosen */ + #if (Timer_1_UsingFixedFunction) + Timer_1_GLOBAL_ENABLE |= Timer_1_BLOCK_EN_MASK; + Timer_1_GLOBAL_STBY_ENABLE |= Timer_1_BLOCK_STBY_EN_MASK; + #endif /* Set Enable bit for enabling Fixed function timer*/ + + /* Remove assignment if control register is removed */ + #if (!Timer_1_ControlRegRemoved || Timer_1_UsingFixedFunction) + Timer_1_CONTROL |= Timer_1_CTRL_ENABLE; + #endif /* Remove assignment if control register is removed */ +} + + +/******************************************************************************* +* Function Name: Timer_1_Start +******************************************************************************** +* +* Summary: +* The start function initializes the timer with the default values, the +* enables the timerto begin counting. It does not enable interrupts, +* the EnableInt command should be called if interrupt generation is required. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_initVar: Is modified when this function is called for the +* first time. Is used to ensure that initialization happens only once. +* +*******************************************************************************/ +void Timer_1_Start(void) +{ + if(Timer_1_initVar == 0u) + { + Timer_1_Init(); + + Timer_1_initVar = 1u; /* Clear this bit for Initialization */ + } + + /* Enable the Timer */ + Timer_1_Enable(); +} + + +/******************************************************************************* +* Function Name: Timer_1_Stop +******************************************************************************** +* +* Summary: +* The stop function halts the timer, but does not change any modes or disable +* interrupts. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: If the Enable mode is set to Hardware only then this function +* has no effect on the operation of the timer. +* +*******************************************************************************/ +void Timer_1_Stop(void) +{ + /* Disable Timer */ + #if(!Timer_1_ControlRegRemoved || Timer_1_UsingFixedFunction) + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_ENABLE)); + #endif /* Remove assignment if control register is removed */ + + /* Globally disable the Fixed Function Block chosen */ + #if (Timer_1_UsingFixedFunction) + Timer_1_GLOBAL_ENABLE &= ((uint8)(~Timer_1_BLOCK_EN_MASK)); + Timer_1_GLOBAL_STBY_ENABLE &= ((uint8)(~Timer_1_BLOCK_STBY_EN_MASK)); + #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/ +} + + +/******************************************************************************* +* Function Name: Timer_1_SetInterruptMode +******************************************************************************** +* +* Summary: +* This function selects which of the interrupt inputs may cause an interrupt. +* The twosources are caputure and terminal. One, both or neither may +* be selected. +* +* Parameters: +* interruptMode: This parameter is used to enable interrups on either/or +* terminal count or capture. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetInterruptMode(uint8 interruptMode) +{ + Timer_1_STATUS_MASK = interruptMode; +} + + +/******************************************************************************* +* Function Name: Timer_1_SoftwareCapture +******************************************************************************** +* +* Summary: +* This function forces a capture independent of the capture signal. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: +* An existing hardware capture could be overwritten. +* +*******************************************************************************/ +void Timer_1_SoftwareCapture(void) +{ + /* Generate a software capture by reading the counter register */ + (void)Timer_1_COUNTER_LSB; + /* Capture Data is now in the FIFO */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadStatusRegister +******************************************************************************** +* +* Summary: +* Reads the status register and returns it's state. This function should use +* defined types for the bit-field information as the bits in this register may +* be permuteable. +* +* Parameters: +* void +* +* Return: +* The contents of the status register +* +* Side Effects: +* Status register bits may be clear on read. +* +*******************************************************************************/ +uint8 Timer_1_ReadStatusRegister(void) +{ + return (Timer_1_STATUS); +} + + +#if (!Timer_1_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_ReadControlRegister +******************************************************************************** +* +* Summary: +* Reads the control register and returns it's value. +* +* Parameters: +* void +* +* Return: +* The contents of the control register +* +*******************************************************************************/ +uint8 Timer_1_ReadControlRegister(void) +{ + return ((uint8)Timer_1_CONTROL); +} + + +/******************************************************************************* +* Function Name: Timer_1_WriteControlRegister +******************************************************************************** +* +* Summary: +* Sets the bit-field of the control register. +* +* Parameters: +* control: The contents of the control register +* +* Return: +* +*******************************************************************************/ +void Timer_1_WriteControlRegister(uint8 control) +{ + Timer_1_CONTROL = control; +} +#endif /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_ReadPeriod +******************************************************************************** +* +* Summary: +* This function returns the current value of the Period. +* +* Parameters: +* void +* +* Return: +* The present value of the counter. +* +*******************************************************************************/ +uint16 Timer_1_ReadPeriod(void) +{ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_PERIOD_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_PERIOD_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_1_WritePeriod +******************************************************************************** +* +* Summary: +* This function is used to change the period of the counter. The new period +* will be loaded the next time terminal count is detected. +* +* Parameters: +* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will +* result in the counter remaining at zero. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_WritePeriod(uint16 period) +{ + #if(Timer_1_UsingFixedFunction) + uint16 period_temp = (uint16)period; + CY_SET_REG16(Timer_1_PERIOD_LSB_PTR, period_temp); + #else + CY_SET_REG16(Timer_1_PERIOD_LSB_PTR, period); + #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCapture +******************************************************************************** +* +* Summary: +* This function returns the last value captured. +* +* Parameters: +* void +* +* Return: +* Present Capture value. +* +*******************************************************************************/ +uint16 Timer_1_ReadCapture(void) +{ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_1_WriteCounter +******************************************************************************** +* +* Summary: +* This funtion is used to set the counter to a specific value +* +* Parameters: +* counter: New counter value. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_WriteCounter(uint16 counter) \ + +{ + #if(Timer_1_UsingFixedFunction) + /* This functionality is removed until a FixedFunction HW update to + * allow this register to be written + */ + CY_SET_REG16(Timer_1_COUNTER_LSB_PTR, (uint16)counter); + + #else + CY_SET_REG16(Timer_1_COUNTER_LSB_PTR, counter); + #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCounter +******************************************************************************** +* +* Summary: +* This function returns the current counter value. +* +* Parameters: +* void +* +* Return: +* Present compare value. +* +*******************************************************************************/ +uint16 Timer_1_ReadCounter(void) +{ + + /* Force capture by reading Accumulator */ + /* Must first do a software capture to be able to read the counter */ + /* It is up to the user code to make sure there isn't already captured data in the FIFO */ + (void)Timer_1_COUNTER_LSB; + + /* Read the data from the FIFO (or capture register for Fixed Function)*/ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +#if(!Timer_1_UsingFixedFunction) /* UDB Specific Functions */ + +/******************************************************************************* + * The functions below this point are only available using the UDB + * implementation. If a feature is selected, then the API is enabled. + ******************************************************************************/ + + +#if (Timer_1_SoftwareCaptureMode) + + +/******************************************************************************* +* Function Name: Timer_1_SetCaptureMode +******************************************************************************** +* +* Summary: +* This function sets the capture mode to either rising or falling edge. +* +* Parameters: +* captureMode: This parameter sets the capture mode of the UDB capture feature +* The parameter values are defined using the +* #define Timer_1__B_TIMER__CM_NONE 0 +#define Timer_1__B_TIMER__CM_RISINGEDGE 1 +#define Timer_1__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_1__B_TIMER__CM_EITHEREDGE 3 +#define Timer_1__B_TIMER__CM_SOFTWARE 4 + identifiers +* The following are the possible values of the parameter +* Timer_1__B_TIMER__CM_NONE - Set Capture mode to None +* Timer_1__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input +* Timer_1__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input +* Timer_1__B_TIMER__CM_EITHEREDGE - Either edge of Capture input +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetCaptureMode(uint8 captureMode) +{ + /* This must only set to two bits of the control register associated */ + captureMode = ((uint8)((uint8)captureMode << Timer_1_CTRL_CAP_MODE_SHIFT)); + captureMode &= (Timer_1_CTRL_CAP_MODE_MASK); + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_CAP_MODE_MASK)); + + /* Write The New Setting */ + Timer_1_CONTROL |= captureMode; +} +#endif /* Remove API if Capture Mode is not Software Controlled */ + + +#if (Timer_1_SoftwareTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_1_SetTriggerMode +******************************************************************************** +* +* Summary: +* This function sets the trigger input mode +* +* Parameters: +* triggerMode: Pass one of the pre-defined Trigger Modes (except Software) + #define Timer_1__B_TIMER__TM_NONE 0x00u + #define Timer_1__B_TIMER__TM_RISINGEDGE 0x04u + #define Timer_1__B_TIMER__TM_FALLINGEDGE 0x08u + #define Timer_1__B_TIMER__TM_EITHEREDGE 0x0Cu + #define Timer_1__B_TIMER__TM_SOFTWARE 0x10u +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetTriggerMode(uint8 triggerMode) +{ + /* This must only set to two bits of the control register associated */ + triggerMode &= Timer_1_CTRL_TRIG_MODE_MASK; + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_TRIG_MODE_MASK)); + + /* Write The New Setting */ + Timer_1_CONTROL |= (triggerMode | Timer_1__B_TIMER__TM_SOFTWARE); + +} +#endif /* Remove API if Trigger Mode is not Software Controlled */ + +#if (Timer_1_EnableTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_1_EnableTrigger +******************************************************************************** +* +* Summary: +* Sets the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_EnableTrigger(void) +{ + #if (!Timer_1_ControlRegRemoved) /* Remove assignment if control register is removed */ + Timer_1_CONTROL |= Timer_1_CTRL_TRIG_EN; + #endif /* Remove code section if control register is not used */ +} + + +/******************************************************************************* +* Function Name: Timer_1_DisableTrigger +******************************************************************************** +* +* Summary: +* Clears the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_DisableTrigger(void) +{ + #if (!Timer_1_ControlRegRemoved) /* Remove assignment if control register is removed */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_TRIG_EN)); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API is Trigger Mode is set to None */ + + +#if(Timer_1_InterruptOnCaptureCount) +#if (!Timer_1_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_SetInterruptCount +******************************************************************************** +* +* Summary: +* This function sets the capture count before an interrupt is triggered. +* +* Parameters: +* interruptCount: A value between 0 and 3 is valid. If the value is 0, then +* an interrupt will occur each time a capture occurs. +* A value of 1 to 3 will cause the interrupt +* to delay by the same number of captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetInterruptCount(uint8 interruptCount) +{ + /* This must only set to two bits of the control register associated */ + interruptCount &= Timer_1_CTRL_INTCNT_MASK; + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_INTCNT_MASK)); + /* Write The New Setting */ + Timer_1_CONTROL |= interruptCount; +} +#endif /* Remove API if control register is removed */ +#endif /* Timer_1_InterruptOnCaptureCount */ + + +#if (Timer_1_UsingHWCaptureCounter) + + +/******************************************************************************* +* Function Name: Timer_1_SetCaptureCount +******************************************************************************** +* +* Summary: +* This function sets the capture count +* +* Parameters: +* captureCount: A value between 2 and 127 inclusive is valid. A value of 1 +* to 127 will cause the interrupt to delay by the same number of +* captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetCaptureCount(uint8 captureCount) +{ + Timer_1_CAP_COUNT = captureCount; +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCaptureCount +******************************************************************************** +* +* Summary: +* This function reads the capture count setting +* +* Parameters: +* void +* +* Return: +* Returns the Capture Count Setting +* +*******************************************************************************/ +uint8 Timer_1_ReadCaptureCount(void) +{ + return ((uint8)Timer_1_CAP_COUNT); +} +#endif /* Timer_1_UsingHWCaptureCounter */ + + +/******************************************************************************* +* Function Name: Timer_1_ClearFIFO +******************************************************************************** +* +* Summary: +* This function clears all capture data from the capture FIFO +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_ClearFIFO(void) +{ + while(0u != (Timer_1_ReadStatusRegister() & Timer_1_STATUS_FIFONEMP)) + { + (void)Timer_1_ReadCapture(); + } +} + +#endif /* UDB Specific Functions */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.h new file mode 100644 index 0000000..9fbf5b6 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1.h @@ -0,0 +1,439 @@ +/******************************************************************************* +* File Name: Timer_1.h +* Version 2.50 +* +* Description: +* Contains the function prototypes and constants available to the timer +* user module. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CY_Timer_v2_30_Timer_1_H) +#define CY_Timer_v2_30_Timer_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + +extern uint8 Timer_1_initVar; + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Timer_v2_50 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5LP) */ + + +/************************************** +* Parameter Defaults +**************************************/ + +#define Timer_1_Resolution 16u +#define Timer_1_UsingFixedFunction 0u +#define Timer_1_UsingHWCaptureCounter 0u +#define Timer_1_SoftwareCaptureMode 0u +#define Timer_1_SoftwareTriggerMode 0u +#define Timer_1_UsingHWEnable 0u +#define Timer_1_EnableTriggerMode 0u +#define Timer_1_InterruptOnCaptureCount 0u +#define Timer_1_RunModeUsed 1u +#define Timer_1_ControlRegRemoved 0u + + +/*************************************** +* Type defines +***************************************/ + + +/************************************************************************** + * Sleep Wakeup Backup structure for Timer Component + *************************************************************************/ +typedef struct +{ + uint8 TimerEnableState; + #if(!Timer_1_UsingFixedFunction) + #if (CY_UDB_V0) + uint16 TimerUdb; /* Timer internal counter value */ + uint16 TimerPeriod; /* Timer Period value */ + uint8 InterruptMaskValue; /* Timer Compare Value */ + #if (Timer_1_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; /* Timer Capture Counter Value */ + #endif /* variable declaration for backing up Capture Counter value*/ + #endif /* variables for non retention registers in CY_UDB_V0 */ + + #if (CY_UDB_V1) + uint16 TimerUdb; + uint8 InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; + #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ + #endif /* (CY_UDB_V1) */ + + #if (!Timer_1_ControlRegRemoved) + uint8 TimerControlRegister; + #endif /* variable declaration for backing up enable state of the Timer */ + #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ +}Timer_1_backupStruct; + + +/*************************************** +* Function Prototypes +***************************************/ + +void Timer_1_Start(void) ; +void Timer_1_Stop(void) ; + +void Timer_1_SetInterruptMode(uint8 interruptMode) ; +uint8 Timer_1_ReadStatusRegister(void) ; +/* Deprecated function. Do not use this in future. Retained for backward compatibility */ +#define Timer_1_GetInterruptSource() Timer_1_ReadStatusRegister() + +#if(!Timer_1_ControlRegRemoved) + uint8 Timer_1_ReadControlRegister(void) ; + void Timer_1_WriteControlRegister(uint8 control) \ + ; +#endif /* (!Timer_1_ControlRegRemoved) */ + +uint16 Timer_1_ReadPeriod(void) ; +void Timer_1_WritePeriod(uint16 period) \ + ; +uint16 Timer_1_ReadCounter(void) ; +void Timer_1_WriteCounter(uint16 counter) \ + ; +uint16 Timer_1_ReadCapture(void) ; +void Timer_1_SoftwareCapture(void) ; + + +#if(!Timer_1_UsingFixedFunction) /* UDB Prototypes */ + #if (Timer_1_SoftwareCaptureMode) + void Timer_1_SetCaptureMode(uint8 captureMode) ; + #endif /* (!Timer_1_UsingFixedFunction) */ + + #if (Timer_1_SoftwareTriggerMode) + void Timer_1_SetTriggerMode(uint8 triggerMode) ; + #endif /* (Timer_1_SoftwareTriggerMode) */ + #if (Timer_1_EnableTriggerMode) + void Timer_1_EnableTrigger(void) ; + void Timer_1_DisableTrigger(void) ; + #endif /* (Timer_1_EnableTriggerMode) */ + + #if(Timer_1_InterruptOnCaptureCount) + #if(!Timer_1_ControlRegRemoved) + void Timer_1_SetInterruptCount(uint8 interruptCount) \ + ; + #endif /* (!Timer_1_ControlRegRemoved) */ + #endif /* (Timer_1_InterruptOnCaptureCount) */ + + #if (Timer_1_UsingHWCaptureCounter) + void Timer_1_SetCaptureCount(uint8 captureCount) \ + ; + uint8 Timer_1_ReadCaptureCount(void) ; + #endif /* (Timer_1_UsingHWCaptureCounter) */ + + void Timer_1_ClearFIFO(void) ; +#endif /* UDB Prototypes */ + +/* Sleep Retention APIs */ +void Timer_1_Init(void) ; +void Timer_1_Enable(void) ; +void Timer_1_SaveConfig(void) ; +void Timer_1_RestoreConfig(void) ; +void Timer_1_Sleep(void) ; +void Timer_1_Wakeup(void) ; + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ +#define Timer_1__B_TIMER__CM_NONE 0 +#define Timer_1__B_TIMER__CM_RISINGEDGE 1 +#define Timer_1__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_1__B_TIMER__CM_EITHEREDGE 3 +#define Timer_1__B_TIMER__CM_SOFTWARE 4 + + + +/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ +#define Timer_1__B_TIMER__TM_NONE 0x00u +#define Timer_1__B_TIMER__TM_RISINGEDGE 0x04u +#define Timer_1__B_TIMER__TM_FALLINGEDGE 0x08u +#define Timer_1__B_TIMER__TM_EITHEREDGE 0x0Cu +#define Timer_1__B_TIMER__TM_SOFTWARE 0x10u + + +/*************************************** +* Initialial Parameter Constants +***************************************/ + +#define Timer_1_INIT_PERIOD 499u +#define Timer_1_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Timer_1_CTRL_CAP_MODE_SHIFT)) +#define Timer_1_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Timer_1_CTRL_TRIG_MODE_SHIFT)) +#if (Timer_1_UsingFixedFunction) + #define Timer_1_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT))) +#else + #define Timer_1_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_FIFOFULL_INT_MASK_SHIFT))) +#endif /* (Timer_1_UsingFixedFunction) */ +#define Timer_1_INIT_CAPTURE_COUNT (2u) +#define Timer_1_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Timer_1_CTRL_INTCNT_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#if (Timer_1_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ + + + /*************************************** + * Fixed Function Registers + ***************************************/ + + #define Timer_1_STATUS (*(reg8 *) Timer_1_TimerHW__SR0 ) + /* In Fixed Function Block Status and Mask are the same register */ + #define Timer_1_STATUS_MASK (*(reg8 *) Timer_1_TimerHW__SR0 ) + #define Timer_1_CONTROL (*(reg8 *) Timer_1_TimerHW__CFG0) + #define Timer_1_CONTROL2 (*(reg8 *) Timer_1_TimerHW__CFG1) + #define Timer_1_CONTROL2_PTR ( (reg8 *) Timer_1_TimerHW__CFG1) + #define Timer_1_RT1 (*(reg8 *) Timer_1_TimerHW__RT1) + #define Timer_1_RT1_PTR ( (reg8 *) Timer_1_TimerHW__RT1) + + #if (CY_PSOC3 || CY_PSOC5LP) + #define Timer_1_CONTROL3 (*(reg8 *) Timer_1_TimerHW__CFG2) + #define Timer_1_CONTROL3_PTR ( (reg8 *) Timer_1_TimerHW__CFG2) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #define Timer_1_GLOBAL_ENABLE (*(reg8 *) Timer_1_TimerHW__PM_ACT_CFG) + #define Timer_1_GLOBAL_STBY_ENABLE (*(reg8 *) Timer_1_TimerHW__PM_STBY_CFG) + + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerHW__CAP0 ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerHW__CAP0 ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerHW__PER0 ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerHW__PER0 ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerHW__CNT_CMP0 ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerHW__CNT_CMP0 ) + + + /*************************************** + * Register Constants + ***************************************/ + + /* Fixed Function Block Chosen */ + #define Timer_1_BLOCK_EN_MASK Timer_1_TimerHW__PM_ACT_MSK + #define Timer_1_BLOCK_STBY_EN_MASK Timer_1_TimerHW__PM_STBY_MSK + + /* Control Register Bit Locations */ + /* Interrupt Count - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_INTCNT_SHIFT 0x00u + /* Trigger Polarity - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_TRIG_MODE_SHIFT 0x00u + /* Trigger Enable - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_TRIG_EN_SHIFT 0x00u + /* Capture Polarity - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_CAP_MODE_SHIFT 0x00u + /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ + #define Timer_1_CTRL_ENABLE_SHIFT 0x00u + + /* Control Register Bit Masks */ + #define Timer_1_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_1_CTRL_ENABLE_SHIFT)) + + /* Control2 Register Bit Masks */ + /* As defined in Register Map, Part of the TMRX_CFG1 register */ + #define Timer_1_CTRL2_IRQ_SEL_SHIFT 0x00u + #define Timer_1_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Timer_1_CTRL2_IRQ_SEL_SHIFT)) + + #if (CY_PSOC5A) + /* Use CFG1 Mode bits to set run mode */ + /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_MODE_SHIFT 0x01u + #define Timer_1_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Timer_1_CTRL_MODE_SHIFT)) + #endif /* (CY_PSOC5A) */ + #if (CY_PSOC3 || CY_PSOC5LP) + /* Control3 Register Bit Locations */ + #define Timer_1_CTRL_RCOD_SHIFT 0x02u + #define Timer_1_CTRL_ENBL_SHIFT 0x00u + #define Timer_1_CTRL_MODE_SHIFT 0x00u + + /* Control3 Register Bit Masks */ + #define Timer_1_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ + #define Timer_1_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Timer_1_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ + #define Timer_1_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_MODE_SHIFT)) /* Run mode bit mask */ + + #define Timer_1_CTRL_RCOD ((uint8)((uint8)0x03u << Timer_1_CTRL_RCOD_SHIFT)) + #define Timer_1_CTRL_ENBL ((uint8)((uint8)0x80u << Timer_1_CTRL_ENBL_SHIFT)) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ + #define Timer_1_RT1_SHIFT 0x04u + /* Sync TC and CMP bit masks */ + #define Timer_1_RT1_MASK ((uint8)((uint8)0x03u << Timer_1_RT1_SHIFT)) + #define Timer_1_SYNC ((uint8)((uint8)0x03u << Timer_1_RT1_SHIFT)) + #define Timer_1_SYNCDSI_SHIFT 0x00u + /* Sync all DSI inputs with Mask */ + #define Timer_1_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Timer_1_SYNCDSI_SHIFT)) + /* Sync all DSI inputs */ + #define Timer_1_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Timer_1_SYNCDSI_SHIFT)) + + #define Timer_1_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Timer_1_CTRL_MODE_SHIFT)) + #define Timer_1_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Timer_1_CTRL_MODE_SHIFT)) + #define Timer_1_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Timer_1_CTRL_MODE_SHIFT)) + + /* Status Register Bit Locations */ + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_1_STATUS_TC_SHIFT 0x07u + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_1_STATUS_CAPTURE_SHIFT 0x06u + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_1_STATUS_TC_INT_MASK_SHIFT (Timer_1_STATUS_TC_SHIFT - 0x04u) + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT (Timer_1_STATUS_CAPTURE_SHIFT - 0x04u) + + /* Status Register Bit Masks */ + #define Timer_1_STATUS_TC ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + #define Timer_1_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on TC */ + #define Timer_1_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on Capture */ + #define Timer_1_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT)) + +#else /* UDB Registers and Register Constants */ + + + /*************************************** + * UDB Registers + ***************************************/ + + #define Timer_1_STATUS (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG ) + #define Timer_1_STATUS_MASK (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG) + #define Timer_1_STATUS_AUX_CTRL (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG) + #define Timer_1_CONTROL (* (reg8 *) Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG ) + + #if(Timer_1_Resolution <= 8u) /* 8-bit Timer */ + #define Timer_1_CAPTURE_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #elif(Timer_1_Resolution <= 16u) /* 8-bit Timer */ + #if(CY_PSOC3) /* 8-bit addres space */ + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 16-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #endif /* CY_PSOC3 */ + #elif(Timer_1_Resolution <= 24u)/* 24-bit Timer */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit Timer */ + #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #endif /* CY_PSOC3 || CY_PSOC5 */ + #endif + + #if (Timer_1_UsingHWCaptureCounter) + #define Timer_1_CAP_COUNT (*(reg8 *) Timer_1_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_1_CAP_COUNT_PTR ( (reg8 *) Timer_1_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_1_CAPTURE_COUNT_CTRL (*(reg8 *) Timer_1_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #define Timer_1_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Timer_1_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #endif /* (Timer_1_UsingHWCaptureCounter) */ + + + /*************************************** + * Register Constants + ***************************************/ + + /* Control Register Bit Locations */ + #define Timer_1_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ + + /* Control Register Bit Masks */ + #define Timer_1_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_INTCNT_SHIFT)) + #define Timer_1_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_TRIG_MODE_SHIFT)) + #define Timer_1_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Timer_1_CTRL_TRIG_EN_SHIFT)) + #define Timer_1_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_CAP_MODE_SHIFT)) + #define Timer_1_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_1_CTRL_ENABLE_SHIFT)) + + /* Bit Counter (7-bit) Control Register Bit Definitions */ + /* As defined by the Register map for the AUX Control Register */ + #define Timer_1_CNTR_ENABLE 0x20u + + /* Status Register Bit Locations */ + #define Timer_1_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_TC_INT_MASK_SHIFT Timer_1_STATUS_TC_SHIFT + #define Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT Timer_1_STATUS_CAPTURE_SHIFT + #define Timer_1_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_FIFOFULL_INT_MASK_SHIFT Timer_1_STATUS_FIFOFULL_SHIFT + + /* Status Register Bit Masks */ + /* Sticky TC Event Bit-Mask */ + #define Timer_1_STATUS_TC ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + /* Sticky Capture Event Bit-Mask */ + #define Timer_1_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* NOT-Sticky FIFO Full Bit-Mask */ + #define Timer_1_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFOFULL_SHIFT)) + /* NOT-Sticky FIFO Not Empty Bit-Mask */ + #define Timer_1_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFONEMP_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFOFULL_SHIFT)) + + #define Timer_1_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ + + /* Datapath Auxillary Control Register definitions */ + #define Timer_1_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ + #define Timer_1_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ + +#endif /* Implementation Specific Registers and Register Constants */ + +#endif /* CY_Timer_v2_30_Timer_1_H */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1_PM.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1_PM.c new file mode 100644 index 0000000..897d3a7 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/Timer_1_PM.c @@ -0,0 +1,194 @@ +/******************************************************************************* +* File Name: Timer_1_PM.c +* Version 2.50 +* +* Description: +* This file provides the power management source code to API for the +* Timer. +* +* Note: +* None +* +******************************************************************************* +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Timer_1.h" +static Timer_1_backupStruct Timer_1_backup; + + +/******************************************************************************* +* Function Name: Timer_1_SaveConfig +******************************************************************************** +* +* Summary: +* Save the current user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup: Variables of this global structure are modified to +* store the values of non retention configuration registers when Sleep() API is +* called. +* +*******************************************************************************/ +void Timer_1_SaveConfig(void) +{ + #if (!Timer_1_UsingFixedFunction) + /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + Timer_1_backup.TimerUdb = Timer_1_ReadCounter(); + Timer_1_backup.TimerPeriod = Timer_1_ReadPeriod(); + Timer_1_backup.InterruptMaskValue = Timer_1_STATUS_MASK; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_backup.TimerCaptureCounter = Timer_1_ReadCaptureCount(); + #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + Timer_1_backup.TimerUdb = Timer_1_ReadCounter(); + Timer_1_backup.InterruptMaskValue = Timer_1_STATUS_MASK; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_backup.TimerCaptureCounter = Timer_1_ReadCaptureCount(); + #endif /* Back Up capture counter register */ + #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!Timer_1_ControlRegRemoved) + Timer_1_backup.TimerControlRegister = Timer_1_ReadControlRegister(); + #endif /* Backup the enable state of the Timer component */ + #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */ +} + + +/******************************************************************************* +* Function Name: Timer_1_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup: Variables of this global structure are used to +* restore the values of non retention registers on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_1_RestoreConfig(void) +{ + #if (!Timer_1_UsingFixedFunction) + /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + /* Interrupt State Backup for Critical Region*/ + uint8 Timer_1_interruptState; + + Timer_1_WriteCounter(Timer_1_backup.TimerUdb); + Timer_1_WritePeriod(Timer_1_backup.TimerPeriod); + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Timer_1_interruptState = CyEnterCriticalSection(); + /* Use the interrupt output of the status register for IRQ output */ + Timer_1_STATUS_AUX_CTRL |= Timer_1_STATUS_ACTL_INT_EN_MASK; + /* Exit Critical Region*/ + CyExitCriticalSection(Timer_1_interruptState); + Timer_1_STATUS_MASK =Timer_1_backup.InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_SetCaptureCount(Timer_1_backup.TimerCaptureCounter); + #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + Timer_1_WriteCounter(Timer_1_backup.TimerUdb); + Timer_1_STATUS_MASK =Timer_1_backup.InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_SetCaptureCount(Timer_1_backup.TimerCaptureCounter); + #endif /* Restore Capture counter register*/ + #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!Timer_1_ControlRegRemoved) + Timer_1_WriteControlRegister(Timer_1_backup.TimerControlRegister); + #endif /* Restore the enable state of the Timer component */ + #endif /* Restore non retention registers in the UDB implementation only */ +} + + +/******************************************************************************* +* Function Name: Timer_1_Sleep +******************************************************************************** +* +* Summary: +* Stop and Save the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup.TimerEnableState: Is modified depending on the +* enable state of the block before entering sleep mode. +* +*******************************************************************************/ +void Timer_1_Sleep(void) +{ + #if(!Timer_1_ControlRegRemoved) + /* Save Counter's enable state */ + if(Timer_1_CTRL_ENABLE == (Timer_1_CONTROL & Timer_1_CTRL_ENABLE)) + { + /* Timer is enabled */ + Timer_1_backup.TimerEnableState = 1u; + } + else + { + /* Timer is disabled */ + Timer_1_backup.TimerEnableState = 0u; + } + #endif /* Back up enable state from the Timer control register */ + Timer_1_Stop(); + Timer_1_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: Timer_1_Wakeup +******************************************************************************** +* +* Summary: +* Restores and enables the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup.enableState: Is used to restore the enable state of +* block on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_1_Wakeup(void) +{ + Timer_1_RestoreConfig(); + #if(!Timer_1_ControlRegRemoved) + if(Timer_1_backup.TimerEnableState == 1u) + { /* Enable Timer's operation */ + Timer_1_Enable(); + } /* Do nothing if Timer was disabled before */ + #endif /* Remove this code section if Control register is removed */ +} + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cm3gcc.ld index 6b98ccb..34c064c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cm3gcc.ld +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -34,7 +34,6 @@ EXTERN(__cs3_reset Reset) EXTERN(__cs3_start_asm __cs3_start_asm_generic_m) /* Bring in the interrupt routines & vector */ INCLUDE micro-names.inc -EXTERN(__cs3_interrupt_vector_micro) EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) /* Provide fall-back values */ @@ -50,10 +49,11 @@ SECTIONS .text : { CREATE_OBJECT_SYMBOLS - __cs3_interrupt_vector = __cs3_interrupt_vector_micro; + PROVIDE(__cs3_interrupt_vector = RomVectors); + *(.romvectors) *(.cs3.interrupt_vector) /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cs3_interrupt_vector_micro, "No interrupt vector"); + ASSERT (. != __cs3_interrupt_vector, "No interrupt vector"); PROVIDE(__cs3_reset = Reset); *(.cs3.reset) @@ -133,7 +133,7 @@ SECTIONS __cs3_regions = .; LONG (0) LONG (__cs3_region_init_ram) - LONG (__cs3_region_start_ram) + LONG (__cs3_region_start_data) LONG (__cs3_region_init_size_ram) LONG (__cs3_region_zero_size_ram) __cs3_regions_end = .; @@ -142,13 +142,23 @@ SECTIONS _etext = .; } >rom - .data : ALIGN(8) + .ramvectors (NOLOAD) : ALIGN(8) { __cs3_region_start_ram = .; *(.cs3.region-head.ram) ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted"); - *(.ramvectors) - + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cs3_region_start_data = .; + KEEP(*(.jcr)) *(.got.plt) *(.got) *(.shdata) @@ -167,12 +177,14 @@ SECTIONS _end = .; __end = .; } >ram AT>rom + __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram); __cs3_region_size_ram = LENGTH(ram); __cs3_region_init_ram = LOADADDR (.data); __cs3_region_init_size_ram = _edata - ADDR (.data); __cs3_region_zero_size_ram = _end - _edata; + .stab 0 (NOLOAD) : { *(.stab) } .stabstr 0 (NOLOAD) : { *(.stabstr) } /* DWARF debug sections. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/config.hex b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/config.hex index ac0200d..6cb0389 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/config.hex +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/config.hex @@ -1,100 +1,130 @@ -:200000000000010001010000520080000000010086003800060088008600680001000000CF -:2000200001000000010000000000FC00400000001E0101017000800000002200000044010A -:20004000040000000000005130FF07FF4020F0050800000040000000040404041101000057 -:2000600040A840200000000000000000000000000000000000000000000000000000000038 -:2000800030004C02000700182C2CD11300C00000800010009C0022800021030A0000003497 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+:200F80000000000000000000000000000000000000000000E000A000800000000000000051 +:200FA000000000000000000000000000000000000000000000000000000000000000000031 +:200FC0000201100000000000000002010000000003001000000000000100030000000000E4 +:200FE000010000616000600000000000007F7F00000000009F00009F80009F000000000074 +:2010000040400000000000009C85000000000000000000000000000000000000000000002F :00000001FF diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h index 7195e81..0809bd6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: core_cm3_psoc5.h -* Version 3.30 +* Version 3.40 * * Description: * Provides important type information for the PSoC5. This includes types @@ -11,7 +11,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.c index d8f87b1..c9c2f3b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cyPm.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the power management. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -194,7 +194,7 @@ void CyPmSaveClocks(void) } /* Need to change nothing if master clock source is IMO */ /* Bus clock - save divider and set it, if needed, to divide-by-one */ - cyPmClockBackup.clkBusDiv = ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG; + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG; if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) { CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); @@ -456,7 +456,7 @@ void CyPmRestoreClocks(void) } /* Bus clock - restore divider, if needed */ - if(cyPmClockBackup.clkBusDiv != (((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG)) + if(cyPmClockBackup.clkBusDiv != ((uint16)((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG)) { CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); } @@ -861,7 +861,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * Reentrant: * No * -* Side Effects: +* Side Effects and Restrictions: * For PSoC 5 silicon the wakeup source is not selectable. In this case the * wakeupSource argument is ignored and any of the available wakeup sources will * wake the device. @@ -875,6 +875,15 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * measure Hibernate/Sleep regulator settling time after a reset. The holdoff * delay is measured using rising edges of the 1 kHz ILO. * +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then use of the CTW is not required. +* Refer to the device errata for more information. +* *******************************************************************************/ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) { @@ -912,10 +921,18 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) #if(CY_PSOC3) - /* Hardware buzz expected to be disabled below for TO6 */ + /* Silicon Revision ID is below TO6 */ if(CYDEV_CHIP_REV_ACTUAL < 5u) { + /* Hardware buzz expected to be disabled in Sleep mode */ CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + + /* LVI/HVI requires hardware buzz to be enabled */ + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + CYASSERT(0u != 0u); + } } #endif /* (CY_PSOC3) */ @@ -1399,6 +1416,21 @@ static void CyPmHibSaveSet(void) /* Make the same preparations for Hibernate and Sleep modes */ CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + } @@ -1469,6 +1501,17 @@ static void CyPmHibRestore(void) } #endif /* (!CY_PSOC5A) */ + + + /*************************************************************************** + * Restore power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ } @@ -1720,15 +1763,10 @@ void CyPmFtwSetInterval(uint8 ftwInterval) * * Save timewheels configuration * * Disable FTW and 1PPS (enable and interrupt) * * Reset CTW -* * Save and disable PICU interrupts (PSoC 5) -* * Save and disable PRES-A and PRES-D (PSoC 5) +* * Save and disable PICU interrupts +* * Save and disable PRES-A and PRES-D * - Save and disable LVI/HVI configuration (PSoC 5) * - Save and set to max buzz interval (PSoC 5) -* - If LVI/HVI is enabled than hardware buzz in required (PSoC 3): -* * Prepare wake trim registers -* * Disable LDO-A in proper way -* - If LVI/HVI is disabled than hardware buzz in not required (PSoC 3): -* * Disabled hardware buzz * - CyPmHibSlpSaveSet() function is called * * Parameters: @@ -1796,53 +1834,6 @@ static void CyPmSlpSaveSet(void) #endif /* (CY_PSOC5A) */ - #if(CY_PSOC3) - - /*************************************************************************** - * If LVI/HVI is enabled than hardware buzz in required: - * - Prepare wake trim registers - * - Disable LDO-A in proper way - * - * If LVI/HVI is disabled than hardware buzz in not required: - * - Disabled hardware buzz - ***************************************************************************/ - - cyPmBackup.wakeTr2 = CY_PM_PWRSYS_WAKE_TR2_REG; - - /* Reconfigure power mode wakeup trim registers */ - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - /* HVI/LVI is enabled - hardware buzz is required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Update entire register */ - CY_PM_PWRSYS_WAKE_TR2_REG = 0x3Bu; - - /* Prepares for disabling LDO-A by moving bandgap reference to VCCD */ - CY_PM_PWRSYS_CR1_REG = 0x01u; - - /* Disables LDO-A */ - CY_PM_PWRSYS_CR1_REG |= 0x02u; - } - else - { - /* For later revisions, just enable buzz */ - CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; - } - } - else - { - /* HVI/LVI is disabled - hardware buzz is not required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Update entire register */ - CY_PM_PWRSYS_WAKE_TR2_REG = 0x3Au; - } - } - - #endif /* (CY_PSOC3) */ - /* Apply configuration that are same for Sleep and Hibernate */ CyPmHibSlpSaveSet(); } @@ -1857,7 +1848,6 @@ static void CyPmSlpSaveSet(void) * - Restore timewheel configuration (PSoC 5) * - Restore PRES-A and PRES-D (PSoC 5) * - Restore PICU interrupts (PSoC 5) -* - Restore LVI/HVI configuration (PSoC 3) * - Restore buzz sleep trim value (PSoC 5) * - Call to CyPmHibSlpSaveRestore() * @@ -1897,28 +1887,6 @@ static void CyPmSlpRestore(void) #endif /* (CY_PSOC5A) */ - #if(CY_PSOC3) - - CY_PM_PWRSYS_WAKE_TR2_REG = cyPmBackup.wakeTr2; - - /* HVI/LVI is enabled - hardware buzz is required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Reconfigure power mode wakeup trim registers */ - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - /* Enables LDO-A */ - CY_PM_PWRSYS_CR1_REG &= ((uint8)(~0x02u)); - - /* Moves bandgap reference back to VCCA */ - CY_PM_PWRSYS_CR1_REG &= ((uint8)(~0x01u)); - } - } - - #endif /* (CY_PSOC3) */ - - /* Restore configuration that are same for Sleep and Hibernate */ CyPmHibSlpRestore(); } diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.h index 2fe6960..6ed1b86 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cyPm.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the power management API. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -294,8 +294,6 @@ typedef struct cyPmBackupStruct #if(CY_PSOC5A) uint8 buzzSleepTrim; - #else - uint8 wakeTr2; #endif /* (CY_PSOC5A) */ @@ -315,6 +313,14 @@ typedef struct cyPmBackupStruct #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #if(CY_PSOC3 || CY_PSOC5LP) + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) uint8 scctData[28u]; /* SC/CT routing registers */ @@ -737,6 +743,23 @@ typedef struct cyPmBackupStruct #define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC5LP) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5LP) */ + + /******************************************************************************* * Following code are OBSOLETE and must not be used starting from cy_boot 3.30 *******************************************************************************/ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice.h index f8f10d6..de859e6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice_trm.h index e19ba93..6533208 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevice_trm.h * -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index 284b5cd..e36a2e1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index 2ebd420..d31a488 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevicegnu_trm.inc * -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv.inc index 14ab3ab..c151e4e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; FILENAME: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 2.2 Component Pack 5 +; PSoC Creator 2.2 Component Pack 6 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 25cf87f..797aeb8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; FILENAME: cydevicerv_trm.inc ; -; PSoC Creator 2.2 Component Pack 5 +; PSoC Creator 2.2 Component Pack 6 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter.h index 1892547..1047567 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -3,6 +3,80 @@ #include #include +/* Timer_1_TimerUDB */ +#define Timer_1_TimerUDB_nrstSts_stsreg__0__MASK 0x01u +#define Timer_1_TimerUDB_nrstSts_stsreg__0__POS 0 +#define Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define Timer_1_TimerUDB_nrstSts_stsreg__2__MASK 0x04u +#define Timer_1_TimerUDB_nrstSts_stsreg__2__POS 2 +#define Timer_1_TimerUDB_nrstSts_stsreg__3__MASK 0x08u +#define Timer_1_TimerUDB_nrstSts_stsreg__3__POS 3 +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK 0x0Du +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG CYREG_B1_UDB04_MSK +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG CYREG_B1_UDB04_ST +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK 0x80u +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS 7 +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG CYREG_B1_UDB04_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG CYREG_B1_UDB04_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK 0x80u +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG CYREG_B1_UDB04_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG CYREG_B1_UDB04_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG CYREG_B1_UDB04_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG CYREG_B1_UDB04_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG CYREG_B1_UDB04_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG CYREG_B1_UDB04_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG CYREG_B1_UDB04_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG CYREG_B1_UDB05_06_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG CYREG_B1_UDB05_06_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG CYREG_B1_UDB05_06_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG CYREG_B1_UDB05_06_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG CYREG_B1_UDB05_06_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG CYREG_B1_UDB05_06_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG CYREG_B1_UDB05_A0_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG CYREG_B1_UDB05_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG CYREG_B1_UDB05_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG CYREG_B1_UDB05_D0_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG CYREG_B1_UDB05_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG CYREG_B1_UDB05_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG CYREG_B1_UDB05_F0_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG CYREG_B1_UDB05_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG CYREG_B1_UDB05_F1 + /* SPIM_IntClock */ #define SPIM_IntClock__CFG0 CYREG_CLKDIST_DCFG0_CFG0 #define SPIM_IntClock__CFG1 CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ #define SPIM_IntClock__PM_STBY_MSK 0x01u /* UART_1_BUART */ -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB01_02_A0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB01_02_A1 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB01_02_D0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB01_02_D1 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB01_02_F0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB01_02_F1 -#define UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB01_A0_A1 -#define UART_1_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB01_A0 -#define UART_1_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB01_A1 -#define UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB01_D0_D1 -#define UART_1_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB01_D0 -#define UART_1_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB01_D1 -#define UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB01_F0_F1 -#define UART_1_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB01_F0 -#define UART_1_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB01_F1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define UART_1_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB04_A0 +#define UART_1_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB04_A1 +#define UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define UART_1_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB04_D0 +#define UART_1_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB04_D1 +#define UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define UART_1_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB04_F0 +#define UART_1_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB04_F1 #define UART_1_BUART_sTX_TxSts__0__MASK 0x01u #define UART_1_BUART_sTX_TxSts__0__POS 0 -#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST #define UART_1_BUART_sTX_TxSts__1__MASK 0x02u #define UART_1_BUART_sTX_TxSts__1__POS 1 #define UART_1_BUART_sTX_TxSts__2__MASK 0x04u @@ -43,26 +117,26 @@ #define UART_1_BUART_sTX_TxSts__3__MASK 0x08u #define UART_1_BUART_sTX_TxSts__3__POS 3 #define UART_1_BUART_sTX_TxSts__MASK 0x0Fu -#define UART_1_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB02_MSK -#define UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define UART_1_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB02_ST -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB00_01_A0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB00_01_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB00_01_D0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB00_01_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB00_01_F0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB00_01_F1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB00_A0_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB00_A0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB00_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB00_D0_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB00_D0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB00_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB00_F0_F1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB00_F0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB00_F1 +#define UART_1_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB04_MSK +#define UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define UART_1_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB04_ST +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB05_06_A0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB05_06_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB05_06_D0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB05_06_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB05_06_F0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB05_06_F1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB05_A0_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB05_A0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB05_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB05_D0_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB05_D0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB05_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB05_F0_F1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB05_F0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB05_F1 /* LCD_LCDPort */ #define LCD_LCDPort__0__MASK 0x01u @@ -243,8 +317,8 @@ #define SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define SPIM_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB03_MSK #define SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST #define SPIM_BSPIM_RxStsReg__4__MASK 0x10u #define SPIM_BSPIM_RxStsReg__4__POS 4 #define SPIM_BSPIM_RxStsReg__5__MASK 0x20u @@ -252,13 +326,13 @@ #define SPIM_BSPIM_RxStsReg__6__MASK 0x40u #define SPIM_BSPIM_RxStsReg__6__POS 6 #define SPIM_BSPIM_RxStsReg__MASK 0x70u -#define SPIM_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB00_MSK -#define SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define SPIM_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB00_ST +#define SPIM_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB02_MSK +#define SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SPIM_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB02_ST #define SPIM_BSPIM_TxStsReg__0__MASK 0x01u #define SPIM_BSPIM_TxStsReg__0__POS 0 -#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST #define SPIM_BSPIM_TxStsReg__1__MASK 0x02u #define SPIM_BSPIM_TxStsReg__1__POS 1 #define SPIM_BSPIM_TxStsReg__2__MASK 0x04u @@ -268,9 +342,9 @@ #define SPIM_BSPIM_TxStsReg__4__MASK 0x10u #define SPIM_BSPIM_TxStsReg__4__POS 4 #define SPIM_BSPIM_TxStsReg__MASK 0x1Fu -#define SPIM_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK -#define SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SPIM_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST +#define SPIM_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB00_MSK +#define SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define SPIM_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB00_ST #define SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB03_04_A0 #define SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB03_04_A1 #define SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ #define Pin_4__SHIFT 3 #define Pin_4__SLW CYREG_PRT3_SLW +/* Pin_5 */ +#define Pin_5__0__MASK 0x10u +#define Pin_5__0__PC CYREG_PRT3_PC4 +#define Pin_5__0__PORT 3u +#define Pin_5__0__SHIFT 4 +#define Pin_5__AG CYREG_PRT3_AG +#define Pin_5__AMUX CYREG_PRT3_AMUX +#define Pin_5__BIE CYREG_PRT3_BIE +#define Pin_5__BIT_MASK CYREG_PRT3_BIT_MASK +#define Pin_5__BYP CYREG_PRT3_BYP +#define Pin_5__CTL CYREG_PRT3_CTL +#define Pin_5__DM0 CYREG_PRT3_DM0 +#define Pin_5__DM1 CYREG_PRT3_DM1 +#define Pin_5__DM2 CYREG_PRT3_DM2 +#define Pin_5__DR CYREG_PRT3_DR +#define Pin_5__INP_DIS CYREG_PRT3_INP_DIS +#define Pin_5__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define Pin_5__LCD_EN CYREG_PRT3_LCD_EN +#define Pin_5__MASK 0x10u +#define Pin_5__PORT 3u +#define Pin_5__PRT CYREG_PRT3_PRT +#define Pin_5__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define Pin_5__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define Pin_5__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define Pin_5__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define Pin_5__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define Pin_5__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define Pin_5__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define Pin_5__PS CYREG_PRT3_PS +#define Pin_5__SHIFT 4 +#define Pin_5__SLW CYREG_PRT3_SLW + /* Tx_1 */ #define Tx_1__0__MASK 0x80u #define Tx_1__0__PC CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ /* SS */ #define SS_Async_ctrl_reg__0__MASK 0x01u #define SS_Async_ctrl_reg__0__POS 0 -#define SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK #define SS_Async_ctrl_reg__1__MASK 0x02u #define SS_Async_ctrl_reg__1__POS 1 -#define SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SS_Async_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SS_Async_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SS_Async_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SS_Async_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define SS_Async_ctrl_reg__MASK 0x03u -#define SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SS_Async_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -#define SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SS_Async_ctrl_reg__2__MASK 0x04u +#define SS_Async_ctrl_reg__2__POS 2 +#define SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SS_Async_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SS_Async_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SS_Async_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SS_Async_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SS_Async_ctrl_reg__MASK 0x07u +#define SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SS_Async_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL /* Miscellaneous */ /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ @@ -494,16 +602,17 @@ #define CYDEV_CONFIG_FASTBOOT_ENABLED 0 #define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u -#define CYDEV_CHIP_MEMBER_5A 2u +#define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_FAMILY_PSOC5 3u -#define CYDEV_CHIP_DIE_PANTHER 2u +#define CYDEV_CHIP_DIE_PANTHER 3u #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PANTHER #define BCLK__BUS_CLK__HZ 24000000U #define BCLK__BUS_CLK__KHZ 24000U #define BCLK__BUS_CLK__MHZ 24U #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC5LP 3u +#define CYDEV_CHIP_DIE_PSOC4A 2u +#define CYDEV_CHIP_DIE_PSOC5LP 4u #define CYDEV_CHIP_DIE_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u @@ -511,13 +620,16 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x0E13C069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_5B 3u +#define CYDEV_CHIP_MEMBER_4A 2u +#define CYDEV_CHIP_MEMBER_5B 4u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5A #define CYDEV_CHIP_REVISION_3A_ES1 0u #define CYDEV_CHIP_REVISION_3A_ES2 1u #define CYDEV_CHIP_REVISION_3A_ES3 3u #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u @@ -530,6 +642,8 @@ #define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u #define CYDEV_CHIP_REV_PANTHER_ES0 0u #define CYDEV_CHIP_REV_PANTHER_ES1 1u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u #define CYDEV_CHIP_REV_PSOC5LP_ES0 0u #define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u #define CYDEV_CONFIGURATION_COMPRESSED 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 2a4057a..b5c3dfb 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.c -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator with device @@ -8,7 +8,7 @@ * CyClockStartupError(), this file should not be modified. * ******************************************************************************** -* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -110,7 +110,7 @@ static void CyClockStartupError(uint8 errorCode) { volatile uint8 * const addr8 = (volatile uint8 *)addr; uint32 i; - for (i = 0; i < count; i++) + for (i = 0u; i < count; i++) { addr8[i] = 0u; } @@ -142,7 +142,7 @@ static void CyClockStartupError(uint8 errorCode) volatile uint8 * const dest8 = (volatile uint8 *)dest; const uint8 * const src8 = (const uint8 *)src; uint32 i; - for (i = 0; i < count; i++) + for (i = 0u; i < count; i++) { dest8[i] = src8[i]; } @@ -217,80 +217,107 @@ static void CyClockStartupError(uint8 errorCode) /* UDB_1_3_1_CONFIG Address: CYDEV_UCFG_B0_P2_U1_BASE Size (bytes): 128 */ #define BS_UDB_1_3_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000280u) +/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ +#define BS_UDB_1_0_0_CONFIG_VAL ((const uint8 CYFAR *)0x48000300u) + +/* UDB_1_0_1_CONFIG Address: CYDEV_UCFG_B1_P2_U1_BASE Size (bytes): 128 */ +#define BS_UDB_1_0_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000380u) + /* UWRK_B0_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u Size (bytes): 32 */ -#define BS_UWRK_B0_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000300u) +#define BS_UWRK_B0_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000400u) -/* DSI0_2_HV_ROUTING Address: CYDEV_UCFG_DSI7_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000320u) +/* UWRK_B1_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u Size (bytes): 32 */ +#define BS_UWRK_B1_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000420u) /* DSI0_3_HV_ROUTING Address: CYDEV_UCFG_DSI6_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480003A0u) +#define BS_DSI0_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000440u) /* DSI0_4_HV_ROUTING Address: CYDEV_UCFG_DSI5_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000420u) +#define BS_DSI0_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480004C0u) /* DSISWITCH_0_5 Address: CYDEV_UCFG_DSI4_BASE Size (bytes): 128 */ -#define BS_DSISWITCH_0_5_VAL ((const uint8 CYFAR *)0x480004A0u) +#define BS_DSISWITCH_0_5_VAL ((const uint8 CYFAR *)0x48000540u) /* DSI0_5_HV_ROUTING Address: CYDEV_UCFG_DSI4_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000520u) +#define BS_DSI0_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480005C0u) + +/* UDBSWITCH_1_0 Address: CYDEV_UCFG_B1_P2_ROUTE_BASE Size (bytes): 128 */ +#define BS_UDBSWITCH_1_0_VAL ((const uint8 CYFAR *)0x48000640u) -/* UDB_1_2_HV_ROUTING Address: CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_1_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480005A0u) +/* UDB_2_0_HV_ROUTING Address: CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_2_0_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480006C0u) + +/* UDB_2_1_HV_ROUTING Address: CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_2_1_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000740u) /* UDB_2_2_HV_ROUTING Address: CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000620u) +#define BS_UDB_2_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480007C0u) /* UDB_1_3_HV_ROUTING Address: CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_1_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480006A0u) +#define BS_UDB_1_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000840u) /* UDBSWITCH_1_3 Address: CYDEV_UCFG_B0_P2_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_3_VAL ((const uint8 CYFAR *)0x48000720u) +#define BS_UDBSWITCH_1_3_VAL ((const uint8 CYFAR *)0x480008C0u) /* UDB_2_3_HV_ROUTING Address: CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480007A0u) +#define BS_UDB_2_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000940u) /* UDBSWITCH_1_4 Address: CYDEV_UCFG_B0_P1_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_4_VAL ((const uint8 CYFAR *)0x48000820u) +#define BS_UDBSWITCH_1_4_VAL ((const uint8 CYFAR *)0x480009C0u) /* UDB_2_4_HV_ROUTING Address: CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480008A0u) +#define BS_UDB_2_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000A40u) + +/* UDB_1_5_HV_ROUTING Address: CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_1_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000AC0u) /* UDBSWITCH_1_5 Address: CYDEV_UCFG_B0_P0_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000920u) +#define BS_UDBSWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000B40u) /* UDB_2_5_HV_ROUTING Address: CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480009A0u) +#define BS_UDB_2_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000BC0u) + +/* DSI3_1_HV_ROUTING Address: CYDEV_UCFG_DSI8_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_DSI3_1_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000C40u) + +/* DSISWITCH_1_2 Address: CYDEV_UCFG_DSI3_BASE Size (bytes): 128 */ +#define BS_DSISWITCH_1_2_VAL ((const uint8 CYFAR *)0x48000CC0u) + +/* DSI3_2_HV_ROUTING Address: CYDEV_UCFG_DSI3_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_DSI3_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000D40u) /* DSI3_3_HV_ROUTING Address: CYDEV_UCFG_DSI2_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000A20u) +#define BS_DSI3_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000DC0u) /* DSI3_4_HV_ROUTING Address: CYDEV_UCFG_DSI1_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000AA0u) +#define BS_DSI3_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000E40u) /* DSISWITCH_1_5 Address: CYDEV_UCFG_DSI0_BASE Size (bytes): 128 */ -#define BS_DSISWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000B20u) +#define BS_DSISWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000EC0u) /* DSI3_5_HV_ROUTING Address: CYDEV_UCFG_DSI0_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000BA0u) +#define BS_DSI3_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000F40u) + +/* UCFG_BCTL1 Address: CYREG_BCTL1_MDCLK_EN Size (bytes): 16 */ +#define BS_UCFG_BCTL1_VAL ((const uint8 CYFAR *)0x48000FC0u) /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ -#define BS_UCFG_BCTL0_VAL ((const uint8 CYFAR *)0x48000C20u) +#define BS_UCFG_BCTL0_VAL ((const uint8 CYFAR *)0x48000FD0u) /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ -#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000C30u) +#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000FE0u) /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ -#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000C3Cu) +#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000FECu) /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ -#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000C44u) +#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000FF4u) /* IOPORT_0 Address: CYDEV_PRTDSI_PRT0_BASE Size (bytes): 7 */ -#define BS_IOPORT_0_VAL ((const uint8 CYFAR *)0x48000C50u) +#define BS_IOPORT_0_VAL ((const uint8 CYFAR *)0x48001000u) /* IOPORT_3 Address: CYDEV_PRTDSI_PRT3_BASE Size (bytes): 7 */ -#define BS_IOPORT_3_VAL ((const uint8 CYFAR *)0x48000C58u) +#define BS_IOPORT_3_VAL ((const uint8 CYFAR *)0x48001008u) /******************************************************************************* @@ -358,44 +385,52 @@ static void cfg_dma_init(void) { 16u, 0x0Cu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYREG_PRT12_DR) }, /* TD 11 */ { 16u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYREG_PRT15_DR) }, /* TD 12 */ { 384u, 0x0Eu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_U0_BASE) }, /* TD 13 */ - { 384u, 0x0Fu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_U0_BASE) }, /* TD 14 */ - { 384u, 0x10u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_U0_BASE) }, /* TD 15 */ - { 1024u, 0x11u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P6_U0_BASE) }, /* TD 16 */ - { 2048u, 0x12u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U0_BASE) }, /* TD 17 */ + { 896u, 0x0Fu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_U0_BASE) }, /* TD 14 */ + { 896u, 0x10u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P6_U0_BASE) }, /* TD 15 */ + { 384u, 0x11u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P3_U0_BASE) }, /* TD 16 */ + { 1024u, 0x12u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P4_U0_BASE) }, /* TD 17 */ { 128u, 0x13u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE) }, /* TD 18 */ { 128u, 0x14u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE) }, /* TD 19 */ - { 256u, 0x15u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE) }, /* TD 20 */ - { 128u, 0x16u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE) }, /* TD 21 */ - { 128u, 0x17u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE) }, /* TD 22 */ - { 128u, 0x18u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE) }, /* TD 23 */ - { 512u, 0x19u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI8_BASE) }, /* TD 24 */ - { 512u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI12_BASE) }, /* TD 25 */ - { 32u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u) }, /* TD 26 */ + { 128u, 0x15u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE) }, /* TD 20 */ + { 128u, 0x16u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE) }, /* TD 21 */ + { 384u, 0x17u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE) }, /* TD 22 */ + { 256u, 0x18u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI9_BASE) }, /* TD 23 */ + { 512u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI12_BASE) }, /* TD 24 */ + { 32u, 0x1Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u) }, /* TD 25 */ + { 32u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u) }, /* TD 26 */ { 128u, 0x1Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_U0_BASE) }, /* TD 27 */ { 128u, 0x1Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_U1_BASE) }, /* TD 28 */ { 128u, 0x1Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_U0_BASE) }, /* TD 29 */ { 128u, 0x1Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_U1_BASE) }, /* TD 30 */ { 128u, 0x20u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_U0_BASE) }, /* TD 31 */ { 128u, 0x21u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_U1_BASE) }, /* TD 32 */ - { 128u, 0x22u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE + 0x00000080u) }, /* TD 33 */ - { 128u, 0x23u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE + 0x00000080u) }, /* TD 34 */ - { 128u, 0x24u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE + 0x00000080u) }, /* TD 35 */ - { 128u, 0x25u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE) }, /* TD 36 */ - { 128u, 0x26u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE + 0x00000080u) }, /* TD 37 */ - { 128u, 0x27u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u) }, /* TD 38 */ - { 128u, 0x28u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u) }, /* TD 39 */ - { 128u, 0x29u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u) }, /* TD 40 */ - { 128u, 0x2Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE) }, /* TD 41 */ - { 128u, 0x2Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u) }, /* TD 42 */ - { 128u, 0x2Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE) }, /* TD 43 */ - { 128u, 0x2Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u) }, /* TD 44 */ - { 128u, 0x2Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE) }, /* TD 45 */ - { 128u, 0x2Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u) }, /* TD 46 */ - { 128u, 0x30u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE + 0x00000080u) }, /* TD 47 */ - { 128u, 0x31u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE + 0x00000080u) }, /* TD 48 */ - { 128u, 0x32u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE) }, /* TD 49 */ - { 128u, 0x33u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE + 0x00000080u) }, /* TD 50 */ - { 16u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL0_MDCLK_EN) }, /* TD 51 */ + { 128u, 0x22u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U0_BASE) }, /* TD 33 */ + { 128u, 0x23u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U1_BASE) }, /* TD 34 */ + { 128u, 0x24u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE + 0x00000080u) }, /* TD 35 */ + { 128u, 0x25u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE + 0x00000080u) }, /* TD 36 */ + { 128u, 0x26u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE) }, /* TD 37 */ + { 128u, 0x27u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE + 0x00000080u) }, /* TD 38 */ + { 128u, 0x28u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE) }, /* TD 39 */ + { 128u, 0x29u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u) }, /* TD 40 */ + { 128u, 0x2Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u) }, /* TD 41 */ + { 128u, 0x2Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u) }, /* TD 42 */ + { 128u, 0x2Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u) }, /* TD 43 */ + { 128u, 0x2Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE) }, /* TD 44 */ + { 128u, 0x2Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u) }, /* TD 45 */ + { 128u, 0x2Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE) }, /* TD 46 */ + { 128u, 0x30u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u) }, /* TD 47 */ + { 128u, 0x31u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u) }, /* TD 48 */ + { 128u, 0x32u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE) }, /* TD 49 */ + { 128u, 0x33u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u) }, /* TD 50 */ + { 128u, 0x34u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI8_BASE + 0x00000080u) }, /* TD 51 */ + { 128u, 0x35u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE) }, /* TD 52 */ + { 128u, 0x36u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE + 0x00000080u) }, /* TD 53 */ + { 128u, 0x37u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE + 0x00000080u) }, /* TD 54 */ + { 128u, 0x38u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE + 0x00000080u) }, /* TD 55 */ + { 128u, 0x39u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE) }, /* TD 56 */ + { 128u, 0x3Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE + 0x00000080u) }, /* TD 57 */ + { 16u, 0x3Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL1_MDCLK_EN) }, /* TD 58 */ + { 16u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL0_MDCLK_EN) }, /* TD 59 */ }; /* Source addresses can be relocated, but only when in 32bit addresses. @@ -428,33 +463,41 @@ static void cfg_dma_init(void) (const void *)(&DMA_ZERO_VAL), /* TD 22 */ (const void *)(&DMA_ZERO_VAL), /* TD 23 */ (const void *)(&DMA_ZERO_VAL), /* TD 24 */ - (const void *)(&DMA_ZERO_VAL), /* TD 25 */ - (const void *)(BS_UWRK_B0_WRK_STATCTL_BITS_VAL), /* TD 26 */ + (const void *)(BS_UWRK_B0_WRK_STATCTL_BITS_VAL), /* TD 25 */ + (const void *)(BS_UWRK_B1_WRK_STATCTL_BITS_VAL), /* TD 26 */ (const void *)(BS_UDB_1_5_0_CONFIG_VAL), /* TD 27 */ (const void *)(BS_UDB_1_5_1_CONFIG_VAL), /* TD 28 */ (const void *)(BS_UDB_1_4_1_CONFIG_VAL), /* TD 29 */ (const void *)(BS_UDB_1_4_0_CONFIG_VAL), /* TD 30 */ (const void *)(BS_UDB_1_3_0_CONFIG_VAL), /* TD 31 */ (const void *)(BS_UDB_1_3_1_CONFIG_VAL), /* TD 32 */ - (const void *)(BS_DSI0_2_HV_ROUTING_VAL), /* TD 33 */ - (const void *)(BS_DSI0_3_HV_ROUTING_VAL), /* TD 34 */ - (const void *)(BS_DSI0_4_HV_ROUTING_VAL), /* TD 35 */ - (const void *)(BS_DSISWITCH_0_5_VAL), /* TD 36 */ - (const void *)(BS_DSI0_5_HV_ROUTING_VAL), /* TD 37 */ - (const void *)(BS_UDB_1_2_HV_ROUTING_VAL), /* TD 38 */ - (const void *)(BS_UDB_2_2_HV_ROUTING_VAL), /* TD 39 */ - (const void *)(BS_UDB_1_3_HV_ROUTING_VAL), /* TD 40 */ - (const void *)(BS_UDBSWITCH_1_3_VAL), /* TD 41 */ - (const void *)(BS_UDB_2_3_HV_ROUTING_VAL), /* TD 42 */ - (const void *)(BS_UDBSWITCH_1_4_VAL), /* TD 43 */ - (const void *)(BS_UDB_2_4_HV_ROUTING_VAL), /* TD 44 */ - (const void *)(BS_UDBSWITCH_1_5_VAL), /* TD 45 */ - (const void *)(BS_UDB_2_5_HV_ROUTING_VAL), /* TD 46 */ - (const void *)(BS_DSI3_3_HV_ROUTING_VAL), /* TD 47 */ - (const void *)(BS_DSI3_4_HV_ROUTING_VAL), /* TD 48 */ - (const void *)(BS_DSISWITCH_1_5_VAL), /* TD 49 */ - (const void *)(BS_DSI3_5_HV_ROUTING_VAL), /* TD 50 */ - (const void *)(BS_UCFG_BCTL0_VAL), /* TD 51 */ + (const void *)(BS_UDB_1_0_0_CONFIG_VAL), /* TD 33 */ + (const void *)(BS_UDB_1_0_1_CONFIG_VAL), /* TD 34 */ + (const void *)(BS_DSI0_3_HV_ROUTING_VAL), /* TD 35 */ + (const void *)(BS_DSI0_4_HV_ROUTING_VAL), /* TD 36 */ + (const void *)(BS_DSISWITCH_0_5_VAL), /* TD 37 */ + (const void *)(BS_DSI0_5_HV_ROUTING_VAL), /* TD 38 */ + (const void *)(BS_UDBSWITCH_1_0_VAL), /* TD 39 */ + (const void *)(BS_UDB_2_0_HV_ROUTING_VAL), /* TD 40 */ + (const void *)(BS_UDB_2_1_HV_ROUTING_VAL), /* TD 41 */ + (const void *)(BS_UDB_2_2_HV_ROUTING_VAL), /* TD 42 */ + (const void *)(BS_UDB_1_3_HV_ROUTING_VAL), /* TD 43 */ + (const void *)(BS_UDBSWITCH_1_3_VAL), /* TD 44 */ + (const void *)(BS_UDB_2_3_HV_ROUTING_VAL), /* TD 45 */ + (const void *)(BS_UDBSWITCH_1_4_VAL), /* TD 46 */ + (const void *)(BS_UDB_2_4_HV_ROUTING_VAL), /* TD 47 */ + (const void *)(BS_UDB_1_5_HV_ROUTING_VAL), /* TD 48 */ + (const void *)(BS_UDBSWITCH_1_5_VAL), /* TD 49 */ + (const void *)(BS_UDB_2_5_HV_ROUTING_VAL), /* TD 50 */ + (const void *)(BS_DSI3_1_HV_ROUTING_VAL), /* TD 51 */ + (const void *)(BS_DSISWITCH_1_2_VAL), /* TD 52 */ + (const void *)(BS_DSI3_2_HV_ROUTING_VAL), /* TD 53 */ + (const void *)(BS_DSI3_3_HV_ROUTING_VAL), /* TD 54 */ + (const void *)(BS_DSI3_4_HV_ROUTING_VAL), /* TD 55 */ + (const void *)(BS_DSISWITCH_1_5_VAL), /* TD 56 */ + (const void *)(BS_DSI3_5_HV_ROUTING_VAL), /* TD 57 */ + (const void *)(BS_UCFG_BCTL1_VAL), /* TD 58 */ + (const void *)(BS_UCFG_BCTL0_VAL), /* TD 59 */ }; @@ -464,7 +507,7 @@ static void cfg_dma_init(void) CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CFGMEM0_CFG0, 0x10u); /* set burstcnt */ CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CH0_BASIC_CFG, 0x01u); /* enable ch0 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH0_BASIC_STATUS+1u), 0x00u); /* set first TD to 0 */ - CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0, 51u*8u); /* transfer size */ + CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0, 59u*8u); /* transfer size */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+2u), 0x01u); /* set next TD to 1 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+3u), 0x03u); /* set TD flags */ CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD1, (uint16)(uint32)CFG_TD_LIST0); /* set td0's src addr */ @@ -473,7 +516,7 @@ static void cfg_dma_init(void) CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_CFGMEM0_CFG1+2u), (uint16)(CYDEV_PHUB_TDMEM1_BASE >> 16)); /* set ch0's dst high addr */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH1_BASIC_STATUS+1u), 0x09u); /* ch1 first TD: 9 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH2_BASIC_STATUS+1u), 0x0Du); /* ch2 first TD: 13 */ - CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH5_BASIC_STATUS+1u), 0x1Au); /* ch5 first TD: 26 */ + CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH5_BASIC_STATUS+1u), 0x19u); /* ch5 first TD: 25 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH6_BASIC_STATUS+1u), 0x1Bu); /* ch6 first TD: 27 */ CY_CFG_MEMORY_BARRIER(); @@ -484,7 +527,7 @@ static void cfg_dma_init(void) while (CY_GET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0) != 0u) { } /* Recombine TD source table (CFG_TD_ADDR0) with full TD table (CFG_TD_LIST0) */ - for (i = 0u; i < 51u; i++) + for (i = 0u; i < 59u; i++) { CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_TDMEM1_ORIG_TD1 + (sizeof(struct td_t)*i)), (uint16)(uint32)CFG_TD_ADDR0[i]); } @@ -527,15 +570,13 @@ static void cfg_dma_init(void) static void ClockSetup(void); static void ClockSetup(void) { - uint32 timeout; - uint8 pllLock; /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x000Bu); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2), 0x18u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0019u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2), 0x18u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u); @@ -548,12 +589,8 @@ static void ClockSetup(void) /* Configure PLL based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0008u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u); - /* Wait up to 250us for the PLL to lock */ - pllLock = 0u; - for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { - pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); - CyDelayCycles(10u * 12u); /* Delay 10us based on 12MHz clock */ - } + /* Wait 250us for the PLL to lock */ + CyDelayCycles(250u * 12u); /* Delay 250us based on 12MHz clock */ /* Configure Bus/Master Clock based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x03u); @@ -653,6 +690,7 @@ void SetAnalogRoutingPumps(uint8 enabled) * void * *******************************************************************************/ + void cyfitter_cfg(void) { #ifdef CYGlobalIntDisable diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index e3c9cdf..06bfc82 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.h -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 96bbbe9..2c4dc87 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -3,6 +3,80 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" +/* Timer_1_TimerUDB */ +.set Timer_1_TimerUDB_nrstSts_stsreg__0__MASK, 0x01 +.set Timer_1_TimerUDB_nrstSts_stsreg__0__POS, 0 +.set Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set Timer_1_TimerUDB_nrstSts_stsreg__2__MASK, 0x04 +.set Timer_1_TimerUDB_nrstSts_stsreg__2__POS, 2 +.set Timer_1_TimerUDB_nrstSts_stsreg__3__MASK, 0x08 +.set Timer_1_TimerUDB_nrstSts_stsreg__3__POS, 3 +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK, 0x0D +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG, CYREG_B1_UDB04_MSK +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG, CYREG_B1_UDB04_ST +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK, 0x80 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS, 7 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG, CYREG_B1_UDB04_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG, CYREG_B1_UDB04_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK, 0x80 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG, CYREG_B1_UDB04_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG, CYREG_B1_UDB05_06_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG, CYREG_B1_UDB05_06_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG, CYREG_B1_UDB05_06_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG, CYREG_B1_UDB05_06_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG, CYREG_B1_UDB05_06_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG, CYREG_B1_UDB05_06_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG, CYREG_B1_UDB05_A0_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG, CYREG_B1_UDB05_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG, CYREG_B1_UDB05_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG, CYREG_B1_UDB05_D0_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG, CYREG_B1_UDB05_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG, CYREG_B1_UDB05_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG, CYREG_B1_UDB05_F0_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG, CYREG_B1_UDB05_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG, CYREG_B1_UDB05_F1 + /* SPIM_IntClock */ .set SPIM_IntClock__CFG0, CYREG_CLKDIST_DCFG0_CFG0 .set SPIM_IntClock__CFG1, CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ .set SPIM_IntClock__PM_STBY_MSK, 0x01 /* UART_1_BUART */ -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG, CYREG_B0_UDB01_02_A0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG, CYREG_B0_UDB01_02_A1 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG, CYREG_B0_UDB01_02_D0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG, CYREG_B0_UDB01_02_D1 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG, CYREG_B0_UDB01_02_F0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG, CYREG_B0_UDB01_02_F1 -.set UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG, CYREG_B0_UDB01_A0_A1 -.set UART_1_BUART_sTX_TxShifter_u0__A0_REG, CYREG_B0_UDB01_A0 -.set UART_1_BUART_sTX_TxShifter_u0__A1_REG, CYREG_B0_UDB01_A1 -.set UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG, CYREG_B0_UDB01_D0_D1 -.set UART_1_BUART_sTX_TxShifter_u0__D0_REG, CYREG_B0_UDB01_D0 -.set UART_1_BUART_sTX_TxShifter_u0__D1_REG, CYREG_B0_UDB01_D1 -.set UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG, CYREG_B0_UDB01_F0_F1 -.set UART_1_BUART_sTX_TxShifter_u0__F0_REG, CYREG_B0_UDB01_F0 -.set UART_1_BUART_sTX_TxShifter_u0__F1_REG, CYREG_B0_UDB01_F1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set UART_1_BUART_sTX_TxShifter_u0__A0_REG, CYREG_B0_UDB04_A0 +.set UART_1_BUART_sTX_TxShifter_u0__A1_REG, CYREG_B0_UDB04_A1 +.set UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set UART_1_BUART_sTX_TxShifter_u0__D0_REG, CYREG_B0_UDB04_D0 +.set UART_1_BUART_sTX_TxShifter_u0__D1_REG, CYREG_B0_UDB04_D1 +.set UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set UART_1_BUART_sTX_TxShifter_u0__F0_REG, CYREG_B0_UDB04_F0 +.set UART_1_BUART_sTX_TxShifter_u0__F1_REG, CYREG_B0_UDB04_F1 .set UART_1_BUART_sTX_TxSts__0__MASK, 0x01 .set UART_1_BUART_sTX_TxSts__0__POS, 0 -.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST .set UART_1_BUART_sTX_TxSts__1__MASK, 0x02 .set UART_1_BUART_sTX_TxSts__1__POS, 1 .set UART_1_BUART_sTX_TxSts__2__MASK, 0x04 @@ -43,26 +117,26 @@ .set UART_1_BUART_sTX_TxSts__3__MASK, 0x08 .set UART_1_BUART_sTX_TxSts__3__POS, 3 .set UART_1_BUART_sTX_TxSts__MASK, 0x0F -.set UART_1_BUART_sTX_TxSts__MASK_REG, CYREG_B0_UDB02_MSK -.set UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set UART_1_BUART_sTX_TxSts__STATUS_REG, CYREG_B0_UDB02_ST -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG, CYREG_B0_UDB00_01_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG, CYREG_B0_UDB00_01_D0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG, CYREG_B0_UDB00_01_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG, CYREG_B0_UDB00_01_F0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG, CYREG_B0_UDB00_01_F1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG, CYREG_B0_UDB00_A0_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG, CYREG_B0_UDB00_A0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG, CYREG_B0_UDB00_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG, CYREG_B0_UDB00_D0_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG, CYREG_B0_UDB00_D0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG, CYREG_B0_UDB00_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG, CYREG_B0_UDB00_F0_F1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG, CYREG_B0_UDB00_F0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG, CYREG_B0_UDB00_F1 +.set UART_1_BUART_sTX_TxSts__MASK_REG, CYREG_B0_UDB04_MSK +.set UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set UART_1_BUART_sTX_TxSts__STATUS_REG, CYREG_B0_UDB04_ST +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG, CYREG_B0_UDB05_A0_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG, CYREG_B0_UDB05_A0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG, CYREG_B0_UDB05_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG, CYREG_B0_UDB05_D0_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG, CYREG_B0_UDB05_D0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG, CYREG_B0_UDB05_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG, CYREG_B0_UDB05_F0_F1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG, CYREG_B0_UDB05_F0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG, CYREG_B0_UDB05_F1 /* LCD_LCDPort */ .set LCD_LCDPort__0__MASK, 0x01 @@ -243,8 +317,8 @@ .set SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set SPIM_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB03_MSK .set SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST .set SPIM_BSPIM_RxStsReg__4__MASK, 0x10 .set SPIM_BSPIM_RxStsReg__4__POS, 4 .set SPIM_BSPIM_RxStsReg__5__MASK, 0x20 @@ -252,13 +326,13 @@ .set SPIM_BSPIM_RxStsReg__6__MASK, 0x40 .set SPIM_BSPIM_RxStsReg__6__POS, 6 .set SPIM_BSPIM_RxStsReg__MASK, 0x70 -.set SPIM_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB00_MSK -.set SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set SPIM_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB00_ST +.set SPIM_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB02_MSK +.set SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SPIM_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB02_ST .set SPIM_BSPIM_TxStsReg__0__MASK, 0x01 .set SPIM_BSPIM_TxStsReg__0__POS, 0 -.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST .set SPIM_BSPIM_TxStsReg__1__MASK, 0x02 .set SPIM_BSPIM_TxStsReg__1__POS, 1 .set SPIM_BSPIM_TxStsReg__2__MASK, 0x04 @@ -268,9 +342,9 @@ .set SPIM_BSPIM_TxStsReg__4__MASK, 0x10 .set SPIM_BSPIM_TxStsReg__4__POS, 4 .set SPIM_BSPIM_TxStsReg__MASK, 0x1F -.set SPIM_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK -.set SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SPIM_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST +.set SPIM_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB00_MSK +.set SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set SPIM_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB00_ST .set SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 .set SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 .set SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ .set Pin_4__SHIFT, 3 .set Pin_4__SLW, CYREG_PRT3_SLW +/* Pin_5 */ +.set Pin_5__0__MASK, 0x10 +.set Pin_5__0__PC, CYREG_PRT3_PC4 +.set Pin_5__0__PORT, 3 +.set Pin_5__0__SHIFT, 4 +.set Pin_5__AG, CYREG_PRT3_AG +.set Pin_5__AMUX, CYREG_PRT3_AMUX +.set Pin_5__BIE, CYREG_PRT3_BIE +.set Pin_5__BIT_MASK, CYREG_PRT3_BIT_MASK +.set Pin_5__BYP, CYREG_PRT3_BYP +.set Pin_5__CTL, CYREG_PRT3_CTL +.set Pin_5__DM0, CYREG_PRT3_DM0 +.set Pin_5__DM1, CYREG_PRT3_DM1 +.set Pin_5__DM2, CYREG_PRT3_DM2 +.set Pin_5__DR, CYREG_PRT3_DR +.set Pin_5__INP_DIS, CYREG_PRT3_INP_DIS +.set Pin_5__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set Pin_5__LCD_EN, CYREG_PRT3_LCD_EN +.set Pin_5__MASK, 0x10 +.set Pin_5__PORT, 3 +.set Pin_5__PRT, CYREG_PRT3_PRT +.set Pin_5__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set Pin_5__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set Pin_5__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set Pin_5__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set Pin_5__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set Pin_5__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set Pin_5__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set Pin_5__PS, CYREG_PRT3_PS +.set Pin_5__SHIFT, 4 +.set Pin_5__SLW, CYREG_PRT3_SLW + /* Tx_1 */ .set Tx_1__0__MASK, 0x80 .set Tx_1__0__PC, CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ /* SS */ .set SS_Async_ctrl_reg__0__MASK, 0x01 .set SS_Async_ctrl_reg__0__POS, 0 -.set SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK .set SS_Async_ctrl_reg__1__MASK, 0x02 .set SS_Async_ctrl_reg__1__POS, 1 -.set SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SS_Async_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SS_Async_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SS_Async_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SS_Async_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SS_Async_ctrl_reg__MASK, 0x03 -.set SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SS_Async_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -.set SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SS_Async_ctrl_reg__2__MASK, 0x04 +.set SS_Async_ctrl_reg__2__POS, 2 +.set SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SS_Async_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SS_Async_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SS_Async_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SS_Async_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SS_Async_ctrl_reg__MASK, 0x07 +.set SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SS_Async_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL /* Miscellaneous */ /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ @@ -494,16 +602,17 @@ .set CYDEV_CONFIG_FASTBOOT_ENABLED, 0 .set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 -.set CYDEV_CHIP_MEMBER_5A, 2 +.set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_FAMILY_PSOC5, 3 -.set CYDEV_CHIP_DIE_PANTHER, 2 +.set CYDEV_CHIP_DIE_PANTHER, 3 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PANTHER .set BCLK__BUS_CLK__HZ, 24000000 .set BCLK__BUS_CLK__KHZ, 24000 .set BCLK__BUS_CLK__MHZ, 24 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC5LP, 3 +.set CYDEV_CHIP_DIE_PSOC4A, 2 +.set CYDEV_CHIP_DIE_PSOC5LP, 4 .set CYDEV_CHIP_DIE_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 @@ -511,13 +620,16 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x0E13C069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_5B, 3 +.set CYDEV_CHIP_MEMBER_4A, 2 +.set CYDEV_CHIP_MEMBER_5B, 4 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5A .set CYDEV_CHIP_REVISION_3A_ES1, 0 .set CYDEV_CHIP_REVISION_3A_ES2, 1 .set CYDEV_CHIP_REVISION_3A_ES3, 3 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 @@ -530,6 +642,8 @@ .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 .set CYDEV_CHIP_REV_PANTHER_ES0, 0 .set CYDEV_CHIP_REV_PANTHER_ES1, 1 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 .set CYDEV_CONFIGURATION_COMPRESSED, 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index fbcacf6..11eee07 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -3,6 +3,80 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc +; Timer_1_TimerUDB +Timer_1_TimerUDB_nrstSts_stsreg__0__MASK EQU 0x01 +Timer_1_TimerUDB_nrstSts_stsreg__0__POS EQU 0 +Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +Timer_1_TimerUDB_nrstSts_stsreg__2__MASK EQU 0x04 +Timer_1_TimerUDB_nrstSts_stsreg__2__POS EQU 2 +Timer_1_TimerUDB_nrstSts_stsreg__3__MASK EQU 0x08 +Timer_1_TimerUDB_nrstSts_stsreg__3__POS EQU 3 +Timer_1_TimerUDB_nrstSts_stsreg__MASK EQU 0x0D +Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG EQU CYREG_B1_UDB04_MSK +Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG EQU CYREG_B1_UDB04_ST +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK EQU 0x80 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS EQU 7 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG EQU CYREG_B1_UDB04_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG EQU CYREG_B1_UDB04_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK EQU 0x80 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG EQU CYREG_B1_UDB04_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG EQU CYREG_B1_UDB05_A0 +Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG EQU CYREG_B1_UDB05_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG EQU CYREG_B1_UDB05_D0 +Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG EQU CYREG_B1_UDB05_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG EQU CYREG_B1_UDB05_F0 +Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG EQU CYREG_B1_UDB05_F1 + ; SPIM_IntClock SPIM_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 SPIM_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ SPIM_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SPIM_IntClock__PM_STBY_MSK EQU 0x01 ; UART_1_BUART -UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1 -UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1 -UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1 -UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1 -UART_1_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB01_A0 -UART_1_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB01_A1 -UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1 -UART_1_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB01_D0 -UART_1_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB01_D1 -UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1 -UART_1_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB01_F0 -UART_1_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB01_F1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +UART_1_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB04_A0 +UART_1_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB04_A1 +UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +UART_1_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB04_D0 +UART_1_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB04_D1 +UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +UART_1_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB04_F0 +UART_1_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB04_F1 UART_1_BUART_sTX_TxSts__0__MASK EQU 0x01 UART_1_BUART_sTX_TxSts__0__POS EQU 0 -UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST UART_1_BUART_sTX_TxSts__1__MASK EQU 0x02 UART_1_BUART_sTX_TxSts__1__POS EQU 1 UART_1_BUART_sTX_TxSts__2__MASK EQU 0x04 @@ -43,26 +117,26 @@ UART_1_BUART_sTX_TxSts__2__POS EQU 2 UART_1_BUART_sTX_TxSts__3__MASK EQU 0x08 UART_1_BUART_sTX_TxSts__3__POS EQU 3 UART_1_BUART_sTX_TxSts__MASK EQU 0x0F -UART_1_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB02_MSK -UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -UART_1_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB02_ST -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB00_A0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB00_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB00_D0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB00_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB00_F0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB00_F1 +UART_1_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB04_MSK +UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +UART_1_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB04_ST +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB05_A0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB05_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB05_D0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB05_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB05_F0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB05_F1 ; LCD_LCDPort LCD_LCDPort__0__MASK EQU 0x01 @@ -243,8 +317,8 @@ SPIM_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL SPIM_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB03_MSK SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SPIM_BSPIM_RxStsReg__4__MASK EQU 0x10 SPIM_BSPIM_RxStsReg__4__POS EQU 4 SPIM_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -252,13 +326,13 @@ SPIM_BSPIM_RxStsReg__5__POS EQU 5 SPIM_BSPIM_RxStsReg__6__MASK EQU 0x40 SPIM_BSPIM_RxStsReg__6__POS EQU 6 SPIM_BSPIM_RxStsReg__MASK EQU 0x70 -SPIM_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB00_MSK -SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SPIM_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB00_ST +SPIM_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB02_MSK +SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SPIM_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB02_ST SPIM_BSPIM_TxStsReg__0__MASK EQU 0x01 SPIM_BSPIM_TxStsReg__0__POS EQU 0 -SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST SPIM_BSPIM_TxStsReg__1__MASK EQU 0x02 SPIM_BSPIM_TxStsReg__1__POS EQU 1 SPIM_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -268,9 +342,9 @@ SPIM_BSPIM_TxStsReg__3__POS EQU 3 SPIM_BSPIM_TxStsReg__4__MASK EQU 0x10 SPIM_BSPIM_TxStsReg__4__POS EQU 4 SPIM_BSPIM_TxStsReg__MASK EQU 0x1F -SPIM_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SPIM_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST +SPIM_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB00_MSK +SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SPIM_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB00_ST SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ Pin_4__PS EQU CYREG_PRT3_PS Pin_4__SHIFT EQU 3 Pin_4__SLW EQU CYREG_PRT3_SLW +; Pin_5 +Pin_5__0__MASK EQU 0x10 +Pin_5__0__PC EQU CYREG_PRT3_PC4 +Pin_5__0__PORT EQU 3 +Pin_5__0__SHIFT EQU 4 +Pin_5__AG EQU CYREG_PRT3_AG +Pin_5__AMUX EQU CYREG_PRT3_AMUX +Pin_5__BIE EQU CYREG_PRT3_BIE +Pin_5__BIT_MASK EQU CYREG_PRT3_BIT_MASK +Pin_5__BYP EQU CYREG_PRT3_BYP +Pin_5__CTL EQU CYREG_PRT3_CTL +Pin_5__DM0 EQU CYREG_PRT3_DM0 +Pin_5__DM1 EQU CYREG_PRT3_DM1 +Pin_5__DM2 EQU CYREG_PRT3_DM2 +Pin_5__DR EQU CYREG_PRT3_DR +Pin_5__INP_DIS EQU CYREG_PRT3_INP_DIS +Pin_5__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +Pin_5__LCD_EN EQU CYREG_PRT3_LCD_EN +Pin_5__MASK EQU 0x10 +Pin_5__PORT EQU 3 +Pin_5__PRT EQU CYREG_PRT3_PRT +Pin_5__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +Pin_5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +Pin_5__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +Pin_5__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +Pin_5__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +Pin_5__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +Pin_5__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +Pin_5__PS EQU CYREG_PRT3_PS +Pin_5__SHIFT EQU 4 +Pin_5__SLW EQU CYREG_PRT3_SLW + ; Tx_1 Tx_1__0__MASK EQU 0x80 Tx_1__0__PC EQU CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ Tx_1__SLW EQU CYREG_PRT3_SLW ; SS SS_Async_ctrl_reg__0__MASK EQU 0x01 SS_Async_ctrl_reg__0__POS EQU 0 -SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SS_Async_ctrl_reg__1__MASK EQU 0x02 SS_Async_ctrl_reg__1__POS EQU 1 -SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SS_Async_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SS_Async_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SS_Async_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SS_Async_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SS_Async_ctrl_reg__MASK EQU 0x03 -SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SS_Async_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SS_Async_ctrl_reg__2__MASK EQU 0x04 +SS_Async_ctrl_reg__2__POS EQU 2 +SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SS_Async_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SS_Async_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SS_Async_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SS_Async_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SS_Async_ctrl_reg__MASK EQU 0x07 +SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SS_Async_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL ; Miscellaneous ; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release @@ -494,16 +602,17 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2 CYDEV_CONFIG_FASTBOOT_ENABLED EQU 0 CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 -CYDEV_CHIP_MEMBER_5A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 -CYDEV_CHIP_DIE_PANTHER EQU 2 +CYDEV_CHIP_DIE_PANTHER EQU 3 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PANTHER BCLK__BUS_CLK__HZ EQU 24000000 BCLK__BUS_CLK__KHZ EQU 24000 BCLK__BUS_CLK__MHZ EQU 24 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC5LP EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 @@ -511,13 +620,16 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x0E13C069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_5B EQU 3 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5A CYDEV_CHIP_REVISION_3A_ES1 EQU 0 CYDEV_CHIP_REVISION_3A_ES2 EQU 1 CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 @@ -530,6 +642,8 @@ CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 CYDEV_CONFIGURATION_COMPRESSED EQU 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cypins.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cypins.h index fcb4129..ed01434 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cypins.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cypins.h -* Version 3.30 +* Version 3.40 * * Description: * This file contains the function prototypes and constants used for port/pin @@ -11,7 +11,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cytypes.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cytypes.h index 8fdb501..0187c1b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cytypes.h -* Version 3.30 +* Version 3.40 * * Description: * CyTypes provides register access macros and approved types for use in @@ -17,7 +17,7 @@ * (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -83,7 +83,9 @@ typedef float float32; #if(!CY_PSOC3) - typedef double float64; + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; #endif /* (!CY_PSOC3) */ @@ -167,6 +169,8 @@ typedef char char8; #define CYSMALL small #define CYXDATA xdata #define XDATA xdata + + #define CY_NOINIT #else @@ -183,6 +187,13 @@ typedef char char8; #define CYSMALL #define CYXDATA #define XDATA + + #if defined(__ARMCC_VERSION) + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #elif defined (__GNUC__) + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #endif /* (__ARMCC_VERSION) */ + #endif /* (CY_PSOC3) */ @@ -254,17 +265,17 @@ typedef volatile uint32 CYXDATA reg32; #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ - #define CY_GET_XTND_REG8(addr) cyread8(addr) - #define CY_SET_XTND_REG8(addr, value) cywrite8(addr,value) + #define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) - #define CY_GET_XTND_REG16(addr) cyread16(addr) - #define CY_SET_XTND_REG16(addr, value) cywrite16(addr,value) + #define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) - #define CY_GET_XTND_REG24(addr) cyread24(addr) - #define CY_SET_XTND_REG24(addr, value) cywrite24(addr,value) + #define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) - #define CY_GET_XTND_REG32(addr) cyread32(addr) - #define CY_SET_XTND_REG32(addr, value) cywrite32(addr,value) + #define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) #else diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyutils.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyutils.c index b064c5e..784a00f 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,12 +1,12 @@ /******************************************************************************* * FILENAME: cyutils.c -* Version 3.30 +* Version 3.40 * * Description: * CyUtils provides function to handle 24-bit value writes. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.c index 29341e2..57a4726 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.h index 273fac5..1b4b352 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin_aliases.h index a2d4f29..c6c88c2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_miso_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.c index 775ddf9..6eee973 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.h index 331acd5..7af1137 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin_aliases.h index 3f51ef6..1bab883 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_mosi_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.c b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.c index 2fbcbe2..7e79e33 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.h index 2a29717..03edcc5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin_aliases.h index 3530ec1..68472d6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/m_sclk_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/post_link.bat b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/post_link.bat index ec1b222..7c32528 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/post_link.bat +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/post_link.bat @@ -15,5 +15,5 @@ move "%~1\%~2\%~n3.hex" "%~1\%~2\%~n3.ihx" @IF %errorlevel% NEQ 0 EXIT /b %errorlevel% CD /D "C:\Keil\UV4" @IF %errorlevel% NEQ 0 EXIT /b %errorlevel% -IF NOT EXIST "C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.svd" rem "C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.sfr" +IF NOT EXIST "C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.svd" rem "C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.sfr" @IF %errorlevel% NEQ 0 EXIT /b %errorlevel% diff --git a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/project.h b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/project.h index 63c9121..7ac38be 100644 --- a/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/project.h +++ b/PSOC5_SPI_LSM303D.cydsn/Generated_Source/PSoC5/project.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: project.h - * PSoC Creator 2.2 Component Pack 5 + * PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator and should not @@ -8,11 +8,12 @@ * * ******************************************************************************** - * Copyright 2008-2011, Cypress Semiconductor Corporation. All rights reserved. + * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. ********************************************************************************/ + #include #include #include @@ -37,6 +38,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -51,3 +55,4 @@ #include /*[]*/ + diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cycdx b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cycdx index a249682..8bc505b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cycdx +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cycdx @@ -1,18 +1,66 @@ + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + @@ -22,24 +70,29 @@ - - - - - - + + + - - + + + + + + + + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cydwr b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cydwr index 1b872365ca58558a97109efce23da1916367ca77..dd301cd9656a57963d7d3a3e13a26a9c12602fb7 100644 GIT binary patch literal 30560 zcmeI5Uu+%OUB@TOhPG_Clu!zyrSjIZA*gkFeXs4MHL_rm5_>%Ku8E4`hdg(5`BaRkZ32gqNoq355Tf7WTh3~&-u-n z`OWy=n~CGtPUTp0@62z``OW#A-~Zn^bMx|hA5HwfHxI?DC%%684i}HU!RO&Sz|-uJ zc>cM^UpsV47chzut?16V zWI6d%a$2pfC+o@Z?c~s#dH}=8QLiOkHCavC$!M~cj3*;P(@MtlIik;HeXrmjiVZ$%N<`QHx1^ z1Eb}NjwR9F(Xpbxj#{PJTLNl*fcowFx{@sFrak=7o5RKPbvqHYP3Wt#Y*x(eik8cP zp-ZCuR`N;B@^kvTpz|BLx2ne;*VU%(UKWclB_B+N1iPW0*92P^bUDDDQQM6mFo?&8 zh3B|tARhFZNp7nBram{+_QPtms&gbfhP=>$WHVNJ7!qAhWJcP`W~=qc+mM5~2hr`Zn#xgWlb0U7#6UDv)} z(5kNepdf{)rx}-N_Cw*b;egW2)bY?U^+MOK%4S~;HhxV5G|yuJ%ynJkfj0CEbnMBm zi5eb5H*Q|mts7F$qes7r_Wt6w^ll+Xbl_2mmL5jkdQM&yUyhION;rr*vC+Hl-=pKg zoeX{B=vNC>k#xQ;Z`Q;kS7W~e>HH3f_m(7@1jB6|q(>v+jHrj$h$sjjfSqs4&SUu} zg0)}P=c=G9`fkg2G`9Q%PjAbQ;oDWye)tZFo;U3h&_}mrJ_)-?1<%QduS)?B1omMU z*urR~St==!WKd}!>79^i9S<=IvPz0fo?_*INu3khw?ZU8B8ly&?U)YA0b^?0(Y>+e z@>>K7(c`b>{(e(9EN;=z2;~U}u=ixT6gO%S`PO*9t_)Tku*_mOD8`UJ-8^uaW>19A z#&HfY)$na_Yn<=ZSIiiyIj7~%^&x$CcoryPnggY7Nc9{h)>FPm%?`c!?#)P~lKZb7?w7e?NvP=;b5SY7G1hSMp5C;-k zf?JH9!N{b$GIN-^6M|7QYH3&>3fJu*Ruj65IJI@Zt@~ga4ObXO0%odE2-KLasV=Mt zx+Fp5y8$iadK``xCTF5aU*>|t^(C-gkj!nU&M=hBhqEgh&t{HKa}NtBAxtP7DCUo6 zj&J9gX*L~3kTW(SAFm@H+d<@Gb>y8LMBb?*ZzPg+R`i*cc7Z(2ju-PbP}mz{9xX8E z>ebr8IcW*G6Bcamssy|h{6EnE6(UrR;-tk6EnSf{t_HQj_ENN5Qw!RR2Suai(m+MF z&cMcwOIU3^cdfutB$HA({DhW{K2K;qC=0iBKB3n8fI4hZjdwVtmLw7?Pw32|aux@Sy3s%< z9O|l#MMTIbbxdlrHaqxUO!Yllo}JY@9FU{#eHsrdK_?YBm1{>Ua$^=6+}O^TWel-a z)UctPyucPzi2Ejkjj|ZhB!TGB&E|Ik<=G0#b31|ZnF`8h zcLL>N1?AFCpnSf9atGq%G`n6wSz6?Kbby}Yw*tzVN)Y4{K3FzLXhk+?AtXT;%d2La zO*ydI=E_le95pVWbD$D2r}c?cnjNTwglrjkVQF(H567o zU>xZ!iJ&dOk*ZsIOX^N)-_qx#J|P_vNr0y`C3{6y&a_T%rje*p{-JI{3{QGXI&SMp z6m6^sO!`ZS*vhJu=U^IT3Pg3!OWaV`qcj2Mn19Mzw)juUp4BZ=IQAZ+W>k?7SoTp< z^tGZ4qHCKy_W|#El(;b>aDsvgGHIoWsBkNy#%g38ondUo)e_@kIU1&ga@>6v{I=~L zoMhGtFX&xdyhf`qj+hQYWjIE-Y^$Gem5h@d6j`O*V$0*q16yME0q=U0xEU$gur0k% z2*f;6!ZzyQ9+GM6wpbM;nB@w1hN(0svJa?ZrP5Uh;2krM#lYD?DbzuqSryx=OdS`y zipygQGHpkLCcPz8^SvJ!)dWZUjUNJ4rey$f;SV8m&A3#+O z60qsE%t?{Kc!UoyQrY^3Y{DaY(tdIe$(qi|awdfJBYTP`<3eo)wAL z^=GfzG~fk0YdB(EA@@19+SZ_deH%`i{a(P9Zv}amF4zWjMI+)R81_dqwpb(o`QDAM zg~h*m6@^&W{>&deoe5~*5p{fCfGh}GSROI8w#w+Y|$jm{xO^z{CokgkwFS!O|BG8 z((IpI*H1dQNBL3>?hFZ&FcbFHccnrN)LoNY-)&~`3~`ukN+2%56Iu+w88#T$Qn09I zZ&~ccVGzgQJ#A}E6i(jzaKk*Jr()@Nop3{cH)TaOn+&&yb$eB~2#ImZ44Gh&04t`a z5W)H-!zD!}d1d(quZSB5iu=H=d?>)ybcJ7x?uAuNn*tVkET^}{Ac7wDK#@cd1lW2u zK|>+AAJp(JNb66_lrK7>uj;|;?z)@=ghH|cT}&gCvBHY;!r77fSkO$GZKE+dpo?UO z)RueHPN0D*dravG<=FK@t%A0;FM_}aS4xN;_e!uvZ)^74B@7}i=t0+od#4K#Vu6fj zu^vur!pZn$gRl^BQkQXY+bLnzROf+CB&Z7-V%i@R3<)tJS>r%1n!{QS}+u8B*O~1nd^( zaDJbyz?bEz@zS`-uC91Fl#QcoCM|f0#YaBRsbNRor;?BBW-f>LxQK=Kx$T8q^tR}a z)tMLCbvlhWn79@ajT050a%a32w=hM}vt%RNgWF_HgX2E+t zPfP-Hd`-5DXG3V3z1xo)LczdBs11FuXe4Xl>@!6NTfWb6_Udp`gkKf`@d>ukA@4wV zc0(Au!W_dWMqSXU`?_%G>#ge(f7BE3{(%0LM!*9;8^-ax&XzUb!~pilII_3+uDmUa z_*@a!EMUw9f|;Myj6bF0qGbP!cN8cQTeW7T3UgA08L7yK&ZZ@AGdeTFhlw~TXh-d+ z*iGr~l-kg0R>lLjFq_Z8z~T*q@8Bx@;$uQe8i5%<-ZE@t{LTd9H>#lNRPs_jgEcJNT$I*swL586@>ZSL z^N6M8(PZEKyOp!4ZbPmcPO;UfV@*WOyh2Ts0xz0tfn&z)-4ji3D7{pQW<(Y#iG%f` zSz4Yn^P=hD+Z0W9C`{|Ym*a-Sh?G&;`9oIJB+VpFX~zLsueC95_bRy!?}_es1s$0HZki~Xgv!RWrfC1Fa$&slQIKlCh$=h2ci;c;Y1z8Ae|6-V8QWx+l)MZ zH8277soKw9>jSTF7>g4*Jf!ioCA_6$^YMyQ)HlXswe?dwWeQLYVjhGD?2^$R6@N~M zAM@hNq`oow(<0Z5K3nzSAt|Pf&rV13^+~}n2`D`G=z)MBBBUXW^7S4fa#S3}abeH# zc>KB-32RI{7lW;DWZ_Zivl`3=S@}8DUWo$ENUgUDg?_S3L0E))zLzm=nl-WZ_`Hbc z?)i$g(>wlpz7rlrJf81u*WMd?pKtki(2xHvsS1@YGvaU=(_m?fnFcn*P#q&xnUKy= z#hD45rW!}JWUzEkC;(l#L_nbjFdC=TMJ&ZrDi8wNHZ2u{DHb~uL_osrBUE2Oy%_zq7vYA&J9 zclf<5wl(9sEIK8ben_lr_o9XxMaJty#hWlR1ZH}m$eigTGWQx491jy=dFb6ug{UM? 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Creator\warp\lib\common\cy_psoc3_inc.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.rpt b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.rpt index e1a5509..a4a22fe 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.rpt +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.rpt @@ -1,16 +1,16 @@ -Loading plugins phase: Elapsed time ==> 0s.201ms -Initializing data phase: Elapsed time ==> 2s.741ms +Loading plugins phase: Elapsed time ==> 0s.206ms +Initializing data phase: Elapsed time ==> 3s.144ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 -s C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\Generated_Source\PSoC5 -- -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 -s C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\Generated_Source\PSoC5 -- -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ADD: prj.M0245: information: PSoC 5LP provides many improvements over PSoC 5. Learn more about migrating to PSoC 5LP at www.cypress.com/go/PSoC5LP +ADD: prj.M0246: information: PSoC 5LP provides many improvements over PSoC 5. Learn more about migrating to PSoC 5LP at www.cypress.com/go/PSoC5LP * PSOC5_SPI_LSM303D () -Elaboration phase: Elapsed time ==> 2s.691ms +Elaboration phase: Elapsed time ==> 3s.174ms -HDL generation phase: Elapsed time ==> 0s.072ms +HDL generation phase: Elapsed time ==> 0s.115ms | | | | | | | @@ -28,23 +28,23 @@ HDL generation phase: Elapsed time ==> 0s.072ms ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog ====================================================================== ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog ====================================================================== ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : vlogfe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Fri Mar 22 10:33:23 2013 +Thu Jul 25 16:48:52 2013 ====================================================================== @@ -54,7 +54,7 @@ Options : -yv2 -q10 PSOC5_SPI_LSM303D.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Fri Mar 22 10:33:23 2013 +Thu Jul 25 16:48:52 2013 Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' @@ -67,6 +67,9 @@ Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\wa Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v' vpp: No errors. @@ -91,6 +94,8 @@ C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\conten C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1503, col 106): Note: Substituting module 'cmp_vv_vv' for '<'. C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1559, col 68): Note: Substituting module 'cmp_vv_vv' for '<'. C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1560, col 68): Note: Substituting module 'cmp_vv_vv' for '<'. +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v (line 368, col 46): Note: Substituting module 'cmp_vv_vv' for '='. +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v (line 374, col 62): Note: Substituting module 'add_vv_vv' for '+'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. @@ -100,11 +105,11 @@ vlogfe: No errors. ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : tovif -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Fri Mar 22 10:33:24 2013 +Thu Jul 25 16:48:53 2013 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,9 +120,9 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v'. @@ -126,6 +131,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\conte Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. @@ -135,11 +142,11 @@ tovif: No errors. ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : topld -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Fri Mar 22 10:33:24 2013 +Thu Jul 25 16:48:54 2013 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -150,9 +157,9 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v'. @@ -161,6 +168,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\conte Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. @@ -190,6 +199,12 @@ Detecting unused logic. \UART_1:BUART:reset_sr\ Net_258 Net_259 + \demux_1:tmp__demux_1_5_reg\ + \demux_1:tmp__demux_1_6_reg\ + \demux_1:tmp__demux_1_7_reg\ + Net_443 + Net_588 + Net_589 \SS:clk\ \SS:rst\ \SS:control_bus_7\ @@ -197,10 +212,24 @@ Detecting unused logic. \SS:control_bus_5\ \SS:control_bus_4\ \SS:control_bus_3\ - \SS:control_bus_2\ - - -Deleted 29 User equations/components. + \Timer_1:Net_260\ + Net_663 + Net_668 + \Timer_1:Net_53\ + \Timer_1:TimerUDB:ctrl_ten\ + \Timer_1:TimerUDB:ctrl_cmode_0\ + \Timer_1:TimerUDB:ctrl_tmode_1\ + \Timer_1:TimerUDB:ctrl_tmode_0\ + \Timer_1:TimerUDB:ctrl_ic_1\ + \Timer_1:TimerUDB:ctrl_ic_0\ + Net_667 + \Timer_1:TimerUDB:zeros_3\ + \Timer_1:TimerUDB:zeros_2\ + \Timer_1:Net_102\ + \Timer_1:Net_266\ + + +Deleted 49 User equations/components. Deleted 0 Synthesized equations/components. ------------------------------------------------------ @@ -238,8 +267,18 @@ Aliasing tmpOE__Pin_1_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_2_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_3_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_4_net_0 to tmpOE__m_miso_pin_net_0 +Aliasing tmpOE__Pin_5_net_0 to tmpOE__m_miso_pin_net_0 +Aliasing Net_12 to zero +Aliasing \Timer_1:TimerUDB:ctrl_cmode_1\ to zero +Aliasing \Timer_1:TimerUDB:trigger_enable\ to tmpOE__m_miso_pin_net_0 +Aliasing \Timer_1:TimerUDB:status_6\ to zero +Aliasing \Timer_1:TimerUDB:status_5\ to zero +Aliasing \Timer_1:TimerUDB:status_4\ to zero +Aliasing \Timer_1:TimerUDB:status_0\ to \Timer_1:TimerUDB:tc_i\ Aliasing \SPIM:BSPIM:dpcounter_one_reg\\D\ to \SPIM:BSPIM:tx_status_3\ Aliasing Net_256D to zero +Aliasing \Timer_1:TimerUDB:capture_last\\D\ to zero +Aliasing \Timer_1:TimerUDB:capture_out_reg_i\\D\ to \Timer_1:TimerUDB:capt_fifo_load_int\ Removing Lhs of wire one[7] = tmpOE__m_miso_pin_net_0[2] Removing Lhs of wire tmpOE__m_mosi_pin_net_0[10] = tmpOE__m_miso_pin_net_0[2] Removing Rhs of wire Net_30[11] = \SPIM:BSPIM:mosi_fin\[36] @@ -283,28 +322,55 @@ Removing Lhs of wire \UART_1:BUART:tx_status_4\[224] = zero[3] Removing Lhs of wire \UART_1:BUART:tx_status_1\[226] = \UART_1:BUART:tx_fifo_empty\[187] Removing Lhs of wire \UART_1:BUART:tx_status_3\[228] = \UART_1:BUART:tx_fifo_notfull\[186] Removing Lhs of wire tmpOE__Tx_1_net_0[236] = tmpOE__m_miso_pin_net_0[2] -Removing Rhs of wire mywire_1_1[242] = \SS:control_out_1\[266] -Removing Rhs of wire mywire_1_1[242] = \SS:control_1\[275] -Removing Rhs of wire mywire_1_0[243] = \SS:control_out_0\[267] -Removing Rhs of wire mywire_1_0[243] = \SS:control_0\[276] -Removing Rhs of wire Net_444[248] = \demux_1:tmp__demux_1_0_reg\[241] -Removing Rhs of wire Net_441[249] = \demux_1:tmp__demux_1_1_reg\[245] -Removing Rhs of wire Net_449[250] = \demux_1:tmp__demux_1_2_reg\[246] -Removing Rhs of wire Net_443[251] = \demux_1:tmp__demux_1_3_reg\[247] -Removing Lhs of wire tmpOE__Pin_1_net_0[278] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_2_net_0[285] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_3_net_0[292] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_4_net_0[299] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \SPIM:BSPIM:dpcounter_one_reg\\D\[306] = \SPIM:BSPIM:dpcounter_one\[54] -Removing Lhs of wire \SPIM:BSPIM:so_send_reg\\D\[307] = \SPIM:BSPIM:so_send\[34] -Removing Lhs of wire \SPIM:BSPIM:mosi_reg\\D\[314] = \SPIM:BSPIM:mosi_pre_reg\[51] -Removing Lhs of wire \SPIM:BSPIM:mosi_from_dp_reg\\D\[316] = \SPIM:BSPIM:mosi_from_dp\[41] -Removing Lhs of wire \UART_1:BUART:reset_reg\\D\[320] = zero[3] -Removing Lhs of wire \UART_1:BUART:tx_bitclk\\D\[325] = \UART_1:BUART:tx_bitclk_enable_pre\[173] -Removing Lhs of wire Net_256D[326] = zero[3] +Removing Rhs of wire mywire_1_2[242] = \SS:control_out_2\[273] +Removing Rhs of wire mywire_1_2[242] = \SS:control_2\[282] +Removing Rhs of wire mywire_1_1[243] = \SS:control_out_1\[274] +Removing Rhs of wire mywire_1_1[243] = \SS:control_1\[283] +Removing Rhs of wire mywire_1_0[244] = \SS:control_out_0\[275] +Removing Rhs of wire mywire_1_0[244] = \SS:control_0\[284] +Removing Rhs of wire Net_590[253] = \demux_1:tmp__demux_1_0_reg\[241] +Removing Rhs of wire Net_591[254] = \demux_1:tmp__demux_1_1_reg\[246] +Removing Rhs of wire Net_592[255] = \demux_1:tmp__demux_1_2_reg\[247] +Removing Rhs of wire Net_594[256] = \demux_1:tmp__demux_1_3_reg\[248] +Removing Rhs of wire Net_596[257] = \demux_1:tmp__demux_1_4_reg\[249] +Removing Lhs of wire tmpOE__Pin_1_net_0[286] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_2_net_0[293] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_3_net_0[300] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_4_net_0[307] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_5_net_0[314] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire Net_12[320] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:ctrl_enable\[338] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:ctrl_cmode_1\[340] = zero[3] +Removing Rhs of wire \Timer_1:TimerUDB:timer_enable\[349] = \Timer_1:TimerUDB:runmode_enable\[361] +Removing Rhs of wire \Timer_1:TimerUDB:run_mode\[350] = \Timer_1:TimerUDB:hwEnable_reg\[351] +Removing Lhs of wire \Timer_1:TimerUDB:trigger_enable\[353] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire \Timer_1:TimerUDB:tc_i\[355] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:hwEnable\[357] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:capt_fifo_load_int\[360] = \Timer_1:TimerUDB:capt_fifo_load\[348] +Removing Lhs of wire \Timer_1:TimerUDB:status_6\[364] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_5\[365] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_4\[366] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_0\[367] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:status_1\[368] = \Timer_1:TimerUDB:capt_fifo_load\[348] +Removing Rhs of wire \Timer_1:TimerUDB:status_2\[369] = \Timer_1:TimerUDB:fifo_full\[370] +Removing Rhs of wire \Timer_1:TimerUDB:status_3\[371] = \Timer_1:TimerUDB:fifo_nempty\[372] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_2\[374] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_1\[375] = \Timer_1:TimerUDB:trig_reg\[363] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_0\[376] = \Timer_1:TimerUDB:per_zero\[354] +Removing Lhs of wire \SPIM:BSPIM:dpcounter_one_reg\\D\[461] = \SPIM:BSPIM:dpcounter_one\[54] +Removing Lhs of wire \SPIM:BSPIM:so_send_reg\\D\[462] = \SPIM:BSPIM:so_send\[34] +Removing Lhs of wire \SPIM:BSPIM:mosi_reg\\D\[469] = \SPIM:BSPIM:mosi_pre_reg\[51] +Removing Lhs of wire \SPIM:BSPIM:mosi_from_dp_reg\\D\[471] = \SPIM:BSPIM:mosi_from_dp\[41] +Removing Lhs of wire \UART_1:BUART:reset_reg\\D\[475] = zero[3] +Removing Lhs of wire \UART_1:BUART:tx_bitclk\\D\[480] = \UART_1:BUART:tx_bitclk_enable_pre\[173] +Removing Lhs of wire Net_256D[481] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:capture_last\\D\[485] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:hwEnable_reg\\D\[486] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:tc_reg_i\\D\[487] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:capture_out_reg_i\\D\[488] = \Timer_1:TimerUDB:capt_fifo_load\[348] ------------------------------------------------------ -Aliased 0 equations, 62 wires. +Aliased 0 equations, 89 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -332,17 +398,26 @@ Note: Expanding virtual equation for '\UART_1:BUART:tx_counter_tc\' (cost = 0): Note: Expanding virtual equation for 'Net_438' (cost = 0): Net_438 <= (not Net_439); -Note: Expanding virtual equation for 'Net_444' (cost = 3): -Net_444 <= ((not Net_439 and not mywire_1_1 and not mywire_1_0)); +Note: Expanding virtual equation for 'Net_590' (cost = 4): +Net_590 <= ((not Net_439 and not mywire_1_2 and not mywire_1_1 and not mywire_1_0)); + +Note: Expanding virtual equation for 'Net_591' (cost = 4): +Net_591 <= ((not Net_439 and not mywire_1_2 and not mywire_1_1 and mywire_1_0)); -Note: Expanding virtual equation for 'Net_441' (cost = 3): -Net_441 <= ((not Net_439 and not mywire_1_1 and mywire_1_0)); +Note: Expanding virtual equation for 'Net_592' (cost = 4): +Net_592 <= ((not Net_439 and not mywire_1_2 and not mywire_1_0 and mywire_1_1)); -Note: Expanding virtual equation for 'Net_449' (cost = 3): -Net_449 <= ((not Net_439 and not mywire_1_0 and mywire_1_1)); +Note: Expanding virtual equation for 'Net_594' (cost = 4): +Net_594 <= ((not Net_439 and not mywire_1_2 and mywire_1_1 and mywire_1_0)); -Note: Expanding virtual equation for 'Net_443' (cost = 3): -Net_443 <= ((not Net_439 and mywire_1_1 and mywire_1_0)); +Note: Expanding virtual equation for 'Net_596' (cost = 4): +Net_596 <= ((not Net_439 and not mywire_1_1 and not mywire_1_0 and mywire_1_2)); + +Note: Expanding virtual equation for '\Timer_1:TimerUDB:fifo_load_polarized\' (cost = 0): +\Timer_1:TimerUDB:fifo_load_polarized\ <= ('0') ; + +Note: Expanding virtual equation for '\Timer_1:TimerUDB:status_tc\' (cost = 3): +\Timer_1:TimerUDB:status_tc\ <= ((\Timer_1:TimerUDB:run_mode\ and \Timer_1:TimerUDB:per_zero\)); Substituting virtuals - pass 2: @@ -351,7 +426,7 @@ Substituting virtuals - pass 2: ---------------------------------------------------------- Circuit simplification results: - Expanded 10 signals. + Expanded 13 signals. Turned 0 signals into soft nodes. Maximum default expansion cost was set at 5. ---------------------------------------------------------- @@ -359,10 +434,13 @@ Circuit simplification results: ------------------------------------------------------ Alias Detection ------------------------------------------------------ -Removing Lhs of wire \UART_1:BUART:tx_ctrl_mark_last\\D\[327] = \UART_1:BUART:tx_ctrl_mark_last\[231] +Aliasing \Timer_1:TimerUDB:capt_fifo_load\ to zero +Removing Lhs of wire \Timer_1:TimerUDB:capt_fifo_load\[348] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:trig_reg\[363] = \Timer_1:TimerUDB:timer_enable\[349] +Removing Lhs of wire \UART_1:BUART:tx_ctrl_mark_last\\D\[482] = \UART_1:BUART:tx_ctrl_mark_last\[231] ------------------------------------------------------ -Aliased 0 equations, 1 wires. +Aliased 0 equations, 3 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -390,21 +468,24 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Warp Arguments : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.794ms +Warp synthesis phase: Elapsed time ==> 2s.217ms -cyp3fit: V2.2.0.293, Family: PSoC3, Started at: Friday, 22 March 2013 10:33:25 -Options: -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 PSOC5_SPI_LSM303D.v -verilog +cyp3fit: V2.2.0.572, Family: PSoC3, Started at: Thursday, 25 July 2013 16:48:55 +Options: -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 PSOC5_SPI_LSM303D.v -verilog -Design parsing phase: Elapsed time ==> 0s.020ms +Design parsing phase: Elapsed time ==> 0s.025ms Converted constant MacroCell: Net_256 from registered to combinatorial + Converted constant MacroCell: \Timer_1:TimerUDB:capture_last\ from registered to combinatorial + Converted constant MacroCell: \Timer_1:TimerUDB:capture_out_reg_i\ from registered to combinatorial Converted constant MacroCell: \UART_1:BUART:reset_reg\ from registered to combinatorial +Assigning clock timer_clock to clock ILO because it is a pass-through Digital Clock 0: Automatic-assigning clock 'SPIM_IntClock'. Fanout=1, Signal=\SPIM:Net_276\ Digital Clock 1: Automatic-assigning clock 'Clock_1'. Fanout=1, Signal=Net_191 @@ -414,6 +495,9 @@ Removing unused cells resulting from optimization Removed unused cell/equation 'Net_256:macrocell' Removed unused cell/equation '\SPIM:BSPIM:mosi_reg\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:so_send_reg\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:capture_last\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:capture_out_reg_i\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:tc_reg_i\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:so_send\:macrocell' Done removing unused cells. @@ -421,6 +505,10 @@ Done removing unused cells. ClockIn: SPIM_IntClock was determined to be a global clock that is synchronous to BUS_CLK EnableIn: Constant 1 was determined to be synchronous to ClockIn ClockOut: SPIM_IntClock, EnableOut: Constant 1 + UDB Clk/Enable \Timer_1:TimerUDB:clock_enable_block\: with output requested to be synchronous + ClockIn: ILO was determined to be a routed clock that is asynchronous + EnableIn: Constant 1 was determined to be synchronous to ClockIn + ClockOut: BUS_CLK, EnableOut: ClockBlock_1k__SYNC:synccell.out UDB Clk/Enable \UART_1:BUART:ClkSync\: with output requested to be synchronous ClockIn: Clock_1 was determined to be a global clock that is synchronous to BUS_CLK EnableIn: Constant 1 was determined to be synchronous to ClockIn @@ -439,6 +527,8 @@ Removing unused cells resulting from optimization Removed unused cell/equation '\SPIM:BSPIM:state_0\\D\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:state_1\\D\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:state_2\\D\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:runmode_enable\\D\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:trig_disable\\D\:macrocell' Removed unused cell/equation '\UART_1:BUART:reset_reg\:macrocell' Removed unused cell/equation '\UART_1:BUART:tx_mark\\D\:macrocell' Removed unused cell/equation '\UART_1:BUART:tx_parity_bit\\D\:macrocell' @@ -653,6 +743,45 @@ Design Equations { } + Pin : Name = Pin_5(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Pin_5(0)__PA , + input => Net_585 , + pad => Pin_5(0)_PAD ); + Properties: + { + } + Pin : Name = Tx_1(0) Attributes: In Group/Port: True @@ -1102,42 +1231,42 @@ Design Equations Output = Net_30 (fanout=1) MacroCell: Name=Net_419, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * !mywire_1_1 * !mywire_1_0 + !Net_439 * !mywire_1_2 * !mywire_1_1 * !mywire_1_0 ); Output = Net_419 (fanout=1) MacroCell: Name=Net_422, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * !mywire_1_1 * mywire_1_0 + !Net_439 * !mywire_1_2 * !mywire_1_1 * mywire_1_0 ); Output = Net_422 (fanout=1) MacroCell: Name=Net_425, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * mywire_1_1 * mywire_1_0 + !Net_439 * !mywire_1_2 * mywire_1_1 * mywire_1_0 ); Output = Net_425 (fanout=1) MacroCell: Name=Net_428, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * mywire_1_1 * !mywire_1_0 + !Net_439 * !mywire_1_2 * mywire_1_1 * !mywire_1_0 ); Output = Net_428 (fanout=1) @@ -1156,7 +1285,7 @@ Design Equations + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * !Net_439 ); - Output = Net_439 (fanout=6) + Output = Net_439 (fanout=7) MacroCell: Name=Net_479, Mode=(D-Register) Total # of inputs : 4 @@ -1174,6 +1303,16 @@ Design Equations ); Output = Net_479 (fanout=2) + MacroCell: Name=Net_585, Mode=(Combinatorial) + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_585 (fanout=1) + MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) Total # of inputs : 10 Total # of product terms : 4 @@ -1435,6 +1574,58 @@ Design Equations ); Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) + MacroCell: Name=\Timer_1:TimerUDB:run_mode\, Mode=(D-Register) + Total # of inputs : 1 + Total # of product terms : 1 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:control_7\ + ); + Output = \Timer_1:TimerUDB:run_mode\ (fanout=3) + + MacroCell: Name=\Timer_1:TimerUDB:status_tc\, Mode=(Combinatorial) + Total # of inputs : 2 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:run_mode\ * \Timer_1:TimerUDB:per_zero\ + ); + Output = \Timer_1:TimerUDB:status_tc\ (fanout=1) + + MacroCell: Name=\Timer_1:TimerUDB:timer_enable\, Mode=(D-Register) + Total # of inputs : 5 + Total # of product terms : 3 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 3 pterms + ( + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:timer_enable\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:run_mode\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:per_zero\ * + !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:timer_enable\ (fanout=4) + + MacroCell: Name=\Timer_1:TimerUDB:trig_disable\, Mode=(T-Register) + Total # of inputs : 4 + Total # of product terms : 1 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:timer_enable\ * \Timer_1:TimerUDB:run_mode\ * + \Timer_1:TimerUDB:per_zero\ * !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:trig_disable\ (fanout=2) + MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) Total # of inputs : 4 Total # of product terms : 2 @@ -1612,6 +1803,79 @@ Design Equations Clock Polarity: Active High Clock Enable: True + datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u0\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + chain_out => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Next in chain : \Timer_1:TimerUDB:sT16:timerdp:u1\ + + datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u1\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + z0_comb => \Timer_1:TimerUDB:per_zero\ , + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\ , + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\ , + chain_in => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Previous in chain : \Timer_1:TimerUDB:sT16:timerdp:u0\ + datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ PORT MAP ( clock => Net_191 , @@ -1721,6 +1985,22 @@ Design Equations Clock Polarity: Active High Clock Enable: True + statusicell: Name =\Timer_1:TimerUDB:nrstSts:stsreg\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + status_3 => \Timer_1:TimerUDB:status_3\ , + status_2 => \Timer_1:TimerUDB:status_2\ , + status_0 => \Timer_1:TimerUDB:status_tc\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "1111111" + cy_md_select = "0000011" + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + statusicell: Name =\UART_1:BUART:sTX:TxSts\ PORT MAP ( clock => Net_191 , @@ -1738,6 +2018,18 @@ Design Equations Clock Enable: True + + ------------------------------------------------------------ + Sync listing + ------------------------------------------------------------ + + synccell: Name =ClockBlock_1k__SYNC + PORT MAP ( + in => ClockBlock_1k , + out => ClockBlock_1k__SYNC_OUT , + clock => ClockBlock_BUS_CLK ); + Clock Polarity: Active High + Clock Enable: True @@ -1752,7 +2044,7 @@ Design Equations control_5 => \SS:control_5\ , control_4 => \SS:control_4\ , control_3 => \SS:control_3\ , - control_2 => \SS:control_2\ , + control_2 => mywire_1_2 , control_1 => mywire_1_1 , control_0 => mywire_1_0 ); Properties: @@ -1764,6 +2056,26 @@ Design Equations cy_init_value = "00000000" } Clock Enable: True + + controlcell: Name =\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ + PORT MAP ( + control_7 => \Timer_1:TimerUDB:control_7\ , + control_6 => \Timer_1:TimerUDB:control_6\ , + control_5 => \Timer_1:TimerUDB:control_5\ , + control_4 => \Timer_1:TimerUDB:control_4\ , + control_3 => \Timer_1:TimerUDB:control_3\ , + control_2 => \Timer_1:TimerUDB:control_2\ , + control_1 => \Timer_1:TimerUDB:control_1\ , + control_0 => \Timer_1:TimerUDB:control_0\ ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True @@ -1809,15 +2121,16 @@ Resource Type : Used : Free : Max : % Used ============================================================ Digital domain clock dividers : 2 : 6 : 8 : 25.00% Analog domain clock dividers : 0 : 4 : 4 : 0.00% -Pins : 18 : 52 : 70 : 25.71% -UDB Macrocells : 32 : 160 : 192 : 16.67% -UDB Unique Pterms : 67 : 317 : 384 : 17.45% -UDB Total Pterms : 74 : : : -UDB Datapath Cells : 3 : 21 : 24 : 12.50% -UDB Status Cells : 3 : 21 : 24 : 12.50% - StatusI Registers : 3 -UDB Control Cells : 2 : 22 : 24 : 8.33% - Control Registers : 1 +Pins : 19 : 51 : 70 : 27.14% +UDB Macrocells : 37 : 155 : 192 : 19.27% +UDB Unique Pterms : 74 : 310 : 384 : 19.27% +UDB Total Pterms : 81 : : : +UDB Datapath Cells : 5 : 19 : 24 : 20.83% +UDB Status Cells : 5 : 19 : 24 : 20.83% + StatusI Registers : 4 + Sync Cells : 1 (in 1 status cell) +UDB Control Cells : 3 : 21 : 24 : 12.50% + Control Registers : 2 Count7 Cells : 1 DMA Channels : 0 : 24 : 24 : 0.00% Interrupts : 0 : 32 : 32 : 0.00% @@ -1838,9 +2151,9 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 2 : 2 : 0.00% -Technology Mapping: Elapsed time ==> 0s.099ms +Technology Mapping: Elapsed time ==> 0s.051ms Info: mpr.M0037: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details. (App=cydsfit) -Tech mapping phase: Elapsed time ==> 0s.210ms +Tech mapping phase: Elapsed time ==> 0s.220ms Initial Analog Placement Results: @@ -1848,6 +2161,7 @@ IO_0@[IOP=(3)][IoId=(0)] : Pin_1(0) (fixed) IO_1@[IOP=(3)][IoId=(1)] : Pin_2(0) (fixed) IO_2@[IOP=(3)][IoId=(2)] : Pin_3(0) (fixed) IO_3@[IOP=(3)][IoId=(3)] : Pin_4(0) (fixed) +IO_4@[IOP=(3)][IoId=(4)] : Pin_5(0) (fixed) IO_7@[IOP=(3)][IoId=(7)] : Tx_1(0) (fixed) IO_0@[IOP=(2)][IoId=(0)] : \LCD:LCDPort(0)\ (fixed) IO_1@[IOP=(2)][IoId=(1)] : \LCD:LCDPort(1)\ (fixed) @@ -1859,10 +2173,10 @@ IO_6@[IOP=(2)][IoId=(6)] : \LCD:LCDPort(6)\ (fixed) IO_0@[IOP=(0)][IoId=(0)] : m_miso_pin(0) (fixed) IO_5@[IOP=(0)][IoId=(5)] : m_mosi_pin(0) (fixed) IO_6@[IOP=(0)][IoId=(6)] : m_sclk_pin(0) (fixed) -Analog Placement phase: Elapsed time ==> 0s.053ms +Analog Placement phase: Elapsed time ==> 0s.052ms -Analog Routing phase: Elapsed time ==> 0s.000ms +Analog Routing phase: Elapsed time ==> 0s.001ms ============ Analog Final Answer Routes ============ @@ -1877,7 +2191,7 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 0s.435ms +Analog Code Generation phase: Elapsed time ==> 0s.614ms @@ -1888,33 +2202,33 @@ PLD Packing Summary ------------------------------------------------------------ Resource Type : Used : Free : Max : % Used ==================================================== - PLDs : 11 : 37 : 48 : 22.92% + PLDs : 13 : 35 : 48 : 27.08% PLD Resource Type : Average/LAB ======================================= - Inputs : 7.82 - Pterms : 6.36 - Macrocells : 2.91 + Inputs : 7.46 + Pterms : 6.00 + Macrocells : 2.85 Packed PLD Contents not displayed at this verbose level. -PLD Packing: Elapsed time ==> 0s.001ms +PLD Packing: Elapsed time ==> 0s.003ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.043ms +Partitioning: Elapsed time ==> 0s.059ms Annealing: Elapsed time ==> 0s.002ms The seed used for moves was 114161200. -Inital cost was 248, final cost is 248 (0.00% improvement). +Inital cost was 261, final cost is 261 (0.00% improvement). @@ -1924,7 +2238,7 @@ Final Placement Summary Resource Type : Count : Avg Inputs : Avg Outputs ======================================================== - UDB : 6 : 10.50 : 5.33 + UDB : 8 : 9.13 : 4.63 @@ -1943,174 +2257,297 @@ UDB [UDB=(1,2)] is empty. UDB [UDB=(1,3)] is empty. UDB [UDB=(1,4)] is empty. UDB [UDB=(1,5)] is empty. -UDB [UDB=(2,0)] is empty. -UDB [UDB=(2,1)] is empty. -UDB [UDB=(2,2)] is empty. -UDB [UDB=(2,3)] contents: -LAB@[UDB=(2,3)][LB=0] #macrocells=3, #inputs=11, #pterms=8 +UDB [UDB=(2,0)] contents: +LAB@[UDB=(2,0)][LB=0] #macrocells=4, #inputs=5, #pterms=6 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(2,3)][LB=0][MC=0] - Total # of inputs : 10 - Total # of product terms : 4 + [McSlotId=0]: MacroCell: Name=\Timer_1:TimerUDB:timer_enable\, Mode=(D-Register) @ [UDB=(2,0)][LB=0][MC=0] + Total # of inputs : 5 + Total # of product terms : 3 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 3 pterms ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:cnt_enable\ - ); - Output = \SPIM:BSPIM:cnt_enable\ (fanout=3) + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:timer_enable\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:run_mode\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:per_zero\ * + !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:timer_enable\ (fanout=4) Properties : { } - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(2,3)][LB=0][MC=1] - Total # of inputs : 10 - Total # of product terms : 4 + [McSlotId=1]: MacroCell: Name=\Timer_1:TimerUDB:trig_disable\, Mode=(T-Register) @ [UDB=(2,0)][LB=0][MC=1] + Total # of inputs : 4 + Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - \SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:timer_enable\ * \Timer_1:TimerUDB:run_mode\ * + \Timer_1:TimerUDB:per_zero\ * !\Timer_1:TimerUDB:trig_disable\ ); - Output = \SPIM:BSPIM:state_1\ (fanout=14) + Output = \Timer_1:TimerUDB:trig_disable\ (fanout=2) Properties : { } - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=2] - Total # of inputs : 3 + [McSlotId=2]: MacroCell: Name=\Timer_1:TimerUDB:status_tc\, Mode=(Combinatorial) @ [UDB=(2,0)][LB=0][MC=2] + Total # of inputs : 2 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ + \Timer_1:TimerUDB:run_mode\ * \Timer_1:TimerUDB:per_zero\ ); - Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) + Output = \Timer_1:TimerUDB:status_tc\ (fanout=1) Properties : { } - [McSlotId=3]: (empty) -} - -LAB@[UDB=(2,3)][LB=1] #macrocells=4, #inputs=10, #pterms=8 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(2,3)][LB=1][MC=0] - Total # of inputs : 9 - Total # of product terms : 4 + [McSlotId=3]: MacroCell: Name=\Timer_1:TimerUDB:run_mode\, Mode=(D-Register) @ [UDB=(2,0)][LB=0][MC=3] + Total # of inputs : 1 + Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ + \Timer_1:TimerUDB:control_7\ ); - Output = \SPIM:BSPIM:load_cond\ (fanout=1) + Output = \Timer_1:TimerUDB:run_mode\ (fanout=3) Properties : { } +} - [McSlotId=1]: MacroCell: Name=Net_479, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=1] - Total # of inputs : 4 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - !( - !Net_479 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = Net_479 (fanout=2) +datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u0\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + chain_out => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Next in chain : \Timer_1:TimerUDB:sT16:timerdp:u1\ + +statusicell: Name =\Timer_1:TimerUDB:nrstSts:stsreg\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + status_3 => \Timer_1:TimerUDB:status_3\ , + status_2 => \Timer_1:TimerUDB:status_2\ , + status_0 => \Timer_1:TimerUDB:status_tc\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "1111111" + cy_md_select = "0000011" + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + +controlcell: Name =\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ + PORT MAP ( + control_7 => \Timer_1:TimerUDB:control_7\ , + control_6 => \Timer_1:TimerUDB:control_6\ , + control_5 => \Timer_1:TimerUDB:control_5\ , + control_4 => \Timer_1:TimerUDB:control_4\ , + control_3 => \Timer_1:TimerUDB:control_3\ , + control_2 => \Timer_1:TimerUDB:control_2\ , + control_1 => \Timer_1:TimerUDB:control_1\ , + control_0 => \Timer_1:TimerUDB:control_0\ ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True + +UDB [UDB=(2,1)] is empty. +UDB [UDB=(2,2)] is empty. +UDB [UDB=(2,3)] contents: +LAB@[UDB=(2,3)][LB=0] #macrocells=3, #inputs=11, #pterms=6 +{ + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=0] + Total # of inputs : 6 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ + ); + Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) Properties : { } - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=2] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_0\, Mode=(T-Register) @ [UDB=(2,3)][LB=0][MC=1] + Total # of inputs : 5 + Total # of product terms : 4 + List of special equations: + Clock = (Net_191) => Global + Clock Enable: True + Main Equation : 4 pterms + ( + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + !\UART_1:BUART:tx_fifo_empty\ * !\UART_1:BUART:tx_state_2\ + + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + !\UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ + ); + Output = \UART_1:BUART:tx_state_0\ (fanout=7) + Properties : + { + } + + [McSlotId=2]: (empty) + [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_0\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=3] Total # of inputs : 5 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ + ); + Output = \UART_1:BUART:tx_status_0\ (fanout=1) + Properties : + { + } +} + +LAB@[UDB=(2,3)][LB=1] #macrocells=3, #inputs=2, #pterms=2 +{ + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_bitclk\, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=0] + Total # of inputs : 1 Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global + Clock = (Net_191) => Global Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ + !\UART_1:BUART:tx_bitclk_dp\ ); - Output = \SPIM:BSPIM:load_rx_data\ (fanout=1) + Output = \UART_1:BUART:tx_bitclk\ (fanout=6) Properties : { } - [McSlotId=3]: MacroCell: Name=\SPIM:BSPIM:dpcounter_one\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=3] - Total # of inputs : 5 + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_bitclk_enable_pre\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=1] + Total # of inputs : 1 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ + !\UART_1:BUART:tx_bitclk_dp\ ); - Output = \SPIM:BSPIM:dpcounter_one\ (fanout=1) + Output = \UART_1:BUART:tx_bitclk_enable_pre\ (fanout=1) + Properties : + { + } + + [McSlotId=2]: (empty) + [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_2\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=3] + Total # of inputs : 1 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:tx_fifo_notfull\ + ); + Output = \UART_1:BUART:tx_status_2\ (fanout=1) Properties : { } } -statusicell: Name =\SPIM:BSPIM:TxStsReg\ +datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ PORT MAP ( - clock => \SPIM:Net_276\ , - status_4 => \SPIM:BSPIM:tx_status_4\ , - status_3 => \SPIM:BSPIM:dpcounter_one\ , - status_2 => \SPIM:BSPIM:tx_status_2\ , - status_1 => \SPIM:BSPIM:tx_status_1\ , - status_0 => \SPIM:BSPIM:tx_status_0\ ); + clock => Net_191 , + cs_addr_2 => \UART_1:BUART:tx_state_1\ , + cs_addr_1 => \UART_1:BUART:tx_state_0\ , + cs_addr_0 => \UART_1:BUART:tx_bitclk_enable_pre\ , + so_comb => \UART_1:BUART:tx_shift_out\ , + f0_bus_stat_comb => \UART_1:BUART:tx_fifo_notfull\ , + f0_blk_stat_comb => \UART_1:BUART:tx_fifo_empty\ ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000000000000000000000000000000000000000000000000000011000000000000000000000000000010010000000000000000000000000000000000000011111111000000001111111111111111000000000000000001000100111100000000000000001100" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: True + +statusicell: Name =\UART_1:BUART:sTX:TxSts\ + PORT MAP ( + clock => Net_191 , + status_3 => \UART_1:BUART:tx_fifo_notfull\ , + status_2 => \UART_1:BUART:tx_status_2\ , + status_1 => \UART_1:BUART:tx_fifo_empty\ , + status_0 => \UART_1:BUART:tx_status_0\ ); Properties: { cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "0001001" + cy_int_mask = "1111111" + cy_md_select = "0000001" } Clock Polarity: Active High Clock Enable: True @@ -2298,190 +2735,106 @@ count7cell: Name =\SPIM:BSPIM:BitCounter\ Clock Enable: True UDB [UDB=(2,5)] contents: -LAB@[UDB=(2,5)][LB=0] #macrocells=4, #inputs=12, #pterms=8 +LAB@[UDB=(2,5)][LB=0] #macrocells=3, #inputs=11, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=0] - Total # of inputs : 6 - Total # of product terms : 1 + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=0] + Total # of inputs : 10 + Total # of product terms : 4 + List of special equations: + Clock = (\SPIM:Net_276\) => Global Clock Enable: True - Main Equation : 1 pterm + Main Equation : 4 pterms ( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ * + \SPIM:BSPIM:cnt_enable\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * + \SPIM:BSPIM:cnt_enable\ ); - Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) + Output = \SPIM:BSPIM:cnt_enable\ (fanout=3) Properties : { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_0\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=1] - Total # of inputs : 5 + [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(2,5)][LB=0][MC=1] + Total # of inputs : 10 Total # of product terms : 4 List of special equations: - Clock = (Net_191) => Global + Clock = (\SPIM:Net_276\) => Global Clock Enable: True Main Equation : 4 pterms - ( - !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - !\UART_1:BUART:tx_fifo_empty\ * !\UART_1:BUART:tx_state_2\ - + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - !\UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_state_0\ (fanout=7) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\UART_1:BUART:tx_state_1\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=2] - Total # of inputs : 5 - Total # of product terms : 3 - List of special equations: - Clock = (Net_191) => Global - Clock Enable: True - Main Equation : 3 pterms - ( - \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ * !\UART_1:BUART:tx_counter_dp\ - + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_state_1\ (fanout=7) - Properties : - { - } - - [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_0\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=3] - Total # of inputs : 5 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_status_0\ (fanout=1) - Properties : - { - } -} - -LAB@[UDB=(2,5)][LB=1] #macrocells=2, #inputs=1, #pterms=1 -{ - [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_bitclk\, Mode=(D-Register) @ [UDB=(2,5)][LB=1][MC=0] - Total # of inputs : 1 - Total # of product terms : 1 - List of special equations: - Clock = (Net_191) => Global - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:tx_bitclk_dp\ + !( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ + + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + \SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ ); - Output = \UART_1:BUART:tx_bitclk\ (fanout=6) + Output = \SPIM:BSPIM:state_1\ (fanout=14) Properties : { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_bitclk_enable_pre\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=1][MC=1] - Total # of inputs : 1 + [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=2] + Total # of inputs : 3 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\UART_1:BUART:tx_bitclk_dp\ + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ ); - Output = \UART_1:BUART:tx_bitclk_enable_pre\ (fanout=1) + Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) Properties : { } - [McSlotId=2]: (empty) [McSlotId=3]: (empty) } -datapathcell: Name =\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ - PORT MAP ( - clock => Net_191 , - cs_addr_0 => \UART_1:BUART:counter_load_not\ , - cl0_comb => \UART_1:BUART:tx_bitclk_dp\ , - cl1_comb => \UART_1:BUART:tx_counter_dp\ ); - Properties: - { - a0_init = "00000000" - a1_init = "00000000" - ce0_sync = 1 - ce1_sync = 1 - cl0_sync = 1 - cl1_sync = 1 - cmsb_sync = 1 - co_msb_sync = 1 - cy_dpconfig = "1010100001000000001000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000001111111100000111001000000100000000000101111100000000000000001000" - d0_init = "00000000" - d1_init = "00000000" - f0_blk_sync = 1 - f0_bus_sync = 1 - f1_blk_sync = 1 - f1_bus_sync = 1 - ff0_sync = 1 - ff1_sync = 1 - ov_msb_sync = 1 - so_sync = 1 - z0_sync = 1 - z1_sync = 1 - } - Clock Polarity: Active High - Clock Enable: True - -statusicell: Name =\SPIM:BSPIM:RxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_6 => \SPIM:BSPIM:rx_status_6\ , - status_5 => \SPIM:BSPIM:rx_status_5\ , - status_4 => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "1000000" - } - Clock Polarity: Active High - Clock Enable: True - -UDB [UDB=(3,0)] is empty. -UDB [UDB=(3,1)] is empty. -UDB [UDB=(3,2)] is empty. -UDB [UDB=(3,3)] contents: -LAB@[UDB=(3,3)][LB=0] #macrocells=4, #inputs=8, #pterms=7 +LAB@[UDB=(2,5)][LB=1] #macrocells=4, #inputs=10, #pterms=7 { - [McSlotId=0]: MacroCell: Name=Net_439, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=0] - Total # of inputs : 4 - Total # of product terms : 3 + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(2,5)][LB=1][MC=0] + Total # of inputs : 9 + Total # of product terms : 4 List of special equations: Clock = (\SPIM:Net_276\) => Global Clock Enable: True - Main Equation : 3 pterms + Main Equation : 4 pterms ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !Net_439 - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * Net_439 - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !Net_439 + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ ); - Output = Net_439 (fanout=6) + Output = \SPIM:BSPIM:load_cond\ (fanout=1) Properties : { } - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:ld_ident\, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=1] + [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:ld_ident\, Mode=(T-Register) @ [UDB=(2,5)][LB=1][MC=1] Total # of inputs : 4 Total # of product terms : 2 List of special equations: @@ -2499,164 +2852,139 @@ LAB@[UDB=(3,3)][LB=0] #macrocells=4, #inputs=8, #pterms=7 { } - [McSlotId=2]: MacroCell: Name=Net_30, Mode=(Combinatorial) @ [UDB=(3,3)][LB=0][MC=2] - Total # of inputs : 2 + [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(D-Register) @ [UDB=(2,5)][LB=1][MC=2] + Total # of inputs : 5 Total # of product terms : 1 + List of special equations: + Clock = (\SPIM:Net_276\) => Global Clock Enable: True Main Equation : 1 pterm ( - !Net_439 * \SPIM:BSPIM:mosi_hs_reg\ - ); - Output = Net_30 (fanout=1) - Properties : - { - } - - [McSlotId=3]: MacroCell: Name=Net_419, Mode=(Combinatorial) @ [UDB=(3,3)][LB=0][MC=3] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * !mywire_1_1 * !mywire_1_0 - ); - Output = Net_419 (fanout=1) - Properties : - { - } -} - -LAB@[UDB=(3,3)][LB=1] #macrocells=3, #inputs=3, #pterms=3 -{ - [McSlotId=0]: MacroCell: Name=Net_422, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=0] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * !mywire_1_1 * mywire_1_0 - ); - Output = Net_422 (fanout=1) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_425, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=1] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * mywire_1_1 * mywire_1_0 + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ ); - Output = Net_425 (fanout=1) + Output = \SPIM:BSPIM:load_rx_data\ (fanout=1) Properties : { } - [McSlotId=2]: MacroCell: Name=Net_428, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=2] - Total # of inputs : 3 + [McSlotId=3]: MacroCell: Name=\SPIM:BSPIM:dpcounter_one\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=1][MC=3] + Total # of inputs : 5 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm - !( - !Net_439 * mywire_1_1 * !mywire_1_0 + ( + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ ); - Output = Net_428 (fanout=1) + Output = \SPIM:BSPIM:dpcounter_one\ (fanout=1) Properties : { } - - [McSlotId=3]: (empty) } -controlcell: Name =\SS:Async:ctrl_reg\ +statusicell: Name =\SPIM:BSPIM:TxStsReg\ PORT MAP ( - control_7 => \SS:control_7\ , - control_6 => \SS:control_6\ , - control_5 => \SS:control_5\ , - control_4 => \SS:control_4\ , - control_3 => \SS:control_3\ , - control_2 => \SS:control_2\ , - control_1 => mywire_1_1 , - control_0 => mywire_1_0 ); + clock => \SPIM:Net_276\ , + status_4 => \SPIM:BSPIM:tx_status_4\ , + status_3 => \SPIM:BSPIM:dpcounter_one\ , + status_2 => \SPIM:BSPIM:tx_status_2\ , + status_1 => \SPIM:BSPIM:tx_status_1\ , + status_0 => \SPIM:BSPIM:tx_status_0\ ); Properties: { - cy_ctrl_mode_0 = "00000000" - cy_ctrl_mode_1 = "00000000" - cy_ext_reset = 0 cy_force_order = 1 - cy_init_value = "00000000" + cy_int_mask = "0000000" + cy_md_select = "0001001" } + Clock Polarity: Active High Clock Enable: True -UDB [UDB=(3,4)] contents: -LAB@[UDB=(3,4)][LB=0] #macrocells=3, #inputs=3, #pterms=3 +UDB [UDB=(3,0)] contents: +LAB@[UDB=(3,0)][LB=1] #macrocells=1, #inputs=5, #pterms=3 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_from_dp_reg\, Mode=(D-Register) @ [UDB=(3,4)][LB=0][MC=0] - Total # of inputs : 1 - Total # of product terms : 1 + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_state_1\, Mode=(T-Register) @ [UDB=(3,0)][LB=1][MC=0] + Total # of inputs : 5 + Total # of product terms : 3 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 1 pterm - ( - \SPIM:BSPIM:mosi_from_dp\ - ); - Output = \SPIM:BSPIM:mosi_from_dp_reg\ (fanout=1) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_234, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=1] - Total # of inputs : 1 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:txn\ - ); - Output = Net_234 (fanout=1) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\UART_1:BUART:tx_status_2\, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=2] - Total # of inputs : 1 - Total # of product terms : 1 + Clock = (Net_191) => Global Clock Enable: True - Main Equation : 1 pterm + Main Equation : 3 pterms ( - !\UART_1:BUART:tx_fifo_notfull\ + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ * !\UART_1:BUART:tx_counter_dp\ + + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ ); - Output = \UART_1:BUART:tx_status_2\ (fanout=1) + Output = \UART_1:BUART:tx_state_1\ (fanout=7) Properties : { } + [McSlotId=1]: (empty) + [McSlotId=2]: (empty) [McSlotId=3]: (empty) } -statusicell: Name =\UART_1:BUART:sTX:TxSts\ +datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u1\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + z0_comb => \Timer_1:TimerUDB:per_zero\ , + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\ , + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\ , + chain_in => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Previous in chain : \Timer_1:TimerUDB:sT16:timerdp:u0\ + +synccell: Name =ClockBlock_1k__SYNC PORT MAP ( - clock => Net_191 , - status_3 => \UART_1:BUART:tx_fifo_notfull\ , - status_2 => \UART_1:BUART:tx_status_2\ , - status_1 => \UART_1:BUART:tx_fifo_empty\ , - status_0 => \UART_1:BUART:tx_status_0\ ); + in => ClockBlock_1k , + out => ClockBlock_1k__SYNC_OUT , + clock => ClockBlock_BUS_CLK ); Properties: { - cy_force_order = 1 - cy_int_mask = "1111111" - cy_md_select = "0000001" } Clock Polarity: Active High Clock Enable: True -UDB [UDB=(3,5)] contents: -LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 +UDB [UDB=(3,1)] is empty. +UDB [UDB=(3,2)] is empty. +UDB [UDB=(3,3)] contents: +LAB@[UDB=(3,3)][LB=0] #macrocells=2, #inputs=7, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\UART_1:BUART:txn\, Mode=(D-Register) @ [UDB=(3,5)][LB=0][MC=0] + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:txn\, Mode=(D-Register) @ [UDB=(3,3)][LB=0][MC=0] Total # of inputs : 7 Total # of product terms : 5 List of special equations: @@ -2680,7 +3008,7 @@ LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_2\, Mode=(T-Register) @ [UDB=(3,5)][LB=0][MC=1] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_2\, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=1] Total # of inputs : 5 Total # of product terms : 3 List of special equations: @@ -2704,9 +3032,9 @@ LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 [McSlotId=3]: (empty) } -LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 +LAB@[UDB=(3,3)][LB=1] #macrocells=2, #inputs=10, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_hs_reg\, Mode=(D-Register) @ [UDB=(3,5)][LB=1][MC=0] + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_hs_reg\, Mode=(D-Register) @ [UDB=(3,3)][LB=1][MC=0] Total # of inputs : 6 Total # of product terms : 6 List of special equations: @@ -2732,7 +3060,7 @@ LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=1] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=1] Total # of inputs : 4 Total # of product terms : 2 Clock Enable: True @@ -2752,15 +3080,12 @@ LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 [McSlotId=3]: (empty) } -datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ +datapathcell: Name =\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ PORT MAP ( clock => Net_191 , - cs_addr_2 => \UART_1:BUART:tx_state_1\ , - cs_addr_1 => \UART_1:BUART:tx_state_0\ , - cs_addr_0 => \UART_1:BUART:tx_bitclk_enable_pre\ , - so_comb => \UART_1:BUART:tx_shift_out\ , - f0_bus_stat_comb => \UART_1:BUART:tx_fifo_notfull\ , - f0_blk_stat_comb => \UART_1:BUART:tx_fifo_empty\ ); + cs_addr_0 => \UART_1:BUART:counter_load_not\ , + cl0_comb => \UART_1:BUART:tx_bitclk_dp\ , + cl1_comb => \UART_1:BUART:tx_counter_dp\ ); Properties: { a0_init = "00000000" @@ -2771,7 +3096,7 @@ datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ cl1_sync = 1 cmsb_sync = 1 co_msb_sync = 1 - cy_dpconfig = "0000000000000000000000000000000000000000000000000000000011000000000000000000000000000010010000000000000000000000000000000000000011111111000000001111111111111111000000000000000001000100111100000000000000001100" + cy_dpconfig = "1010100001000000001000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000001111111100000111001000000100000000000101111100000000000000001000" d0_init = "00000000" d1_init = "00000000" f0_blk_sync = 1 @@ -2788,6 +3113,200 @@ datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ Clock Polarity: Active High Clock Enable: True +UDB [UDB=(3,4)] contents: +LAB@[UDB=(3,4)][LB=0] #macrocells=2, #inputs=2, #pterms=2 +{ + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_from_dp_reg\, Mode=(D-Register) @ [UDB=(3,4)][LB=0][MC=0] + Total # of inputs : 1 + Total # of product terms : 1 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 1 pterm + ( + \SPIM:BSPIM:mosi_from_dp\ + ); + Output = \SPIM:BSPIM:mosi_from_dp_reg\ (fanout=1) + Properties : + { + } + + [McSlotId=1]: (empty) + [McSlotId=2]: MacroCell: Name=Net_234, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=2] + Total # of inputs : 1 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:txn\ + ); + Output = Net_234 (fanout=1) + Properties : + { + } + + [McSlotId=3]: (empty) +} + +statusicell: Name =\SPIM:BSPIM:RxStsReg\ + PORT MAP ( + clock => \SPIM:Net_276\ , + status_6 => \SPIM:BSPIM:rx_status_6\ , + status_5 => \SPIM:BSPIM:rx_status_5\ , + status_4 => \SPIM:BSPIM:rx_status_4\ ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "0000000" + cy_md_select = "1000000" + } + Clock Polarity: Active High + Clock Enable: True + +UDB [UDB=(3,5)] contents: +LAB@[UDB=(3,5)][LB=0] #macrocells=4, #inputs=9, #pterms=8 +{ + [McSlotId=0]: MacroCell: Name=Net_479, Mode=(D-Register) @ [UDB=(3,5)][LB=0][MC=0] + Total # of inputs : 4 + Total # of product terms : 3 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 3 pterms + !( + !Net_479 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ + + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ + ); + Output = Net_479 (fanout=2) + Properties : + { + } + + [McSlotId=1]: MacroCell: Name=Net_439, Mode=(T-Register) @ [UDB=(3,5)][LB=0][MC=1] + Total # of inputs : 4 + Total # of product terms : 3 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 3 pterms + ( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * !Net_439 + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * Net_439 + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * !Net_439 + ); + Output = Net_439 (fanout=7) + Properties : + { + } + + [McSlotId=2]: MacroCell: Name=Net_30, Mode=(Combinatorial) @ [UDB=(3,5)][LB=0][MC=2] + Total # of inputs : 2 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !Net_439 * \SPIM:BSPIM:mosi_hs_reg\ + ); + Output = Net_30 (fanout=1) + Properties : + { + } + + [McSlotId=3]: MacroCell: Name=Net_419, Mode=(Combinatorial) @ [UDB=(3,5)][LB=0][MC=3] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_419 (fanout=1) + Properties : + { + } +} + +LAB@[UDB=(3,5)][LB=1] #macrocells=4, #inputs=4, #pterms=4 +{ + [McSlotId=0]: MacroCell: Name=Net_422, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=0] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * !mywire_1_1 * mywire_1_0 + ); + Output = Net_422 (fanout=1) + Properties : + { + } + + [McSlotId=1]: MacroCell: Name=Net_425, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=1] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * mywire_1_1 * mywire_1_0 + ); + Output = Net_425 (fanout=1) + Properties : + { + } + + [McSlotId=2]: MacroCell: Name=Net_428, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=2] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * mywire_1_1 * !mywire_1_0 + ); + Output = Net_428 (fanout=1) + Properties : + { + } + + [McSlotId=3]: MacroCell: Name=Net_585, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=3] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_585 (fanout=1) + Properties : + { + } +} + +controlcell: Name =\SS:Async:ctrl_reg\ + PORT MAP ( + control_7 => \SS:control_7\ , + control_6 => \SS:control_6\ , + control_5 => \SS:control_5\ , + control_4 => \SS:control_4\ , + control_3 => \SS:control_3\ , + control_2 => mywire_1_2 , + control_1 => mywire_1_1 , + control_0 => mywire_1_0 ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True + Intr hod @ [IntrHod=(0)]: empty Drq hod @ [DrqHod=(0)]: empty Port 0 contains the following IO cells: @@ -3347,6 +3866,46 @@ Pin : Name = Pin_4(0) { } +[IoId=4]: +Pin : Name = Pin_5(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Pin_5(0)__PA , + input => Net_585 , + pad => Pin_5(0)_PAD ); + Properties: + { + } + [IoId=7]: Pin : Name = Tx_1(0) Attributes: @@ -3462,37 +4021,38 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connectio | 1 | * | NONE | RES_PULL_UP | Pin_2(0) | In(Net_422) | 2 | * | NONE | RES_PULL_UP | Pin_3(0) | In(Net_428) | 3 | * | NONE | RES_PULL_UP | Pin_4(0) | In(Net_425) + | 4 | * | NONE | RES_PULL_UP | Pin_5(0) | In(Net_585) | 7 | * | NONE | CMOS_OUT | Tx_1(0) | In(Net_234) ---------------------------------------------------------------------------------- -Digital component placer commit/Report: Elapsed time ==> 0s.003ms -Digital Placement phase: Elapsed time ==> 1s.395ms +Digital component placer commit/Report: Elapsed time ==> 0s.005ms +Digital Placement phase: Elapsed time ==> 1s.451ms Routing successful. -Digital Routing phase: Elapsed time ==> 2s.255ms +Digital Routing phase: Elapsed time ==> 3s.163ms -Bitstream and API generation phase: Elapsed time ==> 0s.215ms +Bitstream and API generation phase: Elapsed time ==> 0s.247ms -Bitstream verification phase: Elapsed time ==> 0s.073ms +Bitstream verification phase: Elapsed time ==> 0s.088ms Timing report is in PSOC5_SPI_LSM303D_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.512ms +Static timing analysis phase: Elapsed time ==> 0s.652ms -Data reporting phase: Elapsed time ==> 0s.001ms +Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.220ms +Design database save phase: Elapsed time ==> 0s.331ms -cydsfit: Elapsed time ==> 5s.413ms +cydsfit: Elapsed time ==> 6s.878ms -Fitter phase: Elapsed time ==> 5s.453ms -API generation phase: Elapsed time ==> 0s.801ms -Dependency generation phase: Elapsed time ==> 0s.004ms -Cleanup phase: Elapsed time ==> 0s.001ms +Fitter phase: Elapsed time ==> 6s.922ms +API generation phase: Elapsed time ==> 1s.277ms +Dependency generation phase: Elapsed time ==> 0s.015ms +Cleanup phase: Elapsed time ==> 0s.002ms diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.svd b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.svd index 478d670..57e21c2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.svd +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.svd @@ -7,33 +7,252 @@ 32 - SS + Timer_1 No description available - 0x40006475 + 0x40006504 0 - 0x1 + 0x91 registers - SS_CONTROL_REG - No description available + Timer_1_COUNTER + UDB.A0 - Current Down Counter Value 0x0 + 16 + read-write + 0 + 0 + + + Timer_1_PERIOD + UDB.D0 - Assigned Period + 0x20 + 16 + read-write + 0 + 0 + + + Timer_1_Control_Reg + UDB Control Register - Assigned Control Register Value + 0x70 8 read-write 0 0 + + + CTRL_ENABLE + Enable the Timer + 7 + 7 + read-write + + + CTRL_CMODE + Capture Mode + 5 + 6 + read-write + + + CTRL_TEN + Trigger Enable Bit + 4 + 4 + read-write + + + CTRL_TMODE + Trigger Mode + 2 + 3 + read-write + + + CTRL_IC + Interrupt Count + 0 + 1 + read-write + + + + + Timer_1_STATUS_MASK + UDB Status bits Interrupt Mask Enable Register + 0x80 + 8 + read-write + 0 + 0 + + + TIMER_STS_TC + Enables the Interrupt on TC + 0 + 0 + read-only + + + TIMER_STS_CAPT + Enables the Interrupt on Capture + 1 + 1 + read-only + + + TIMER_STS_FIFO_FULL + FIFO Full Status + 2 + 2 + read-only + + + TIMER_STS_FIFO_NEMPTY + FIFO Empty status + 3 + 3 + read-only + + + + + Timer_1_STATUS_AUX_CTRL + UDB Auxilliary Control Register + 0x90 + 8 + read-write + 0 + 0 + + + FIFO0_CLR + FIFO0 clear + 0 + 0 + read-write + + + E_FIFO_CLR_0 + Normal FIFO operation + 0 + + + E_FIFO_CLR_1 + Clear FIFO state + 1 + + + + + FIFO1_CLR + FIFO1 clear + 1 + 1 + read-write + + + E_FIFO_CLR_0 + Normal FIFO operation + 0 + + + E_FIFO_CLR_1 + Clear FIFO state + 1 + + + + + FIFO0_LVL + FIFO level + 2 + 2 + read-write + + + E_FIFO_LVL_0 + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + E_FIFO_LVL_1 + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + + + FIFO1_LVL + FIFO level + 3 + 3 + read-write + + + E_FIFO_LVL_0 + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + E_FIFO_LVL_1 + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + + + INT_EN + No description available + 4 + 4 + read-write + + + E_INT_EN0 + Interrupt disabled + 0 + + + E_INT_EN1 + Interrupt enabled + 1 + + + + + CNT_START + FIFO0 clear + 5 + 5 + read-write + + + E_CNT_START0 + Disable counter + 0 + + + E_CNT_START1 + Enable counter + 1 + + + + UART_1 UART - 0x40006441 + 0x40006444 0 - 0x22 + 0x21 registers @@ -49,7 +268,7 @@ TX_UART_1_TX_STATUS TX status register - 0x21 + 0x20 8 read-write 0 @@ -87,5 +306,26 @@ + + SS + No description available + 0x40006471 + + 0 + 0x1 + registers + + + + SS_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj index 31dd60d..332ff6e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj @@ -662,6 +662,36 @@ 5 .\Generated_Source\PSoC5\SPIM_IntClock.h + + Pin_5_aliases.h + 5 + .\Generated_Source\PSoC5\Pin_5_aliases.h + + + Pin_5.c + 1 + .\Generated_Source\PSoC5\Pin_5.c + + + Pin_5.h + 5 + .\Generated_Source\PSoC5\Pin_5.h + + + Timer_1.c + 1 + .\Generated_Source\PSoC5\Timer_1.c + + + Timer_1.h + 5 + .\Generated_Source\PSoC5\Timer_1.h + + + Timer_1_PM.c + 1 + .\Generated_Source\PSoC5\Timer_1_PM.c + @@ -1326,6 +1356,36 @@ 5 .\Generated_Source\PSoC5\SPIM_IntClock.h + + Pin_5_aliases.h + 5 + .\Generated_Source\PSoC5\Pin_5_aliases.h + + + Pin_5.c + 1 + .\Generated_Source\PSoC5\Pin_5.c + + + Pin_5.h + 5 + .\Generated_Source\PSoC5\Pin_5.h + + + Timer_1.c + 1 + .\Generated_Source\PSoC5\Timer_1.c + + + Timer_1.h + 5 + .\Generated_Source\PSoC5\Timer_1.h + + + Timer_1_PM.c + 1 + .\Generated_Source\PSoC5\Timer_1_PM.c + diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_timing.html b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_timing.html index 6ba435b..9f1c194 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_timing.html +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_timing.html @@ -539,7 +539,7 @@

Static Timing Analysis

Project : PSOC5_SPI_LSM303D Build Time : - 03/22/13 10:33:30 + 07/25/13 16:49:01 Device : CY8C5568AXI-060 Temperature : @@ -623,7 +623,7 @@

Static Timing Analysis

CyMASTER_CLK 2.000 MHz 2.000 MHz - 61.376 MHz + 52.394 MHz @@ -631,7 +631,7 @@

Static Timing Analysis

CyMASTER_CLK 923.077 kHz 923.077 kHz - 43.850 MHz + 42.472 MHz @@ -639,8 +639,8 @@

Static Timing Analysis

CyMASTER_CLK 24.000 MHz 24.000 MHz - N/A - + 43.373 MHz + CyPLL_OUT @@ -692,11 +692,11 @@

Static Timing Analysis

- \UART_1:BUART:tx_state_0\/q + \UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 43.850 MHz - 22.805 - 1060.528 + 42.472 MHz + 23.545 + 1059.788 @@ -715,29 +715,29 @@

Static Timing Analysis

- macrocell27 - U(2,5) + macrocell33 + U(3,0) 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/clock_0 - \UART_1:BUART:tx_state_0\/q + \UART_1:BUART:tx_state_1\ + \UART_1:BUART:tx_state_1\/clock_0 + \UART_1:BUART:tx_state_1\/q 1.250 Route 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/q - \UART_1:BUART:counter_load_not\/main_1 - 4.383 + \UART_1:BUART:tx_state_1\ + \UART_1:BUART:tx_state_1\/q + \UART_1:BUART:counter_load_not\/main_0 + 5.133 - macrocell24 - U(3,5) + macrocell29 + U(3,3) 1 \UART_1:BUART:counter_load_not\ - \UART_1:BUART:counter_load_not\/main_1 + \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350 @@ -748,11 +748,11 @@

Static Timing Analysis

\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 2.302 + 2.292 - datapathcell3 - U(2,5) + datapathcell5 + U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ @@ -773,11 +773,11 @@

Static Timing Analysis

- \UART_1:BUART:tx_state_1\/q + \UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 45.027 MHz - 22.209 - 1061.124 + 44.039 MHz + 22.707 + 1060.626 @@ -796,29 +796,29 @@

Static Timing Analysis

- macrocell28 - U(2,5) + macrocell32 + U(2,3) 1 - \UART_1:BUART:tx_state_1\ - \UART_1:BUART:tx_state_1\/clock_0 - \UART_1:BUART:tx_state_1\/q + \UART_1:BUART:tx_state_0\ + \UART_1:BUART:tx_state_0\/clock_0 + \UART_1:BUART:tx_state_0\/q 1.250 Route 1 - \UART_1:BUART:tx_state_1\ - \UART_1:BUART:tx_state_1\/q - \UART_1:BUART:counter_load_not\/main_0 - 3.787 + \UART_1:BUART:tx_state_0\ + \UART_1:BUART:tx_state_0\/q + \UART_1:BUART:counter_load_not\/main_1 + 4.295 - macrocell24 - U(3,5) + macrocell29 + U(3,3) 1 \UART_1:BUART:counter_load_not\ - \UART_1:BUART:counter_load_not\/main_0 + \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350 @@ -829,11 +829,11 @@

Static Timing Analysis

\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 2.302 + 2.292 - datapathcell3 - U(2,5) + datapathcell5 + U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ @@ -856,9 +856,9 @@

Static Timing Analysis

\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 46.471 MHz - 21.519 - 1061.814 + 46.484 MHz + 21.513 + 1061.820 @@ -877,8 +877,8 @@

Static Timing Analysis

- macrocell25 - U(2,5) + macrocell30 + U(2,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 @@ -892,11 +892,11 @@

Static Timing Analysis

\UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 - 3.097 + 3.101 - macrocell24 - U(3,5) + macrocell29 + U(3,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 @@ -910,11 +910,11 @@

Static Timing Analysis

\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 2.302 + 2.292 - datapathcell3 - U(2,5) + datapathcell5 + U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ @@ -937,9 +937,9 @@

Static Timing Analysis

\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 46.544 MHz - 21.485 - 1061.848 + 46.572 MHz + 21.472 + 1061.861 @@ -958,8 +958,8 @@

Static Timing Analysis

- macrocell29 - U(3,5) + macrocell34 + U(3,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 @@ -973,11 +973,11 @@

Static Timing Analysis

\UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 - 3.063 + 3.060 - macrocell24 - U(3,5) + macrocell29 + U(3,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 @@ -991,11 +991,11 @@

Static Timing Analysis

\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 - 2.302 + 2.292 - datapathcell3 - U(2,5) + datapathcell5 + U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ @@ -1018,9 +1018,9 @@

Static Timing Analysis

\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 - 50.176 MHz - 19.930 - 1063.403 + 50.181 MHz + 19.928 + 1063.405 @@ -1039,8 +1039,8 @@

Static Timing Analysis

- datapathcell3 - U(2,5) + datapathcell5 + U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock @@ -1054,11 +1054,11 @@

Static Timing Analysis

\UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 - 2.290 + 2.301 - macrocell26 - U(2,5) + macrocell31 + U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 @@ -1072,11 +1072,11 @@

Static Timing Analysis

\UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 - 2.320 + 2.307 - datapathcell2 - U(3,5) + datapathcell4 + U(2,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ @@ -1099,9 +1099,9 @@

Static Timing Analysis

\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 - 61.241 MHz - 16.329 - 1067.004 + 61.908 MHz + 16.153 + 1067.180 @@ -1120,8 +1120,8 @@

Static Timing Analysis

- datapathcell2 - U(3,5) + datapathcell4 + U(2,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock @@ -1135,11 +1135,11 @@

Static Timing Analysis

\UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 - 3.227 + 3.639 - macrocell30 - U(2,5) + macrocell35 + U(2,3) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 @@ -1153,11 +1153,11 @@

Static Timing Analysis

\UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 - 2.902 + 2.314 - statusicell3 - U(3,4) + statusicell4 + U(2,3) 1 \UART_1:BUART:sTX:TxSts\ @@ -1178,11 +1178,11 @@

Static Timing Analysis

- \UART_1:BUART:sTX:TxShifter:u0\/so_comb - \UART_1:BUART:txn\/main_3 - 76.348 MHz - 13.098 - 1070.235 + \UART_1:BUART:tx_state_1\/q + \UART_1:BUART:sTX:TxSts\/status_0 + 73.578 MHz + 13.591 + 1069.742 @@ -1201,31 +1201,49 @@

Static Timing Analysis

- datapathcell2 - U(3,5) + macrocell33 + U(3,0) 1 - \UART_1:BUART:sTX:TxShifter:u0\ - \UART_1:BUART:sTX:TxShifter:u0\/clock - \UART_1:BUART:sTX:TxShifter:u0\/so_comb - 7.280 + \UART_1:BUART:tx_state_1\ + \UART_1:BUART:tx_state_1\/clock_0 + \UART_1:BUART:tx_state_1\/q + 1.250 Route 1 - \UART_1:BUART:tx_shift_out\ - \UART_1:BUART:sTX:TxShifter:u0\/so_comb - \UART_1:BUART:txn\/main_3 - 2.308 + \UART_1:BUART:tx_state_1\ + \UART_1:BUART:tx_state_1\/q + \UART_1:BUART:tx_status_0\/main_0 + 5.107 - macrocell32 - U(3,5) + macrocell35 + U(2,3) 1 - \UART_1:BUART:txn\ + \UART_1:BUART:tx_status_0\ + \UART_1:BUART:tx_status_0\/main_0 + \UART_1:BUART:tx_status_0\/q + 3.350 + + + Route + + 1 + \UART_1:BUART:tx_status_0\ + \UART_1:BUART:tx_status_0\/q + \UART_1:BUART:sTX:TxSts\/status_0 + 2.314 + + + statusicell4 + U(2,3) + 1 + \UART_1:BUART:sTX:TxSts\ SETUP - 3.510 + 1.570 Clock @@ -1241,11 +1259,11 @@

Static Timing Analysis

- \UART_1:BUART:tx_state_0\/q - \UART_1:BUART:sTX:TxSts\/status_0 - 77.640 MHz - 12.880 - 1070.453 + \UART_1:BUART:sTX:TxShifter:u0\/so_comb + \UART_1:BUART:txn\/main_3 + 76.318 MHz + 13.103 + 1070.230 @@ -1264,49 +1282,31 @@

Static Timing Analysis

- macrocell27 - U(2,5) - 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/clock_0 - \UART_1:BUART:tx_state_0\/q - 1.250 - - - Route - - 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/q - \UART_1:BUART:tx_status_0\/main_1 - 3.808 - - - macrocell30 - U(2,5) + datapathcell4 + U(2,3) 1 - \UART_1:BUART:tx_status_0\ - \UART_1:BUART:tx_status_0\/main_1 - \UART_1:BUART:tx_status_0\/q - 3.350 + \UART_1:BUART:sTX:TxShifter:u0\ + \UART_1:BUART:sTX:TxShifter:u0\/clock + \UART_1:BUART:sTX:TxShifter:u0\/so_comb + 7.280 Route 1 - \UART_1:BUART:tx_status_0\ - \UART_1:BUART:tx_status_0\/q - \UART_1:BUART:sTX:TxSts\/status_0 - 2.902 + \UART_1:BUART:tx_shift_out\ + \UART_1:BUART:sTX:TxShifter:u0\/so_comb + \UART_1:BUART:txn\/main_3 + 2.313 - statusicell3 - U(3,4) + macrocell37 + U(3,3) 1 - \UART_1:BUART:sTX:TxSts\ + \UART_1:BUART:txn\ SETUP - 1.570 + 3.510 Clock @@ -1323,10 +1323,10 @@

Static Timing Analysis

\UART_1:BUART:tx_state_1\/q - \UART_1:BUART:sTX:TxSts\/status_0 - 77.845 MHz - 12.846 - 1070.487 + \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 + 78.858 MHz + 12.681 + 1070.652 @@ -1345,8 +1345,8 @@

Static Timing Analysis

- macrocell28 - U(2,5) + macrocell33 + U(3,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 @@ -1359,35 +1359,17 @@

Static Timing Analysis

1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q - \UART_1:BUART:tx_status_0\/main_0 - 3.774 - - - macrocell30 - U(2,5) - 1 - \UART_1:BUART:tx_status_0\ - \UART_1:BUART:tx_status_0\/main_0 - \UART_1:BUART:tx_status_0\/q - 3.350 - - - Route - - 1 - \UART_1:BUART:tx_status_0\ - \UART_1:BUART:tx_status_0\/q - \UART_1:BUART:sTX:TxSts\/status_0 - 2.902 + \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 + 5.141 - statusicell3 - U(3,4) + datapathcell4 + U(2,3) 1 - \UART_1:BUART:sTX:TxSts\ + \UART_1:BUART:sTX:TxShifter:u0\ SETUP - 1.570 + 6.290 Clock @@ -1403,11 +1385,11 @@

Static Timing Analysis

- \UART_1:BUART:tx_state_0\/q - \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 - 79.327 MHz - 12.606 - 1070.727 + \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb + \UART_1:BUART:tx_state_0\/main_2 + 80.457 MHz + 12.429 + 1070.904 @@ -1426,31 +1408,31 @@

Static Timing Analysis

- macrocell27 - U(2,5) + datapathcell4 + U(2,3) 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/clock_0 - \UART_1:BUART:tx_state_0\/q - 1.250 + \UART_1:BUART:sTX:TxShifter:u0\ + \UART_1:BUART:sTX:TxShifter:u0\/clock + \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb + 5.280 Route 1 - \UART_1:BUART:tx_state_0\ - \UART_1:BUART:tx_state_0\/q - \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 - 5.066 + \UART_1:BUART:tx_fifo_empty\ + \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb + \UART_1:BUART:tx_state_0\/main_2 + 3.639 - datapathcell2 - U(3,5) + macrocell32 + U(2,3) 1 - \UART_1:BUART:sTX:TxShifter:u0\ + \UART_1:BUART:tx_state_0\ SETUP - 6.290 + 3.510 Clock @@ -1475,15 +1457,15 @@

Static Timing Analysis

Path Delay Requirement : 500ns(2 MHz)
+
Path Delay Requirement : 41.6667ns(24 MHz)
@@ -1497,11 +1479,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1520,49 +1502,67 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - + + - + + + + + + + + + + + + + + + + + + + - + @@ -1578,11 +1578,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1601,31 +1601,49 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + + + + + + + + + + + + + + + + + + + - + @@ -1641,11 +1659,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1664,31 +1682,49 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + + + + + + + + + + + + + + + + + + + - + @@ -1704,11 +1740,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1727,31 +1763,49 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + + + + + + + + + + + + + + + + + + + - + @@ -1767,11 +1821,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1790,49 +1844,49 @@

Static Timing Analysis

- - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - + + - + - + @@ -1848,11 +1902,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1871,49 +1925,31 @@

Static Timing Analysis

- - - - - - - - - - - - - - - - - - - - + + - - - - + + + + - - - - + + + + - - + + - + - + @@ -1929,11 +1965,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -1952,49 +1988,31 @@

Static Timing Analysis

- - - - - - - - - - - - - - - - - - - - + + - - - - + + + + - - + + - - - - + + + + - - + + - + - + @@ -2010,11 +2028,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -2033,49 +2051,31 @@

Static Timing Analysis

- - - - - - - - - - - - - - - - - - - - + + - - - - + + + + - - - - + + + + - - + + - + - + @@ -2091,11 +2091,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -2114,31 +2114,31 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + - + @@ -2154,11 +2154,11 @@

Static Timing Analysis

- - - - - + + + + + @@ -2177,46 +2177,64 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - - - + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - + + - + @@ -2240,25 +2258,1450 @@

Static Timing Analysis

- -
-
Path Delay Requirement : 500ns(2 MHz)
+
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:RxStsReg\/status_661.376 MHz16.293483.707\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/ci43.373 MHz23.05618.611
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb5.280\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:rx_status_4\\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:rx_status_6\/main_53.785\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell18U(2,5)datapathcell3U(3,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_5\SPIM:BSPIM:rx_status_6\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
statusicell1U(2,5)datapathcell2U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.5705.090
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_364.416 MHz15.524484.476\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci46.241 MHz21.62620.041
datapathcell1U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_33.714\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
macrocell16U(3,5)datapathcell2U(2,0) 1\SPIM:BSPIM:mosi_hs_reg\\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.5105.090
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_pre_reg\/main_368.306 MHz14.640485.360\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_050.566 MHz19.77621.891
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_pre_reg\/main_32.830\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell17U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:mosi_pre_reg\\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
datapathcell2U(2,0)1\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP3.51011.520
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_from_dp_reg\/main_068.353 MHz14.630485.370\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_050.571 MHz19.77421.893
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_from_dp_reg\/main_02.820\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell15U(3,4)datapathcell3U(3,0) 1\SPIM:BSPIM:mosi_from_dp_reg\\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_02.974
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.51011.520
Clock
\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:TxStsReg\/status_073.676 MHz13.573486.427\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/ci52.576 MHz19.02022.647
macrocell21U(2,4)macrocell27U(2,0) 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/clock_0\SPIM:BSPIM:state_2\/q\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q 1.250
Route 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:tx_status_0\/main_04.486\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_12.970
macrocell22U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_0\SPIM:BSPIM:tx_status_0\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.917\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
statusicell2U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.5705.090
Clock
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:TxStsReg\/status_374.772 MHz13.374486.626\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_054.508 MHz18.34623.321
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:dpcounter_one\/main_34.028
macrocell10U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_3\SPIM:BSPIM:dpcounter_one\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_32.316\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
statusicell2U(2,3)datapathcell2U(2,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP1.57011.520
Clock
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:TxStsReg\/status_075.313 MHz13.278486.722\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_054.514 MHz18.34423.323
macrocell20U(2,3)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:tx_status_0\/main_14.191
macrocell22U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_1\SPIM:BSPIM:tx_status_0\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route datapathcell3U(3,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.917\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_02.974
statusicell2U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.57011.520
Clock
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:RxStsReg\/status_675.919 MHz13.172486.828\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_163.532 MHz15.74025.927
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:rx_status_6\/main_33.834
macrocell18U(2,5)macrocell27U(2,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_3\SPIM:BSPIM:rx_status_6\/q3.350\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q1.250
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_12.970
statusicell1U(2,5)datapathcell2U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP1.57011.520
Clock
\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_875.976 MHz13.162486.838\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_163.971 MHz15.63226.035
datapathcell1U(2,4)macrocell27U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb5.280\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q1.250
Route 1\SPIM:BSPIM:tx_status_1\\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_84.372\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_12.862
macrocell20U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:state_1\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.51011.520
Clock
\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:RxStsReg\/status_676.023 MHz13.154486.846\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:nrstSts:stsreg\/status_065.240 MHz15.32826.339
count7cellU(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_32.110\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:count_3\\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:rx_status_6\/main_13.816\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell18U(2,5)datapathcell3U(3,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_1\SPIM:BSPIM:rx_status_6\/q\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:status_tc\/main_12.866
macrocell26U(2,0)1\Timer_1:TimerUDB:status_tc\\Timer_1:TimerUDB:status_tc\/main_1\Timer_1:TimerUDB:status_tc\/q 3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:status_tc\\Timer_1:TimerUDB:status_tc\/q\Timer_1:TimerUDB:nrstSts:stsreg\/status_02.262
statusicell1U(2,5)statusicell3U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:nrstSts:stsreg\ SETUP 1.570
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceDestinationFMaxDelay (ns)Slack (ns)Violation
\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:TxStsReg\/status_352.394 MHz19.086480.914
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_22.110
Route 1\SPIM:BSPIM:count_2\\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:dpcounter_one\/main_26.478
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_2\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:TxStsReg\/status_056.770 MHz17.615482.385
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell21U(2,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:tx_status_0\/main_18.508
macrocell23U(2,4)1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_1\SPIM:BSPIM:tx_status_0\/q3.350
Route 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.937
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_157.166 MHz17.493482.507
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell21U(2,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_19.073
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\SETUP7.170
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:TxStsReg\/status_358.493 MHz17.096482.904
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_02.110
Route 1\SPIM:BSPIM:count_0\\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:dpcounter_one\/main_44.488
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_4\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:TxStsReg\/status_358.772 MHz17.015482.985
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_32.110
Route 1\SPIM:BSPIM:count_3\\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:dpcounter_one\/main_14.407
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_1\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:TxStsReg\/status_359.841 MHz16.711483.289
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_42.110
Route 1\SPIM:BSPIM:count_4\\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:dpcounter_one\/main_04.103
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_0\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:TxStsReg\/status_360.245 MHz16.599483.401
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:dpcounter_one\/main_33.991
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_3\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:RxStsReg\/status_661.072 MHz16.374483.626
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb5.280
Route 1\SPIM:BSPIM:rx_status_4\\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:rx_status_6\/main_53.241
macrocell19U(2,3)1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_5\SPIM:BSPIM:rx_status_6\/q3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.933
statusicell1U(3,4)1\SPIM:BSPIM:RxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:mosi_hs_reg\/main_063.147 MHz15.836484.164
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell22U(2,4)1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/clock_0\SPIM:BSPIM:state_2\/q1.250
Route 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:mosi_hs_reg\/main_011.076
macrocell17U(3,3)1\SPIM:BSPIM:mosi_hs_reg\SETUP3.510
Clock Skew0.000
+
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_363.605 MHz15.722484.278
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_33.912
macrocell17U(3,3)1\SPIM:BSPIM:mosi_hs_reg\SETUP3.510
Clock Skew0.000
+
+
+
+
+ + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceDestinationSlack (ns)Violation
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_1\/main_03.482
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q1.250
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_1\/main_02.232
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_03.544
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell37U(3,3)1\UART_1:BUART:txn\\UART_1:BUART:txn\/clock_0\UART_1:BUART:txn\/q1.250
macrocell37U(3,3)1\UART_1:BUART:txn\\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_02.294
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_24.205
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_22.955
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_44.205
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
Route1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_42.955
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_34.218
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_32.968
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_54.218
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_52.968
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_34.312
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
Route1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_33.062
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_44.354
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_43.104
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_2\/main_14.847
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250
Route1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_2\/main_13.597
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:txn\/main_24.847
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250
Route1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:txn\/main_23.597
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
+
+
+
+
+
+
+
@@ -2271,9 +3714,9 @@

Static Timing Analysis

- - - + + + @@ -2292,28 +3735,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - + + - - - - + + + + - - + + - + @@ -2332,9 +3775,9 @@

Static Timing Analysis

- - - + + + @@ -2353,28 +3796,28 @@

Static Timing Analysis

- - + + - - - + + + - - - - + + + + - - + + - + @@ -2393,9 +3836,9 @@

Static Timing Analysis

- - - + + + @@ -2415,27 +3858,27 @@

Static Timing Analysis

- + - - - + + + - - - - + + + + - - + + - + @@ -2454,9 +3897,9 @@

Static Timing Analysis

- - - + + + @@ -2475,28 +3918,28 @@

Static Timing Analysis

- - + + - - - + + + - - - - + + + + - - + + - + @@ -2515,9 +3958,9 @@

Static Timing Analysis

- - - + + + @@ -2536,28 +3979,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -2576,9 +4019,9 @@

Static Timing Analysis

- - - + + + @@ -2597,28 +4040,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2637,9 +4080,9 @@

Static Timing Analysis

- - - + + + @@ -2658,28 +4101,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2698,9 +4141,9 @@

Static Timing Analysis

- - - + + + @@ -2719,28 +4162,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2759,9 +4202,9 @@

Static Timing Analysis

- - - + + + @@ -2780,28 +4223,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - + + - - - - + + + + - - + + - + @@ -2820,9 +4263,9 @@

Static Timing Analysis

- - - + + + @@ -2841,28 +4284,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2909,8 +4352,8 @@

Static Timing Analysis

- - + + @@ -2930,28 +4373,89 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - + + + - - + + - + + + + + + + + + + + + + + + +
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_24.183\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci3.210
macrocell29U(3,5)datapathcell2U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb3.210
macrocell29U(3,5)Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_22.933\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
macrocell29U(3,5)datapathcell3U(3,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_44.183\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:timer_enable\/main_23.487
macrocell29U(3,5)macrocell25U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/clock_0\Timer_1:TimerUDB:run_mode\/q 1.250
Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_42.933\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:timer_enable\/main_22.237
macrocell32U(3,5)macrocell27U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_34.218\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:trig_disable\/main_13.487
macrocell25U(2,5)U(2,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/clock_0\Timer_1:TimerUDB:run_mode\/q 1.250
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_32.968\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:trig_disable\/main_12.237
macrocell29U(3,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:trig_disable\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_54.218\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:timer_enable\/main_43.490
macrocell25U(2,5)macrocell28U(2,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/clock_0\Timer_1:TimerUDB:trig_disable\/q 1.250
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_52.968\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:timer_enable\/main_42.240
macrocell32U(3,5)macrocell27U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_34.315\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:trig_disable\/main_33.490
macrocell29U(3,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/clock_0\Timer_1:TimerUDB:trig_disable\/q 1.250
Routemacrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_33.065\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:trig_disable\/main_32.240
macrocell27U(2,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_0\\Timer_1:TimerUDB:trig_disable\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_1\/main_24.315ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en3.677
macrocell29U(3,5)synccellU(3,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_1\/main_23.065ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en2.677
macrocell28U(2,5)datapathcell3U(3,0) 1\UART_1:BUART:tx_state_1\\Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_44.346ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:nrstSts:stsreg\/clk_en3.700
macrocell25U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_43.096ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:nrstSts:stsreg\/clk_en2.700
macrocell27U(2,5)statusicell3U(2,0) 1\UART_1:BUART:tx_state_0\\Timer_1:TimerUDB:nrstSts:stsreg\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_1\/main_34.346ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:run_mode\/clk_en3.700
macrocell25U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_1\/main_33.096ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:run_mode\/clk_en2.700
macrocell28U(2,5)macrocell25U(2,0) 1\UART_1:BUART:tx_state_1\\Timer_1:TimerUDB:run_mode\ HOLD 0.000
\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_04.426ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en3.700
macrocell32U(3,5)synccellU(3,0) 1\UART_1:BUART:txn\\UART_1:BUART:txn\/clock_0\UART_1:BUART:txn\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
macrocell32U(3,5)Route 1\UART_1:BUART:txn\\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_03.176ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en2.700
macrocell32U(3,5)datapathcell2U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_2\/main_05.011ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:timer_enable\/clk_en3.700
macrocell28U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_2\/main_03.761ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:timer_enable\/clk_en2.700
macrocell29U(3,5)macrocell27U(2,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_9\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_9 3.539
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/clock_0\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/clock_0\SPIM:BSPIM:mosi_pre_reg\/q 1.250
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_9\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_9 2.289
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:mosi_pre_reg\ HOLD0.000
Clock Skew0.000
+ + + + \SPIM:BSPIM:load_cond\/q + \SPIM:BSPIM:load_cond\/main_8 + 3.547 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2972,7 +4476,7 @@

Static Timing Analysis

- + @@ -2991,7 +4495,7 @@

Static Timing Analysis

- + @@ -3000,16 +4504,16 @@

Static Timing Analysis

- + - + - + @@ -3033,7 +4537,7 @@

Static Timing Analysis

- + @@ -3052,7 +4556,7 @@

Static Timing Analysis

- + @@ -3067,10 +4571,10 @@

Static Timing Analysis

- + - + @@ -3092,9 +4596,9 @@

Static Timing Analysis

- - - + + + @@ -3113,28 +4617,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3175,7 +4679,7 @@

Static Timing Analysis

- + @@ -3184,7 +4688,7 @@

Static Timing Analysis

- + @@ -3193,7 +4697,7 @@

Static Timing Analysis

- + @@ -3214,9 +4718,9 @@

Static Timing Analysis

- - - + + + @@ -3235,28 +4739,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3277,7 +4781,7 @@

Static Timing Analysis

- + @@ -3296,8 +4800,8 @@

Static Timing Analysis

- - + + @@ -3311,7 +4815,7 @@

Static Timing Analysis

- + @@ -3338,7 +4842,7 @@

Static Timing Analysis

- + @@ -3357,7 +4861,7 @@

Static Timing Analysis

- + @@ -3372,11 +4876,11 @@

Static Timing Analysis

- + - - + + @@ -3397,70 +4901,9 @@

Static Timing Analysis

- - - - - - - - - - - - + + + @@ -3479,28 +4922,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3552,7 +4995,7 @@

Static Timing Analysis

- + - + @@ -3594,7 +5037,7 @@

Static Timing Analysis

- + @@ -3648,7 +5091,7 @@

Static Timing Analysis

- + - - + + @@ -3681,7 +5124,7 @@

Static Timing Analysis

- + @@ -3699,10 +5142,10 @@

Static Timing Analysis

- + - + @@ -3752,9 +5195,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/clock_0\SPIM:BSPIM:load_cond\/q1.250
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/q\SPIM:BSPIM:load_cond\/main_82.297
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\ HOLD 0.000
\SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:is_spi_done\/main_93.5603.554
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ 1.250
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:is_spi_done\/main_92.3102.304
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\
\SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:state_2\/main_93.5603.554
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:state_2\/main_92.3102.304
macrocell21macrocell22 U(2,4) 1 \SPIM:BSPIM:state_2\
\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_93.571\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_33.559
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/clock_0\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/clock_0\SPIM:BSPIM:ld_ident\/q 1.250
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_92.321\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_32.309
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:ld_ident\ HOLD 0.000
macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/q
macrocell7U(3,3)U(3,5) 1 Net_439
\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_33.876\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_93.888
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/clock_0\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/clock_0\SPIM:BSPIM:cnt_enable\/q 1.250
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_32.626\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_92.638
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:cnt_enable\ HOLD 0.000
\SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load4.1634.146
macrocell14U(2,3)macrocell15U(2,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/clock_0 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load2.9132.896
datapathcell1
\SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_54.1734.160
macrocell15macrocell16 U(3,4) 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_52.9232.910
macrocell16U(3,5)macrocell17U(3,3) 1 \SPIM:BSPIM:mosi_hs_reg\
\SPIM:BSPIM:state_1\/qNet_479/main_24.198
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell20U(2,3)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/qNet_479/main_22.948
macrocell8U(2,3)1Net_479 HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:load_cond\/main_14.198\SPIM:BSPIM:mosi_hs_reg\/q\SPIM:BSPIM:mosi_hs_reg\/main_44.445
macrocell20U(2,3)macrocell17U(3,3) 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:mosi_hs_reg\\SPIM:BSPIM:mosi_hs_reg\/clock_0\SPIM:BSPIM:mosi_hs_reg\/q 1.250
Routemacrocell17U(3,3) 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:load_cond\/main_12.948\SPIM:BSPIM:mosi_hs_reg\\SPIM:BSPIM:mosi_hs_reg\/q\SPIM:BSPIM:mosi_hs_reg\/main_43.195
macrocell13U(2,3)macrocell17U(3,3) 1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
m_miso_pin(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si41.67741.678
@@ -3579,7 +5022,7 @@

Static Timing Analysis

0.000
iocell13iocell14 P0[0] 1 m_miso_pin(0) Net_20 m_miso_pin(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si7.1877.188
datapathcell1
\UART_1:BUART:txn\/q Tx_1(0)_PAD33.32431.436
@@ -3666,8 +5109,8 @@

Static Timing Analysis

macrocell32U(3,5)macrocell37U(3,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_234/main_04.5213.195
macrocell1 Net_234 Net_234/q Tx_1(0)/pin_input6.3595.797
iocell5iocell6 P3[7] 1 Tx_1(0)
\SS:Async:ctrl_reg\/control_1Pin_2(0)_PAD33.212\SS:Async:ctrl_reg\/control_2Pin_3(0)_PAD32.395
@@ -3773,56 +5216,143 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_422/main_12.791mywire_1_2\SS:Async:ctrl_reg\/control_2Net_428/main_12.792
macrocell4U(3,3)macrocell6U(3,5) 1Net_422Net_422/main_1Net_422/qNet_428Net_428/main_1Net_428/q 3.350
Route 1Net_422Net_422/qPin_2(0)/pin_input7.423Net_428Net_428/qPin_3(0)/pin_input6.361
iocell3P3[2]1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312
Route1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PAD0.000
Clock Clock path delay0.000
+ + + + \SS:Async:ctrl_reg\/control_0 + Pin_1(0)_PAD + 32.006 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - - - + + + + - - - + + + @@ -3839,9 +5369,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -3926,9 +5456,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -4013,9 +5543,9 @@

Static Timing Analysis

- + - + - + - + - - + + - + - + @@ -4066,7 +5596,7 @@

Static Timing Analysis

- + @@ -4121,7 +5651,7 @@

Static Timing Analysis

- + - - + + @@ -4154,11 +5684,11 @@

Static Timing Analysis

- + - + @@ -4172,10 +5702,10 @@

Static Timing Analysis

- + - + @@ -4207,8 +5737,8 @@

Static Timing Analysis

- - + + - + @@ -4240,43 +5770,43 @@

Static Timing Analysis

- + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -4295,7 +5825,7 @@

Static Timing Analysis

- + - + @@ -4332,7 +5862,7 @@

Static Timing Analysis

- + @@ -4346,7 +5876,7 @@

Static Timing Analysis

- + @@ -4381,8 +5911,8 @@

Static Timing Analysis

- - + + - + @@ -4414,43 +5944,130 @@

Static Timing Analysis

- + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
controlcell1U(3,5)1\SS:Async:ctrl_reg\\SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_02.580
Route1mywire_1_0\SS:Async:ctrl_reg\/control_0Net_419/main_32.809
macrocell3U(3,5)1Net_419Net_419/main_3Net_419/q3.350
Route1Net_419Net_419/qPin_1(0)/pin_input6.356
iocell2P3[1]iocell1P3[0] 1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068Pin_1(0)Pin_1(0)/pin_inputPin_1(0)/pad_out16.911
Route 1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PADPin_1(0)_PADPin_1(0)/pad_outPin_1(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1Pin_1(0)_PAD33.047\SS:Async:ctrl_reg\/control_2Pin_5(0)_PAD31.882
@@ -3860,56 +5390,56 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_419/main_12.795mywire_1_2\SS:Async:ctrl_reg\/control_2Net_585/main_12.792
macrocell3U(3,3)macrocell9U(3,5) 1Net_419Net_419/main_1Net_419/qNet_585Net_585/main_1Net_585/q 3.350
Route 1Net_419Net_419/qPin_1(0)/pin_input7.411Net_585Net_585/qPin_5(0)/pin_input6.321
iocell1P3[0]iocell5P3[4] 1Pin_1(0)Pin_1(0)/pin_inputPin_1(0)/pad_out16.911Pin_5(0)Pin_5(0)/pin_inputPin_5(0)/pad_out16.839
Route 1Pin_1(0)_PADPin_1(0)/pad_outPin_1(0)_PADPin_5(0)_PADPin_5(0)/pad_outPin_5(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1Pin_3(0)_PAD32.781\SS:Async:ctrl_reg\/control_2Pin_2(0)_PAD31.296
@@ -3947,56 +5477,56 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_428/main_12.791mywire_1_2\SS:Async:ctrl_reg\/control_2Net_422/main_12.792
macrocell6U(3,3)macrocell4U(3,5) 1Net_428Net_428/main_1Net_428/qNet_422Net_422/main_1Net_422/q 3.350
Route 1Net_428Net_428/qPin_3(0)/pin_input6.748Net_422Net_422/qPin_2(0)/pin_input5.506
iocell3P3[2]iocell2P3[1] 1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068
Route 1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PADPin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 Pin_4(0)_PAD31.44031.158
@@ -4034,25 +5564,25 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1mywire_1_2\SS:Async:ctrl_reg\/control_2 Net_425/main_12.7912.792
macrocell5U(3,3)U(3,5) 1 Net_425 Net_425/main_1 Net_425 Net_425/q Pin_4(0)/pin_input6.6136.330
iocell4
\SPIM:BSPIM:mosi_hs_reg\/q m_mosi_pin(0)_PAD36.07435.028
@@ -4139,8 +5669,8 @@

Static Timing Analysis

macrocell16U(3,5)macrocell17U(3,3) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/clock_0 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/q Net_30/main_15.2575.244
macrocell2U(3,3)U(3,5) 1 Net_30 Net_30/main_1 Net_30 Net_30/q m_mosi_pin(0)/pin_input8.2467.213
iocell14iocell15 P0[5] 1 m_mosi_pin(0)
Net_439/qPin_2(0)_PAD31.687Pin_3(0)_PAD30.869
@@ -4227,7 +5757,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0 1 Net_439 Net_439/qNet_422/main_0Net_428/main_0 2.596
macrocell4U(3,3)macrocell6U(3,5) 1Net_422Net_422/main_0Net_422/qNet_428Net_428/main_0Net_428/q 3.350
Route 1Net_422Net_422/qPin_2(0)/pin_input7.423Net_428Net_428/qPin_3(0)/pin_input6.361
iocell2P3[1]iocell3P3[2] 1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312
Route 1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PADPin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PAD 0.000
Net_439/q Pin_1(0)_PAD31.51230.457
@@ -4314,7 +5844,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell3U(3,3)U(3,5) 1 Net_419 Net_419/main_0 Net_419 Net_419/q Pin_1(0)/pin_input7.4116.356
iocell1
Net_439/qPin_3(0)_PAD31.256Pin_5(0)_PAD30.356
@@ -4401,7 +5931,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0 1 Net_439 Net_439/qNet_428/main_0Net_585/main_0 2.596
macrocell6U(3,3)macrocell9U(3,5) 1Net_428Net_428/main_0Net_428/qNet_585Net_585/main_0Net_585/q 3.350
Route 1Net_428Net_428/qPin_3(0)/pin_input6.748Net_585Net_585/qPin_5(0)/pin_input6.321
iocell3P3[2]iocell5P3[4] 1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312Pin_5(0)Pin_5(0)/pin_inputPin_5(0)/pad_out16.839
Route 1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PADPin_5(0)_PADPin_5(0)/pad_outPin_5(0)_PAD0.000
Clock Clock path delay0.000
+ + + + Net_439/q + Pin_2(0)_PAD + 29.770 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4469,7 +6086,7 @@

Static Timing Analysis

- + - + @@ -4506,7 +6123,7 @@

Static Timing Analysis

- + @@ -4520,7 +6137,7 @@

Static Timing Analysis

- + @@ -4556,7 +6173,7 @@

Static Timing Analysis

- + - + @@ -4589,10 +6206,10 @@

Static Timing Analysis

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All rights reserved. -;* You may use this file only in accordance with the license, terms, conditions, -;* disclaimers, and limitations in the end user license agreement accompanying +;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying ;* the software package with which this file was provided. ;********************************************************************************/ @@ -50,6 +50,11 @@ LOAD_ROM 0 (262144 - 0) * (.ramvectors) } + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + DATA +0 { * (+RW, +ZI) diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Cm3Start.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Cm3Start.c index db78216..f7d4c9e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Cm3Start.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Cm3Start.c @@ -1,12 +1,12 @@ /******************************************************************************* * File Name: Cm3Start.c -* Version 3.30 +* Version 3.40 * * Description: * Startup code for the ARM CM3. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,9 +19,9 @@ #include "CyDmac.h" #include "cyfitter.h" - #define NUM_INTERRUPTS 32u #define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS) +#define NUM_ROM_VECTORS 4u #define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR) #define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL) #define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */ @@ -37,10 +37,20 @@ CY_ISR(IntDefaultHandler); void Reset(void); CY_ISR(IntDefaultHandler); +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER __cs3_stack +#endif /* (__ARMCC_VERSION) */ + +/* Global variables */ +CY_NOINIT static uint32 cySysNoInitDataValid; + /******************************************************************************* * Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. *******************************************************************************/ + __attribute__ ((section(".ramvectors"))) #if defined(__ARMCC_VERSION) __align(256) @@ -53,6 +63,7 @@ cyisraddress CyRamVectors[NUM_VECTORS]; /******************************************************************************* * Function Name: IntDefaultHandler ******************************************************************************** +* * Summary: * This function is called for all interrupts, other than reset, that get * called before the system is setup. @@ -79,6 +90,7 @@ CY_ISR(IntDefaultHandler) } } + #if defined(__ARMCC_VERSION) /* Local function for the device reset. */ @@ -93,69 +105,11 @@ extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; /* RealView C Library initialization. */ extern int __main(void); -/******************************************************************************* -* -* Default Rom Interrupt Vector table. -* -*******************************************************************************/ -#pragma diag_suppress 1296 -__attribute__ ((section(".romvectors"))) -const cyisraddress RomVectors[NUM_VECTORS] = -{ - (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit, /* The initial stack pointer 0 */ - (cyisraddress)Reset, /* The reset handler 1 */ - IntDefaultHandler, /* The NMI handler 2 */ - IntDefaultHandler, /* The hard fault handler 3 */ - IntDefaultHandler, /* The MPU fault handler 4 */ - IntDefaultHandler, /* The bus fault handler 5 */ - IntDefaultHandler, /* The usage fault handler 6 */ - IntDefaultHandler, /* Reserved 7 */ - IntDefaultHandler, /* Reserved 8 */ - IntDefaultHandler, /* Reserved 9 */ - IntDefaultHandler, /* Reserved 10 */ - IntDefaultHandler, /* SVCall handler 11 */ - IntDefaultHandler, /* Debug monitor handler 12 */ - IntDefaultHandler, /* Reserved 13 */ - IntDefaultHandler, /* The PendSV handler 14 */ - IntDefaultHandler, /* The SysTick handler 15 */ - IntDefaultHandler, /* External Interrupt(0) 16 */ - IntDefaultHandler, /* External Interrupt(1) 17 */ - IntDefaultHandler, /* External Interrupt(2) 18 */ - IntDefaultHandler, /* External Interrupt(3) 19 */ - IntDefaultHandler, /* External Interrupt(4) 20 */ - IntDefaultHandler, /* External Interrupt(5) 21 */ - IntDefaultHandler, /* External Interrupt(6) 22 */ - IntDefaultHandler, /* External Interrupt(7) 23 */ - IntDefaultHandler, /* External Interrupt(8) 24 */ - IntDefaultHandler, /* External Interrupt(9) 25 */ - IntDefaultHandler, /* External Interrupt(A) 26 */ - IntDefaultHandler, /* External Interrupt(B) 27 */ - IntDefaultHandler, /* External Interrupt(C) 28 */ - IntDefaultHandler, /* External Interrupt(D) 29 */ - IntDefaultHandler, /* External Interrupt(E) 30 */ - IntDefaultHandler, /* External Interrupt(F) 31 */ - IntDefaultHandler, /* External Interrupt(10) 32 */ - IntDefaultHandler, /* External Interrupt(11) 33 */ - IntDefaultHandler, /* External Interrupt(12) 34 */ - IntDefaultHandler, /* External Interrupt(13) 35 */ - IntDefaultHandler, /* External Interrupt(14) 36 */ - IntDefaultHandler, /* External Interrupt(15) 37 */ - IntDefaultHandler, /* External Interrupt(16) 38 */ - IntDefaultHandler, /* External Interrupt(17) 39 */ - IntDefaultHandler, /* External Interrupt(18) 40 */ - IntDefaultHandler, /* External Interrupt(19) 41 */ - IntDefaultHandler, /* External Interrupt(1A) 42 */ - IntDefaultHandler, /* External Interrupt(1B) 43 */ - IntDefaultHandler, /* External Interrupt(1C) 44 */ - IntDefaultHandler, /* External Interrupt(1D) 45 */ - IntDefaultHandler, /* External Interrupt(1E) 46 */ - IntDefaultHandler /* External Interrupt(1F) 47 */ -}; - /******************************************************************************* * Function Name: Reset ******************************************************************************** +* * Summary: * This function handles the reset interrupt for the RVDS/MDK toolchains. * This is the first bit of code that is executed at startup. @@ -180,14 +134,14 @@ __asm void Reset(void) #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) #if(CYDEV_DEBUGGING_ENABLE) - ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */ + ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */ ldrb r4, [r3, #0] orr r4, r4, #01 strb r4, [r3, #0] debugEnabled #endif /* (CYDEV_DEBUGGING_ENABLE) */ - ldr r3, =0x400046f8 /* CYREG_RESET_SR0 */ + ldr r3, =0x400046fa /* CYREG_RESET_SR0 */ ldrb r2, [r3, #0] #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ @@ -209,6 +163,7 @@ debugEnabled /******************************************************************************* * Function Name: $Sub$$main ******************************************************************************** +* * Summary: * This function is called imediatly before the users main * @@ -232,15 +187,14 @@ void $Sub$$main(void) #elif defined(__GNUC__) -extern uint32 __cs3_interrupt_vector; +extern void __cs3_stack(void); extern void __cs3_start_c(void); -#define RomVectors (cyisraddress)(&__cs3_interrupt_vector) - /******************************************************************************* * Function Name: Reset ******************************************************************************** +* * Summary: * This function handles the reset interrupt for the GCC toolchain. This is the * first bit of code that is executed at startup. @@ -284,9 +238,33 @@ void Reset(void) #endif /* __GNUC__ */ + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + #pragma diag_suppress 1296 +#endif +__attribute__ ((section(".romvectors"))) +const cyisraddress RomVectors[NUM_ROM_VECTORS] = +{ + #if defined(__ARMCC_VERSION) + INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #elif defined (__GNUC__) + &INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ + #endif /* (__ARMCC_VERSION) */ + (cyisraddress)&Reset, /* The reset handler 1 */ + &IntDefaultHandler, /* The NMI handler 2 */ + &IntDefaultHandler, /* The hard fault handler 3 */ +}; + + /******************************************************************************* * Function Name: initialize_psoc ******************************************************************************** +* * Summary: * This function used to initialize the PSoC chip before calling main. * @@ -314,7 +292,7 @@ void initialize_psoc(void) /* Set Ram interrupt vectors to default functions. */ for(i = 0u; i < NUM_VECTORS; i++) { - CyRamVectors[i] = RomVectors[i]; + CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; } /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ @@ -332,6 +310,9 @@ void initialize_psoc(void) CyDmacConfigure(); #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; } diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmGnu.s b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmGnu.s index 64404e9..062dba4 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmGnu.s +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmGnu.s @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: CyBootAsmGnu.s -* Version 3.30 +* Version 3.40 * * Description: * Assembly routines for GNU as. * ******************************************************************************** -* Copyright 2010-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying +* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmRv.s b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmRv.s index 1109303..3b362bc 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmRv.s +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyBootAsmRv.s @@ -1,14 +1,14 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 3.30 +; Version 3.40 ; ; DESCRIPTION: ; Assembly routines for RealView. ; ;------------------------------------------------------------------------------- -; Copyright 2010-2012, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying +; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. ;------------------------------------------------------------------------------- diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.c index 763431b..1ed276f 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyDmac.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the DMAC component. The API includes functions for the @@ -21,7 +21,7 @@ * The user can over write this once the TD is allocated. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -570,7 +570,8 @@ cystatus CyDmaChGetRequest(uint8 chHandle) if(chHandle < CY_DMA_NUMBEROF_CHANNELS) { - status = (cystatus) (CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & (CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); } return(status); @@ -818,32 +819,36 @@ uint8 CyDmaTdFreeCount(void) * uint8 nextTd: * Zero based index of the next Transfer Descriptor in the TD chain. Zero is a * valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. * * uint8 configuration: * Stores the Bit field of configuration bits. * -* TD_SWAP_EN - Perform endian swap +* CY_DMA_TD_SWAP_EN - Perform endian swap * -* TD_SWAP_SIZE4 - Swap size = 4 bytes +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes * -* TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger automatically -* when the current TD completes. +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. * -* TD_TERMIN_EN - Terminate this TD if a positive edge on the trq input -* line occurs. The positive edge must occur during a -* burst. That is the only time the DMAC will listen for -* it. +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. * -* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will -* generate a pulse. Note that this option is instance -* specific with the instance name followed by two -* underscores. In this example, the instance name is DMA. +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. * -* TD_INC_DST_ADR - Increment DST_ADR according to the size of each data -* transaction in the burst. +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. * -* TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each data -* transaction in the burst. +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. * * Return: * CYRET_SUCCESS if successful. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.h index 0f42fdf..b7aaef1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyDmac.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyDmac.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the DMA Controller. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -109,9 +109,9 @@ typedef struct dmac_tdmem2_struct #define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ #define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ -#if(CY_PSOC3) +#if(CY_PSOC3 || CY_PSOC5LP) #define CY_DMA_DISABLE_TD 0xFEu -#endif /* (CY_PSOC3) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ #define CY_DMA_TD_SIZE 0x08u @@ -195,9 +195,9 @@ typedef struct dmac_tdmem2_struct #define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) #define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) #define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) -#if(CY_PSOC3) +#if(CY_PSOC3 || CY_PSOC5LP) #define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) -#endif /* (CY_PSOC3) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ #define DMAC_CFG (CY_DMA_CFG_PTR) #define DMAC_ERR (CY_DMA_ERR_PTR) diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.c index e216c45..939ff7c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyFlash.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the FLASH/EEPROM. @@ -13,7 +13,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -364,7 +364,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) /* Copy the rowdata to the temporary buffer. */ #if(CY_PSOC3) - (void) memcpy((void *) rowBuffer, (const void *) rowData, (int16) CYDEV_FLS_ROW_SIZE); + (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); #else (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); #endif /* (CY_PSOC3) */ @@ -403,15 +403,19 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) * CYRET_UNKNOWN if there was an SPC error. * *******************************************************************************/ - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, uint8 * rowECC) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) { uint32 offset; uint16 i; cystatus status; /* Read the existing flash data. */ - offset = CYDEV_FLS_BASE + ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) + + offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) + ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE); + + #if (CYDEV_FLS_BASE != 0u) + offset += CYDEV_FLS_BASE; + #endif for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) { @@ -419,9 +423,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) } #if(CY_PSOC3) - (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *) rowECC, (int16) CYDEV_ECC_ROW_SIZE); + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE); #else - (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *) rowECC, CYDEV_ECC_ROW_SIZE); + (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE); #endif /* (CY_PSOC3) */ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.h index ee767ef..18c5d4a 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyFlash.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyFlash.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the FLASH/EEPROM. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -68,7 +68,8 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, uint8 * rowECC) ; + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ void CyFlash_SetWaitCycles(uint8 freq) ; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.c index 0f59206..0c52ec9 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyLib.c -* Version 3.30 +* Version 3.40 * * Description: * Provides system API for the clocking, interrupts and watchdog timer. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.h index fd2d94a..b036110 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CyLib.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CyLib.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the system, clocking, interrupts and @@ -11,7 +11,7 @@ * Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -803,7 +803,7 @@ uint8 CyVdRealTimeStatus(void) ; #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} - #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR &= (uint8)(~DISABLE_IRQ_SET);} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} #endif /* (CY_PSOC3) */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.c index 1baf598..6824a20 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CySpc.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the System Performance Component. @@ -8,7 +8,7 @@ * application. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.h index f2c0c02..afdf79d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/CySpc.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: CySpc.c -* Version 3.30 +* Version 3.40 * * Description: * Provides definitions for the System Performance Component API. @@ -8,7 +8,7 @@ * application. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.c index 0c7c2ce..a88cd76 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD.c -* Version 1.80 +* Version 1.90 * * Description: * This file provides source code for the Character LCD component's API. @@ -56,13 +56,13 @@ void LCD_Init(void) { /* INIT CODE */ CyDelay(40u); /* Delay 40 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(5u); /* Delay 5 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(15u); /* Delay 15 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_8_BIT_INIT); /* Selects 8-bit mode */ CyDelay(1u); /* Delay 1 ms */ - LCD_WrCntrlNib(LCD_DISPLAY_4_BIT_INIT); /* Selects 4-bit mode */ + LCD_WrCntrlNib(LCD_DISPLAY_4_BIT_INIT); /* Selects 4-bit mode */ CyDelay(5u); /* Delay 5 ms */ LCD_WriteControl(LCD_CURSOR_AUTO_INCR_ON); /* Incr Cursor After Writes */ @@ -358,7 +358,7 @@ void LCD_IsReady(void) #if (CY_PSOC4) /* Mask off data pins to clear old values out */ - value = LCD_PORT_PC_REG & ((uint8)(~ LCD_DM_DATA_MASK)); + value = LCD_PORT_PC_REG & ((uint32) (~ LCD_DM_DATA_MASK)); /* Load in high Z values for data pins, others unchanged */ LCD_PORT_PC_REG = value | LCD_HIGH_Z_DATA_DM; @@ -406,6 +406,9 @@ void LCD_IsReady(void) /* Set enable low */ LCD_PORT_DR_REG &= ((uint8)(~LCD_E)); + /* This gives a true delay between disably Enable bit and poling Ready bit */ + CyDelayUs(0u); + /* Extract ready bit */ value &= LCD_READY_BIT; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.h index 0b0bda9..261343e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD.h -* Version 1.80 +* Version 1.90 * * Description: * This header file contains registers and constants associated with the @@ -185,26 +185,30 @@ extern uint8 const CYCODE LCD_customFonts[64u]; * Registers ***************************************/ -/* Port Register Definitions */ -#define LCD_PORT_DR_REG (*(reg8 *) LCD_LCDPort__DR) /* Data Output Register */ -#define LCD_PORT_DR_PTR ( (reg8 *) LCD_LCDPort__DR) -#define LCD_PORT_PS_REG (*(reg8 *) LCD_LCDPort__PS) /* Pin State Register */ -#define LCD_PORT_PS_PTR ( (reg8 *) LCD_LCDPort__PS) - /* Device specific registers */ #if (CY_PSOC4) - #define LCD_PORT_PC_REG (*(reg32 *) LCD_LCDPort__PC) - #define LCD_PORT_PC_PTR (*(reg32 *) LCD_LCDPort__PC) + #define LCD_PORT_DR_REG (*(reg32 *) LCD_LCDPort__DR) /* Data Output Register */ + #define LCD_PORT_DR_PTR ( (reg32 *) LCD_LCDPort__DR) + #define LCD_PORT_PS_REG (*(reg32 *) LCD_LCDPort__PS) /* Pin State Register */ + #define LCD_PORT_PS_PTR ( (reg32 *) LCD_LCDPort__PS) + + #define LCD_PORT_PC_REG (*(reg32 *) LCD_LCDPort__PC) + #define LCD_PORT_PC_PTR (*(reg32 *) LCD_LCDPort__PC) #else - #define LCD_PORT_DM0_REG (*(reg8 *) LCD_LCDPort__DM0) /* Port Drive Mode 0 */ - #define LCD_PORT_DM0_PTR ( (reg8 *) LCD_LCDPort__DM0) - #define LCD_PORT_DM1_REG (*(reg8 *) LCD_LCDPort__DM1) /* Port Drive Mode 1 */ - #define LCD_PORT_DM1_PTR ( (reg8 *) LCD_LCDPort__DM1) - #define LCD_PORT_DM2_REG (*(reg8 *) LCD_LCDPort__DM2) /* Port Drive Mode 2 */ - #define LCD_PORT_DM2_PTR ( (reg8 *) LCD_LCDPort__DM2) + #define LCD_PORT_DR_REG (*(reg8 *) LCD_LCDPort__DR) /* Data Output Register */ + #define LCD_PORT_DR_PTR ( (reg8 *) LCD_LCDPort__DR) + #define LCD_PORT_PS_REG (*(reg8 *) LCD_LCDPort__PS) /* Pin State Register */ + #define LCD_PORT_PS_PTR ( (reg8 *) LCD_LCDPort__PS) + + #define LCD_PORT_DM0_REG (*(reg8 *) LCD_LCDPort__DM0) /* Port Drive Mode 0 */ + #define LCD_PORT_DM0_PTR ( (reg8 *) LCD_LCDPort__DM0) + #define LCD_PORT_DM1_REG (*(reg8 *) LCD_LCDPort__DM1) /* Port Drive Mode 1 */ + #define LCD_PORT_DM1_PTR ( (reg8 *) LCD_LCDPort__DM1) + #define LCD_PORT_DM2_REG (*(reg8 *) LCD_LCDPort__DM2) /* Port Drive Mode 2 */ + #define LCD_PORT_DM2_PTR ( (reg8 *) LCD_LCDPort__DM2) #endif /* CY_PSOC4 */ @@ -214,8 +218,13 @@ extern uint8 const CYCODE LCD_customFonts[64u]; ***************************************/ /* SHIFT must be 1 or 0 */ -#define LCD_PORT_SHIFT (LCD_LCDPort__SHIFT) -#define LCD_PORT_MASK (LCD_LCDPort__MASK) +#if (0 == LCD_LCDPort__SHIFT) + #define LCD_PORT_SHIFT (0x00u) +#else + #define LCD_PORT_SHIFT (0x01u) +#endif /* (0 == LCD_LCDPort__SHIFT) */ + +#define LCD_PORT_MASK ((uint8) (LCD_LCDPort__MASK)) #if (CY_PSOC4) @@ -225,7 +234,9 @@ extern uint8 const CYCODE LCD_customFonts[64u]; */ #define LCD_HIGH_Z_DATA_DM (0x00000249ul) #define LCD_STRONG_DATA_DM (0x00000DB6ul) - #define LCD_DM_DATA_MASK (0xFFFul << (LCD_PORT_SHIFT * 3u)) + #define LCD_DATA_PINS_MASK (0x00000FFFul) + #define LCD_DM_DATA_MASK ((uint32)(LCD_DATA_PINS_MASK << \ + (LCD_PORT_SHIFT * 3u))) #else @@ -247,11 +258,16 @@ extern uint8 const CYCODE LCD_customFonts[64u]; #endif /* CY_PSOC4 */ /* Pin Masks */ -#define LCD_RS ((uint8) (((uint8) 0x20u) << LCD_LCDPort__SHIFT)) -#define LCD_RW ((uint8) (((uint8) 0x40u) << LCD_LCDPort__SHIFT)) -#define LCD_E ((uint8) (((uint8) 0x10u) << LCD_LCDPort__SHIFT)) -#define LCD_READY_BIT ((uint8) (((uint8) 0x08u) << LCD_LCDPort__SHIFT)) -#define LCD_DATA_MASK ((uint8) (((uint8) 0x0Fu) << LCD_LCDPort__SHIFT)) +#define LCD_RS ((uint8) \ + (((uint8) 0x20u) << LCD_LCDPort__SHIFT)) +#define LCD_RW ((uint8) \ + (((uint8) 0x40u) << LCD_LCDPort__SHIFT)) +#define LCD_E ((uint8) \ + (((uint8) 0x10u) << LCD_LCDPort__SHIFT)) +#define LCD_READY_BIT ((uint8) \ + (((uint8) 0x08u) << LCD_LCDPort__SHIFT)) +#define LCD_DATA_MASK ((uint8) \ + (((uint8) 0x0Fu) << LCD_LCDPort__SHIFT)) /* These names are obsolete and will be removed in future revisions */ #define LCD_PORT_DR LCD_PORT_DR_REG diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.c index 7d5cdb8..3fa29b2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.h index 6f77bc0..4417263 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort_aliases.h index bfba954..15c22c8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_LCDPort_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_LCDPort.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_PM.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_PM.c index b34c396..855f7f2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_PM.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/LCD_PM.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LCD_PM.c -* Version 1.80 +* Version 1.90 * * Description: * This file provides the API source code for the Static Segment LCD component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.bvf b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.bvf index 682e81b..d677d59 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.bvf +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.bvf @@ -11,275 +11,367 @@ Verifying bitstream. ---------Processing bitstream.--------- -Utilized "udb_hv_b@[UDB Pair=(1,2)]" +Utilized "udb_hc@[UDB Pair=(1,0)]" +Utilized "udb_hv_a@[UDB Pair=(1,1)]" Utilized "udb_hv_a@[UDB Pair=(1,3)]" Utilized "udb_hc@[UDB Pair=(1,3)]" Utilized "udb_hv_b@[UDB Pair=(1,4)]" Utilized "udb_hc@[UDB Pair=(1,4)]" +Utilized "udb_hv_a@[UDB Pair=(1,5)]" Utilized "udb_hc@[UDB Pair=(1,5)]" -Utilized "dsi_hv_b@[DSI=(0,2)][side=top]" +Utilized "dsi_hv_b@[DSI=(1,1)][side=bottom]" +Utilized "dsi_hc@[DSI=(1,2)][side=bottom]" Utilized "dsi_hv_a@[DSI=(0,3)][side=top]" Utilized "dsi_hv_b@[DSI=(1,3)][side=bottom]" Utilized "dsi_hv_a@[DSI=(1,4)][side=bottom]" Utilized "dsi_hc@[DSI=(0,5)][side=top]" +Utilized "dsi_hv_a@[DSI=(0,5)][side=top]" Utilized "dsi_hc@[DSI=(1,5)][side=bottom]" +Utilized "dsi_hv_b@[DSI=(1,5)][side=bottom]" ---------Propagating signals.--------- -Found signal "\SPIM:BSPIM:cnt_enable\" on jack "pld0:out0[UDB=(2,3)]". -Number of connected bvjacks: 2. +Found signal "\Timer_1:TimerUDB:status_tc\" on jack "pld0:out0[UDB=(2,0)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:inout3[UDB=(2,4)]" - - 2. Connected jack name: "pld0:in3[UDB=(2,3)]" + 1. Connected jack name: "statctrl:in0[UDB=(2,0)]" -Found signal "\SPIM:BSPIM:state_1\" on jack "pld0:out2[UDB=(2,3)]". -Number of connected bvjacks: 7. +Found signal "\Timer_1:TimerUDB:trig_disable\" on jack "pld0:out1[UDB=(2,0)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "pld1:in6[UDB=(3,5)]" + 1. Connected jack name: "pld0:in5[UDB=(2,0)]" - 2. Connected jack name: "pld0:in2[UDB=(2,4)]" - 3. Connected jack name: "pld1:in10[UDB=(2,4)]" + +Found signal "\Timer_1:TimerUDB:timer_enable\" on jack "pld0:out2[UDB=(2,0)]". +Number of connected bvjacks: 3. + + 1. Connected jack name: "pld0:in1[UDB=(2,0)]" - 4. Connected jack name: "dp:in5[UDB=(2,4)]" + 2. Connected jack name: "dp:in1[UDB=(2,0)]" - 5. Connected jack name: "pld1:in10[UDB=(2,3)]" + 3. Connected jack name: "dp:in5[UDB=(3,0)]" - 6. Connected jack name: "pld0:in6[UDB=(2,3)]" - 7. Connected jack name: "pld0:in6[UDB=(3,3)]" + +Found signal "\Timer_1:TimerUDB:run_mode\" on jack "pld0:out3[UDB=(2,0)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "pld0:in7[UDB=(2,0)]" -Found signal "\SPIM:BSPIM:tx_status_4\" on jack "pld0:out3[UDB=(2,3)]". +Found signal "\Timer_1:TimerUDB:control_7\" on jack "statctrl:out7[UDB=(2,0)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:inout0[UDB=(2,3)]" + 1. Connected jack name: "pld0:in11[UDB=(2,0)]" + + + +Found signal "\UART_1:BUART:tx_state_1\" on jack "pld1:out3[UDB=(3,0)]". +Number of connected bvjacks: 5. + + 1. Connected jack name: "pld0:in3[UDB=(2,3)]" + + 2. Connected jack name: "pld0:in3[UDB=(3,3)]" + + 3. Connected jack name: "pld1:in4[UDB=(3,3)]" + + 4. Connected jack name: "dp:in3[UDB=(2,3)]" + + 5. Connected jack name: "pld1:in4[UDB=(3,0)]" -Found signal "\SPIM:BSPIM:dpcounter_one\" on jack "pld1:out0[UDB=(2,3)]". +Found signal "\Timer_1:TimerUDB:status_2\" on jack "dp:out0[UDB=(3,0)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:in3[UDB=(2,3)]" + 1. Connected jack name: "statctrl:in2[UDB=(2,0)]" -Found signal "\SPIM:BSPIM:load_cond\" on jack "pld1:out1[UDB=(2,3)]". +Found signal "\Timer_1:TimerUDB:status_3\" on jack "dp:out1[UDB=(3,0)]". Number of connected bvjacks: 1. - 1. Connected jack name: "pld1:in11[UDB=(2,3)]" + 1. Connected jack name: "statctrl:in3[UDB=(2,0)]" + + + +Found signal "\Timer_1:TimerUDB:per_zero\" on jack "dp:out2[UDB=(3,0)]". +Number of connected bvjacks: 3. + + 1. Connected jack name: "pld0:in8[UDB=(2,0)]" + + 2. Connected jack name: "dp:in3[UDB=(2,0)]" + + 3. Connected jack name: "dp:in3[UDB=(3,0)]" -Found signal "Net_479" on jack "pld1:out2[UDB=(2,3)]". +Found signal "ClockBlock_1k__SYNC_OUT" on jack "statctrl:inout0[UDB=(3,0)]". Number of connected bvjacks: 2. - 1. Connected jack name: "io_ijack_6[IOP=(0)]" + 1. Connected jack name: "clkrst:in3[UDB=(2,0)]" + + 2. Connected jack name: "clkrst:in0[UDB=(3,0)]" + + + +Found signal "\UART_1:BUART:tx_state_0\" on jack "pld0:out0[UDB=(2,3)]". +Number of connected bvjacks: 5. + + 1. Connected jack name: "pld0:in4[UDB=(2,3)]" + + 2. Connected jack name: "pld0:in4[UDB=(3,3)]" + + 3. Connected jack name: "pld1:in11[UDB=(3,0)]" + + 4. Connected jack name: "pld1:in11[UDB=(3,3)]" - 2. Connected jack name: "pld1:in6[UDB=(2,3)]" + 5. Connected jack name: "dp:in4[UDB=(2,3)]" -Found signal "\SPIM:BSPIM:load_rx_data\" on jack "pld1:out3[UDB=(2,3)]". +Found signal "\SPIM:BSPIM:rx_status_6\" on jack "pld0:out1[UDB=(2,3)]". Number of connected bvjacks: 1. - 1. Connected jack name: "dp:in4[UDB=(2,4)]" + 1. Connected jack name: "statctrl:inout2[UDB=(3,4)]" -Found signal "Net_30" on jack "pld0:out0[UDB=(3,3)]". +Found signal "\UART_1:BUART:tx_status_0\" on jack "pld0:out3[UDB=(2,3)]". Number of connected bvjacks: 1. - 1. Connected jack name: "io_ijack_5[IOP=(0)]" + 1. Connected jack name: "statctrl:in0[UDB=(2,3)]" + + + +Found signal "\UART_1:BUART:tx_status_2\" on jack "pld1:out1[UDB=(2,3)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "statctrl:in2[UDB=(2,3)]" + + + +Found signal "\UART_1:BUART:tx_bitclk\" on jack "pld1:out2[UDB=(2,3)]". +Number of connected bvjacks: 4. + + 1. Connected jack name: "pld1:in6[UDB=(3,0)]" + + 2. Connected jack name: "pld0:in1[UDB=(2,3)]" + + 3. Connected jack name: "pld1:in6[UDB=(3,3)]" + + 4. Connected jack name: "pld0:in9[UDB=(3,3)]" + + + +Found signal "\UART_1:BUART:tx_bitclk_enable_pre\" on jack "pld1:out3[UDB=(2,3)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "dp:in0[UDB=(2,3)]" -Found signal "Net_439" on jack "pld0:out1[UDB=(3,3)]". +Found signal "\UART_1:BUART:tx_fifo_empty\" on jack "dp:out0[UDB=(2,3)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in5[UDB=(3,3)]" + 1. Connected jack name: "pld0:in2[UDB=(2,3)]" - 2. Connected jack name: "pld1:in6[UDB=(3,3)]" + 2. Connected jack name: "statctrl:in1[UDB=(2,3)]" -Found signal "\SPIM:BSPIM:ld_ident\" on jack "pld0:out2[UDB=(3,3)]". +Found signal "\UART_1:BUART:tx_fifo_notfull\" on jack "dp:out1[UDB=(2,3)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in2[UDB=(3,3)]" + 1. Connected jack name: "pld1:in4[UDB=(2,3)]" - 2. Connected jack name: "pld0:in5[UDB=(2,4)]" + 2. Connected jack name: "statctrl:in3[UDB=(2,3)]" -Found signal "Net_419" on jack "pld0:out3[UDB=(3,3)]". +Found signal "\UART_1:BUART:tx_shift_out\" on jack "dp:out3[UDB=(2,3)]". Number of connected bvjacks: 1. - 1. Connected jack name: "io_ijack_0[IOP=(3)]" + 1. Connected jack name: "pld0:in10[UDB=(3,3)]" -Found signal "Net_428" on jack "pld1:out0[UDB=(3,3)]". -Number of connected bvjacks: 1. +Found signal "\UART_1:BUART:txn\" on jack "pld0:out1[UDB=(3,3)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "io_ijack_2[IOP=(3)]" + 1. Connected jack name: "pld0:in5[UDB=(3,4)]" + + 2. Connected jack name: "pld0:in5[UDB=(3,3)]" -Found signal "Net_422" on jack "pld1:out1[UDB=(3,3)]". -Number of connected bvjacks: 1. +Found signal "\UART_1:BUART:tx_state_2\" on jack "pld0:out2[UDB=(3,3)]". +Number of connected bvjacks: 4. - 1. Connected jack name: "io_ijack_1[IOP=(3)]" + 1. Connected jack name: "pld0:in1[UDB=(3,3)]" + + 2. Connected jack name: "pld1:in9[UDB=(3,0)]" + + 3. Connected jack name: "pld0:in5[UDB=(2,3)]" + + 4. Connected jack name: "pld1:in9[UDB=(3,3)]" -Found signal "Net_425" on jack "pld1:out2[UDB=(3,3)]". +Found signal "\UART_1:BUART:counter_load_not\" on jack "pld1:out1[UDB=(3,3)]". Number of connected bvjacks: 1. - 1. Connected jack name: "io_ijack_3[IOP=(3)]" + 1. Connected jack name: "dp:in1[UDB=(3,3)]" -Found signal "mywire_1_0" on jack "statctrl:out0[UDB=(3,3)]". +Found signal "\SPIM:BSPIM:mosi_hs_reg\" on jack "pld1:out3[UDB=(3,3)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in3[UDB=(3,3)]" + 1. Connected jack name: "pld1:in3[UDB=(3,3)]" + + 2. Connected jack name: "pld0:in0[UDB=(3,5)]" + - 2. Connected jack name: "pld1:in4[UDB=(3,3)]" + +Found signal "\UART_1:BUART:tx_bitclk_dp\" on jack "dp:out3[UDB=(3,3)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "pld1:in2[UDB=(2,3)]" -Found signal "mywire_1_1" on jack "statctrl:out1[UDB=(3,3)]". +Found signal "\UART_1:BUART:tx_counter_dp\" on jack "dp:out4[UDB=(3,3)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld1:in2[UDB=(3,3)]" + 1. Connected jack name: "pld1:in1[UDB=(3,0)]" - 2. Connected jack name: "pld0:in9[UDB=(3,3)]" + 2. Connected jack name: "pld0:in6[UDB=(3,3)]" -Found signal "\SPIM:BSPIM:mosi_pre_reg\" on jack "pld0:out3[UDB=(2,4)]". +Found signal "\SPIM:BSPIM:mosi_pre_reg\" on jack "pld0:out0[UDB=(2,4)]". Number of connected bvjacks: 1. - 1. Connected jack name: "pld0:in0[UDB=(2,4)]" + 1. Connected jack name: "pld0:in3[UDB=(2,4)]" -Found signal "\SPIM:BSPIM:tx_status_0\" on jack "pld1:out0[UDB=(2,4)]". -Number of connected bvjacks: 1. +Found signal "\SPIM:BSPIM:is_spi_done\" on jack "pld1:out0[UDB=(2,4)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "statctrl:in0[UDB=(2,3)]" + 1. Connected jack name: "pld0:in11[UDB=(2,5)]" + + 2. Connected jack name: "pld1:in4[UDB=(2,4)]" Found signal "\SPIM:BSPIM:state_0\" on jack "pld1:out1[UDB=(2,4)]". Number of connected bvjacks: 7. - 1. Connected jack name: "dp:in2[UDB=(2,4)]" + 1. Connected jack name: "pld0:in5[UDB=(2,4)]" - 2. Connected jack name: "pld0:in6[UDB=(2,4)]" + 2. Connected jack name: "pld1:in5[UDB=(2,4)]" - 3. Connected jack name: "pld1:in5[UDB=(2,4)]" + 3. Connected jack name: "pld1:in10[UDB=(3,3)]" - 4. Connected jack name: "pld1:in2[UDB=(3,5)]" + 4. Connected jack name: "pld0:in10[UDB=(2,5)]" - 5. Connected jack name: "pld1:in2[UDB=(2,3)]" + 5. Connected jack name: "pld1:in2[UDB=(2,5)]" - 6. Connected jack name: "pld0:in1[UDB=(3,3)]" + 6. Connected jack name: "dp:in5[UDB=(2,4)]" - 7. Connected jack name: "pld0:in10[UDB=(2,3)]" + 7. Connected jack name: "pld0:in2[UDB=(3,5)]" Found signal "\SPIM:BSPIM:state_2\" on jack "pld1:out2[UDB=(2,4)]". Number of connected bvjacks: 7. - 1. Connected jack name: "pld0:in1[UDB=(2,4)]" + 1. Connected jack name: "pld0:in6[UDB=(3,5)]" - 2. Connected jack name: "dp:in1[UDB=(2,4)]" + 2. Connected jack name: "pld1:in6[UDB=(2,4)]" - 3. Connected jack name: "pld0:in10[UDB=(3,3)]" + 3. Connected jack name: "dp:in1[UDB=(2,4)]" - 4. Connected jack name: "pld1:in6[UDB=(2,4)]" + 4. Connected jack name: "pld0:in5[UDB=(2,5)]" - 5. Connected jack name: "pld1:in9[UDB=(2,3)]" + 5. Connected jack name: "pld1:in10[UDB=(2,5)]" - 6. Connected jack name: "pld1:in1[UDB=(3,5)]" + 6. Connected jack name: "pld1:in8[UDB=(3,3)]" - 7. Connected jack name: "pld0:in9[UDB=(2,3)]" + 7. Connected jack name: "pld0:in7[UDB=(2,4)]" -Found signal "\SPIM:BSPIM:is_spi_done\" on jack "pld1:out3[UDB=(2,4)]". -Number of connected bvjacks: 2. +Found signal "\SPIM:BSPIM:tx_status_0\" on jack "pld1:out3[UDB=(2,4)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "pld0:in4[UDB=(2,3)]" - - 2. Connected jack name: "pld1:in7[UDB=(2,4)]" + 1. Connected jack name: "statctrl:in0[UDB=(2,5)]" Found signal "\SPIM:BSPIM:tx_status_2\" on jack "dp:out0[UDB=(2,4)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:in2[UDB=(2,3)]" + 1. Connected jack name: "statctrl:in2[UDB=(2,5)]" Found signal "\SPIM:BSPIM:rx_status_4\" on jack "dp:out1[UDB=(2,4)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in0[UDB=(2,5)]" + 1. Connected jack name: "pld0:in7[UDB=(2,3)]" - 2. Connected jack name: "statctrl:inout0[UDB=(2,5)]" + 2. Connected jack name: "statctrl:inout0[UDB=(3,4)]" -Found signal "\SPIM:BSPIM:mosi_from_dp\" on jack "dp:out2[UDB=(2,4)]". +Found signal "\SPIM:BSPIM:tx_status_1\" on jack "dp:out2[UDB=(2,4)]". Number of connected bvjacks: 3. - 1. Connected jack name: "pld0:in0[UDB=(3,4)]" + 1. Connected jack name: "pld0:in8[UDB=(2,5)]" - 2. Connected jack name: "pld1:in8[UDB=(3,5)]" + 2. Connected jack name: "statctrl:in1[UDB=(2,5)]" - 3. Connected jack name: "pld0:in4[UDB=(2,4)]" + 3. Connected jack name: "pld1:in11[UDB=(2,4)]" Found signal "\SPIM:BSPIM:rx_status_5\" on jack "dp:out3[UDB=(2,4)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:inout1[UDB=(2,5)]" + 1. Connected jack name: "statctrl:inout1[UDB=(3,4)]" -Found signal "\SPIM:BSPIM:tx_status_1\" on jack "dp:out4[UDB=(2,4)]". +Found signal "\SPIM:BSPIM:mosi_from_dp\" on jack "dp:out4[UDB=(2,4)]". Number of connected bvjacks: 3. - 1. Connected jack name: "pld0:in5[UDB=(2,3)]" + 1. Connected jack name: "pld0:in10[UDB=(3,4)]" - 2. Connected jack name: "statctrl:in1[UDB=(2,3)]" + 2. Connected jack name: "pld1:in5[UDB=(3,3)]" - 3. Connected jack name: "pld1:in9[UDB=(2,4)]" + 3. Connected jack name: "pld0:in6[UDB=(2,4)]" Found signal "\SPIM:BSPIM:count_0\" on jack "statctrl:out0[UDB=(2,4)]". Number of connected bvjacks: 5. - 1. Connected jack name: "pld0:in3[UDB=(2,5)]" + 1. Connected jack name: "pld0:in11[UDB=(2,3)]" - 2. Connected jack name: "pld0:in11[UDB=(2,3)]" + 2. Connected jack name: "pld0:in11[UDB=(2,4)]" - 3. Connected jack name: "pld1:in3[UDB=(2,3)]" + 3. Connected jack name: "pld1:in3[UDB=(2,4)]" - 4. Connected jack name: "pld0:in11[UDB=(2,4)]" + 4. Connected jack name: "pld1:in3[UDB=(2,5)]" - 5. Connected jack name: "pld1:in3[UDB=(2,4)]" + 5. Connected jack name: "pld0:in3[UDB=(2,5)]" @@ -288,11 +380,11 @@ Number of connected bvjacks: 5. 1. Connected jack name: "pld0:in1[UDB=(2,5)]" - 2. Connected jack name: "pld1:in5[UDB=(2,3)]" + 2. Connected jack name: "pld1:in5[UDB=(2,5)]" - 3. Connected jack name: "pld0:in10[UDB=(2,4)]" + 3. Connected jack name: "pld0:in10[UDB=(2,3)]" - 4. Connected jack name: "pld0:in2[UDB=(2,3)]" + 4. Connected jack name: "pld0:in10[UDB=(2,4)]" 5. Connected jack name: "pld1:in2[UDB=(2,4)]" @@ -301,201 +393,211 @@ Number of connected bvjacks: 5. Found signal "\SPIM:BSPIM:count_2\" on jack "statctrl:out2[UDB=(2,4)]". Number of connected bvjacks: 5. - 1. Connected jack name: "pld0:in9[UDB=(2,5)]" + 1. Connected jack name: "pld0:in2[UDB=(2,4)]" - 2. Connected jack name: "pld0:in1[UDB=(2,3)]" + 2. Connected jack name: "pld1:in9[UDB=(2,5)]" - 3. Connected jack name: "pld1:in1[UDB=(2,3)]" + 3. Connected jack name: "pld0:in9[UDB=(2,5)]" - 4. Connected jack name: "pld0:in9[UDB=(2,4)]" + 4. Connected jack name: "pld0:in6[UDB=(2,3)]" - 5. Connected jack name: "pld1:in1[UDB=(2,4)]" + 5. Connected jack name: "pld1:in9[UDB=(2,4)]" Found signal "\SPIM:BSPIM:count_3\" on jack "statctrl:out3[UDB=(2,4)]". Number of connected bvjacks: 5. - 1. Connected jack name: "pld0:in7[UDB=(2,5)]" + 1. Connected jack name: "pld1:in7[UDB=(2,5)]" - 2. Connected jack name: "pld0:in7[UDB=(2,4)]" + 2. Connected jack name: "pld0:in7[UDB=(2,5)]" - 3. Connected jack name: "pld1:in4[UDB=(2,4)]" + 3. Connected jack name: "pld0:in8[UDB=(2,3)]" - 4. Connected jack name: "pld0:in0[UDB=(2,3)]" + 4. Connected jack name: "pld0:in8[UDB=(2,4)]" - 5. Connected jack name: "pld1:in7[UDB=(2,3)]" + 5. Connected jack name: "pld1:in7[UDB=(2,4)]" Found signal "\SPIM:BSPIM:count_4\" on jack "statctrl:out4[UDB=(2,4)]". Number of connected bvjacks: 5. - 1. Connected jack name: "pld1:in8[UDB=(2,3)]" + 1. Connected jack name: "pld1:in8[UDB=(2,5)]" 2. Connected jack name: "pld1:in8[UDB=(2,4)]" - 3. Connected jack name: "pld0:in8[UDB=(2,5)]" + 3. Connected jack name: "pld0:in0[UDB=(2,5)]" - 4. Connected jack name: "pld0:in8[UDB=(2,3)]" + 4. Connected jack name: "pld0:in0[UDB=(2,3)]" - 5. Connected jack name: "pld0:in8[UDB=(2,4)]" + 5. Connected jack name: "pld0:in0[UDB=(2,4)]" -Found signal "Net_234" on jack "pld0:out0[UDB=(3,4)]". +Found signal "\SPIM:BSPIM:mosi_from_dp_reg\" on jack "pld0:out1[UDB=(3,4)]". Number of connected bvjacks: 1. - 1. Connected jack name: "io_ijack_7[IOP=(3)]" + 1. Connected jack name: "pld1:in2[UDB=(3,3)]" -Found signal "\UART_1:BUART:tx_status_2\" on jack "pld0:out2[UDB=(3,4)]". +Found signal "Net_234" on jack "pld0:out2[UDB=(3,4)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:in2[UDB=(3,4)]" + 1. Connected jack name: "io_ijack_7[IOP=(3)]" -Found signal "\SPIM:BSPIM:mosi_from_dp_reg\" on jack "pld0:out3[UDB=(3,4)]". -Number of connected bvjacks: 1. +Found signal "\SPIM:BSPIM:cnt_enable\" on jack "pld0:out0[UDB=(2,5)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "pld1:in0[UDB=(3,5)]" + 1. Connected jack name: "pld0:in4[UDB=(2,5)]" + + 2. Connected jack name: "statctrl:inout0[UDB=(2,4)]" -Found signal "\UART_1:BUART:tx_state_0\" on jack "pld0:out0[UDB=(2,5)]". -Number of connected bvjacks: 4. +Found signal "\SPIM:BSPIM:state_1\" on jack "pld0:out2[UDB=(2,5)]". +Number of connected bvjacks: 7. - 1. Connected jack name: "pld0:in4[UDB=(2,5)]" + 1. Connected jack name: "pld0:in3[UDB=(3,5)]" - 2. Connected jack name: "pld1:in3[UDB=(3,5)]" + 2. Connected jack name: "pld1:in1[UDB=(2,4)]" - 3. Connected jack name: "pld0:in0[UDB=(3,5)]" + 3. Connected jack name: "pld0:in1[UDB=(2,4)]" - 4. Connected jack name: "dp:in3[UDB=(3,5)]" + 4. Connected jack name: "dp:in2[UDB=(2,4)]" + 5. Connected jack name: "pld1:in1[UDB=(3,3)]" - -Found signal "\SPIM:BSPIM:rx_status_6\" on jack "pld0:out1[UDB=(2,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:inout2[UDB=(2,5)]" + 6. Connected jack name: "pld1:in1[UDB=(2,5)]" + + 7. Connected jack name: "pld0:in6[UDB=(2,5)]" -Found signal "\UART_1:BUART:tx_state_1\" on jack "pld0:out2[UDB=(2,5)]". -Number of connected bvjacks: 4. +Found signal "\SPIM:BSPIM:tx_status_4\" on jack "pld0:out3[UDB=(2,5)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "pld0:in2[UDB=(3,5)]" - - 2. Connected jack name: "pld0:in6[UDB=(2,5)]" - - 3. Connected jack name: "dp:in5[UDB=(3,5)]" - - 4. Connected jack name: "pld1:in9[UDB=(3,5)]" + 1. Connected jack name: "statctrl:inout0[UDB=(2,5)]" -Found signal "\UART_1:BUART:tx_status_0\" on jack "pld0:out3[UDB=(2,5)]". +Found signal "\SPIM:BSPIM:load_cond\" on jack "pld1:out0[UDB=(2,5)]". Number of connected bvjacks: 1. - 1. Connected jack name: "statctrl:in0[UDB=(3,4)]" + 1. Connected jack name: "pld1:in0[UDB=(2,5)]" -Found signal "\UART_1:BUART:tx_bitclk_enable_pre\" on jack "pld1:out0[UDB=(2,5)]". +Found signal "\SPIM:BSPIM:dpcounter_one\" on jack "pld1:out1[UDB=(2,5)]". Number of connected bvjacks: 1. - 1. Connected jack name: "dp:in4[UDB=(3,5)]" + 1. Connected jack name: "statctrl:in3[UDB=(2,5)]" -Found signal "\UART_1:BUART:tx_bitclk\" on jack "pld1:out1[UDB=(2,5)]". -Number of connected bvjacks: 3. +Found signal "\SPIM:BSPIM:ld_ident\" on jack "pld1:out2[UDB=(2,5)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in10[UDB=(2,5)]" + 1. Connected jack name: "pld0:in9[UDB=(2,4)]" + + 2. Connected jack name: "pld1:in6[UDB=(2,5)]" - 2. Connected jack name: "pld1:in5[UDB=(3,5)]" - 3. Connected jack name: "pld0:in10[UDB=(3,5)]" + +Found signal "\SPIM:BSPIM:load_rx_data\" on jack "pld1:out3[UDB=(2,5)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "dp:in4[UDB=(2,4)]" -Found signal "\UART_1:BUART:tx_bitclk_dp\" on jack "dp:out4[UDB=(2,5)]". +Found signal "Net_30" on jack "pld0:out0[UDB=(3,5)]". Number of connected bvjacks: 1. - 1. Connected jack name: "pld1:in1[UDB=(2,5)]" + 1. Connected jack name: "io_ijack_5[IOP=(0)]" -Found signal "\UART_1:BUART:tx_counter_dp\" on jack "dp:out5[UDB=(2,5)]". +Found signal "Net_439" on jack "pld0:out1[UDB=(3,5)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in4[UDB=(3,5)]" + 1. Connected jack name: "pld0:in5[UDB=(3,5)]" - 2. Connected jack name: "pld0:in11[UDB=(2,5)]" + 2. Connected jack name: "pld1:in6[UDB=(3,5)]" -Found signal "\UART_1:BUART:tx_state_2\" on jack "pld0:out1[UDB=(3,5)]". -Number of connected bvjacks: 3. +Found signal "Net_479" on jack "pld0:out2[UDB=(3,5)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in5[UDB=(3,5)]" - - 2. Connected jack name: "pld0:in2[UDB=(2,5)]" + 1. Connected jack name: "io_ijack_6[IOP=(0)]" - 3. Connected jack name: "pld1:in10[UDB=(3,5)]" + 2. Connected jack name: "pld0:in1[UDB=(3,5)]" -Found signal "\UART_1:BUART:txn\" on jack "pld0:out2[UDB=(3,5)]". -Number of connected bvjacks: 2. +Found signal "Net_419" on jack "pld0:out3[UDB=(3,5)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "pld0:in6[UDB=(3,5)]" + 1. Connected jack name: "io_ijack_0[IOP=(3)]" - 2. Connected jack name: "pld0:in9[UDB=(3,4)]" + + +Found signal "Net_585" on jack "pld1:out0[UDB=(3,5)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "io_ijack_4[IOP=(3)]" -Found signal "\SPIM:BSPIM:mosi_hs_reg\" on jack "pld1:out0[UDB=(3,5)]". -Number of connected bvjacks: 2. +Found signal "Net_428" on jack "pld1:out1[UDB=(3,5)]". +Number of connected bvjacks: 1. - 1. Connected jack name: "pld1:in7[UDB=(3,5)]" + 1. Connected jack name: "io_ijack_2[IOP=(3)]" - 2. Connected jack name: "pld0:in8[UDB=(3,3)]" + + +Found signal "Net_422" on jack "pld1:out2[UDB=(3,5)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "io_ijack_1[IOP=(3)]" -Found signal "\UART_1:BUART:counter_load_not\" on jack "pld1:out3[UDB=(3,5)]". +Found signal "Net_425" on jack "pld1:out3[UDB=(3,5)]". Number of connected bvjacks: 1. - 1. Connected jack name: "dp:in3[UDB=(2,5)]" + 1. Connected jack name: "io_ijack_3[IOP=(3)]" -Found signal "\UART_1:BUART:tx_fifo_notfull\" on jack "dp:out1[UDB=(3,5)]". +Found signal "mywire_1_0" on jack "statctrl:out0[UDB=(3,5)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in8[UDB=(3,4)]" + 1. Connected jack name: "pld0:in11[UDB=(3,5)]" - 2. Connected jack name: "statctrl:in3[UDB=(3,4)]" + 2. Connected jack name: "pld1:in4[UDB=(3,5)]" -Found signal "\UART_1:BUART:tx_shift_out\" on jack "dp:out2[UDB=(3,5)]". -Number of connected bvjacks: 1. +Found signal "mywire_1_1" on jack "statctrl:out1[UDB=(3,5)]". +Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in8[UDB=(3,5)]" + 1. Connected jack name: "pld1:in2[UDB=(3,5)]" + + 2. Connected jack name: "pld0:in9[UDB=(3,5)]" -Found signal "\UART_1:BUART:tx_fifo_empty\" on jack "dp:out4[UDB=(3,5)]". +Found signal "mywire_1_2" on jack "statctrl:out2[UDB=(3,5)]". Number of connected bvjacks: 2. - 1. Connected jack name: "pld0:in5[UDB=(2,5)]" + 1. Connected jack name: "pld1:in1[UDB=(3,5)]" - 2. Connected jack name: "statctrl:in1[UDB=(3,4)]" + 2. Connected jack name: "pld0:in10[UDB=(3,5)]" @@ -506,6 +608,13 @@ Number of connected bvjacks: 1. +Found signal "ClockBlock_1k" on jack "clk_1k[FFB(Clock,0)]". +Number of connected bvjacks: 1. + + 1. Connected jack name: "statctrl:in0[UDB=(3,0)]" + + + ---------Verifying signals (routing).--------- diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.ctl b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.ctl index 616e924..82f15f0 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.ctl +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.ctl @@ -1,6 +1,6 @@ -- ====================================================================== -- PSOC5_SPI_LSM303D.ctl generated from PSOC5_SPI_LSM303D --- 03/22/2013 at 10:33 +-- 07/25/2013 at 16:48 -- This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! -- ====================================================================== diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cycdx b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cycdx index a249682..8bc505b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cycdx +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cycdx @@ -1,18 +1,66 @@ + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + @@ -22,24 +70,29 @@ - - - - - - + + + - - + + + + + + + + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cyfit b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.cyfit index 65292095f6b0b1e9f4e6813a497006e06a0a8f64..f2b9d323f9da8212253d8b576a8ae899c3fc159f 100644 GIT binary patch literal 192850 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zfV4B?1uAwr-o}CN=qCvP;N_RlA^-q_M8*5_A`--Hd_NIO5ZV3<008&=|BE20WE_za z#7k1r!vf+ zpgEEk;9dK$nTbCW!m|>Bm*rLZH(5Uh}bOeb{YW0z#|lF Lq0uw&YX<%U5lllq diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.dsf b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.dsf index 5279f96..094fdbe 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.dsf +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.dsf @@ -1,3 +1,43 @@ +:udbswitch@[UDB=(2,0)][side=top]:97,1_f +:udbswitch@[UDB=(2,0)][side=top]:97,4_f +:udbswitch@[UDB=(2,0)][side=top]:97,43_f +:udbswitch@[UDB=(2,0)][side=top]:97,46_f +:udbswitch@[UDB=(2,0)][side=top]:97,67_f +:udbswitch@[UDB=(2,0)][side=top]:97,70_f +:udbswitch@[UDB=(2,0)][side=top]:97,72_f +:udbswitch@[UDB=(2,0)][side=top]:97,75_f +:udbswitch@[UDB=(2,0)][side=top]:99,7_f +:udbswitch@[UDB=(2,0)][side=top]:99,10_f +:udbswitch@[UDB=(2,0)][side=top]:99,37_f +:udbswitch@[UDB=(2,0)][side=top]:99,40_f +:udbswitch@[UDB=(2,0)][side=top]:99,61_f +:udbswitch@[UDB=(2,0)][side=top]:99,64_f +:udbswitch@[UDB=(2,0)][side=top]:99,78_f +:udbswitch@[UDB=(2,0)][side=top]:99,81_f +:udbswitch@[UDB=(2,0)][side=top]:101,13_f +:udbswitch@[UDB=(2,0)][side=top]:101,16_f +:udbswitch@[UDB=(2,0)][side=top]:101,31_f +:udbswitch@[UDB=(2,0)][side=top]:101,34_f +:udbswitch@[UDB=(2,0)][side=top]:101,55_f +:udbswitch@[UDB=(2,0)][side=top]:101,58_f +:udbswitch@[UDB=(2,0)][side=top]:101,84_f +:udbswitch@[UDB=(2,0)][side=top]:101,87_f +:udbswitch@[UDB=(2,0)][side=top]:103,19_f +:udbswitch@[UDB=(2,0)][side=top]:103,22_f +:udbswitch@[UDB=(2,0)][side=top]:103,25_f +:udbswitch@[UDB=(2,0)][side=top]:103,28_f +:udbswitch@[UDB=(2,0)][side=top]:103,49_f +:udbswitch@[UDB=(2,0)][side=top]:103,52_f +:udbswitch@[UDB=(2,0)][side=top]:103,90_f +:udbswitch@[UDB=(2,0)][side=top]:103,93_f +:udbswitch@[UDB=(2,4)][side=top]:103,19_f +:udbswitch@[UDB=(2,4)][side=top]:103,22_f +:udbswitch@[UDB=(2,4)][side=top]:103,25_f +:udbswitch@[UDB=(2,4)][side=top]:103,28_f +:udbswitch@[UDB=(2,4)][side=top]:103,49_f +:udbswitch@[UDB=(2,4)][side=top]:103,52_f +:udbswitch@[UDB=(2,4)][side=top]:103,90_f +:udbswitch@[UDB=(2,4)][side=top]:103,93_f :udbswitch@[UDB=(2,5)][side=top]:102,18_f :udbswitch@[UDB=(2,5)][side=top]:102,22_f :udbswitch@[UDB=(2,5)][side=top]:102,25_f @@ -6,6 +46,14 @@ :udbswitch@[UDB=(2,5)][side=top]:102,53_f :udbswitch@[UDB=(2,5)][side=top]:102,90_f :udbswitch@[UDB=(2,5)][side=top]:102,92_f +:udbswitch@[UDB=(2,0)][side=top]:102,18_f +:udbswitch@[UDB=(2,0)][side=top]:102,22_f +:udbswitch@[UDB=(2,0)][side=top]:102,25_f +:udbswitch@[UDB=(2,0)][side=top]:102,29_f +:udbswitch@[UDB=(2,0)][side=top]:102,49_f +:udbswitch@[UDB=(2,0)][side=top]:102,53_f +:udbswitch@[UDB=(2,0)][side=top]:102,90_f +:udbswitch@[UDB=(2,0)][side=top]:102,92_f :udbswitch@[UDB=(2,3)][side=top]:102,18_f :udbswitch@[UDB=(2,3)][side=top]:102,22_f :udbswitch@[UDB=(2,3)][side=top]:102,25_f @@ -14,11 +62,3 @@ :udbswitch@[UDB=(2,3)][side=top]:102,53_f :udbswitch@[UDB=(2,3)][side=top]:102,90_f :udbswitch@[UDB=(2,3)][side=top]:102,92_f -:udbswitch@[UDB=(2,4)][side=top]:103,19_f -:udbswitch@[UDB=(2,4)][side=top]:103,22_f -:udbswitch@[UDB=(2,4)][side=top]:103,25_f -:udbswitch@[UDB=(2,4)][side=top]:103,28_f -:udbswitch@[UDB=(2,4)][side=top]:103,49_f -:udbswitch@[UDB=(2,4)][side=top]:103,52_f -:udbswitch@[UDB=(2,4)][side=top]:103,90_f -:udbswitch@[UDB=(2,4)][side=top]:103,93_f diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pci b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pci index b3c2c82..4e4da0b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pci +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pci @@ -1,5 +1,5 @@ # PSOC5_SPI_LSM303D -# 2013-03-22 09:33:26Z +# 2013-07-25 14:48:56Z # IO_0@[IOP=(1)][IoId=(0)] is reserved: SWDDebugEnabled dont_use_io iocell 1 0 @@ -11,6 +11,7 @@ set_io "Pin_1(0)" iocell 3 0 set_io "Pin_2(0)" iocell 3 1 set_io "Pin_3(0)" iocell 3 2 set_io "Pin_4(0)" iocell 3 3 +set_io "Pin_5(0)" iocell 3 4 set_io "Tx_1(0)" iocell 3 7 set_io "\LCD:LCDPort(0)\" iocell 2 0 set_io "\LCD:LCDPort(1)\" iocell 2 1 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pco b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pco index ffe013e..7e7cd47 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pco +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.pco @@ -1,5 +1,5 @@ # PSOC5_SPI_LSM303D -# 2013-03-22 09:33:27Z +# 2013-07-25 14:48:57Z # IO_0@[IOP=(1)][IoId=(0)] is reserved: SWDDebugEnabled dont_use_io iocell 1 0 @@ -8,18 +8,21 @@ dont_use_io iocell 1 1 # IO_3@[IOP=(1)][IoId=(3)] is reserved: SWDDebugEnabled dont_use_io iocell 1 3 set_location "ClockBlock" clockblockcell -1 -1 0 -set_location "Net_234" 3 4 0 1 -set_location "Net_30" 3 3 0 2 -set_location "Net_419" 3 3 0 3 -set_location "Net_422" 3 3 1 0 -set_location "Net_425" 3 3 1 1 -set_location "Net_428" 3 3 1 2 -set_location "Net_439" 3 3 0 0 -set_location "Net_479" 2 3 1 1 +set_location "ClockBlock_1k__SYNC" 3 0 5 0 +set_location "Net_234" 3 4 0 2 +set_location "Net_30" 3 5 0 2 +set_location "Net_419" 3 5 0 3 +set_location "Net_422" 3 5 1 0 +set_location "Net_425" 3 5 1 1 +set_location "Net_428" 3 5 1 2 +set_location "Net_439" 3 5 0 1 +set_location "Net_479" 3 5 0 0 +set_location "Net_585" 3 5 1 3 set_io "Pin_1(0)" iocell 3 0 set_io "Pin_2(0)" iocell 3 1 set_io "Pin_3(0)" iocell 3 2 set_io "Pin_4(0)" iocell 3 3 +set_io "Pin_5(0)" iocell 3 4 set_io "Tx_1(0)" iocell 3 7 set_io "\LCD:LCDPort(0)\" iocell 2 0 set_io "\LCD:LCDPort(1)\" iocell 2 1 @@ -29,37 +32,45 @@ set_io "\LCD:LCDPort(4)\" iocell 2 4 set_io "\LCD:LCDPort(5)\" iocell 2 5 set_io "\LCD:LCDPort(6)\" iocell 2 6 set_location "\SPIM:BSPIM:BitCounter\" 2 4 7 -set_location "\SPIM:BSPIM:RxStsReg\" 2 5 4 -set_location "\SPIM:BSPIM:TxStsReg\" 2 3 4 -set_location "\SPIM:BSPIM:cnt_enable\" 2 3 0 0 -set_location "\SPIM:BSPIM:dpcounter_one\" 2 3 1 3 +set_location "\SPIM:BSPIM:RxStsReg\" 3 4 4 +set_location "\SPIM:BSPIM:TxStsReg\" 2 5 4 +set_location "\SPIM:BSPIM:cnt_enable\" 2 5 0 0 +set_location "\SPIM:BSPIM:dpcounter_one\" 2 5 1 3 set_location "\SPIM:BSPIM:is_spi_done\" 2 4 1 0 -set_location "\SPIM:BSPIM:ld_ident\" 3 3 0 1 -set_location "\SPIM:BSPIM:load_cond\" 2 3 1 0 -set_location "\SPIM:BSPIM:load_rx_data\" 2 3 1 2 +set_location "\SPIM:BSPIM:ld_ident\" 2 5 1 1 +set_location "\SPIM:BSPIM:load_cond\" 2 5 1 0 +set_location "\SPIM:BSPIM:load_rx_data\" 2 5 1 2 set_location "\SPIM:BSPIM:mosi_from_dp_reg\" 3 4 0 0 -set_location "\SPIM:BSPIM:mosi_hs_reg\" 3 5 1 0 +set_location "\SPIM:BSPIM:mosi_hs_reg\" 3 3 1 0 set_location "\SPIM:BSPIM:mosi_pre_reg\" 2 4 0 0 -set_location "\SPIM:BSPIM:rx_status_6\" 2 5 0 0 +set_location "\SPIM:BSPIM:rx_status_6\" 2 3 0 0 set_location "\SPIM:BSPIM:sR8:Dp:u0\" 2 4 2 set_location "\SPIM:BSPIM:state_0\" 2 4 1 3 -set_location "\SPIM:BSPIM:state_1\" 2 3 0 1 +set_location "\SPIM:BSPIM:state_1\" 2 5 0 1 set_location "\SPIM:BSPIM:state_2\" 2 4 1 1 set_location "\SPIM:BSPIM:tx_status_0\" 2 4 1 2 -set_location "\SPIM:BSPIM:tx_status_4\" 2 3 0 2 -set_location "\SS:Async:ctrl_reg\" 3 3 6 -set_location "\UART_1:BUART:counter_load_not\" 3 5 1 1 -set_location "\UART_1:BUART:sTX:TxShifter:u0\" 3 5 2 -set_location "\UART_1:BUART:sTX:TxSts\" 3 4 4 -set_location "\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\" 2 5 2 -set_location "\UART_1:BUART:tx_bitclk\" 2 5 1 0 -set_location "\UART_1:BUART:tx_bitclk_enable_pre\" 2 5 1 1 -set_location "\UART_1:BUART:tx_state_0\" 2 5 0 1 -set_location "\UART_1:BUART:tx_state_1\" 2 5 0 2 -set_location "\UART_1:BUART:tx_state_2\" 3 5 0 1 -set_location "\UART_1:BUART:tx_status_0\" 2 5 0 3 -set_location "\UART_1:BUART:tx_status_2\" 3 4 0 2 -set_location "\UART_1:BUART:txn\" 3 5 0 0 +set_location "\SPIM:BSPIM:tx_status_4\" 2 5 0 2 +set_location "\SS:Async:ctrl_reg\" 3 5 6 +set_location "\Timer_1:TimerUDB:nrstSts:stsreg\" 2 0 4 +set_location "\Timer_1:TimerUDB:run_mode\" 2 0 0 3 +set_location "\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\" 2 0 6 +set_location "\Timer_1:TimerUDB:sT16:timerdp:u0\" 2 0 2 +set_location "\Timer_1:TimerUDB:sT16:timerdp:u1\" 3 0 2 +set_location "\Timer_1:TimerUDB:status_tc\" 2 0 0 2 +set_location "\Timer_1:TimerUDB:timer_enable\" 2 0 0 0 +set_location "\Timer_1:TimerUDB:trig_disable\" 2 0 0 1 +set_location "\UART_1:BUART:counter_load_not\" 3 3 1 1 +set_location "\UART_1:BUART:sTX:TxShifter:u0\" 2 3 2 +set_location "\UART_1:BUART:sTX:TxSts\" 2 3 4 +set_location "\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\" 3 3 2 +set_location "\UART_1:BUART:tx_bitclk\" 2 3 1 0 +set_location "\UART_1:BUART:tx_bitclk_enable_pre\" 2 3 1 1 +set_location "\UART_1:BUART:tx_state_0\" 2 3 0 1 +set_location "\UART_1:BUART:tx_state_1\" 3 0 1 0 +set_location "\UART_1:BUART:tx_state_2\" 3 3 0 1 +set_location "\UART_1:BUART:tx_status_0\" 2 3 0 3 +set_location "\UART_1:BUART:tx_status_2\" 2 3 1 3 +set_location "\UART_1:BUART:txn\" 3 3 0 0 set_io "m_miso_pin(0)" iocell 0 0 set_io "m_mosi_pin(0)" iocell 0 5 set_io "m_sclk_pin(0)" iocell 0 6 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.plc_log b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.plc_log index 9cd1cba..691d4cd 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.plc_log +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.plc_log @@ -1,2 +1,2 @@ -I2076: Total run-time: 1.0 sec. +I2076: Total run-time: 1.1 sec. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.route b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.route index 92b817a..e7ea0c6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.route +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.route @@ -1,317 +1,368 @@ -net \SPIM:BSPIM:rx_status_4\ - term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_blk_stat_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_blk_stat_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.f1_blk_stat_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v78" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v78" - switch ":udbswitch@[UDB=(2,4)][side=top]:78,28" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_28_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:0,28_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v0" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v0==>:udb@[UDB=(2,5)]:pld0:input_permute.input_0" +net \Timer_1:TimerUDB:per_zero\ + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.z0_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:datapath.z0_comb==>:udb@[UDB=(3,0)]:dp_wrapper:output_permute.z0_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:output_permute.outs_2==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v81" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v81" + switch ":udbswitch@[UDB=(2,0)][side=top]:81,70" + switch ":udbswitch@[UDB=(2,0)][side=top]:70,70_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v70" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v70==>:udb@[UDB=(2,0)]:dp_wrapper:input_permute.ina_3" + switch ":udb@[UDB=(2,0)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.cs_addr_0" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cs_addr_0" + switch ":udbswitch@[UDB=(2,0)][side=top]:71,70_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v71" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v71==>:udb@[UDB=(3,0)]:dp_wrapper:input_permute.ina_3" + switch ":udb@[UDB=(3,0)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.cs_addr_0" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cs_addr_0" + switch ":udbswitch@[UDB=(2,0)][side=top]:81,23" + switch ":udbswitch@[UDB=(2,0)][side=top]:16,23_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v16" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v16==>:udb@[UDB=(2,0)]:pld0:input_permute.input_8" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(2,0)]:pld0:mc2.main_1" + term ":udb@[UDB=(2,0)]:pld0:mc2.main_1" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,0)]:pld0:mc0.main_3" + term ":udb@[UDB=(2,0)]:pld0:mc0.main_3" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(2,0)]:pld0:mc1.main_2" + term ":udb@[UDB=(2,0)]:pld0:mc1.main_2" +end \Timer_1:TimerUDB:per_zero\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.z0" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.z0==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.z0i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.z0i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.co_msb" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.co_msb==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.ci" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.ci" +end \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ +net \Timer_1:TimerUDB:timer_enable\ + term ":udb@[UDB=(2,0)]:pld0:mc0.q" + switch ":udb@[UDB=(2,0)]:pld0:mc0.q==>:udb@[UDB=(2,0)]:pld0:output_permute2.q_0" + switch ":udb@[UDB=(2,0)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v28" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v28" + switch ":udbswitch@[UDB=(2,0)][side=top]:28,6" + switch ":udbswitch@[UDB=(2,0)][side=top]:66,6_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v66" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v66==>:udb@[UDB=(2,0)]:dp_wrapper:input_permute.ina_1" + switch ":udb@[UDB=(2,0)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.cs_addr_1" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cs_addr_1" + switch ":udbswitch@[UDB=(2,0)][side=top]:28,86" + switch ":udbswitch@[UDB=(2,0)][side=top]:75,86_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v75" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v75==>:udb@[UDB=(3,0)]:dp_wrapper:input_permute.ina_5" + switch ":udb@[UDB=(3,0)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.cs_addr_1" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cs_addr_1" + switch ":udbswitch@[UDB=(2,0)][side=top]:2,6_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v2" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v2==>:udb@[UDB=(2,0)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,0)]:pld0:mc0.main_1" + term ":udb@[UDB=(2,0)]:pld0:mc0.main_1" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(2,0)]:pld0:mc1.main_0" + term ":udb@[UDB=(2,0)]:pld0:mc1.main_0" +end \Timer_1:TimerUDB:timer_enable\ +net \Timer_1:TimerUDB:status_tc\ + term ":udb@[UDB=(2,0)]:pld0:mc2.q" + switch ":udb@[UDB=(2,0)]:pld0:mc2.q==>:udb@[UDB=(2,0)]:pld0:output_permute0.q_2" + switch ":udb@[UDB=(2,0)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v24" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v24" + switch ":udbswitch@[UDB=(2,0)][side=top]:24,66" + switch ":udbswitch@[UDB=(2,0)][side=top]:88,66_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v88" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v88==>:udb@[UDB=(2,0)]:statusicell.status_0" + term ":udb@[UDB=(2,0)]:statusicell.status_0" +end \Timer_1:TimerUDB:status_tc\ +net \Timer_1:TimerUDB:run_mode\ + term ":udb@[UDB=(2,0)]:pld0:mc3.q" + switch ":udb@[UDB=(2,0)]:pld0:mc3.q==>:udb@[UDB=(2,0)]:pld0:output_permute3.q_3" + switch ":udb@[UDB=(2,0)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v30" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v30" + switch ":udbswitch@[UDB=(2,0)][side=top]:30,51" + switch ":udbswitch@[UDB=(2,0)][side=top]:14,51_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v14" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v14==>:udb@[UDB=(2,0)]:pld0:input_permute.input_7" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(2,0)]:pld0:mc2.main_0" + term ":udb@[UDB=(2,0)]:pld0:mc2.main_0" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,0)]:pld0:mc0.main_2" + term ":udb@[UDB=(2,0)]:pld0:mc0.main_2" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(2,0)]:pld0:mc1.main_1" + term ":udb@[UDB=(2,0)]:pld0:mc1.main_1" +end \Timer_1:TimerUDB:run_mode\ +net \Timer_1:TimerUDB:control_7\ + term ":udb@[UDB=(2,0)]:controlcell.control_7" + switch ":udb@[UDB=(2,0)]:controlcell.control_7==>:udb@[UDB=(2,0)]:controlcell_control_7_permute.in_0" + switch ":udb@[UDB=(2,0)]:controlcell_control_7_permute.controlcell_control_7==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v118" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v118" + switch ":udbswitch@[UDB=(2,0)][side=top]:118,5" + switch ":udbswitch@[UDB=(2,0)][side=top]:22,5_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v22" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v22==>:udb@[UDB=(2,0)]:pld0:input_permute.input_11" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(2,0)]:pld0:mc3.main_0" + term ":udb@[UDB=(2,0)]:pld0:mc3.main_0" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,0)]:pld0:mc0.main_0" + term ":udb@[UDB=(2,0)]:pld0:mc0.main_0" +end \Timer_1:TimerUDB:control_7\ +net \Timer_1:TimerUDB:trig_disable\ + term ":udb@[UDB=(2,0)]:pld0:mc1.q" + switch ":udb@[UDB=(2,0)]:pld0:mc1.q==>:udb@[UDB=(2,0)]:pld0:output_permute1.q_1" + switch ":udb@[UDB=(2,0)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v26" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v26" + switch ":udbswitch@[UDB=(2,0)][side=top]:26,60" + switch ":udbswitch@[UDB=(2,0)][side=top]:10,60_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v10" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v10==>:udb@[UDB=(2,0)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,0)]:pld0:mc0.main_4" + term ":udb@[UDB=(2,0)]:pld0:mc0.main_4" + switch ":udb@[UDB=(2,0)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(2,0)]:pld0:mc1.main_3" + term ":udb@[UDB=(2,0)]:pld0:mc1.main_3" +end \Timer_1:TimerUDB:trig_disable\ +net ClockBlock_1k__SYNC_OUT + term ":udb@[UDB=(3,0)]:sync_wrapper:sync0.out" + switch ":udb@[UDB=(3,0)]:sync_wrapper:sync0.out==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v97" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v97" + switch ":udbswitch@[UDB=(2,0)][side=top]:97,1_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:126,1_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v126" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v126==>:udb@[UDB=(2,0)]:clockreset:clken_sc_mux.in_3" + switch ":udb@[UDB=(2,0)]:clockreset:clken_sc_mux.sc_clken==>:udb@[UDB=(2,0)]:statusicell.clk_en" + term ":udb@[UDB=(2,0)]:statusicell.clk_en" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v126==>:udb@[UDB=(2,0)]:clockreset:clken_pld0_mux.in_3" + switch ":udb@[UDB=(2,0)]:clockreset:clken_pld0_mux.pld0_clken==>:udb@[UDB=(2,0)]:pld0:mc3.clk_en" + term ":udb@[UDB=(2,0)]:pld0:mc3.clk_en" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v126==>:udb@[UDB=(2,0)]:clockreset:clken_dp_mux.in_3" + switch ":udb@[UDB=(2,0)]:clockreset:clken_dp_mux.dp_clken==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.clk_en" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.clk_en" + switch ":udbswitch@[UDB=(2,0)][side=top]:97,75_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:121,75_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v121" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v121==>:udb@[UDB=(3,0)]:clockreset:clken_dp_mux.in_0" + switch ":udb@[UDB=(3,0)]:clockreset:clken_dp_mux.dp_clken==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.clk_en" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.clk_en" + switch ":udb@[UDB=(2,0)]:clockreset:clken_pld0_mux.pld0_clken==>:udb@[UDB=(2,0)]:pld0:mc0.clk_en" + term ":udb@[UDB=(2,0)]:pld0:mc0.clk_en" + switch ":udb@[UDB=(2,0)]:clockreset:clken_pld0_mux.pld0_clken==>:udb@[UDB=(2,0)]:pld0:mc1.clk_en" + term ":udb@[UDB=(2,0)]:pld0:mc1.clk_en" +end ClockBlock_1k__SYNC_OUT +net \SPIM:BSPIM:count_2\ + term ":udb@[UDB=(2,4)]:count7cell.count_2" + switch ":udb@[UDB=(2,4)]:count7cell.count_2==>:udb@[UDB=(2,4)]:controlcell_control_2_permute.in_1" + switch ":udb@[UDB=(2,4)]:controlcell_control_2_permute.controlcell_control_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v108" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v108" + switch ":udbswitch@[UDB=(2,4)][side=top]:108,57" + switch ":udbswitch@[UDB=(2,4)][side=top]:123,57_f" + switch ":udbswitch@[UDB=(2,4)][side=top]:123,16_b" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_16_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:44,16_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v44" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v44==>:udb@[UDB=(2,5)]:pld1:input_permute.input_9" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc3_main_2==>:udb@[UDB=(2,5)]:pld1:mc3.main_2" + term ":udb@[UDB=(2,5)]:pld1:mc3.main_2" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_16_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:12,16_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v12" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v12==>:udb@[UDB=(2,3)]:pld0:input_permute.input_6" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,3)]:pld0:mc0.main_2" + term ":udb@[UDB=(2,3)]:pld0:mc0.main_2" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(2,5)]:pld1:mc0.main_5" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_5" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(2,5)]:pld1:mc2.main_2" + term ":udb@[UDB=(2,5)]:pld1:mc2.main_2" + switch ":udbswitch@[UDB=(2,4)][side=top]:44,16_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v44" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v44==>:udb@[UDB=(2,4)]:pld1:input_permute.input_9" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(2,4)]:pld1:mc0.main_5" + term ":udb@[UDB=(2,4)]:pld1:mc0.main_5" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_5==>:udb@[UDB=(2,4)]:pld1:mc1.main_5" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_5" + switch ":udbswitch@[UDB=(2,5)][side=top]:44,13_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:18,13_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v18" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v18==>:udb@[UDB=(2,5)]:pld0:input_permute.input_9" switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(2,5)]:pld0:mc0.main_5" term ":udb@[UDB=(2,5)]:pld0:mc0.main_5" - switch ":udbswitch@[UDB=(2,5)][side=top]:0,0_b" - switch ":udbswitch@[UDB=(2,5)][side=top]:96,0_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v96" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v96==>:udb@[UDB=(2,5)]:statusicell.status_4" - term ":udb@[UDB=(2,5)]:statusicell.status_4" -end \SPIM:BSPIM:rx_status_4\ -net \SPIM:BSPIM:rx_status_6\ - term ":udb@[UDB=(2,5)]:pld0:mc0.q" - switch ":udb@[UDB=(2,5)]:pld0:mc0.q==>:udb@[UDB=(2,5)]:pld0:output_permute1.q_0" - switch ":udb@[UDB=(2,5)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v26" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v26" - switch ":udbswitch@[UDB=(2,5)][side=top]:26,12" - switch ":udbswitch@[UDB=(2,5)][side=top]:100,12_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v100" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v100==>:udb@[UDB=(2,5)]:statusicell.status_6" - term ":udb@[UDB=(2,5)]:statusicell.status_6" -end \SPIM:BSPIM:rx_status_6\ -net \SPIM:BSPIM:mosi_from_dp\ - term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.so_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.so_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.so_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v80" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v80" - switch ":udbswitch@[UDB=(2,4)][side=top]:80,93" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_93_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:47,93_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v47" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v47==>:udb@[UDB=(3,5)]:pld1:input_permute.input_8" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(3,5)]:pld1:mc0.main_3" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_3" - switch ":udbswitch@[UDB=(2,4)][side=top]:80,67" - switch ":udbswitch@[UDB=(2,4)][side=top]:1,67_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v1" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v1==>:udb@[UDB=(3,4)]:pld0:input_permute.input_0" - switch ":udb@[UDB=(3,4)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,4)]:pld0:mc0.main_0" - term ":udb@[UDB=(3,4)]:pld0:mc0.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:8,93_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v8" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v8==>:udb@[UDB=(2,4)]:pld0:input_permute.input_4" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,4)]:pld0:mc0.main_3" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_3" -end \SPIM:BSPIM:mosi_from_dp\ -net \SPIM:BSPIM:state_2\ - term ":udb@[UDB=(2,4)]:pld1:mc1.q" - switch ":udb@[UDB=(2,4)]:pld1:mc1.q==>:udb@[UDB=(2,4)]:pld1:output_permute2.q_1" - switch ":udb@[UDB=(2,4)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v34" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v34" - switch ":udbswitch@[UDB=(2,4)][side=top]:34,63" - switch ":udbswitch@[UDB=(2,4)][side=top]:50,63_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v50" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v50==>:udb@[UDB=(2,4)]:pld1:input_permute.input_6" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(2,4)]:pld1:mc2.main_0" - term ":udb@[UDB=(2,4)]:pld1:mc2.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:34,6" - switch ":udbswitch@[UDB=(2,4)][side=top]:66,6_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v66" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v66==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_1" - switch ":udb@[UDB=(2,4)]:dp_wrapper:input_permute.cs_addr_2==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_2" - term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_2" - switch ":udbswitch@[UDB=(2,4)][side=top]:50,89_b" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_89_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:44,89_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v44" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v44==>:udb@[UDB=(2,3)]:pld1:input_permute.input_9" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(2,3)]:pld1:mc1.main_1" - term ":udb@[UDB=(2,3)]:pld1:mc1.main_1" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,3)]:pld1:mc0.main_0" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:34,39" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_39_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:21,39_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v21" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v21==>:udb@[UDB=(3,3)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,3)]:pld0:mc0.main_0" - term ":udb@[UDB=(3,3)]:pld0:mc0.main_0" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(3,3)]:pld0:mc1.main_0" - term ":udb@[UDB=(3,3)]:pld0:mc1.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:34,78" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_78_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:18,78_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v18" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v18==>:udb@[UDB=(2,3)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,3)]:pld0:mc0.main_0" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_0" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(2,3)]:pld0:mc1.main_0" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_0" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_78_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:61,78_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v61" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v61==>:udb@[UDB=(3,5)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(3,5)]:pld1:mc0.main_0" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:2,6_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v2" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v2==>:udb@[UDB=(2,4)]:pld0:input_permute.input_1" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,4)]:pld0:mc0.main_0" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_0" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,4)]:pld1:mc0.main_0" - term ":udb@[UDB=(2,4)]:pld1:mc0.main_0" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(2,4)]:pld1:mc3.main_0" - term ":udb@[UDB=(2,4)]:pld1:mc3.main_0" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(2,4)]:pld1:mc1.main_0" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_0" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(2,3)]:pld0:mc2.main_0" - term ":udb@[UDB=(2,3)]:pld0:mc2.main_0" -end \SPIM:BSPIM:state_2\ -net \SPIM:BSPIM:tx_status_0\ - term ":udb@[UDB=(2,4)]:pld1:mc2.q" - switch ":udb@[UDB=(2,4)]:pld1:mc2.q==>:udb@[UDB=(2,4)]:pld1:output_permute0.q_2" - switch ":udb@[UDB=(2,4)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v38" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v38" - switch ":udbswitch@[UDB=(2,4)][side=top]:38,94" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_94_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:88,94_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v88" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v88==>:udb@[UDB=(2,3)]:statusicell.status_0" - term ":udb@[UDB=(2,3)]:statusicell.status_0" -end \SPIM:BSPIM:tx_status_0\ -net \SPIM:BSPIM:count_1\ - term ":udb@[UDB=(2,4)]:count7cell.count_1" - switch ":udb@[UDB=(2,4)]:count7cell.count_1==>:udb@[UDB=(2,4)]:controlcell_control_1_permute.in_1" - switch ":udb@[UDB=(2,4)]:controlcell_control_1_permute.controlcell_control_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v106" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v106" - switch ":udbswitch@[UDB=(2,4)][side=top]:106,11" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_11_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:52,11_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v52" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v52==>:udb@[UDB=(2,3)]:pld1:input_permute.input_5" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_3==>:udb@[UDB=(2,3)]:pld1:mc3.main_3" - term ":udb@[UDB=(2,3)]:pld1:mc3.main_3" - switch ":udbswitch@[UDB=(2,4)][side=top]:106,8" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_8_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:2,8_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v2" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v2==>:udb@[UDB=(2,5)]:pld0:input_permute.input_1" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,5)]:pld0:mc0.main_3" - term ":udb@[UDB=(2,5)]:pld0:mc0.main_3" - switch ":udbswitch@[UDB=(2,4)][side=top]:106,36" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_36_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:4,36_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v4" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v4==>:udb@[UDB=(2,3)]:pld0:input_permute.input_2" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(2,3)]:pld0:mc0.main_6" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_6" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_6==>:udb@[UDB=(2,3)]:pld0:mc1.main_6" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_6" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(2,3)]:pld1:mc0.main_6" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_6" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc2_main_3==>:udb@[UDB=(2,3)]:pld1:mc2.main_3" - term ":udb@[UDB=(2,3)]:pld1:mc2.main_3" - switch ":udbswitch@[UDB=(2,4)][side=top]:20,11_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v20" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v20==>:udb@[UDB=(2,4)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(2,4)]:pld0:mc0.main_7" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_7" - switch ":udbswitch@[UDB=(2,4)][side=top]:58,36_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v58" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v58==>:udb@[UDB=(2,4)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(2,4)]:pld1:mc0.main_6" - term ":udb@[UDB=(2,4)]:pld1:mc0.main_6" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_6==>:udb@[UDB=(2,4)]:pld1:mc1.main_6" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_6" -end \SPIM:BSPIM:count_1\ + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_5==>:udb@[UDB=(2,5)]:pld0:mc1.main_5" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_5" + switch ":udbswitch@[UDB=(2,4)][side=top]:108,14" + switch ":udbswitch@[UDB=(2,4)][side=top]:4,14_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v4" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v4==>:udb@[UDB=(2,4)]:pld0:input_permute.input_2" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(2,4)]:pld0:mc0.main_6" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_6" +end \SPIM:BSPIM:count_2\ net \SPIM:BSPIM:dpcounter_one\ - term ":udb@[UDB=(2,3)]:pld1:mc3.q" - switch ":udb@[UDB=(2,3)]:pld1:mc3.q==>:udb@[UDB=(2,3)]:pld1:output_permute0.q_3" - switch ":udb@[UDB=(2,3)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v38" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v38" - switch ":udbswitch@[UDB=(2,3)][side=top]:38,51" - switch ":udbswitch@[UDB=(2,3)][side=top]:94,51_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v94" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v94==>:udb@[UDB=(2,3)]:statusicell.status_3" - term ":udb@[UDB=(2,3)]:statusicell.status_3" + term ":udb@[UDB=(2,5)]:pld1:mc3.q" + switch ":udb@[UDB=(2,5)]:pld1:mc3.q==>:udb@[UDB=(2,5)]:pld1:output_permute1.q_3" + switch ":udb@[UDB=(2,5)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v36" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v36" + switch ":udbswitch@[UDB=(2,5)][side=top]:36,35" + switch ":hvswitch@[UDB=(2,5)][side=left]:1,35_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:1,1_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:94,1_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v94" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v94==>:udb@[UDB=(2,5)]:statusicell.status_3" + term ":udb@[UDB=(2,5)]:statusicell.status_3" end \SPIM:BSPIM:dpcounter_one\ net \SPIM:BSPIM:state_1\ - term ":udb@[UDB=(2,3)]:pld0:mc1.q" - switch ":udb@[UDB=(2,3)]:pld0:mc1.q==>:udb@[UDB=(2,3)]:pld0:output_permute2.q_1" - switch ":udb@[UDB=(2,3)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v28" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v28" - switch ":udbswitch@[UDB=(2,3)][side=top]:28,40" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_40_f" - switch ":udbswitch@[UDB=(2,4)][side=top]:42,40_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v42" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v42==>:udb@[UDB=(2,4)]:pld1:input_permute.input_10" + term ":udb@[UDB=(2,5)]:pld0:mc1.q" + switch ":udb@[UDB=(2,5)]:pld0:mc1.q==>:udb@[UDB=(2,5)]:pld0:output_permute2.q_1" + switch ":udb@[UDB=(2,5)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v28" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v28" + switch ":udbswitch@[UDB=(2,5)][side=top]:28,9" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_9_b" + switch ":udbswitch@[UDB=(2,4)][side=top]:60,9_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v60" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v60==>:udb@[UDB=(2,4)]:pld1:input_permute.input_1" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(2,4)]:pld1:mc2.main_1" term ":udb@[UDB=(2,4)]:pld1:mc2.main_1" - switch ":udbswitch@[UDB=(2,4)][side=top]:74,40_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v74" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v74==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_5" + switch ":udbswitch@[UDB=(2,4)][side=top]:60,33_b" + switch ":udbswitch@[UDB=(2,4)][side=top]:68,33_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v68" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v68==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_2" switch ":udb@[UDB=(2,4)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_1" term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_1" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_40_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:51,40_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v51" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v51==>:udb@[UDB=(3,5)]:pld1:input_permute.input_6" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(3,5)]:pld1:mc0.main_1" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_1" + switch ":udbswitch@[UDB=(2,4)][side=top]:60,78_b" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_78_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:61,78_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v61" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v61==>:udb@[UDB=(3,3)]:pld1:input_permute.input_1" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(3,3)]:pld1:mc0.main_1" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_1" + switch ":udbswitch@[UDB=(2,4)][side=top]:60,30_b" + switch ":udbswitch@[UDB=(2,4)][side=top]:2,30_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v2" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v2==>:udb@[UDB=(2,4)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,4)]:pld0:mc0.main_1" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_1" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(2,4)]:pld1:mc0.main_1" term ":udb@[UDB=(2,4)]:pld1:mc0.main_1" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_1==>:udb@[UDB=(2,4)]:pld1:mc3.main_1" term ":udb@[UDB=(2,4)]:pld1:mc3.main_1" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(2,4)]:pld1:mc1.main_1" term ":udb@[UDB=(2,4)]:pld1:mc1.main_1" - switch ":udbswitch@[UDB=(2,4)][side=top]:4,40_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v4" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v4==>:udb@[UDB=(2,4)]:pld0:input_permute.input_2" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,4)]:pld0:mc0.main_1" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_1" - switch ":udbswitch@[UDB=(2,3)][side=top]:28,54" - switch ":udbswitch@[UDB=(2,3)][side=top]:12,54_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v12" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v12==>:udb@[UDB=(2,3)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,3)]:pld0:mc0.main_1" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_1" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(2,3)]:pld0:mc1.main_1" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_1" - switch ":udbswitch@[UDB=(2,3)][side=top]:13,54_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v13" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v13==>:udb@[UDB=(3,3)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(3,3)]:pld0:mc0.main_1" - term ":udb@[UDB=(3,3)]:pld0:mc0.main_1" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(3,3)]:pld0:mc1.main_1" - term ":udb@[UDB=(3,3)]:pld0:mc1.main_1" - switch ":udbswitch@[UDB=(2,3)][side=top]:42,40_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v42" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v42==>:udb@[UDB=(2,3)]:pld1:input_permute.input_10" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(2,3)]:pld1:mc1.main_2" - term ":udb@[UDB=(2,3)]:pld1:mc1.main_2" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(2,3)]:pld1:mc0.main_1" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_1" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(2,3)]:pld0:mc2.main_1" - term ":udb@[UDB=(2,3)]:pld0:mc2.main_1" + switch ":hvswitch@[UDB=(2,5)][side=left]:11,9_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:11,76_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:7,76_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v7" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v7==>:udb@[UDB=(3,5)]:pld0:input_permute.input_3" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(3,5)]:pld0:mc1.main_1" + term ":udb@[UDB=(3,5)]:pld0:mc1.main_1" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(3,5)]:pld0:mc0.main_2" + term ":udb@[UDB=(3,5)]:pld0:mc0.main_2" + switch ":udbswitch@[UDB=(2,5)][side=top]:28,57" + switch ":udbswitch@[UDB=(2,5)][side=top]:12,57_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v12" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v12==>:udb@[UDB=(2,5)]:pld0:input_permute.input_6" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,5)]:pld0:mc0.main_1" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_1" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(2,5)]:pld0:mc1.main_1" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_1" + switch ":udbswitch@[UDB=(2,5)][side=top]:60,9_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v60" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v60==>:udb@[UDB=(2,5)]:pld1:input_permute.input_1" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(2,5)]:pld1:mc1.main_1" + term ":udb@[UDB=(2,5)]:pld1:mc1.main_1" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(2,5)]:pld1:mc0.main_1" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_1" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(2,5)]:pld0:mc2.main_1" + term ":udb@[UDB=(2,5)]:pld0:mc2.main_1" end \SPIM:BSPIM:state_1\ -net \SPIM:BSPIM:tx_status_1\ - term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f0_blk_stat_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.f0_blk_stat_comb" - switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_4==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v84" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v84" - switch ":udbswitch@[UDB=(2,4)][side=top]:84,35" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_35_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:10,35_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v10" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v10==>:udb@[UDB=(2,3)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_8==>:udb@[UDB=(2,3)]:pld0:mc1.main_8" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_8" - switch ":udbswitch@[UDB=(2,4)][side=top]:84,55" - switch ":udbswitch@[UDB=(2,4)][side=top]:44,55_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v44" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v44==>:udb@[UDB=(2,4)]:pld1:input_permute.input_9" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(2,4)]:pld1:mc0.main_8" - term ":udb@[UDB=(2,4)]:pld1:mc0.main_8" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_3==>:udb@[UDB=(2,4)]:pld1:mc3.main_3" - term ":udb@[UDB=(2,4)]:pld1:mc3.main_3" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_8==>:udb@[UDB=(2,4)]:pld1:mc1.main_8" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_8" - switch ":udbswitch@[UDB=(2,3)][side=top]:10,63_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:90,63_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v90" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v90==>:udb@[UDB=(2,3)]:statusicell.status_1" - term ":udb@[UDB=(2,3)]:statusicell.status_1" -end \SPIM:BSPIM:tx_status_1\ +net \SPIM:BSPIM:tx_status_0\ + term ":udb@[UDB=(2,4)]:pld1:mc2.q" + switch ":udb@[UDB=(2,4)]:pld1:mc2.q==>:udb@[UDB=(2,4)]:pld1:output_permute3.q_2" + switch ":udb@[UDB=(2,4)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v32" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v32" + switch ":udbswitch@[UDB=(2,4)][side=top]:32,69" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_69_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:88,69_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v88" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v88==>:udb@[UDB=(2,5)]:statusicell.status_0" + term ":udb@[UDB=(2,5)]:statusicell.status_0" +end \SPIM:BSPIM:tx_status_0\ +net \SPIM:BSPIM:count_0\ + term ":udb@[UDB=(2,4)]:count7cell.count_0" + switch ":udb@[UDB=(2,4)]:count7cell.count_0==>:udb@[UDB=(2,4)]:controlcell_control_0_permute.in_1" + switch ":udb@[UDB=(2,4)]:controlcell_control_0_permute.controlcell_control_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v104" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v104" + switch ":udbswitch@[UDB=(2,4)][side=top]:104,45" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_45_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:56,45_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v56" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v56==>:udb@[UDB=(2,5)]:pld1:input_permute.input_3" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc3_main_4==>:udb@[UDB=(2,5)]:pld1:mc3.main_4" + term ":udb@[UDB=(2,5)]:pld1:mc3.main_4" + switch ":udbswitch@[UDB=(2,4)][side=top]:104,42" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_42_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:22,42_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v22" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v22==>:udb@[UDB=(2,3)]:pld0:input_permute.input_11" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,3)]:pld0:mc0.main_4" + term ":udb@[UDB=(2,3)]:pld0:mc0.main_4" + switch ":udbswitch@[UDB=(2,5)][side=top]:56,18_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:6,18_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v6" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v6==>:udb@[UDB=(2,5)]:pld0:input_permute.input_3" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(2,5)]:pld0:mc0.main_7" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_7" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_7==>:udb@[UDB=(2,5)]:pld0:mc1.main_7" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_7" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(2,5)]:pld1:mc0.main_7" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_7" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc2_main_4==>:udb@[UDB=(2,5)]:pld1:mc2.main_4" + term ":udb@[UDB=(2,5)]:pld1:mc2.main_4" + switch ":udbswitch@[UDB=(2,4)][side=top]:56,42_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v56" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v56==>:udb@[UDB=(2,4)]:pld1:input_permute.input_3" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(2,4)]:pld1:mc0.main_7" + term ":udb@[UDB=(2,4)]:pld1:mc0.main_7" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_7==>:udb@[UDB=(2,4)]:pld1:mc1.main_7" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_7" + switch ":udbswitch@[UDB=(2,4)][side=top]:22,42_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v22" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v22==>:udb@[UDB=(2,4)]:pld0:input_permute.input_11" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(2,4)]:pld0:mc0.main_8" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_8" +end \SPIM:BSPIM:count_0\ net \SPIM:BSPIM:count_3\ term ":udb@[UDB=(2,4)]:count7cell.count_3" switch ":udb@[UDB=(2,4)]:count7cell.count_3==>:udb@[UDB=(2,4)]:controlcell_control_3_permute.in_1" switch ":udb@[UDB=(2,4)]:controlcell_control_3_permute.controlcell_control_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v110" switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v110" - switch ":udbswitch@[UDB=(2,4)][side=top]:110,91" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_91_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:48,91_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v48" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v48==>:udb@[UDB=(2,3)]:pld1:input_permute.input_7" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_1==>:udb@[UDB=(2,3)]:pld1:mc3.main_1" - term ":udb@[UDB=(2,3)]:pld1:mc3.main_1" - switch ":udbswitch@[UDB=(2,4)][side=top]:110,51" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_51_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:14,51_f" + switch ":udbswitch@[UDB=(2,4)][side=top]:110,23" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_23_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:48,23_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v48" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v48==>:udb@[UDB=(2,5)]:pld1:input_permute.input_7" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc3_main_1==>:udb@[UDB=(2,5)]:pld1:mc3.main_1" + term ":udb@[UDB=(2,5)]:pld1:mc3.main_1" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_23_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:16,23_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v16" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v16==>:udb@[UDB=(2,3)]:pld0:input_permute.input_8" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,3)]:pld0:mc0.main_1" + term ":udb@[UDB=(2,3)]:pld0:mc0.main_1" + switch ":udbswitch@[UDB=(2,5)][side=top]:48,19_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:14,19_f" switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v14" switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v14==>:udb@[UDB=(2,5)]:pld0:input_permute.input_7" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(2,5)]:pld0:mc0.main_1" - term ":udb@[UDB=(2,5)]:pld0:mc0.main_1" - switch ":udbswitch@[UDB=(2,3)][side=top]:0,91_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v0" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v0==>:udb@[UDB=(2,3)]:pld0:input_permute.input_0" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,3)]:pld0:mc0.main_4" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_4" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(2,3)]:pld0:mc1.main_4" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_4" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(2,3)]:pld1:mc0.main_4" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_4" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(2,3)]:pld1:mc2.main_1" - term ":udb@[UDB=(2,3)]:pld1:mc2.main_1" - switch ":udbswitch@[UDB=(2,4)][side=top]:54,51_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v54" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v54==>:udb@[UDB=(2,4)]:pld1:input_permute.input_4" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,5)]:pld0:mc0.main_4" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_4" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(2,5)]:pld0:mc1.main_4" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_4" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(2,5)]:pld1:mc0.main_4" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_4" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(2,5)]:pld1:mc2.main_1" + term ":udb@[UDB=(2,5)]:pld1:mc2.main_1" + switch ":udbswitch@[UDB=(2,4)][side=top]:16,23_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v16" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v16==>:udb@[UDB=(2,4)]:pld0:input_permute.input_8" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(2,4)]:pld0:mc0.main_5" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_5" + switch ":udbswitch@[UDB=(2,4)][side=top]:48,23_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v48" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v48==>:udb@[UDB=(2,4)]:pld1:input_permute.input_7" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(2,4)]:pld1:mc0.main_4" term ":udb@[UDB=(2,4)]:pld1:mc0.main_4" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_4==>:udb@[UDB=(2,4)]:pld1:mc1.main_4" term ":udb@[UDB=(2,4)]:pld1:mc1.main_4" - switch ":udbswitch@[UDB=(2,4)][side=top]:14,51_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v14" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v14==>:udb@[UDB=(2,4)]:pld0:input_permute.input_7" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(2,4)]:pld0:mc0.main_5" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_5" end \SPIM:BSPIM:count_3\ net \SPIM:BSPIM:count_4\ term ":udb@[UDB=(2,4)]:count7cell.count_4" @@ -319,37 +370,37 @@ net \SPIM:BSPIM:count_4\ switch ":udb@[UDB=(2,4)]:controlcell_control_4_permute.controlcell_control_4==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v112" switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v112" switch ":udbswitch@[UDB=(2,4)][side=top]:112,52" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_52_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:46,52_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v46" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v46==>:udb@[UDB=(2,3)]:pld1:input_permute.input_8" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(2,3)]:pld1:mc3.main_0" - term ":udb@[UDB=(2,3)]:pld1:mc3.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:112,76" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_76_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:16,76_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v16" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v16==>:udb@[UDB=(2,5)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,5)]:pld0:mc0.main_0" - term ":udb@[UDB=(2,5)]:pld0:mc0.main_0" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_76_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:16,76_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v16" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v16==>:udb@[UDB=(2,3)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,3)]:pld0:mc0.main_3" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_3" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(2,3)]:pld0:mc1.main_3" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_3" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(2,3)]:pld1:mc0.main_3" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_3" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(2,3)]:pld1:mc2.main_0" - term ":udb@[UDB=(2,3)]:pld1:mc2.main_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:16,76_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v16" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v16==>:udb@[UDB=(2,4)]:pld0:input_permute.input_8" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_52_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:46,52_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v46" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v46==>:udb@[UDB=(2,5)]:pld1:input_permute.input_8" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(2,5)]:pld1:mc3.main_0" + term ":udb@[UDB=(2,5)]:pld1:mc3.main_0" + switch ":udbswitch@[UDB=(2,4)][side=top]:46,52_f" + switch ":udbswitch@[UDB=(2,4)][side=top]:46,28_b" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_28_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:0,28_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v0" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v0==>:udb@[UDB=(2,3)]:pld0:input_permute.input_0" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,3)]:pld0:mc0.main_0" + term ":udb@[UDB=(2,3)]:pld0:mc0.main_0" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_28_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:0,28_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v0" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v0==>:udb@[UDB=(2,5)]:pld0:input_permute.input_0" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,5)]:pld0:mc0.main_3" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_3" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(2,5)]:pld0:mc1.main_3" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_3" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(2,5)]:pld1:mc0.main_3" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_3" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(2,5)]:pld1:mc2.main_0" + term ":udb@[UDB=(2,5)]:pld1:mc2.main_0" + switch ":udbswitch@[UDB=(2,4)][side=top]:0,28_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v0" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v0==>:udb@[UDB=(2,4)]:pld0:input_permute.input_0" switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,4)]:pld0:mc0.main_4" term ":udb@[UDB=(2,4)]:pld0:mc0.main_4" - switch ":udbswitch@[UDB=(2,4)][side=top]:46,52_f" switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v46" switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v46==>:udb@[UDB=(2,4)]:pld1:input_permute.input_8" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(2,4)]:pld1:mc0.main_3" @@ -357,535 +408,659 @@ net \SPIM:BSPIM:count_4\ switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(2,4)]:pld1:mc1.main_3" term ":udb@[UDB=(2,4)]:pld1:mc1.main_3" end \SPIM:BSPIM:count_4\ -net \SPIM:BSPIM:count_0\ - term ":udb@[UDB=(2,4)]:count7cell.count_0" - switch ":udb@[UDB=(2,4)]:count7cell.count_0==>:udb@[UDB=(2,4)]:controlcell_control_0_permute.in_1" - switch ":udb@[UDB=(2,4)]:controlcell_control_0_permute.controlcell_control_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v104" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v104" - switch ":udbswitch@[UDB=(2,4)][side=top]:104,42" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_42_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:56,42_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v56" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v56==>:udb@[UDB=(2,3)]:pld1:input_permute.input_3" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_4==>:udb@[UDB=(2,3)]:pld1:mc3.main_4" - term ":udb@[UDB=(2,3)]:pld1:mc3.main_4" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_42_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:6,42_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v6" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v6==>:udb@[UDB=(2,5)]:pld0:input_permute.input_3" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(2,5)]:pld0:mc0.main_4" - term ":udb@[UDB=(2,5)]:pld0:mc0.main_4" - switch ":udbswitch@[UDB=(2,3)][side=top]:22,42_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v22" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v22==>:udb@[UDB=(2,3)]:pld0:input_permute.input_11" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(2,3)]:pld0:mc0.main_7" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_7" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_7==>:udb@[UDB=(2,3)]:pld0:mc1.main_7" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_7" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(2,3)]:pld1:mc0.main_7" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_7" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc2_main_4==>:udb@[UDB=(2,3)]:pld1:mc2.main_4" - term ":udb@[UDB=(2,3)]:pld1:mc2.main_4" - switch ":udbswitch@[UDB=(2,4)][side=top]:22,42_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v22" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v22==>:udb@[UDB=(2,4)]:pld0:input_permute.input_11" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(2,4)]:pld0:mc0.main_8" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_8" - switch ":udbswitch@[UDB=(2,4)][side=top]:56,42_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v56" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v56==>:udb@[UDB=(2,4)]:pld1:input_permute.input_3" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(2,4)]:pld1:mc0.main_7" - term ":udb@[UDB=(2,4)]:pld1:mc0.main_7" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_7==>:udb@[UDB=(2,4)]:pld1:mc1.main_7" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_7" -end \SPIM:BSPIM:count_0\ -net \SPIM:BSPIM:count_2\ - term ":udb@[UDB=(2,4)]:count7cell.count_2" - switch ":udb@[UDB=(2,4)]:count7cell.count_2==>:udb@[UDB=(2,4)]:controlcell_control_2_permute.in_1" - switch ":udb@[UDB=(2,4)]:controlcell_control_2_permute.controlcell_control_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v108" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v108" - switch ":udbswitch@[UDB=(2,4)][side=top]:108,30" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_30_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:60,30_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v60" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v60==>:udb@[UDB=(2,3)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_2==>:udb@[UDB=(2,3)]:pld1:mc3.main_2" - term ":udb@[UDB=(2,3)]:pld1:mc3.main_2" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_30_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:18,30_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v18" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v18==>:udb@[UDB=(2,5)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,5)]:pld0:mc0.main_2" - term ":udb@[UDB=(2,5)]:pld0:mc0.main_2" - switch ":udbswitch@[UDB=(2,3)][side=top]:2,30_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v2" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v2==>:udb@[UDB=(2,3)]:pld0:input_permute.input_1" +net \SPIM:BSPIM:count_1\ + term ":udb@[UDB=(2,4)]:count7cell.count_1" + switch ":udb@[UDB=(2,4)]:count7cell.count_1==>:udb@[UDB=(2,4)]:controlcell_control_1_permute.in_1" + switch ":udb@[UDB=(2,4)]:controlcell_control_1_permute.controlcell_control_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v106" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v106" + switch ":udbswitch@[UDB=(2,4)][side=top]:106,8" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_8_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:2,8_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v2" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v2==>:udb@[UDB=(2,5)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(2,5)]:pld0:mc0.main_6" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_6" + switch ":udbswitch@[UDB=(2,4)][side=top]:106,11" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_11_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:52,11_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v52" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v52==>:udb@[UDB=(2,5)]:pld1:input_permute.input_5" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc3_main_3==>:udb@[UDB=(2,5)]:pld1:mc3.main_3" + term ":udb@[UDB=(2,5)]:pld1:mc3.main_3" + switch ":udbswitch@[UDB=(2,4)][side=top]:106,36" + switch ":udbswitch@[UDB=(2,4)][side=top]:58,36_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v58" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v58==>:udb@[UDB=(2,4)]:pld1:input_permute.input_2" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(2,4)]:pld1:mc0.main_6" + term ":udb@[UDB=(2,4)]:pld1:mc0.main_6" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(2,5)]:pld1:mc0.main_6" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_6" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc2_main_3==>:udb@[UDB=(2,5)]:pld1:mc2.main_3" + term ":udb@[UDB=(2,5)]:pld1:mc2.main_3" + switch ":udbswitch@[UDB=(2,4)][side=top]:20,11_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v20" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v20==>:udb@[UDB=(2,4)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(2,4)]:pld0:mc0.main_7" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_7" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_11_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:20,11_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v20" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v20==>:udb@[UDB=(2,3)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,3)]:pld0:mc0.main_3" + term ":udb@[UDB=(2,3)]:pld0:mc0.main_3" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_6==>:udb@[UDB=(2,5)]:pld0:mc1.main_6" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_6" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_6==>:udb@[UDB=(2,4)]:pld1:mc1.main_6" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_6" +end \SPIM:BSPIM:count_1\ +net \SPIM:BSPIM:rx_status_4\ + term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_blk_stat_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_blk_stat_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.f1_blk_stat_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v78" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v78" + switch ":udbswitch@[UDB=(2,4)][side=top]:78,75" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_75_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:14,75_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v14" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v14==>:udb@[UDB=(2,3)]:pld0:input_permute.input_7" switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(2,3)]:pld0:mc0.main_5" term ":udb@[UDB=(2,3)]:pld0:mc0.main_5" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_5==>:udb@[UDB=(2,3)]:pld0:mc1.main_5" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_5" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(2,3)]:pld1:mc0.main_5" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_5" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(2,3)]:pld1:mc2.main_2" - term ":udb@[UDB=(2,3)]:pld1:mc2.main_2" - switch ":udbswitch@[UDB=(2,4)][side=top]:18,30_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v18" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v18==>:udb@[UDB=(2,4)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(2,4)]:pld0:mc0.main_6" - term ":udb@[UDB=(2,4)]:pld0:mc0.main_6" - switch ":udbswitch@[UDB=(2,4)][side=top]:60,30_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v60" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v60==>:udb@[UDB=(2,4)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(2,4)]:pld1:mc0.main_5" - term ":udb@[UDB=(2,4)]:pld1:mc0.main_5" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_5==>:udb@[UDB=(2,4)]:pld1:mc1.main_5" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_5" -end \SPIM:BSPIM:count_2\ + switch ":udbswitch@[UDB=(2,4)][side=top]:97,75_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v97" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v97==>:udb@[UDB=(3,4)]:statusicell.status_4" + term ":udb@[UDB=(3,4)]:statusicell.status_4" +end \SPIM:BSPIM:rx_status_4\ +net \SPIM:BSPIM:rx_status_6\ + term ":udb@[UDB=(2,3)]:pld0:mc0.q" + switch ":udb@[UDB=(2,3)]:pld0:mc0.q==>:udb@[UDB=(2,3)]:pld0:output_permute1.q_0" + switch ":udb@[UDB=(2,3)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v26" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v26" + switch ":udbswitch@[UDB=(2,3)][side=top]:26,34" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_34_f" + switch ":udbswitch@[UDB=(2,4)][side=top]:101,34_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v101" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v101==>:udb@[UDB=(3,4)]:statusicell.status_6" + term ":udb@[UDB=(3,4)]:statusicell.status_6" +end \SPIM:BSPIM:rx_status_6\ +net \SPIM:BSPIM:state_2\ + term ":udb@[UDB=(2,4)]:pld1:mc1.q" + switch ":udb@[UDB=(2,4)]:pld1:mc1.q==>:udb@[UDB=(2,4)]:pld1:output_permute2.q_1" + switch ":udb@[UDB=(2,4)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v34" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v34" + switch ":udbswitch@[UDB=(2,4)][side=top]:34,41" + switch ":udbswitch@[UDB=(2,4)][side=top]:50,41_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v50" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v50==>:udb@[UDB=(2,4)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(2,4)]:pld1:mc2.main_0" + term ":udb@[UDB=(2,4)]:pld1:mc2.main_0" + switch ":udbswitch@[UDB=(2,4)][side=top]:66,41_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v66" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v66==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_1" + switch ":udb@[UDB=(2,4)]:dp_wrapper:input_permute.cs_addr_2==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_2" + term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_2" + switch ":udbswitch@[UDB=(2,4)][side=top]:66,10_b" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_10_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:42,10_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v42" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v42==>:udb@[UDB=(2,5)]:pld1:input_permute.input_10" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(2,5)]:pld1:mc1.main_0" + term ":udb@[UDB=(2,5)]:pld1:mc1.main_0" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,5)]:pld1:mc0.main_0" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_0" + switch ":udbswitch@[UDB=(2,5)][side=top]:10,10_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v10" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v10==>:udb@[UDB=(2,5)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,5)]:pld0:mc0.main_0" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_0" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(2,5)]:pld0:mc1.main_0" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_0" + switch ":hvswitch@[UDB=(2,4)][side=left]:8,10_f" + switch ":hvswitch@[UDB=(2,4)][side=left]:8,19_b" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_19_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:47,19_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v47" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v47==>:udb@[UDB=(3,3)]:pld1:input_permute.input_8" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(3,3)]:pld1:mc0.main_0" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_0" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,4)]:pld1:mc0.main_0" + term ":udb@[UDB=(2,4)]:pld1:mc0.main_0" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(2,4)]:pld1:mc3.main_0" + term ":udb@[UDB=(2,4)]:pld1:mc3.main_0" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(2,4)]:pld1:mc1.main_0" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_0" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_41_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:13,41_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v13" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v13==>:udb@[UDB=(3,5)]:pld0:input_permute.input_6" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(3,5)]:pld0:mc1.main_0" + term ":udb@[UDB=(3,5)]:pld0:mc1.main_0" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(3,5)]:pld0:mc0.main_1" + term ":udb@[UDB=(3,5)]:pld0:mc0.main_1" + switch ":udbswitch@[UDB=(2,4)][side=top]:14,19_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v14" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v14==>:udb@[UDB=(2,4)]:pld0:input_permute.input_7" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(2,4)]:pld0:mc0.main_0" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_0" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(2,5)]:pld0:mc2.main_0" + term ":udb@[UDB=(2,5)]:pld0:mc2.main_0" +end \SPIM:BSPIM:state_2\ +net \SPIM:BSPIM:mosi_from_dp\ + term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.so_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.so_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.so_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_4==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v84" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v84" + switch ":udbswitch@[UDB=(2,4)][side=top]:84,59" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_59_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:53,59_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v53" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v53==>:udb@[UDB=(3,3)]:pld1:input_permute.input_5" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(3,3)]:pld1:mc0.main_3" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_3" + switch ":udbswitch@[UDB=(2,4)][side=top]:84,81" + switch ":udbswitch@[UDB=(2,4)][side=top]:12,81_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v12" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v12==>:udb@[UDB=(2,4)]:pld0:input_permute.input_6" + switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(2,4)]:pld0:mc0.main_3" + term ":udb@[UDB=(2,4)]:pld0:mc0.main_3" + switch ":udbswitch@[UDB=(2,4)][side=top]:84,55" + switch ":udbswitch@[UDB=(2,4)][side=top]:21,55_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v21" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v21==>:udb@[UDB=(3,4)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(3,4)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,4)]:pld0:mc0.main_0" + term ":udb@[UDB=(3,4)]:pld0:mc0.main_0" +end \SPIM:BSPIM:mosi_from_dp\ +net \SPIM:BSPIM:tx_status_1\ + term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f0_blk_stat_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.f0_blk_stat_comb" + switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v80" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v80" + switch ":udbswitch@[UDB=(2,4)][side=top]:80,67" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_67_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:16,67_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v16" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v16==>:udb@[UDB=(2,5)]:pld0:input_permute.input_8" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_8==>:udb@[UDB=(2,5)]:pld0:mc1.main_8" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_8" + switch ":udbswitch@[UDB=(2,4)][side=top]:40,67_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v40" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v40==>:udb@[UDB=(2,4)]:pld1:input_permute.input_11" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(2,4)]:pld1:mc0.main_8" + term ":udb@[UDB=(2,4)]:pld1:mc0.main_8" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_3==>:udb@[UDB=(2,4)]:pld1:mc3.main_3" + term ":udb@[UDB=(2,4)]:pld1:mc3.main_3" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_8==>:udb@[UDB=(2,4)]:pld1:mc1.main_8" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_8" + switch ":udbswitch@[UDB=(2,5)][side=top]:16,26_b" + switch ":hvswitch@[UDB=(2,4)][side=left]:20,26_f" + switch ":hvswitch@[UDB=(2,4)][side=left]:20,40_b" + switch ":udbswitch@[UDB=(2,5)][side=top]:90,40_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v90" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v90==>:udb@[UDB=(2,5)]:statusicell.status_1" + term ":udb@[UDB=(2,5)]:statusicell.status_1" +end \SPIM:BSPIM:tx_status_1\ net \SPIM:BSPIM:state_0\ term ":udb@[UDB=(2,4)]:pld1:mc3.q" switch ":udb@[UDB=(2,4)]:pld1:mc3.q==>:udb@[UDB=(2,4)]:pld1:output_permute1.q_3" switch ":udb@[UDB=(2,4)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v36" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v36" - switch ":udbswitch@[UDB=(2,4)][side=top]:36,57" - switch ":udbswitch@[UDB=(2,4)][side=top]:52,57_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v52" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v52==>:udb@[UDB=(2,4)]:pld1:input_permute.input_5" - switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(2,4)]:pld1:mc2.main_2" - term ":udb@[UDB=(2,4)]:pld1:mc2.main_2" - switch ":udbswitch@[UDB=(2,4)][side=top]:36,12" - switch ":udbswitch@[UDB=(2,4)][side=top]:68,12_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v68" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v68==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_2" - switch ":udb@[UDB=(2,4)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_0" - term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_0" - switch ":udbswitch@[UDB=(2,4)][side=top]:36,88" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_88_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:3,88_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v3" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v3==>:udb@[UDB=(3,3)]:pld0:input_permute.input_1" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(3,3)]:pld0:mc0.main_2" - term ":udb@[UDB=(3,3)]:pld0:mc0.main_2" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(3,3)]:pld0:mc1.main_2" - term ":udb@[UDB=(3,3)]:pld0:mc1.main_2" - switch ":udbswitch@[UDB=(2,3)][side=top]:20,88_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v20" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v20==>:udb@[UDB=(2,3)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,3)]:pld0:mc0.main_2" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_2" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(2,3)]:pld0:mc1.main_2" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_2" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v36" + switch ":udbswitch@[UDB=(2,4)][side=top]:36,35" + switch ":udbswitch@[UDB=(2,4)][side=top]:52,35_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v52" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v52==>:udb@[UDB=(2,4)]:pld1:input_permute.input_5" + switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(2,4)]:pld1:mc2.main_2" + term ":udb@[UDB=(2,4)]:pld1:mc2.main_2" switch ":udbswitch@[UDB=(2,4)][side=top]:36,84" + switch ":udbswitch@[UDB=(2,4)][side=top]:74,84_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v74" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v74==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_5" + switch ":udb@[UDB=(2,4)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_0" + term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.cs_addr_0" + switch ":udbswitch@[UDB=(2,4)][side=top]:74,37_b" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_37_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:5,37_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v5" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v5==>:udb@[UDB=(3,5)]:pld0:input_permute.input_2" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(3,5)]:pld0:mc1.main_2" + term ":udb@[UDB=(3,5)]:pld0:mc1.main_2" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(3,5)]:pld0:mc0.main_3" + term ":udb@[UDB=(3,5)]:pld0:mc0.main_3" + switch ":udbswitch@[UDB=(2,4)][side=top]:52,83_b" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_83_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:43,83_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v43" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v43==>:udb@[UDB=(3,3)]:pld1:input_permute.input_10" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(3,3)]:pld1:mc0.main_2" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_2" switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_84_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:59,84_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v59" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v59==>:udb@[UDB=(3,5)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(3,5)]:pld1:mc0.main_2" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_2" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_84_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:58,84_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v58" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v58==>:udb@[UDB=(2,3)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(2,3)]:pld1:mc1.main_3" - term ":udb@[UDB=(2,3)]:pld1:mc1.main_3" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(2,3)]:pld1:mc0.main_2" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_2" + switch ":udbswitch@[UDB=(2,5)][side=top]:20,84_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v20" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v20==>:udb@[UDB=(2,5)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,5)]:pld0:mc0.main_2" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_2" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(2,5)]:pld0:mc1.main_2" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_2" + switch ":udbswitch@[UDB=(2,5)][side=top]:58,84_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v58" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v58==>:udb@[UDB=(2,5)]:pld1:input_permute.input_2" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(2,5)]:pld1:mc1.main_2" + term ":udb@[UDB=(2,5)]:pld1:mc1.main_2" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(2,5)]:pld1:mc0.main_2" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_2" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(2,4)]:pld1:mc0.main_2" term ":udb@[UDB=(2,4)]:pld1:mc0.main_2" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc3_main_2==>:udb@[UDB=(2,4)]:pld1:mc3.main_2" term ":udb@[UDB=(2,4)]:pld1:mc3.main_2" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(2,4)]:pld1:mc1.main_2" term ":udb@[UDB=(2,4)]:pld1:mc1.main_2" - switch ":udbswitch@[UDB=(2,4)][side=top]:12,57_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v12" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v12==>:udb@[UDB=(2,4)]:pld0:input_permute.input_6" + switch ":udbswitch@[UDB=(2,4)][side=top]:10,35_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v10" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v10==>:udb@[UDB=(2,4)]:pld0:input_permute.input_5" switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(2,4)]:pld0:mc0.main_2" term ":udb@[UDB=(2,4)]:pld0:mc0.main_2" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc2_main_2==>:udb@[UDB=(2,3)]:pld0:mc2.main_2" - term ":udb@[UDB=(2,3)]:pld0:mc2.main_2" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_2==>:udb@[UDB=(2,5)]:pld0:mc2.main_2" + term ":udb@[UDB=(2,5)]:pld0:mc2.main_2" end \SPIM:BSPIM:state_0\ -net \UART_1:BUART:tx_state_0\ - term ":udb@[UDB=(2,5)]:pld0:mc1.q" - switch ":udb@[UDB=(2,5)]:pld0:mc1.q==>:udb@[UDB=(2,5)]:pld0:output_permute0.q_1" - switch ":udb@[UDB=(2,5)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v24" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v24" - switch ":udbswitch@[UDB=(2,5)][side=top]:24,66" - switch ":udbswitch@[UDB=(2,5)][side=top]:57,66_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v57" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v57==>:udb@[UDB=(3,5)]:pld1:input_permute.input_3" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(3,5)]:pld1:mc1.main_1" - term ":udb@[UDB=(3,5)]:pld1:mc1.main_1" - switch ":udbswitch@[UDB=(2,5)][side=top]:8,66_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v8" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v8==>:udb@[UDB=(2,5)]:pld0:input_permute.input_4" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc3_main_1==>:udb@[UDB=(2,5)]:pld0:mc3.main_1" - term ":udb@[UDB=(2,5)]:pld0:mc3.main_1" - switch ":udbswitch@[UDB=(2,5)][side=top]:57,70_b" - switch ":udbswitch@[UDB=(2,5)][side=top]:71,70_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v71" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v71==>:udb@[UDB=(3,5)]:dp_wrapper:input_permute.ina_3" - switch ":udb@[UDB=(3,5)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_1" - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_1" - switch ":udbswitch@[UDB=(2,5)][side=top]:1,70_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v1" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v1==>:udb@[UDB=(3,5)]:pld0:input_permute.input_0" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(3,5)]:pld0:mc1.main_1" - term ":udb@[UDB=(3,5)]:pld0:mc1.main_1" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(3,5)]:pld0:mc0.main_2" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_2" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(2,5)]:pld0:mc1.main_1" - term ":udb@[UDB=(2,5)]:pld0:mc1.main_1" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(2,5)]:pld0:mc2.main_1" - term ":udb@[UDB=(2,5)]:pld0:mc2.main_1" -end \UART_1:BUART:tx_state_0\ -net \UART_1:BUART:counter_load_not\ - term ":udb@[UDB=(3,5)]:pld1:mc1.q" - switch ":udb@[UDB=(3,5)]:pld1:mc1.q==>:udb@[UDB=(3,5)]:pld1:output_permute3.q_1" - switch ":udb@[UDB=(3,5)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v33" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v33" - switch ":udbswitch@[UDB=(2,5)][side=top]:33,73" - switch ":udbswitch@[UDB=(2,5)][side=top]:70,73_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v70" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v70==>:udb@[UDB=(2,5)]:dp_wrapper:input_permute.ina_3" - switch ":udb@[UDB=(2,5)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(2,5)]:dp_wrapper:datapath.cs_addr_0" - term ":udb@[UDB=(2,5)]:dp_wrapper:datapath.cs_addr_0" -end \UART_1:BUART:counter_load_not\ -net \SPIM:BSPIM:load_cond\ - term ":udb@[UDB=(2,3)]:pld1:mc0.q" - switch ":udb@[UDB=(2,3)]:pld1:mc0.q==>:udb@[UDB=(2,3)]:pld1:output_permute1.q_0" - switch ":udb@[UDB=(2,3)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v36" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v36" - switch ":udbswitch@[UDB=(2,3)][side=top]:36,33" - switch ":hvswitch@[UDB=(2,2)][side=left]:19,33_f" - switch ":hvswitch@[UDB=(2,2)][side=left]:19,46_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:40,46_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v40" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v40==>:udb@[UDB=(2,3)]:pld1:input_permute.input_11" - switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(2,3)]:pld1:mc0.main_8" - term ":udb@[UDB=(2,3)]:pld1:mc0.main_8" -end \SPIM:BSPIM:load_cond\ net \UART_1:BUART:tx_state_1\ - term ":udb@[UDB=(2,5)]:pld0:mc2.q" - switch ":udb@[UDB=(2,5)]:pld0:mc2.q==>:udb@[UDB=(2,5)]:pld0:output_permute2.q_2" - switch ":udb@[UDB=(2,5)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v28" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v28" - switch ":udbswitch@[UDB=(2,5)][side=top]:28,89" - switch ":udbswitch@[UDB=(2,5)][side=top]:45,89_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v45" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v45==>:udb@[UDB=(3,5)]:pld1:input_permute.input_9" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(3,5)]:pld1:mc1.main_0" - term ":udb@[UDB=(3,5)]:pld1:mc1.main_0" - switch ":udbswitch@[UDB=(2,5)][side=top]:28,54" - switch ":udbswitch@[UDB=(2,5)][side=top]:12,54_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v12" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v12==>:udb@[UDB=(2,5)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(2,5)]:pld0:mc3.main_0" - term ":udb@[UDB=(2,5)]:pld0:mc3.main_0" - switch ":udbswitch@[UDB=(2,5)][side=top]:28,57" - switch ":udbswitch@[UDB=(2,5)][side=top]:75,57_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v75" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v75==>:udb@[UDB=(3,5)]:dp_wrapper:input_permute.ina_5" - switch ":udb@[UDB=(3,5)]:dp_wrapper:input_permute.cs_addr_2==>:udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_2" - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_2" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(2,5)]:pld0:mc1.main_0" - term ":udb@[UDB=(2,5)]:pld0:mc1.main_0" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(2,5)]:pld0:mc2.main_0" - term ":udb@[UDB=(2,5)]:pld0:mc2.main_0" - switch ":udbswitch@[UDB=(2,5)][side=top]:28,37" - switch ":udbswitch@[UDB=(2,5)][side=top]:5,37_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v5" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v5==>:udb@[UDB=(3,5)]:pld0:input_permute.input_2" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(3,5)]:pld0:mc1.main_0" - term ":udb@[UDB=(3,5)]:pld0:mc1.main_0" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(3,5)]:pld0:mc0.main_1" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_1" + term ":udb@[UDB=(3,0)]:pld1:mc0.q" + switch ":udb@[UDB=(3,0)]:pld1:mc0.q==>:udb@[UDB=(3,0)]:pld1:output_permute3.q_0" + switch ":udb@[UDB=(3,0)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v33" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v33" + switch ":udbswitch@[UDB=(2,0)][side=top]:33,73" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_73_f" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_73_f" + switch ":hvswitch@[UDB=(2,2)][side=left]:hseg_73_f" + switch ":udbswitch@[UDB=(2,3)][side=top]:55,73_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v55" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v55==>:udb@[UDB=(3,3)]:pld1:input_permute.input_4" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(3,3)]:pld1:mc1.main_0" + term ":udb@[UDB=(3,3)]:pld1:mc1.main_0" + switch ":udbswitch@[UDB=(2,3)][side=top]:6,73_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v6" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v6==>:udb@[UDB=(2,3)]:pld0:input_permute.input_3" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(2,3)]:pld0:mc3.main_0" + term ":udb@[UDB=(2,3)]:pld0:mc3.main_0" + switch ":udbswitch@[UDB=(2,3)][side=top]:70,73_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v70" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v70==>:udb@[UDB=(2,3)]:dp_wrapper:input_permute.ina_3" + switch ":udb@[UDB=(2,3)]:dp_wrapper:input_permute.cs_addr_2==>:udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_2" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_2" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(2,3)]:pld0:mc1.main_0" + term ":udb@[UDB=(2,3)]:pld0:mc1.main_0" + switch ":udbswitch@[UDB=(2,3)][side=top]:7,73_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v7" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v7==>:udb@[UDB=(3,3)]:pld0:input_permute.input_3" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(3,3)]:pld0:mc1.main_0" + term ":udb@[UDB=(3,3)]:pld0:mc1.main_0" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(3,3)]:pld0:mc0.main_1" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_1" + switch ":udbswitch@[UDB=(2,0)][side=top]:55,73_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v55" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v55==>:udb@[UDB=(3,0)]:pld1:input_permute.input_4" + switch ":udb@[UDB=(3,0)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(3,0)]:pld1:mc0.main_0" + term ":udb@[UDB=(3,0)]:pld1:mc0.main_0" end \UART_1:BUART:tx_state_1\ +net \UART_1:BUART:counter_load_not\ + term ":udb@[UDB=(3,3)]:pld1:mc1.q" + switch ":udb@[UDB=(3,3)]:pld1:mc1.q==>:udb@[UDB=(3,3)]:pld1:output_permute1.q_1" + switch ":udb@[UDB=(3,3)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v37" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v37" + switch ":udbswitch@[UDB=(2,3)][side=top]:37,88" + switch ":udbswitch@[UDB=(2,3)][side=top]:67,88_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v67" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v67==>:udb@[UDB=(3,3)]:dp_wrapper:input_permute.ina_1" + switch ":udb@[UDB=(3,3)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(3,3)]:dp_wrapper:datapath.cs_addr_0" + term ":udb@[UDB=(3,3)]:dp_wrapper:datapath.cs_addr_0" +end \UART_1:BUART:counter_load_not\ +net \UART_1:BUART:tx_state_0\ + term ":udb@[UDB=(2,3)]:pld0:mc1.q" + switch ":udb@[UDB=(2,3)]:pld0:mc1.q==>:udb@[UDB=(2,3)]:pld0:output_permute0.q_1" + switch ":udb@[UDB=(2,3)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v24" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v24" + switch ":udbswitch@[UDB=(2,3)][side=top]:24,77" + switch ":udbswitch@[UDB=(2,3)][side=top]:41,77_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v41" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v41==>:udb@[UDB=(3,3)]:pld1:input_permute.input_11" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(3,3)]:pld1:mc1.main_1" + term ":udb@[UDB=(3,3)]:pld1:mc1.main_1" + switch ":udbswitch@[UDB=(2,3)][side=top]:41,5_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:72,5_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v72" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v72==>:udb@[UDB=(2,3)]:dp_wrapper:input_permute.ina_4" + switch ":udb@[UDB=(2,3)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_1" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_1" + switch ":udbswitch@[UDB=(2,3)][side=top]:24,66" + switch ":udbswitch@[UDB=(2,3)][side=top]:8,66_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v8" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v8==>:udb@[UDB=(2,3)]:pld0:input_permute.input_4" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc3_main_1==>:udb@[UDB=(2,3)]:pld0:mc3.main_1" + term ":udb@[UDB=(2,3)]:pld0:mc3.main_1" + switch ":hvswitch@[UDB=(2,2)][side=left]:hseg_77_b" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_77_b" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_77_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:41,77_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v41" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v41==>:udb@[UDB=(3,0)]:pld1:input_permute.input_11" + switch ":udb@[UDB=(3,0)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(3,0)]:pld1:mc0.main_1" + term ":udb@[UDB=(3,0)]:pld1:mc0.main_1" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(2,3)]:pld0:mc1.main_1" + term ":udb@[UDB=(2,3)]:pld0:mc1.main_1" + switch ":udbswitch@[UDB=(2,3)][side=top]:9,66_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v9" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v9==>:udb@[UDB=(3,3)]:pld0:input_permute.input_4" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(3,3)]:pld0:mc1.main_1" + term ":udb@[UDB=(3,3)]:pld0:mc1.main_1" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(3,3)]:pld0:mc0.main_2" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_2" +end \UART_1:BUART:tx_state_0\ net \UART_1:BUART:tx_bitclk\ - term ":udb@[UDB=(2,5)]:pld1:mc0.q" - switch ":udb@[UDB=(2,5)]:pld1:mc0.q==>:udb@[UDB=(2,5)]:pld1:output_permute1.q_0" - switch ":udb@[UDB=(2,5)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v36" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v36" - switch ":udbswitch@[UDB=(2,5)][side=top]:36,59" - switch ":udbswitch@[UDB=(2,5)][side=top]:53,59_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v53" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v53==>:udb@[UDB=(3,5)]:pld1:input_permute.input_5" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(3,5)]:pld1:mc1.main_3" - term ":udb@[UDB=(3,5)]:pld1:mc1.main_3" - switch ":udbswitch@[UDB=(2,5)][side=top]:20,59_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v20" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v20==>:udb@[UDB=(2,5)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc3_main_4==>:udb@[UDB=(2,5)]:pld0:mc3.main_4" - term ":udb@[UDB=(2,5)]:pld0:mc3.main_4" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(2,5)]:pld0:mc1.main_4" - term ":udb@[UDB=(2,5)]:pld0:mc1.main_4" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_3==>:udb@[UDB=(2,5)]:pld0:mc2.main_3" - term ":udb@[UDB=(2,5)]:pld0:mc2.main_3" - switch ":udbswitch@[UDB=(2,5)][side=top]:36,88" - switch ":udbswitch@[UDB=(2,5)][side=top]:21,88_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v21" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v21==>:udb@[UDB=(3,5)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(3,5)]:pld0:mc1.main_3" - term ":udb@[UDB=(3,5)]:pld0:mc1.main_3" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(3,5)]:pld0:mc0.main_5" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_5" + term ":udb@[UDB=(2,3)]:pld1:mc0.q" + switch ":udb@[UDB=(2,3)]:pld1:mc0.q==>:udb@[UDB=(2,3)]:pld1:output_permute2.q_0" + switch ":udb@[UDB=(2,3)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v34" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v34" + switch ":udbswitch@[UDB=(2,3)][side=top]:34,65" + switch ":udbswitch@[UDB=(2,3)][side=top]:51,65_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v51" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v51==>:udb@[UDB=(3,3)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(3,3)]:pld1:mc1.main_3" + term ":udb@[UDB=(3,3)]:pld1:mc1.main_3" + switch ":udbswitch@[UDB=(2,3)][side=top]:2,65_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v2" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v2==>:udb@[UDB=(2,3)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc3_main_4==>:udb@[UDB=(2,3)]:pld0:mc3.main_4" + term ":udb@[UDB=(2,3)]:pld0:mc3.main_4" + switch ":hvswitch@[UDB=(2,2)][side=left]:hseg_65_b" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_65_b" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_65_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:51,65_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v51" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v51==>:udb@[UDB=(3,0)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(3,0)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(3,0)]:pld1:mc0.main_3" + term ":udb@[UDB=(3,0)]:pld1:mc0.main_3" + switch ":udbswitch@[UDB=(2,3)][side=top]:34,82" + switch ":udbswitch@[UDB=(2,3)][side=top]:19,82_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v19" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v19==>:udb@[UDB=(3,3)]:pld0:input_permute.input_9" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(3,3)]:pld0:mc1.main_3" + term ":udb@[UDB=(3,3)]:pld0:mc1.main_3" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(3,3)]:pld0:mc0.main_5" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_5" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(2,3)]:pld0:mc1.main_4" + term ":udb@[UDB=(2,3)]:pld0:mc1.main_4" end \UART_1:BUART:tx_bitclk\ net \UART_1:BUART:tx_state_2\ - term ":udb@[UDB=(3,5)]:pld0:mc1.q" - switch ":udb@[UDB=(3,5)]:pld0:mc1.q==>:udb@[UDB=(3,5)]:pld0:output_permute1.q_1" - switch ":udb@[UDB=(3,5)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v27" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v27" - switch ":udbswitch@[UDB=(2,5)][side=top]:27,83" - switch ":udbswitch@[UDB=(2,5)][side=top]:43,83_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v43" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v43==>:udb@[UDB=(3,5)]:pld1:input_permute.input_10" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(3,5)]:pld1:mc1.main_2" - term ":udb@[UDB=(3,5)]:pld1:mc1.main_2" - switch ":udbswitch@[UDB=(2,5)][side=top]:4,83_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v4" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v4==>:udb@[UDB=(2,5)]:pld0:input_permute.input_2" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc3_main_3==>:udb@[UDB=(2,5)]:pld0:mc3.main_3" - term ":udb@[UDB=(2,5)]:pld0:mc3.main_3" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(2,5)]:pld0:mc1.main_3" - term ":udb@[UDB=(2,5)]:pld0:mc1.main_3" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_2==>:udb@[UDB=(2,5)]:pld0:mc2.main_2" - term ":udb@[UDB=(2,5)]:pld0:mc2.main_2" - switch ":udbswitch@[UDB=(2,5)][side=top]:27,62" - switch ":udbswitch@[UDB=(2,5)][side=top]:11,62_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v11" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v11==>:udb@[UDB=(3,5)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(3,5)]:pld0:mc1.main_2" - term ":udb@[UDB=(3,5)]:pld0:mc1.main_2" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(3,5)]:pld0:mc0.main_4" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_4" + term ":udb@[UDB=(3,3)]:pld0:mc1.q" + switch ":udb@[UDB=(3,3)]:pld0:mc1.q==>:udb@[UDB=(3,3)]:pld0:output_permute2.q_1" + switch ":udb@[UDB=(3,3)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v29" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v29" + switch ":udbswitch@[UDB=(2,3)][side=top]:29,87" + switch ":udbswitch@[UDB=(2,3)][side=top]:45,87_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v45" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v45==>:udb@[UDB=(3,3)]:pld1:input_permute.input_9" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(3,3)]:pld1:mc1.main_2" + term ":udb@[UDB=(3,3)]:pld1:mc1.main_2" + switch ":udbswitch@[UDB=(2,3)][side=top]:10,87_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v10" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v10==>:udb@[UDB=(2,3)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc3_main_3==>:udb@[UDB=(2,3)]:pld0:mc3.main_3" + term ":udb@[UDB=(2,3)]:pld0:mc3.main_3" + switch ":hvswitch@[UDB=(2,2)][side=left]:hseg_87_b" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_87_b" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_87_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:45,87_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v45" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v45==>:udb@[UDB=(3,0)]:pld1:input_permute.input_9" + switch ":udb@[UDB=(3,0)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(3,0)]:pld1:mc0.main_2" + term ":udb@[UDB=(3,0)]:pld1:mc0.main_2" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(2,3)]:pld0:mc1.main_3" + term ":udb@[UDB=(2,3)]:pld0:mc1.main_3" + switch ":udbswitch@[UDB=(2,3)][side=top]:29,6" + switch ":udbswitch@[UDB=(2,3)][side=top]:3,6_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v3" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v3==>:udb@[UDB=(3,3)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(3,3)]:pld0:mc1.main_2" + term ":udb@[UDB=(3,3)]:pld0:mc1.main_2" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(3,3)]:pld0:mc0.main_4" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_4" end \UART_1:BUART:tx_state_2\ -net \UART_1:BUART:tx_bitclk_dp\ - term ":udb@[UDB=(2,5)]:dp_wrapper:datapath.cl0_comb" - switch ":udb@[UDB=(2,5)]:dp_wrapper:datapath.cl0_comb==>:udb@[UDB=(2,5)]:dp_wrapper:output_permute.cl0_comb" - switch ":udb@[UDB=(2,5)]:dp_wrapper:output_permute.outs_4==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v84" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v84" - switch ":udbswitch@[UDB=(2,5)][side=top]:84,9" - switch ":udbswitch@[UDB=(2,5)][side=top]:60,9_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v60" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v60==>:udb@[UDB=(2,5)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(2,5)]:pld1:mc1.main_0" - term ":udb@[UDB=(2,5)]:pld1:mc1.main_0" - switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,5)]:pld1:mc0.main_0" - term ":udb@[UDB=(2,5)]:pld1:mc0.main_0" -end \UART_1:BUART:tx_bitclk_dp\ net \UART_1:BUART:tx_bitclk_enable_pre\ - term ":udb@[UDB=(2,5)]:pld1:mc1.q" - switch ":udb@[UDB=(2,5)]:pld1:mc1.q==>:udb@[UDB=(2,5)]:pld1:output_permute0.q_1" - switch ":udb@[UDB=(2,5)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v38" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v38" - switch ":udbswitch@[UDB=(2,5)][side=top]:38,90" - switch ":udbswitch@[UDB=(2,5)][side=top]:73,90_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v73" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v73==>:udb@[UDB=(3,5)]:dp_wrapper:input_permute.ina_4" - switch ":udb@[UDB=(3,5)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_0" - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.cs_addr_0" -end \UART_1:BUART:tx_bitclk_enable_pre\ -net Net_479 term ":udb@[UDB=(2,3)]:pld1:mc1.q" - switch ":udb@[UDB=(2,3)]:pld1:mc1.q==>:udb@[UDB=(2,3)]:pld1:output_permute2.q_1" - switch ":udb@[UDB=(2,3)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v34" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v34" - switch ":udbswitch@[UDB=(2,3)][side=top]:34,41" - switch ":udbswitch@[UDB=(2,3)][side=top]:50,41_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v50" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v50==>:udb@[UDB=(2,3)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(2,3)]:pld1:mc1.q==>:udb@[UDB=(2,3)]:pld1:output_permute3.q_1" + switch ":udb@[UDB=(2,3)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v32" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v32" + switch ":udbswitch@[UDB=(2,3)][side=top]:32,45" + switch ":udbswitch@[UDB=(2,3)][side=top]:64,45_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v64" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v64==>:udb@[UDB=(2,3)]:dp_wrapper:input_permute.ina_0" + switch ":udb@[UDB=(2,3)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_0" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.cs_addr_0" +end \UART_1:BUART:tx_bitclk_enable_pre\ +net \UART_1:BUART:tx_bitclk_dp\ + term ":udb@[UDB=(3,3)]:dp_wrapper:datapath.cl0_comb" + switch ":udb@[UDB=(3,3)]:dp_wrapper:datapath.cl0_comb==>:udb@[UDB=(3,3)]:dp_wrapper:output_permute.cl0_comb" + switch ":udb@[UDB=(3,3)]:dp_wrapper:output_permute.outs_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v83" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v83" + switch ":udbswitch@[UDB=(2,3)][side=top]:83,61" + switch ":udbswitch@[UDB=(2,3)][side=top]:58,61_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v58" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v58==>:udb@[UDB=(2,3)]:pld1:input_permute.input_2" + switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(2,3)]:pld1:mc0.main_0" + term ":udb@[UDB=(2,3)]:pld1:mc0.main_0" switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(2,3)]:pld1:mc1.main_0" term ":udb@[UDB=(2,3)]:pld1:mc1.main_0" - switch ":hvswitch@[UDB=(2,2)][side=left]:28,41_f" - switch ":hvswitch@[UDB=(1,2)][side=left]:vseg_28_bot_f" - switch ":hvswitch@[UDB=(0,2)][side=left]:vseg_28_bot_f" - switch ":hvswitch@[UDB=(0,2)][side=left]:28,7_b" - switch ":hvswitch@[UDB=(0,3)][side=left]:hseg_7_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:hseg_7_f" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:99,7_f" +end \UART_1:BUART:tx_bitclk_dp\ +net Net_479 + term ":udb@[UDB=(3,5)]:pld0:mc0.q" + switch ":udb@[UDB=(3,5)]:pld0:mc0.q==>:udb@[UDB=(3,5)]:pld0:output_permute2.q_0" + switch ":udb@[UDB=(3,5)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v29" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v29" + switch ":udbswitch@[UDB=(2,5)][side=top]:29,6" + switch ":udbswitch@[UDB=(2,5)][side=top]:3,6_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v3" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v3==>:udb@[UDB=(3,5)]:pld0:input_permute.input_1" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,5)]:pld0:mc0.main_0" + term ":udb@[UDB=(3,5)]:pld0:mc0.main_0" + switch ":hvswitch@[UDB=(2,5)][side=left]:2,6_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:vseg_2_top_b" + switch ":hvswitch@[UDB=(1,5)][side=left]:vseg_2_top_b" + switch ":hvswitch@[UDB=(0,5)][side=left]:2,25_b" + switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:103,25_f" switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v101+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v103+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v99" switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v101+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v103+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v99==>:ioport0:inputs2_mux.in_3" switch ":ioport0:inputs2_mux.pin6__pin_input==>:ioport0:pin6.pin_input" term ":ioport0:pin6.pin_input" end Net_479 +net \SPIM:BSPIM:cnt_enable\ + term ":udb@[UDB=(2,5)]:pld0:mc0.q" + switch ":udb@[UDB=(2,5)]:pld0:mc0.q==>:udb@[UDB=(2,5)]:pld0:output_permute0.q_0" + switch ":udb@[UDB=(2,5)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v24" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v24" + switch ":udbswitch@[UDB=(2,5)][side=top]:24,74" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_74_b" + switch ":udbswitch@[UDB=(2,4)][side=top]:96,74_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v96" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v96==>:udb@[UDB=(2,4)]:c7_en_mux.in_0" + switch ":udb@[UDB=(2,4)]:c7_en_mux.c7_en==>:udb@[UDB=(2,4)]:count7cell.enable" + term ":udb@[UDB=(2,4)]:count7cell.enable" + switch ":udbswitch@[UDB=(2,5)][side=top]:24,66" + switch ":udbswitch@[UDB=(2,5)][side=top]:8,66_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v8" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v8==>:udb@[UDB=(2,5)]:pld0:input_permute.input_4" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_9==>:udb@[UDB=(2,5)]:pld0:mc0.main_9" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_9" +end \SPIM:BSPIM:cnt_enable\ net \SPIM:BSPIM:ld_ident\ - term ":udb@[UDB=(3,3)]:pld0:mc1.q" - switch ":udb@[UDB=(3,3)]:pld0:mc1.q==>:udb@[UDB=(3,3)]:pld0:output_permute2.q_1" - switch ":udb@[UDB=(3,3)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v29" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v29" - switch ":udbswitch@[UDB=(2,3)][side=top]:29,87" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_87_f" - switch ":udbswitch@[UDB=(2,4)][side=top]:10,87_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v10" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v10==>:udb@[UDB=(2,4)]:pld0:input_permute.input_5" + term ":udb@[UDB=(2,5)]:pld1:mc1.q" + switch ":udb@[UDB=(2,5)]:pld1:mc1.q==>:udb@[UDB=(2,5)]:pld1:output_permute2.q_1" + switch ":udb@[UDB=(2,5)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v34" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v34" + switch ":udbswitch@[UDB=(2,5)][side=top]:34,65" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_65_b" + switch ":udbswitch@[UDB=(2,4)][side=top]:18,65_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v18" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v18==>:udb@[UDB=(2,4)]:pld0:input_permute.input_9" switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_10==>:udb@[UDB=(2,4)]:pld0:mc0.main_10" term ":udb@[UDB=(2,4)]:pld0:mc0.main_10" - switch ":udbswitch@[UDB=(2,3)][side=top]:29,37" - switch ":udbswitch@[UDB=(2,3)][side=top]:5,37_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v5" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v5==>:udb@[UDB=(3,3)]:pld0:input_permute.input_2" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(3,3)]:pld0:mc1.main_3" - term ":udb@[UDB=(3,3)]:pld0:mc1.main_3" + switch ":udbswitch@[UDB=(2,5)][side=top]:50,65_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v50" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v50==>:udb@[UDB=(2,5)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(2,5)]:pld1:mc1.main_3" + term ":udb@[UDB=(2,5)]:pld1:mc1.main_3" end \SPIM:BSPIM:ld_ident\ net \SPIM:BSPIM:is_spi_done\ term ":udb@[UDB=(2,4)]:pld1:mc0.q" - switch ":udb@[UDB=(2,4)]:pld1:mc0.q==>:udb@[UDB=(2,4)]:pld1:output_permute3.q_0" - switch ":udb@[UDB=(2,4)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v32" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v32" - switch ":udbswitch@[UDB=(2,4)][side=top]:32,69" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_69_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:8,69_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v8" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v8==>:udb@[UDB=(2,3)]:pld0:input_permute.input_4" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(2,3)]:pld0:mc0.main_8" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_8" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_9==>:udb@[UDB=(2,3)]:pld0:mc1.main_9" - term ":udb@[UDB=(2,3)]:pld0:mc1.main_9" - switch ":udbswitch@[UDB=(2,4)][side=top]:48,69_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v48" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v48==>:udb@[UDB=(2,4)]:pld1:input_permute.input_7" + switch ":udb@[UDB=(2,4)]:pld1:mc0.q==>:udb@[UDB=(2,4)]:pld1:output_permute0.q_0" + switch ":udb@[UDB=(2,4)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v38" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v38" + switch ":udbswitch@[UDB=(2,4)][side=top]:38,53" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_53_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:22,53_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v22" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v22==>:udb@[UDB=(2,5)]:pld0:input_permute.input_11" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(2,5)]:pld0:mc0.main_8" + term ":udb@[UDB=(2,5)]:pld0:mc0.main_8" + switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_9==>:udb@[UDB=(2,5)]:pld0:mc1.main_9" + term ":udb@[UDB=(2,5)]:pld0:mc1.main_9" + switch ":udbswitch@[UDB=(2,4)][side=top]:54,53_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v54" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v54==>:udb@[UDB=(2,4)]:pld1:input_permute.input_4" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc0_main_9==>:udb@[UDB=(2,4)]:pld1:mc0.main_9" term ":udb@[UDB=(2,4)]:pld1:mc0.main_9" switch ":udb@[UDB=(2,4)]:pld1:input_permute.mc1_main_9==>:udb@[UDB=(2,4)]:pld1:mc1.main_9" - term ":udb@[UDB=(2,4)]:pld1:mc1.main_9" -end \SPIM:BSPIM:is_spi_done\ -net \SPIM:BSPIM:mosi_hs_reg\ - term ":udb@[UDB=(3,5)]:pld1:mc0.q" - switch ":udb@[UDB=(3,5)]:pld1:mc0.q==>:udb@[UDB=(3,5)]:pld1:output_permute0.q_0" - switch ":udb@[UDB=(3,5)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v39" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v39" - switch ":udbswitch@[UDB=(2,5)][side=top]:39,94" - switch ":udbswitch@[UDB=(2,5)][side=top]:49,94_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v49" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v49==>:udb@[UDB=(3,5)]:pld1:input_permute.input_7" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(3,5)]:pld1:mc0.main_4" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_4" - switch ":udbswitch@[UDB=(2,5)][side=top]:49,19_b" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_19_b" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_19_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:17,19_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v17" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v17==>:udb@[UDB=(3,3)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(3,3)]:pld0:mc2.main_1" - term ":udb@[UDB=(3,3)]:pld0:mc2.main_1" + term ":udb@[UDB=(2,4)]:pld1:mc1.main_9" +end \SPIM:BSPIM:is_spi_done\ +net \SPIM:BSPIM:mosi_hs_reg\ + term ":udb@[UDB=(3,3)]:pld1:mc0.q" + switch ":udb@[UDB=(3,3)]:pld1:mc0.q==>:udb@[UDB=(3,3)]:pld1:output_permute3.q_0" + switch ":udb@[UDB=(3,3)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v33" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v33" + switch ":udbswitch@[UDB=(2,3)][side=top]:33,44" + switch ":udbswitch@[UDB=(2,3)][side=top]:57,44_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v57" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v57==>:udb@[UDB=(3,3)]:pld1:input_permute.input_3" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(3,3)]:pld1:mc0.main_4" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_4" + switch ":udbswitch@[UDB=(2,3)][side=top]:57,70_b" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_70_f" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_70_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:1,70_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v1" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v1==>:udb@[UDB=(3,5)]:pld0:input_permute.input_0" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(3,5)]:pld0:mc2.main_1" + term ":udb@[UDB=(3,5)]:pld0:mc2.main_1" end \SPIM:BSPIM:mosi_hs_reg\ -net \SPIM:BSPIM:cnt_enable\ - term ":udb@[UDB=(2,3)]:pld0:mc0.q" - switch ":udb@[UDB=(2,3)]:pld0:mc0.q==>:udb@[UDB=(2,3)]:pld0:output_permute0.q_0" - switch ":udb@[UDB=(2,3)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v24" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v24" - switch ":udbswitch@[UDB=(2,3)][side=top]:24,18" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_18_f" - switch ":udbswitch@[UDB=(2,4)][side=top]:102,18_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v102" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v102==>:udb@[UDB=(2,4)]:c7_en_mux.in_3" - switch ":udb@[UDB=(2,4)]:c7_en_mux.c7_en==>:udb@[UDB=(2,4)]:count7cell.enable" - term ":udb@[UDB=(2,4)]:count7cell.enable" - switch ":udbswitch@[UDB=(2,3)][side=top]:6,18_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v6" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v6==>:udb@[UDB=(2,3)]:pld0:input_permute.input_3" - switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc0_main_9==>:udb@[UDB=(2,3)]:pld0:mc0.main_9" - term ":udb@[UDB=(2,3)]:pld0:mc0.main_9" -end \SPIM:BSPIM:cnt_enable\ net \SPIM:BSPIM:mosi_from_dp_reg\ term ":udb@[UDB=(3,4)]:pld0:mc0.q" - switch ":udb@[UDB=(3,4)]:pld0:mc0.q==>:udb@[UDB=(3,4)]:pld0:output_permute3.q_0" - switch ":udb@[UDB=(3,4)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v31" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v31" - switch ":udbswitch@[UDB=(2,4)][side=top]:31,48" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_48_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:63,48_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v63" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v63==>:udb@[UDB=(3,5)]:pld1:input_permute.input_0" - switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(3,5)]:pld1:mc0.main_5" - term ":udb@[UDB=(3,5)]:pld1:mc0.main_5" + switch ":udb@[UDB=(3,4)]:pld0:mc0.q==>:udb@[UDB=(3,4)]:pld0:output_permute1.q_0" + switch ":udb@[UDB=(3,4)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v27" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v27" + switch ":udbswitch@[UDB=(2,4)][side=top]:27,60" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_60_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:59,60_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v59" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v59==>:udb@[UDB=(3,3)]:pld1:input_permute.input_2" + switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(3,3)]:pld1:mc0.main_5" + term ":udb@[UDB=(3,3)]:pld1:mc0.main_5" end \SPIM:BSPIM:mosi_from_dp_reg\ net \UART_1:BUART:tx_fifo_empty\ - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.f0_blk_stat_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(3,5)]:dp_wrapper:output_permute.f0_blk_stat_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:output_permute.outs_4==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v85" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v85" - switch ":udbswitch@[UDB=(2,5)][side=top]:85,32" - switch ":udbswitch@[UDB=(2,5)][side=top]:10,32_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v10" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v10==>:udb@[UDB=(2,5)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc3_main_2==>:udb@[UDB=(2,5)]:pld0:mc3.main_2" - term ":udb@[UDB=(2,5)]:pld0:mc3.main_2" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(2,5)]:pld0:mc1.main_2" - term ":udb@[UDB=(2,5)]:pld0:mc1.main_2" - switch ":udbswitch@[UDB=(2,5)][side=top]:10,60_b" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_60_b" - switch ":udbswitch@[UDB=(2,4)][side=top]:91,60_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v91" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v91==>:udb@[UDB=(3,4)]:statusicell.status_1" - term ":udb@[UDB=(3,4)]:statusicell.status_1" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.f0_blk_stat_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(2,3)]:dp_wrapper:output_permute.f0_blk_stat_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:output_permute.outs_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v76" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v76" + switch ":udbswitch@[UDB=(2,3)][side=top]:76,14" + switch ":udbswitch@[UDB=(2,3)][side=top]:4,14_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v4" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v4==>:udb@[UDB=(2,3)]:pld0:input_permute.input_2" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc3_main_2==>:udb@[UDB=(2,3)]:pld0:mc3.main_2" + term ":udb@[UDB=(2,3)]:pld0:mc3.main_2" + switch ":udb@[UDB=(2,3)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(2,3)]:pld0:mc1.main_2" + term ":udb@[UDB=(2,3)]:pld0:mc1.main_2" + switch ":udbswitch@[UDB=(2,3)][side=top]:4,40_b" + switch ":udbswitch@[UDB=(2,3)][side=top]:90,40_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v90" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v90==>:udb@[UDB=(2,3)]:statusicell.status_1" + term ":udb@[UDB=(2,3)]:statusicell.status_1" end \UART_1:BUART:tx_fifo_empty\ net \UART_1:BUART:tx_status_0\ - term ":udb@[UDB=(2,5)]:pld0:mc3.q" - switch ":udb@[UDB=(2,5)]:pld0:mc3.q==>:udb@[UDB=(2,5)]:pld0:output_permute3.q_3" - switch ":udb@[UDB=(2,5)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v30" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v30" - switch ":udbswitch@[UDB=(2,5)][side=top]:30,46" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_46_b" - switch ":udbswitch@[UDB=(2,4)][side=top]:89,46_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v89" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v89==>:udb@[UDB=(3,4)]:statusicell.status_0" - term ":udb@[UDB=(3,4)]:statusicell.status_0" + term ":udb@[UDB=(2,3)]:pld0:mc3.q" + switch ":udb@[UDB=(2,3)]:pld0:mc3.q==>:udb@[UDB=(2,3)]:pld0:output_permute3.q_3" + switch ":udb@[UDB=(2,3)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v30" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v30" + switch ":udbswitch@[UDB=(2,3)][side=top]:30,43" + switch ":udbswitch@[UDB=(2,3)][side=top]:88,43_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v88" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v88==>:udb@[UDB=(2,3)]:statusicell.status_0" + term ":udb@[UDB=(2,3)]:statusicell.status_0" end \UART_1:BUART:tx_status_0\ net Net_439 - term ":udb@[UDB=(3,3)]:pld0:mc0.q" - switch ":udb@[UDB=(3,3)]:pld0:mc0.q==>:udb@[UDB=(3,3)]:pld0:output_permute1.q_0" - switch ":udb@[UDB=(3,3)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v27" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v27" - switch ":udbswitch@[UDB=(2,3)][side=top]:27,62" - switch ":udbswitch@[UDB=(2,3)][side=top]:11,62_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v11" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v11==>:udb@[UDB=(3,3)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(3,3)]:pld0:mc0.main_3" - term ":udb@[UDB=(3,3)]:pld0:mc0.main_3" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(3,3)]:pld0:mc2.main_0" - term ":udb@[UDB=(3,3)]:pld0:mc2.main_0" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(3,3)]:pld0:mc3.main_0" - term ":udb@[UDB=(3,3)]:pld0:mc3.main_0" - switch ":udbswitch@[UDB=(2,3)][side=top]:51,62_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v51" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v51==>:udb@[UDB=(3,3)]:pld1:input_permute.input_6" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(3,3)]:pld1:mc0.main_0" - term ":udb@[UDB=(3,3)]:pld1:mc0.main_0" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(3,3)]:pld1:mc1.main_0" - term ":udb@[UDB=(3,3)]:pld1:mc1.main_0" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(3,3)]:pld1:mc2.main_0" - term ":udb@[UDB=(3,3)]:pld1:mc2.main_0" + term ":udb@[UDB=(3,5)]:pld0:mc1.q" + switch ":udb@[UDB=(3,5)]:pld0:mc1.q==>:udb@[UDB=(3,5)]:pld0:output_permute1.q_1" + switch ":udb@[UDB=(3,5)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v27" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v27" + switch ":udbswitch@[UDB=(2,5)][side=top]:27,62" + switch ":udbswitch@[UDB=(2,5)][side=top]:11,62_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v11" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v11==>:udb@[UDB=(3,5)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(3,5)]:pld0:mc1.main_3" + term ":udb@[UDB=(3,5)]:pld0:mc1.main_3" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(3,5)]:pld0:mc2.main_0" + term ":udb@[UDB=(3,5)]:pld0:mc2.main_0" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(3,5)]:pld0:mc3.main_0" + term ":udb@[UDB=(3,5)]:pld0:mc3.main_0" + switch ":udbswitch@[UDB=(2,5)][side=top]:51,62_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v51" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v51==>:udb@[UDB=(3,5)]:pld1:input_permute.input_6" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(3,5)]:pld1:mc0.main_0" + term ":udb@[UDB=(3,5)]:pld1:mc0.main_0" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(3,5)]:pld1:mc1.main_0" + term ":udb@[UDB=(3,5)]:pld1:mc1.main_0" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(3,5)]:pld1:mc2.main_0" + term ":udb@[UDB=(3,5)]:pld1:mc2.main_0" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(3,5)]:pld1:mc3.main_0" + term ":udb@[UDB=(3,5)]:pld1:mc3.main_0" end Net_439 +net \SPIM:BSPIM:load_cond\ + term ":udb@[UDB=(2,5)]:pld1:mc0.q" + switch ":udb@[UDB=(2,5)]:pld1:mc0.q==>:udb@[UDB=(2,5)]:pld1:output_permute0.q_0" + switch ":udb@[UDB=(2,5)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v38" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v38" + switch ":udbswitch@[UDB=(2,5)][side=top]:38,27" + switch ":udbswitch@[UDB=(2,5)][side=top]:62,27_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v62" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v62==>:udb@[UDB=(2,5)]:pld1:input_permute.input_0" + switch ":udb@[UDB=(2,5)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(2,5)]:pld1:mc0.main_8" + term ":udb@[UDB=(2,5)]:pld1:mc0.main_8" +end \SPIM:BSPIM:load_cond\ net \SPIM:BSPIM:mosi_pre_reg\ term ":udb@[UDB=(2,4)]:pld0:mc0.q" - switch ":udb@[UDB=(2,4)]:pld0:mc0.q==>:udb@[UDB=(2,4)]:pld0:output_permute3.q_0" - switch ":udb@[UDB=(2,4)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v30" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v30" - switch ":udbswitch@[UDB=(2,4)][side=top]:30,95" - switch ":udbswitch@[UDB=(2,4)][side=top]:0,95_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v0" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v0==>:udb@[UDB=(2,4)]:pld0:input_permute.input_0" + switch ":udb@[UDB=(2,4)]:pld0:mc0.q==>:udb@[UDB=(2,4)]:pld0:output_permute0.q_0" + switch ":udb@[UDB=(2,4)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v24" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v24" + switch ":udbswitch@[UDB=(2,4)][side=top]:24,18" + switch ":udbswitch@[UDB=(2,4)][side=top]:6,18_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v6" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v6==>:udb@[UDB=(2,4)]:pld0:input_permute.input_3" switch ":udb@[UDB=(2,4)]:pld0:input_permute.mc0_main_9==>:udb@[UDB=(2,4)]:pld0:mc0.main_9" term ":udb@[UDB=(2,4)]:pld0:mc0.main_9" end \SPIM:BSPIM:mosi_pre_reg\ net \UART_1:BUART:tx_shift_out\ - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.so_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:datapath.so_comb==>:udb@[UDB=(3,5)]:dp_wrapper:output_permute.so_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:output_permute.outs_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v81" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v81" - switch ":udbswitch@[UDB=(2,5)][side=top]:81,67" - switch ":udbswitch@[UDB=(2,5)][side=top]:17,67_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v17" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v17==>:udb@[UDB=(3,5)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(3,5)]:pld0:mc0.main_3" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_3" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.so_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:datapath.so_comb==>:udb@[UDB=(2,3)]:dp_wrapper:output_permute.so_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:output_permute.outs_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v82" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v82" + switch ":udbswitch@[UDB=(2,3)][side=top]:82,39" + switch ":udbswitch@[UDB=(2,3)][side=top]:21,39_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v21" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v21==>:udb@[UDB=(3,3)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(3,3)]:pld0:mc0.main_3" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_3" end \UART_1:BUART:tx_shift_out\ net \SPIM:BSPIM:load_rx_data\ - term ":udb@[UDB=(2,3)]:pld1:mc2.q" - switch ":udb@[UDB=(2,3)]:pld1:mc2.q==>:udb@[UDB=(2,3)]:pld1:output_permute3.q_2" - switch ":udb@[UDB=(2,3)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v32" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v32" - switch ":udbswitch@[UDB=(2,3)][side=top]:32,2" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_2_f" + term ":udb@[UDB=(2,5)]:pld1:mc2.q" + switch ":udb@[UDB=(2,5)]:pld1:mc2.q==>:udb@[UDB=(2,5)]:pld1:output_permute3.q_2" + switch ":udb@[UDB=(2,5)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v32" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v32" + switch ":udbswitch@[UDB=(2,5)][side=top]:32,2" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_2_b" switch ":udbswitch@[UDB=(2,4)][side=top]:72,2_f" switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v72" switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v72==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_4" @@ -893,59 +1068,58 @@ net \SPIM:BSPIM:load_rx_data\ term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_load" end \SPIM:BSPIM:load_rx_data\ net \UART_1:BUART:txn\ - term ":udb@[UDB=(3,5)]:pld0:mc0.q" - switch ":udb@[UDB=(3,5)]:pld0:mc0.q==>:udb@[UDB=(3,5)]:pld0:output_permute2.q_0" - switch ":udb@[UDB=(3,5)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v29" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v29" - switch ":udbswitch@[UDB=(2,5)][side=top]:29,56" - switch ":udbswitch@[UDB=(2,5)][side=top]:13,56_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v13" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v13==>:udb@[UDB=(3,5)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,5)]:pld0:mc0.main_0" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_0" - switch ":udbswitch@[UDB=(2,5)][side=top]:13,13_b" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_13_b" - switch ":udbswitch@[UDB=(2,4)][side=top]:19,13_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v19" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v19==>:udb@[UDB=(3,4)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(3,4)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(3,4)]:pld0:mc1.main_0" - term ":udb@[UDB=(3,4)]:pld0:mc1.main_0" + term ":udb@[UDB=(3,3)]:pld0:mc0.q" + switch ":udb@[UDB=(3,3)]:pld0:mc0.q==>:udb@[UDB=(3,3)]:pld0:output_permute1.q_0" + switch ":udb@[UDB=(3,3)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v27" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v27" + switch ":udbswitch@[UDB=(2,3)][side=top]:27,62" + switch ":udbswitch@[UDB=(2,3)][side=top]:11,62_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v11" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v11==>:udb@[UDB=(3,3)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(3,3)]:pld0:mc0.main_0" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_0" + switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_62_f" + switch ":udbswitch@[UDB=(2,4)][side=top]:11,62_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v11" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v11==>:udb@[UDB=(3,4)]:pld0:input_permute.input_5" + switch ":udb@[UDB=(3,4)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(3,4)]:pld0:mc2.main_0" + term ":udb@[UDB=(3,4)]:pld0:mc2.main_0" end \UART_1:BUART:txn\ net \SPIM:Net_276\ term ":clockblockcell.dclk_glb_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.in_0" - switch ":udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,3)]:pld0:mc0.clock_0" - term ":udb@[UDB=(3,3)]:pld0:mc0.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.in_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,3)]:pld1:mc1.clock_0" - term ":udb@[UDB=(2,3)]:pld1:mc1.clock_0" + switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.in_0" + switch ":udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,5)]:pld0:mc1.clock_0" + term ":udb@[UDB=(3,5)]:pld0:mc1.clock_0" + switch ":udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,5)]:pld0:mc0.clock_0" + term ":udb@[UDB=(3,5)]:pld0:mc0.clock_0" switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,4)]:clockreset:clk_sc_mux.in_0" switch ":udb@[UDB=(2,4)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(2,4)]:count7cell.clock" term ":udb@[UDB=(2,4)]:count7cell.clock" + switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,4)]:clockreset:clk_sc_mux.in_0" + switch ":udb@[UDB=(3,4)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(3,4)]:statusicell.clock" + term ":udb@[UDB=(3,4)]:statusicell.clock" switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,5)]:clockreset:clk_sc_mux.in_0" switch ":udb@[UDB=(2,5)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(2,5)]:statusicell.clock" term ":udb@[UDB=(2,5)]:statusicell.clock" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,3)]:clockreset:clk_sc_mux.in_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(2,3)]:statusicell.clock" - term ":udb@[UDB=(2,3)]:statusicell.clock" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,3)]:clockreset:clk_pld0_mux.in_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,3)]:pld0:mc0.clock_0" - term ":udb@[UDB=(2,3)]:pld0:mc0.clock_0" + switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.in_0" + switch ":udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,5)]:pld0:mc0.clock_0" + term ":udb@[UDB=(2,5)]:pld0:mc0.clock_0" switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,4)]:clockreset:clk_pld1_mux.in_0" switch ":udb@[UDB=(2,4)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,4)]:pld1:mc0.clock_0" term ":udb@[UDB=(2,4)]:pld1:mc0.clock_0" - switch ":udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,3)]:pld0:mc1.clock_0" - term ":udb@[UDB=(3,3)]:pld0:mc1.clock_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,3)]:pld1:mc0.clock_0" - term ":udb@[UDB=(2,3)]:pld1:mc0.clock_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,3)]:pld1:mc2.clock_0" - term ":udb@[UDB=(2,3)]:pld1:mc2.clock_0" + switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.in_0" + switch ":udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,5)]:pld1:mc1.clock_0" + term ":udb@[UDB=(2,5)]:pld1:mc1.clock_0" + switch ":udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,5)]:pld1:mc0.clock_0" + term ":udb@[UDB=(2,5)]:pld1:mc0.clock_0" + switch ":udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,5)]:pld1:mc2.clock_0" + term ":udb@[UDB=(2,5)]:pld1:mc2.clock_0" switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,4)]:clockreset:clk_pld0_mux.in_0" switch ":udb@[UDB=(3,4)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,4)]:pld0:mc0.clock_0" term ":udb@[UDB=(3,4)]:pld0:mc0.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,5)]:clockreset:clk_pld1_mux.in_0" - switch ":udb@[UDB=(3,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(3,5)]:pld1:mc0.clock_0" - term ":udb@[UDB=(3,5)]:pld1:mc0.clock_0" + switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(3,3)]:clockreset:clk_pld1_mux.in_0" + switch ":udb@[UDB=(3,3)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(3,3)]:pld1:mc0.clock_0" + term ":udb@[UDB=(3,3)]:pld1:mc0.clock_0" switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(2,4)]:clockreset:clk_pld0_mux.in_0" switch ":udb@[UDB=(2,4)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,4)]:pld0:mc0.clock_0" term ":udb@[UDB=(2,4)]:pld0:mc0.clock_0" @@ -954,136 +1128,209 @@ net \SPIM:Net_276\ term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.clock" switch ":udb@[UDB=(2,4)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,4)]:pld1:mc3.clock_0" term ":udb@[UDB=(2,4)]:pld1:mc3.clock_0" - switch ":udb@[UDB=(2,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,3)]:pld0:mc1.clock_0" - term ":udb@[UDB=(2,3)]:pld0:mc1.clock_0" + switch ":udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,5)]:pld0:mc1.clock_0" + term ":udb@[UDB=(2,5)]:pld0:mc1.clock_0" switch ":udb@[UDB=(2,4)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,4)]:pld1:mc1.clock_0" term ":udb@[UDB=(2,4)]:pld1:mc1.clock_0" end \SPIM:Net_276\ -net Net_191 - term ":clockblockcell.dclk_glb_1" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,5)]:clockreset:clk_dp_mux.in_1" - switch ":udb@[UDB=(3,5)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(3,5)]:dp_wrapper:datapath.clock" - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.clock" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,4)]:clockreset:clk_sc_mux.in_1" - switch ":udb@[UDB=(3,4)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(3,4)]:statusicell.clock" - term ":udb@[UDB=(3,4)]:statusicell.clock" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,5)]:clockreset:clk_dp_mux.in_1" - switch ":udb@[UDB=(2,5)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(2,5)]:dp_wrapper:datapath.clock" - term ":udb@[UDB=(2,5)]:dp_wrapper:datapath.clock" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.in_1" - switch ":udb@[UDB=(2,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,5)]:pld1:mc0.clock_0" - term ":udb@[UDB=(2,5)]:pld1:mc0.clock_0" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.in_1" - switch ":udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,5)]:pld0:mc1.clock_0" - term ":udb@[UDB=(2,5)]:pld0:mc1.clock_0" - switch ":udb@[UDB=(2,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,5)]:pld0:mc2.clock_0" - term ":udb@[UDB=(2,5)]:pld0:mc2.clock_0" - switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.in_1" - switch ":udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,5)]:pld0:mc1.clock_0" - term ":udb@[UDB=(3,5)]:pld0:mc1.clock_0" - switch ":udb@[UDB=(3,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,5)]:pld0:mc0.clock_0" - term ":udb@[UDB=(3,5)]:pld0:mc0.clock_0" -end Net_191 net ClockBlock_BUS_CLK term ":clockblockcell.clk_bus_glb" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,0)]:clockreset:clk_sc_mux.in_9" + switch ":udb@[UDB=(3,0)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(3,0)]:sync_wrapper:sync0.clock" + term ":udb@[UDB=(3,0)]:sync_wrapper:sync0.clock" switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,4)]:dp_wrapper:datapath.busclk" term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.busclk" - switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,3)]:controlcell.busclk" - term ":udb@[UDB=(3,3)]:controlcell.busclk" - switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,5)]:dp_wrapper:datapath.busclk" - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.busclk" - switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,5)]:dp_wrapper:datapath.busclk" - term ":udb@[UDB=(2,5)]:dp_wrapper:datapath.busclk" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,5)]:controlcell.busclk" + term ":udb@[UDB=(3,5)]:controlcell.busclk" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,0)]:clockreset:clk_sc_mux.in_9" + switch ":udb@[UDB=(2,0)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(2,0)]:statusicell.clock" + term ":udb@[UDB=(2,0)]:statusicell.clock" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,0)]:clockreset:clk_pld0_mux.in_9" + switch ":udb@[UDB=(2,0)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,0)]:pld0:mc3.clock_0" + term ":udb@[UDB=(2,0)]:pld0:mc3.clock_0" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,0)]:controlcell.busclk" + term ":udb@[UDB=(2,0)]:controlcell.busclk" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,0)]:clockreset:clk_dp_mux.in_9" + switch ":udb@[UDB=(2,0)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.clock" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.clock" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.busclk" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.busclk" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,0)]:clockreset:clk_dp_mux.in_9" + switch ":udb@[UDB=(3,0)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.clock" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.clock" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.busclk" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.busclk" + switch ":udb@[UDB=(2,0)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,0)]:pld0:mc0.clock_0" + term ":udb@[UDB=(2,0)]:pld0:mc0.clock_0" + switch ":udb@[UDB=(2,0)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,0)]:pld0:mc1.clock_0" + term ":udb@[UDB=(2,0)]:pld0:mc1.clock_0" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(2,3)]:dp_wrapper:datapath.busclk" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.busclk" + switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(3,3)]:dp_wrapper:datapath.busclk" + term ":udb@[UDB=(3,3)]:dp_wrapper:datapath.busclk" end ClockBlock_BUS_CLK +net Net_191 + term ":clockblockcell.dclk_glb_1" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,3)]:clockreset:clk_dp_mux.in_1" + switch ":udb@[UDB=(2,3)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(2,3)]:dp_wrapper:datapath.clock" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.clock" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,3)]:clockreset:clk_sc_mux.in_1" + switch ":udb@[UDB=(2,3)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(2,3)]:statusicell.clock" + term ":udb@[UDB=(2,3)]:statusicell.clock" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,3)]:clockreset:clk_dp_mux.in_1" + switch ":udb@[UDB=(3,3)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(3,3)]:dp_wrapper:datapath.clock" + term ":udb@[UDB=(3,3)]:dp_wrapper:datapath.clock" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.in_1" + switch ":udb@[UDB=(2,3)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(2,3)]:pld1:mc0.clock_0" + term ":udb@[UDB=(2,3)]:pld1:mc0.clock_0" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(2,3)]:clockreset:clk_pld0_mux.in_1" + switch ":udb@[UDB=(2,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(2,3)]:pld0:mc1.clock_0" + term ":udb@[UDB=(2,3)]:pld0:mc1.clock_0" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,0)]:clockreset:clk_pld1_mux.in_1" + switch ":udb@[UDB=(3,0)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(3,0)]:pld1:mc0.clock_0" + term ":udb@[UDB=(3,0)]:pld1:mc0.clock_0" + switch ":clockblockcell.dclk_glb_1==>:udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.in_1" + switch ":udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,3)]:pld0:mc1.clock_0" + term ":udb@[UDB=(3,3)]:pld0:mc1.clock_0" + switch ":udb@[UDB=(3,3)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(3,3)]:pld0:mc0.clock_0" + term ":udb@[UDB=(3,3)]:pld0:mc0.clock_0" +end Net_191 net mywire_1_0 - term ":udb@[UDB=(3,3)]:controlcell.control_0" - switch ":udb@[UDB=(3,3)]:controlcell.control_0==>:udb@[UDB=(3,3)]:controlcell_control_0_permute.in_0" - switch ":udb@[UDB=(3,3)]:controlcell_control_0_permute.controlcell_control_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v105" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v105" - switch ":udbswitch@[UDB=(2,3)][side=top]:105,73" - switch ":udbswitch@[UDB=(2,3)][side=top]:7,73_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v7" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v7==>:udb@[UDB=(3,3)]:pld0:input_permute.input_3" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc3_main_2==>:udb@[UDB=(3,3)]:pld0:mc3.main_2" - term ":udb@[UDB=(3,3)]:pld0:mc3.main_2" - switch ":udbswitch@[UDB=(2,3)][side=top]:55,73_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v55" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v55==>:udb@[UDB=(3,3)]:pld1:input_permute.input_4" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(3,3)]:pld1:mc0.main_2" - term ":udb@[UDB=(3,3)]:pld1:mc0.main_2" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(3,3)]:pld1:mc1.main_2" - term ":udb@[UDB=(3,3)]:pld1:mc1.main_2" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(3,3)]:pld1:mc2.main_2" - term ":udb@[UDB=(3,3)]:pld1:mc2.main_2" + term ":udb@[UDB=(3,5)]:controlcell.control_0" + switch ":udb@[UDB=(3,5)]:controlcell.control_0==>:udb@[UDB=(3,5)]:controlcell_control_0_permute.in_0" + switch ":udb@[UDB=(3,5)]:controlcell_control_0_permute.controlcell_control_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v105" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v105" + switch ":udbswitch@[UDB=(2,5)][side=top]:105,42" + switch ":udbswitch@[UDB=(2,5)][side=top]:23,42_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v23" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v23==>:udb@[UDB=(3,5)]:pld0:input_permute.input_11" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc3_main_3==>:udb@[UDB=(3,5)]:pld0:mc3.main_3" + term ":udb@[UDB=(3,5)]:pld0:mc3.main_3" + switch ":udbswitch@[UDB=(2,5)][side=top]:105,73" + switch ":udbswitch@[UDB=(2,5)][side=top]:55,73_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v55" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v55==>:udb@[UDB=(3,5)]:pld1:input_permute.input_4" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(3,5)]:pld1:mc0.main_3" + term ":udb@[UDB=(3,5)]:pld1:mc0.main_3" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(3,5)]:pld1:mc1.main_3" + term ":udb@[UDB=(3,5)]:pld1:mc1.main_3" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc2_main_3==>:udb@[UDB=(3,5)]:pld1:mc2.main_3" + term ":udb@[UDB=(3,5)]:pld1:mc2.main_3" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc3_main_3==>:udb@[UDB=(3,5)]:pld1:mc3.main_3" + term ":udb@[UDB=(3,5)]:pld1:mc3.main_3" end mywire_1_0 net mywire_1_1 - term ":udb@[UDB=(3,3)]:controlcell.control_1" - switch ":udb@[UDB=(3,3)]:controlcell.control_1==>:udb@[UDB=(3,3)]:controlcell_control_1_permute.in_0" - switch ":udb@[UDB=(3,3)]:controlcell_control_1_permute.controlcell_control_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v107" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v107" - switch ":udbswitch@[UDB=(2,3)][side=top]:107,79" - switch ":udbswitch@[UDB=(2,3)][side=top]:19,79_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v19" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v19==>:udb@[UDB=(3,3)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc3_main_1==>:udb@[UDB=(3,3)]:pld0:mc3.main_1" - term ":udb@[UDB=(3,3)]:pld0:mc3.main_1" - switch ":udbswitch@[UDB=(2,3)][side=top]:107,60" - switch ":udbswitch@[UDB=(2,3)][side=top]:59,60_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v59" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v59==>:udb@[UDB=(3,3)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(3,3)]:pld1:mc0.main_1" - term ":udb@[UDB=(3,3)]:pld1:mc0.main_1" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(3,3)]:pld1:mc1.main_1" - term ":udb@[UDB=(3,3)]:pld1:mc1.main_1" - switch ":udb@[UDB=(3,3)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(3,3)]:pld1:mc2.main_1" - term ":udb@[UDB=(3,3)]:pld1:mc2.main_1" + term ":udb@[UDB=(3,5)]:controlcell.control_1" + switch ":udb@[UDB=(3,5)]:controlcell.control_1==>:udb@[UDB=(3,5)]:controlcell_control_1_permute.in_0" + switch ":udb@[UDB=(3,5)]:controlcell_control_1_permute.controlcell_control_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v107" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v107" + switch ":udbswitch@[UDB=(2,5)][side=top]:107,79" + switch ":udbswitch@[UDB=(2,5)][side=top]:19,79_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v19" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v19==>:udb@[UDB=(3,5)]:pld0:input_permute.input_9" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc3_main_2==>:udb@[UDB=(3,5)]:pld0:mc3.main_2" + term ":udb@[UDB=(3,5)]:pld0:mc3.main_2" + switch ":udbswitch@[UDB=(2,5)][side=top]:107,60" + switch ":udbswitch@[UDB=(2,5)][side=top]:59,60_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v59" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v59==>:udb@[UDB=(3,5)]:pld1:input_permute.input_2" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(3,5)]:pld1:mc0.main_2" + term ":udb@[UDB=(3,5)]:pld1:mc0.main_2" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(3,5)]:pld1:mc1.main_2" + term ":udb@[UDB=(3,5)]:pld1:mc1.main_2" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(3,5)]:pld1:mc2.main_2" + term ":udb@[UDB=(3,5)]:pld1:mc2.main_2" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc3_main_2==>:udb@[UDB=(3,5)]:pld1:mc3.main_2" + term ":udb@[UDB=(3,5)]:pld1:mc3.main_2" end mywire_1_1 +net mywire_1_2 + term ":udb@[UDB=(3,5)]:controlcell.control_2" + switch ":udb@[UDB=(3,5)]:controlcell.control_2==>:udb@[UDB=(3,5)]:controlcell_control_2_permute.in_0" + switch ":udb@[UDB=(3,5)]:controlcell_control_2_permute.controlcell_control_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v109" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v109" + switch ":udbswitch@[UDB=(2,5)][side=top]:109,85" + switch ":udbswitch@[UDB=(2,5)][side=top]:21,85_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v21" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v21==>:udb@[UDB=(3,5)]:pld0:input_permute.input_10" + switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc3_main_1==>:udb@[UDB=(3,5)]:pld0:mc3.main_1" + term ":udb@[UDB=(3,5)]:pld0:mc3.main_1" + switch ":udbswitch@[UDB=(2,5)][side=top]:109,54" + switch ":udbswitch@[UDB=(2,5)][side=top]:61,54_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v61" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v61==>:udb@[UDB=(3,5)]:pld1:input_permute.input_1" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(3,5)]:pld1:mc0.main_1" + term ":udb@[UDB=(3,5)]:pld1:mc0.main_1" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(3,5)]:pld1:mc1.main_1" + term ":udb@[UDB=(3,5)]:pld1:mc1.main_1" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(3,5)]:pld1:mc2.main_1" + term ":udb@[UDB=(3,5)]:pld1:mc2.main_1" + switch ":udb@[UDB=(3,5)]:pld1:input_permute.mc3_main_1==>:udb@[UDB=(3,5)]:pld1:mc3.main_1" + term ":udb@[UDB=(3,5)]:pld1:mc3.main_1" +end mywire_1_2 net \UART_1:BUART:tx_counter_dp\ - term ":udb@[UDB=(2,5)]:dp_wrapper:datapath.cl1_comb" - switch ":udb@[UDB=(2,5)]:dp_wrapper:datapath.cl1_comb==>:udb@[UDB=(2,5)]:dp_wrapper:output_permute.cl1_comb" - switch ":udb@[UDB=(2,5)]:dp_wrapper:output_permute.outs_5==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v86" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v86" - switch ":udbswitch@[UDB=(2,5)][side=top]:86,5" - switch ":udbswitch@[UDB=(2,5)][side=top]:22,5_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v22" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v22==>:udb@[UDB=(2,5)]:pld0:input_permute.input_11" - switch ":udb@[UDB=(2,5)]:pld0:input_permute.mc2_main_4==>:udb@[UDB=(2,5)]:pld0:mc2.main_4" - term ":udb@[UDB=(2,5)]:pld0:mc2.main_4" - switch ":udbswitch@[UDB=(2,5)][side=top]:9,5_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v9" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v9==>:udb@[UDB=(3,5)]:pld0:input_permute.input_4" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(3,5)]:pld0:mc1.main_4" - term ":udb@[UDB=(3,5)]:pld0:mc1.main_4" - switch ":udb@[UDB=(3,5)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(3,5)]:pld0:mc0.main_6" - term ":udb@[UDB=(3,5)]:pld0:mc0.main_6" + term ":udb@[UDB=(3,3)]:dp_wrapper:datapath.cl1_comb" + switch ":udb@[UDB=(3,3)]:dp_wrapper:datapath.cl1_comb==>:udb@[UDB=(3,3)]:dp_wrapper:output_permute.cl1_comb" + switch ":udb@[UDB=(3,3)]:dp_wrapper:output_permute.outs_4==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v85" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v85" + switch ":udbswitch@[UDB=(2,3)][side=top]:85,32" + switch ":hvswitch@[UDB=(2,2)][side=left]:hseg_32_b" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_32_b" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_32_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:61,32_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v61" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v61==>:udb@[UDB=(3,0)]:pld1:input_permute.input_1" + switch ":udb@[UDB=(3,0)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(3,0)]:pld1:mc0.main_4" + term ":udb@[UDB=(3,0)]:pld1:mc0.main_4" + switch ":udbswitch@[UDB=(2,3)][side=top]:85,80" + switch ":udbswitch@[UDB=(2,3)][side=top]:13,80_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v13" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v13==>:udb@[UDB=(3,3)]:pld0:input_permute.input_6" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(3,3)]:pld0:mc1.main_4" + term ":udb@[UDB=(3,3)]:pld0:mc1.main_4" + switch ":udb@[UDB=(3,3)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(3,3)]:pld0:mc0.main_6" + term ":udb@[UDB=(3,3)]:pld0:mc0.main_6" end \UART_1:BUART:tx_counter_dp\ net \UART_1:BUART:tx_fifo_notfull\ - term ":udb@[UDB=(3,5)]:dp_wrapper:datapath.f0_bus_stat_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:datapath.f0_bus_stat_comb==>:udb@[UDB=(3,5)]:dp_wrapper:output_permute.f0_bus_stat_comb" - switch ":udb@[UDB=(3,5)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v79" - switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v79" - switch ":udbswitch@[UDB=(2,5)][side=top]:79,24" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_24_b" - switch ":udbswitch@[UDB=(2,4)][side=top]:95,24_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v95" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v95==>:udb@[UDB=(3,4)]:statusicell.status_3" - term ":udb@[UDB=(3,4)]:statusicell.status_3" - switch ":udbswitch@[UDB=(2,4)][side=top]:17,24_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v17" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v17==>:udb@[UDB=(3,4)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(3,4)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(3,4)]:pld0:mc2.main_0" - term ":udb@[UDB=(3,4)]:pld0:mc2.main_0" + term ":udb@[UDB=(2,3)]:dp_wrapper:datapath.f0_bus_stat_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:datapath.f0_bus_stat_comb==>:udb@[UDB=(2,3)]:dp_wrapper:output_permute.f0_bus_stat_comb" + switch ":udb@[UDB=(2,3)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v78" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v78" + switch ":udbswitch@[UDB=(2,3)][side=top]:78,25" + switch ":udbswitch@[UDB=(2,3)][side=top]:94,25_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v94" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v94==>:udb@[UDB=(2,3)]:statusicell.status_3" + term ":udb@[UDB=(2,3)]:statusicell.status_3" + switch ":udbswitch@[UDB=(2,3)][side=top]:54,25_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v54" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v54==>:udb@[UDB=(2,3)]:pld1:input_permute.input_4" + switch ":udb@[UDB=(2,3)]:pld1:input_permute.mc3_main_0==>:udb@[UDB=(2,3)]:pld1:mc3.main_0" + term ":udb@[UDB=(2,3)]:pld1:mc3.main_0" end \UART_1:BUART:tx_fifo_notfull\ +net ClockBlock_1k + term ":clockblockcell.clk_1k" + switch ":clockblockcell.clk_1k==>Stub-:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v32+:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v34" + switch "OStub-:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v32+:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v34" + switch ":dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:32,47" + switch ":hvswitch@[UDB=(3,1)][side=left]:27,47_f" + switch ":hvswitch@[UDB=(2,1)][side=left]:vseg_27_bot_f" + switch ":hvswitch@[UDB=(2,1)][side=left]:27,22_b" + switch ":hvswitch@[UDB=(2,1)][side=left]:hseg_22_b" + switch ":hvswitch@[UDB=(2,0)][side=left]:hseg_22_b" + switch ":udbswitch@[UDB=(2,0)][side=top]:89,22_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v89" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v89==>:udb@[UDB=(3,0)]:sync_wrapper:sync0.in" + term ":udb@[UDB=(3,0)]:sync_wrapper:sync0.in" +end ClockBlock_1k net Net_20 term ":ioport0:pin0.fb" switch ":ioport0:pin0.fb==>Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v0+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v2" switch "OStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v0+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v2" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:0,67" - switch ":hvswitch@[UDB=(0,4)][side=left]:hseg_67_b" - switch ":hvswitch@[UDB=(0,3)][side=left]:19,67_f" - switch ":hvswitch@[UDB=(1,3)][side=left]:vseg_19_top_f" - switch ":hvswitch@[UDB=(2,3)][side=left]:vseg_19_top_f" - switch ":hvswitch@[UDB=(2,3)][side=left]:19,77_b" + switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:2,85" + switch ":hvswitch@[UDB=(0,4)][side=left]:hseg_85_b" + switch ":hvswitch@[UDB=(0,3)][side=left]:18,85_f" + switch ":hvswitch@[UDB=(1,3)][side=left]:vseg_18_top_f" + switch ":hvswitch@[UDB=(2,3)][side=left]:vseg_18_top_f" + switch ":hvswitch@[UDB=(2,3)][side=left]:18,77_b" switch ":udbswitch@[UDB=(2,4)][side=top]:70,77_f" switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v70" switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v70==>:udb@[UDB=(2,4)]:dp_wrapper:input_permute.ina_3" @@ -1091,118 +1338,122 @@ net Net_20 term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.route_si" end Net_20 net Net_234 - term ":udb@[UDB=(3,4)]:pld0:mc1.q" - switch ":udb@[UDB=(3,4)]:pld0:mc1.q==>:udb@[UDB=(3,4)]:pld0:output_permute0.q_1" - switch ":udb@[UDB=(3,4)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v25" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v25" - switch ":udbswitch@[UDB=(2,4)][side=top]:25,75" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_75_f" - switch ":hvswitch@[UDB=(2,4)][side=left]:25,75_f" - switch ":hvswitch@[UDB=(2,4)][side=left]:vseg_25_bot_b" - switch ":hvswitch@[UDB=(3,4)][side=left]:25,80_b" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:98,80_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v100+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v102+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v98" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v100+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v102+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v98==>:ioport3:inputs2_mux.in_2" + term ":udb@[UDB=(3,4)]:pld0:mc2.q" + switch ":udb@[UDB=(3,4)]:pld0:mc2.q==>:udb@[UDB=(3,4)]:pld0:output_permute2.q_2" + switch ":udb@[UDB=(3,4)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v29" + switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v29" + switch ":udbswitch@[UDB=(2,4)][side=top]:29,89" + switch ":hvswitch@[UDB=(2,3)][side=left]:23,89_f" + switch ":hvswitch@[UDB=(3,3)][side=left]:vseg_23_top_f" + switch ":hvswitch@[UDB=(3,3)][side=left]:23,81_b" + switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_81_f" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:99,81_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v101+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v103+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v99" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v101+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v103+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v99==>:ioport3:inputs2_mux.in_3" switch ":ioport3:inputs2_mux.pin7__pin_input==>:ioport3:pin7.pin_input" term ":ioport3:pin7.pin_input" end Net_234 net Net_30 - term ":udb@[UDB=(3,3)]:pld0:mc2.q" - switch ":udb@[UDB=(3,3)]:pld0:mc2.q==>:udb@[UDB=(3,3)]:pld0:output_permute0.q_2" - switch ":udb@[UDB=(3,3)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v25" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v25" - switch ":udbswitch@[UDB=(2,3)][side=top]:25,20" - switch ":hvswitch@[UDB=(2,3)][side=left]:14,20_f" - switch ":hvswitch@[UDB=(1,3)][side=left]:vseg_14_bot_f" - switch ":hvswitch@[UDB=(0,3)][side=left]:vseg_14_bot_f" - switch ":hvswitch@[UDB=(0,3)][side=left]:14,70_b" - switch ":hvswitch@[UDB=(0,3)][side=left]:hseg_70_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:hseg_70_f" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:97,70_f" - switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v93+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v95+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v97" - switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v93+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v95+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v97==>:ioport0:inputs2_mux.in_1" + term ":udb@[UDB=(3,5)]:pld0:mc2.q" + switch ":udb@[UDB=(3,5)]:pld0:mc2.q==>:udb@[UDB=(3,5)]:pld0:output_permute0.q_2" + switch ":udb@[UDB=(3,5)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v25" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v25" + switch ":udbswitch@[UDB=(2,5)][side=top]:25,77" + switch ":hvswitch@[UDB=(2,5)][side=left]:3,77_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:vseg_3_top_b" + switch ":hvswitch@[UDB=(1,5)][side=left]:vseg_3_top_b" + switch ":hvswitch@[UDB=(0,5)][side=left]:3,7_b" + switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:92,7_f" + switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v92+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v94+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v96" + switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v92+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v94+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v96==>:ioport0:inputs2_mux.in_0" switch ":ioport0:inputs2_mux.pin5__pin_input==>:ioport0:pin5.pin_input" term ":ioport0:pin5.pin_input" end Net_30 net Net_419 - term ":udb@[UDB=(3,3)]:pld0:mc3.q" - switch ":udb@[UDB=(3,3)]:pld0:mc3.q==>:udb@[UDB=(3,3)]:pld0:output_permute3.q_3" - switch ":udb@[UDB=(3,3)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v31" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v31" - switch ":udbswitch@[UDB=(2,3)][side=top]:31,48" - switch ":hvswitch@[UDB=(2,3)][side=left]:12,48_f" - switch ":hvswitch@[UDB=(2,3)][side=left]:vseg_12_bot_b" - switch ":hvswitch@[UDB=(3,3)][side=left]:12,84_b" - switch ":hvswitch@[UDB=(3,3)][side=left]:hseg_84_f" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_84_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:91,84_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v87+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v89+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v91" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v87+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v89+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v91==>:ioport3:inputs1_mux.in_3" + term ":udb@[UDB=(3,5)]:pld0:mc3.q" + switch ":udb@[UDB=(3,5)]:pld0:mc3.q==>:udb@[UDB=(3,5)]:pld0:output_permute3.q_3" + switch ":udb@[UDB=(3,5)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v31" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v31" + switch ":udbswitch@[UDB=(2,5)][side=top]:31,93" + switch ":hvswitch@[UDB=(2,5)][side=left]:12,93_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:vseg_12_bot_b" + switch ":hvswitch@[UDB=(3,5)][side=left]:12,77_b" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:86,77_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v86+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v88+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v90" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v86+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v88+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v90==>:ioport3:inputs1_mux.in_2" switch ":ioport3:inputs1_mux.pin0__pin_input==>:ioport3:pin0.pin_input" term ":ioport3:pin0.pin_input" end Net_419 net Net_422 - term ":udb@[UDB=(3,3)]:pld1:mc0.q" - switch ":udb@[UDB=(3,3)]:pld1:mc0.q==>:udb@[UDB=(3,3)]:pld1:output_permute1.q_0" - switch ":udb@[UDB=(3,3)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v37" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v37" - switch ":udbswitch@[UDB=(2,3)][side=top]:37,15" - switch ":hvswitch@[UDB=(2,3)][side=left]:13,15_f" - switch ":hvswitch@[UDB=(2,3)][side=left]:vseg_13_bot_b" - switch ":hvswitch@[UDB=(3,3)][side=left]:13,23_b" - switch ":hvswitch@[UDB=(3,3)][side=left]:hseg_23_f" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_23_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:81,23_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v81+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v83+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v85" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v81+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v83+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v85==>:ioport3:inputs1_mux.in_1" + term ":udb@[UDB=(3,5)]:pld1:mc0.q" + switch ":udb@[UDB=(3,5)]:pld1:mc0.q==>:udb@[UDB=(3,5)]:pld1:output_permute2.q_0" + switch ":udb@[UDB=(3,5)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v35" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v35" + switch ":udbswitch@[UDB=(2,5)][side=top]:35,82" + switch ":hvswitch@[UDB=(2,4)][side=left]:18,82_f" + switch ":hvswitch@[UDB=(3,4)][side=left]:vseg_18_top_f" + switch ":hvswitch@[UDB=(3,4)][side=left]:18,23_b" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:80,23_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v80+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v82+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v84" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v80+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v82+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v84==>:ioport3:inputs1_mux.in_0" switch ":ioport3:inputs1_mux.pin1__pin_input==>:ioport3:pin1.pin_input" term ":ioport3:pin1.pin_input" end Net_422 net Net_425 - term ":udb@[UDB=(3,3)]:pld1:mc1.q" - switch ":udb@[UDB=(3,3)]:pld1:mc1.q==>:udb@[UDB=(3,3)]:pld1:output_permute2.q_1" - switch ":udb@[UDB=(3,3)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v35" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v35" - switch ":udbswitch@[UDB=(2,3)][side=top]:35,65" - switch ":hvswitch@[UDB=(2,3)][side=left]:5,65_f" - switch ":hvswitch@[UDB=(3,3)][side=left]:vseg_5_top_f" - switch ":hvswitch@[UDB=(3,3)][side=left]:5,22_b" - switch ":hvswitch@[UDB=(3,3)][side=left]:hseg_22_f" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_22_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:88,22_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v86+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v88+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v90" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v86+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v88+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v90==>:ioport3:inputs1_mux.in_2" + term ":udb@[UDB=(3,5)]:pld1:mc1.q" + switch ":udb@[UDB=(3,5)]:pld1:mc1.q==>:udb@[UDB=(3,5)]:pld1:output_permute3.q_1" + switch ":udb@[UDB=(3,5)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v33" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v33" + switch ":udbswitch@[UDB=(2,5)][side=top]:33,71" + switch ":hvswitch@[UDB=(2,4)][side=left]:25,71_f" + switch ":hvswitch@[UDB=(2,4)][side=left]:vseg_25_bot_b" + switch ":hvswitch@[UDB=(3,4)][side=left]:25,95_b" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:81,95_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v81+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v83+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v85" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v81+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v83+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v85==>:ioport3:inputs1_mux.in_1" switch ":ioport3:inputs1_mux.pin3__pin_input==>:ioport3:pin3.pin_input" term ":ioport3:pin3.pin_input" end Net_425 net Net_428 - term ":udb@[UDB=(3,3)]:pld1:mc2.q" - switch ":udb@[UDB=(3,3)]:pld1:mc2.q==>:udb@[UDB=(3,3)]:pld1:output_permute0.q_2" - switch ":udb@[UDB=(3,3)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v39" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v39" - switch ":udbswitch@[UDB=(2,3)][side=top]:39,53" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_53_f" - switch ":hvswitch@[UDB=(2,4)][side=left]:15,53_f" - switch ":hvswitch@[UDB=(2,4)][side=left]:vseg_15_bot_b" - switch ":hvswitch@[UDB=(3,4)][side=left]:15,11_b" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_11_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:84,11_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v80+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v82+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v84" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v80+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v82+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v84==>:ioport3:inputs1_mux.in_0" + term ":udb@[UDB=(3,5)]:pld1:mc2.q" + switch ":udb@[UDB=(3,5)]:pld1:mc2.q==>:udb@[UDB=(3,5)]:pld1:output_permute1.q_2" + switch ":udb@[UDB=(3,5)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v37" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v37" + switch ":udbswitch@[UDB=(2,5)][side=top]:37,88" + switch ":hvswitch@[UDB=(2,5)][side=left]:15,88_f" + switch ":hvswitch@[UDB=(2,5)][side=left]:vseg_15_bot_b" + switch ":hvswitch@[UDB=(3,5)][side=left]:15,94_b" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:89,94_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v87+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v89+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v91" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v87+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v89+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v91==>:ioport3:inputs1_mux.in_3" switch ":ioport3:inputs1_mux.pin2__pin_input==>:ioport3:pin2.pin_input" term ":ioport3:pin2.pin_input" end Net_428 +net Net_585 + term ":udb@[UDB=(3,5)]:pld1:mc3.q" + switch ":udb@[UDB=(3,5)]:pld1:mc3.q==>:udb@[UDB=(3,5)]:pld1:output_permute0.q_3" + switch ":udb@[UDB=(3,5)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v39" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v39" + switch ":udbswitch@[UDB=(2,5)][side=top]:39,91" + switch ":hvswitch@[UDB=(2,4)][side=left]:27,91_f" + switch ":hvswitch@[UDB=(2,4)][side=left]:vseg_27_bot_b" + switch ":hvswitch@[UDB=(3,4)][side=left]:27,76_b" + switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:95,76_f" + switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v93+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v95+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v97" + switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v93+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v95+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v97==>:ioport3:inputs2_mux.in_1" + switch ":ioport3:inputs2_mux.pin4__pin_input==>:ioport3:pin4.pin_input" + term ":ioport3:pin4.pin_input" +end Net_585 net \SPIM:BSPIM:rx_status_5\ term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_bus_stat_comb" switch ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f1_bus_stat_comb==>:udb@[UDB=(2,4)]:dp_wrapper:output_permute.f1_bus_stat_comb" switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_3==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v82" switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v82" - switch ":udbswitch@[UDB=(2,4)][side=top]:82,41" - switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_41_f" - switch ":udbswitch@[UDB=(2,5)][side=top]:98,41_f" - switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v98" - switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v98==>:udb@[UDB=(2,5)]:statusicell.status_5" - term ":udb@[UDB=(2,5)]:statusicell.status_5" + switch ":udbswitch@[UDB=(2,4)][side=top]:82,61" + switch ":udbswitch@[UDB=(2,4)][side=top]:99,61_f" + switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v99" + switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v99==>:udb@[UDB=(3,4)]:statusicell.status_5" + term ":udb@[UDB=(3,4)]:statusicell.status_5" end \SPIM:BSPIM:rx_status_5\ net \SPIM:BSPIM:tx_status_2\ term ":udb@[UDB=(2,4)]:dp_wrapper:datapath.f0_bus_stat_comb" @@ -1210,31 +1461,108 @@ net \SPIM:BSPIM:tx_status_2\ switch ":udb@[UDB=(2,4)]:dp_wrapper:output_permute.outs_0==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v76" switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v76" switch ":udbswitch@[UDB=(2,4)][side=top]:76,31" - switch ":hvswitch@[UDB=(2,3)][side=left]:hseg_31_b" - switch ":udbswitch@[UDB=(2,3)][side=top]:92,31_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v92" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v92==>:udb@[UDB=(2,3)]:statusicell.status_2" - term ":udb@[UDB=(2,3)]:statusicell.status_2" + switch ":hvswitch@[UDB=(2,4)][side=left]:hseg_31_f" + switch ":udbswitch@[UDB=(2,5)][side=top]:92,31_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v92" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v92==>:udb@[UDB=(2,5)]:statusicell.status_2" + term ":udb@[UDB=(2,5)]:statusicell.status_2" end \SPIM:BSPIM:tx_status_2\ net \SPIM:BSPIM:tx_status_4\ - term ":udb@[UDB=(2,3)]:pld0:mc2.q" - switch ":udb@[UDB=(2,3)]:pld0:mc2.q==>:udb@[UDB=(2,3)]:pld0:output_permute3.q_2" - switch ":udb@[UDB=(2,3)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v30" - switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v30" - switch ":udbswitch@[UDB=(2,3)][side=top]:30,43" - switch ":udbswitch@[UDB=(2,3)][side=top]:96,43_f" - switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v96" - switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v96==>:udb@[UDB=(2,3)]:statusicell.status_4" - term ":udb@[UDB=(2,3)]:statusicell.status_4" + term ":udb@[UDB=(2,5)]:pld0:mc2.q" + switch ":udb@[UDB=(2,5)]:pld0:mc2.q==>:udb@[UDB=(2,5)]:pld0:output_permute3.q_2" + switch ":udb@[UDB=(2,5)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(2,5)][side=top]:v30" + switch "OStub-:udbswitch@[UDB=(2,5)][side=top]:v30" + switch ":udbswitch@[UDB=(2,5)][side=top]:30,43" + switch ":udbswitch@[UDB=(2,5)][side=top]:96,43_f" + switch "IStub-:udbswitch@[UDB=(2,5)][side=top]:v96" + switch "Stub-:udbswitch@[UDB=(2,5)][side=top]:v96==>:udb@[UDB=(2,5)]:statusicell.status_4" + term ":udb@[UDB=(2,5)]:statusicell.status_4" end \SPIM:BSPIM:tx_status_4\ +net \Timer_1:TimerUDB:status_2\ + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.f0_blk_stat_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(3,0)]:dp_wrapper:output_permute.f0_blk_stat_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:output_permute.outs_0==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v77" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v77" + switch ":udbswitch@[UDB=(2,0)][side=top]:77,34" + switch ":udbswitch@[UDB=(2,0)][side=top]:92,34_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v92" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v92==>:udb@[UDB=(2,0)]:statusicell.status_2" + term ":udb@[UDB=(2,0)]:statusicell.status_2" +end \Timer_1:TimerUDB:status_2\ +net \Timer_1:TimerUDB:status_3\ + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.f0_bus_stat_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:datapath.f0_bus_stat_comb==>:udb@[UDB=(3,0)]:dp_wrapper:output_permute.f0_bus_stat_comb" + switch ":udb@[UDB=(3,0)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(2,0)][side=top]:v79" + switch "OStub-:udbswitch@[UDB=(2,0)][side=top]:v79" + switch ":udbswitch@[UDB=(2,0)][side=top]:79,28" + switch ":udbswitch@[UDB=(2,0)][side=top]:94,28_f" + switch "IStub-:udbswitch@[UDB=(2,0)][side=top]:v94" + switch "Stub-:udbswitch@[UDB=(2,0)][side=top]:v94==>:udb@[UDB=(2,0)]:statusicell.status_3" + term ":udb@[UDB=(2,0)]:statusicell.status_3" +end \Timer_1:TimerUDB:status_3\ net \UART_1:BUART:tx_status_2\ - term ":udb@[UDB=(3,4)]:pld0:mc2.q" - switch ":udb@[UDB=(3,4)]:pld0:mc2.q==>:udb@[UDB=(3,4)]:pld0:output_permute2.q_2" - switch ":udb@[UDB=(3,4)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(2,4)][side=top]:v29" - switch "OStub-:udbswitch@[UDB=(2,4)][side=top]:v29" - switch ":udbswitch@[UDB=(2,4)][side=top]:29,56" - switch ":udbswitch@[UDB=(2,4)][side=top]:93,56_f" - switch "IStub-:udbswitch@[UDB=(2,4)][side=top]:v93" - switch "Stub-:udbswitch@[UDB=(2,4)][side=top]:v93==>:udb@[UDB=(3,4)]:statusicell.status_2" - term ":udb@[UDB=(3,4)]:statusicell.status_2" + term ":udb@[UDB=(2,3)]:pld1:mc3.q" + switch ":udb@[UDB=(2,3)]:pld1:mc3.q==>:udb@[UDB=(2,3)]:pld1:output_permute1.q_3" + switch ":udb@[UDB=(2,3)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(2,3)][side=top]:v36" + switch "OStub-:udbswitch@[UDB=(2,3)][side=top]:v36" + switch ":udbswitch@[UDB=(2,3)][side=top]:36,57" + switch ":udbswitch@[UDB=(2,3)][side=top]:92,57_f" + switch "IStub-:udbswitch@[UDB=(2,3)][side=top]:v92" + switch "Stub-:udbswitch@[UDB=(2,3)][side=top]:v92==>:udb@[UDB=(2,3)]:statusicell.status_2" + term ":udb@[UDB=(2,3)]:statusicell.status_2" end \UART_1:BUART:tx_status_2\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ce0" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ce0==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.ce0i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.ce0i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cl0" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cl0==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.cl0i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cl0i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ff0" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ff0==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.ff0i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.ff0i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ce1" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ce1==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.ce1i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.ce1i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cl1" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cl1==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.cl1i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cl1i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.z1" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.z1==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.z1i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.z1i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ff1" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.ff1==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.ff1i" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.ff1i" +end \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.sol_msb" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.sol_msb==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.sir" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.sir" +end \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\ + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cfbo" + switch ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cfbo==>:udb@[UDB=(3,0)]:dp_wrapper:datapath.cfbi" + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cfbi" +end \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\ + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.sor" + switch ":udb@[UDB=(3,0)]:dp_wrapper:datapath.sor==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.sil" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.sil" +end \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\ +net \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\ + term ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cmsbo" + switch ":udb@[UDB=(3,0)]:dp_wrapper:datapath.cmsbo==>:udb@[UDB=(2,0)]:dp_wrapper:datapath.cmsbi" + term ":udb@[UDB=(2,0)]:dp_wrapper:datapath.cmsbi" +end \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rpt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rpt index e1a5509..a4a22fe 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rpt +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rpt @@ -1,16 +1,16 @@ -Loading plugins phase: Elapsed time ==> 0s.201ms -Initializing data phase: Elapsed time ==> 2s.741ms +Loading plugins phase: Elapsed time ==> 0s.206ms +Initializing data phase: Elapsed time ==> 3s.144ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 -s C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\Generated_Source\PSoC5 -- -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 -s C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\Generated_Source\PSoC5 -- -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ADD: prj.M0245: information: PSoC 5LP provides many improvements over PSoC 5. Learn more about migrating to PSoC 5LP at www.cypress.com/go/PSoC5LP +ADD: prj.M0246: information: PSoC 5LP provides many improvements over PSoC 5. Learn more about migrating to PSoC 5LP at www.cypress.com/go/PSoC5LP * PSOC5_SPI_LSM303D () -Elaboration phase: Elapsed time ==> 2s.691ms +Elaboration phase: Elapsed time ==> 3s.174ms -HDL generation phase: Elapsed time ==> 0s.072ms +HDL generation phase: Elapsed time ==> 0s.115ms | | | | | | | @@ -28,23 +28,23 @@ HDL generation phase: Elapsed time ==> 0s.072ms ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog ====================================================================== ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog ====================================================================== ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : vlogfe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Fri Mar 22 10:33:23 2013 +Thu Jul 25 16:48:52 2013 ====================================================================== @@ -54,7 +54,7 @@ Options : -yv2 -q10 PSOC5_SPI_LSM303D.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Fri Mar 22 10:33:23 2013 +Thu Jul 25 16:48:52 2013 Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' @@ -67,6 +67,9 @@ Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\wa Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v' Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v' vpp: No errors. @@ -91,6 +94,8 @@ C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\conten C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1503, col 106): Note: Substituting module 'cmp_vv_vv' for '<'. C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1559, col 68): Note: Substituting module 'cmp_vv_vv' for '<'. C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_UART_v2_30\B_UART_v2_30.v (line 1560, col 68): Note: Substituting module 'cmp_vv_vv' for '<'. +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v (line 368, col 46): Note: Substituting module 'cmp_vv_vv' for '='. +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v (line 374, col 62): Note: Substituting module 'add_vv_vv' for '+'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. @@ -100,11 +105,11 @@ vlogfe: No errors. ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : tovif -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Fri Mar 22 10:33:24 2013 +Thu Jul 25 16:48:53 2013 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,9 +120,9 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v'. @@ -126,6 +131,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\conte Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. @@ -135,11 +142,11 @@ tovif: No errors. ====================================================================== Compiling: PSOC5_SPI_LSM303D.v Program : topld -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v +Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 -verilog PSOC5_SPI_LSM303D.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Fri Mar 22 10:33:24 2013 +Thu Jul 25 16:48:54 2013 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -150,9 +157,9 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.ctl'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. +Linking 'C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\codegentemp\PSOC5_SPI_LSM303D.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\cypress.v'. @@ -161,6 +168,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\conte Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. @@ -190,6 +199,12 @@ Detecting unused logic. \UART_1:BUART:reset_sr\ Net_258 Net_259 + \demux_1:tmp__demux_1_5_reg\ + \demux_1:tmp__demux_1_6_reg\ + \demux_1:tmp__demux_1_7_reg\ + Net_443 + Net_588 + Net_589 \SS:clk\ \SS:rst\ \SS:control_bus_7\ @@ -197,10 +212,24 @@ Detecting unused logic. \SS:control_bus_5\ \SS:control_bus_4\ \SS:control_bus_3\ - \SS:control_bus_2\ - - -Deleted 29 User equations/components. + \Timer_1:Net_260\ + Net_663 + Net_668 + \Timer_1:Net_53\ + \Timer_1:TimerUDB:ctrl_ten\ + \Timer_1:TimerUDB:ctrl_cmode_0\ + \Timer_1:TimerUDB:ctrl_tmode_1\ + \Timer_1:TimerUDB:ctrl_tmode_0\ + \Timer_1:TimerUDB:ctrl_ic_1\ + \Timer_1:TimerUDB:ctrl_ic_0\ + Net_667 + \Timer_1:TimerUDB:zeros_3\ + \Timer_1:TimerUDB:zeros_2\ + \Timer_1:Net_102\ + \Timer_1:Net_266\ + + +Deleted 49 User equations/components. Deleted 0 Synthesized equations/components. ------------------------------------------------------ @@ -238,8 +267,18 @@ Aliasing tmpOE__Pin_1_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_2_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_3_net_0 to tmpOE__m_miso_pin_net_0 Aliasing tmpOE__Pin_4_net_0 to tmpOE__m_miso_pin_net_0 +Aliasing tmpOE__Pin_5_net_0 to tmpOE__m_miso_pin_net_0 +Aliasing Net_12 to zero +Aliasing \Timer_1:TimerUDB:ctrl_cmode_1\ to zero +Aliasing \Timer_1:TimerUDB:trigger_enable\ to tmpOE__m_miso_pin_net_0 +Aliasing \Timer_1:TimerUDB:status_6\ to zero +Aliasing \Timer_1:TimerUDB:status_5\ to zero +Aliasing \Timer_1:TimerUDB:status_4\ to zero +Aliasing \Timer_1:TimerUDB:status_0\ to \Timer_1:TimerUDB:tc_i\ Aliasing \SPIM:BSPIM:dpcounter_one_reg\\D\ to \SPIM:BSPIM:tx_status_3\ Aliasing Net_256D to zero +Aliasing \Timer_1:TimerUDB:capture_last\\D\ to zero +Aliasing \Timer_1:TimerUDB:capture_out_reg_i\\D\ to \Timer_1:TimerUDB:capt_fifo_load_int\ Removing Lhs of wire one[7] = tmpOE__m_miso_pin_net_0[2] Removing Lhs of wire tmpOE__m_mosi_pin_net_0[10] = tmpOE__m_miso_pin_net_0[2] Removing Rhs of wire Net_30[11] = \SPIM:BSPIM:mosi_fin\[36] @@ -283,28 +322,55 @@ Removing Lhs of wire \UART_1:BUART:tx_status_4\[224] = zero[3] Removing Lhs of wire \UART_1:BUART:tx_status_1\[226] = \UART_1:BUART:tx_fifo_empty\[187] Removing Lhs of wire \UART_1:BUART:tx_status_3\[228] = \UART_1:BUART:tx_fifo_notfull\[186] Removing Lhs of wire tmpOE__Tx_1_net_0[236] = tmpOE__m_miso_pin_net_0[2] -Removing Rhs of wire mywire_1_1[242] = \SS:control_out_1\[266] -Removing Rhs of wire mywire_1_1[242] = \SS:control_1\[275] -Removing Rhs of wire mywire_1_0[243] = \SS:control_out_0\[267] -Removing Rhs of wire mywire_1_0[243] = \SS:control_0\[276] -Removing Rhs of wire Net_444[248] = \demux_1:tmp__demux_1_0_reg\[241] -Removing Rhs of wire Net_441[249] = \demux_1:tmp__demux_1_1_reg\[245] -Removing Rhs of wire Net_449[250] = \demux_1:tmp__demux_1_2_reg\[246] -Removing Rhs of wire Net_443[251] = \demux_1:tmp__demux_1_3_reg\[247] -Removing Lhs of wire tmpOE__Pin_1_net_0[278] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_2_net_0[285] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_3_net_0[292] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__Pin_4_net_0[299] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \SPIM:BSPIM:dpcounter_one_reg\\D\[306] = \SPIM:BSPIM:dpcounter_one\[54] -Removing Lhs of wire \SPIM:BSPIM:so_send_reg\\D\[307] = \SPIM:BSPIM:so_send\[34] -Removing Lhs of wire \SPIM:BSPIM:mosi_reg\\D\[314] = \SPIM:BSPIM:mosi_pre_reg\[51] -Removing Lhs of wire \SPIM:BSPIM:mosi_from_dp_reg\\D\[316] = \SPIM:BSPIM:mosi_from_dp\[41] -Removing Lhs of wire \UART_1:BUART:reset_reg\\D\[320] = zero[3] -Removing Lhs of wire \UART_1:BUART:tx_bitclk\\D\[325] = \UART_1:BUART:tx_bitclk_enable_pre\[173] -Removing Lhs of wire Net_256D[326] = zero[3] +Removing Rhs of wire mywire_1_2[242] = \SS:control_out_2\[273] +Removing Rhs of wire mywire_1_2[242] = \SS:control_2\[282] +Removing Rhs of wire mywire_1_1[243] = \SS:control_out_1\[274] +Removing Rhs of wire mywire_1_1[243] = \SS:control_1\[283] +Removing Rhs of wire mywire_1_0[244] = \SS:control_out_0\[275] +Removing Rhs of wire mywire_1_0[244] = \SS:control_0\[284] +Removing Rhs of wire Net_590[253] = \demux_1:tmp__demux_1_0_reg\[241] +Removing Rhs of wire Net_591[254] = \demux_1:tmp__demux_1_1_reg\[246] +Removing Rhs of wire Net_592[255] = \demux_1:tmp__demux_1_2_reg\[247] +Removing Rhs of wire Net_594[256] = \demux_1:tmp__demux_1_3_reg\[248] +Removing Rhs of wire Net_596[257] = \demux_1:tmp__demux_1_4_reg\[249] +Removing Lhs of wire tmpOE__Pin_1_net_0[286] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_2_net_0[293] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_3_net_0[300] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_4_net_0[307] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire tmpOE__Pin_5_net_0[314] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire Net_12[320] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:ctrl_enable\[338] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:ctrl_cmode_1\[340] = zero[3] +Removing Rhs of wire \Timer_1:TimerUDB:timer_enable\[349] = \Timer_1:TimerUDB:runmode_enable\[361] +Removing Rhs of wire \Timer_1:TimerUDB:run_mode\[350] = \Timer_1:TimerUDB:hwEnable_reg\[351] +Removing Lhs of wire \Timer_1:TimerUDB:trigger_enable\[353] = tmpOE__m_miso_pin_net_0[2] +Removing Lhs of wire \Timer_1:TimerUDB:tc_i\[355] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:hwEnable\[357] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:capt_fifo_load_int\[360] = \Timer_1:TimerUDB:capt_fifo_load\[348] +Removing Lhs of wire \Timer_1:TimerUDB:status_6\[364] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_5\[365] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_4\[366] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:status_0\[367] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:status_1\[368] = \Timer_1:TimerUDB:capt_fifo_load\[348] +Removing Rhs of wire \Timer_1:TimerUDB:status_2\[369] = \Timer_1:TimerUDB:fifo_full\[370] +Removing Rhs of wire \Timer_1:TimerUDB:status_3\[371] = \Timer_1:TimerUDB:fifo_nempty\[372] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_2\[374] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_1\[375] = \Timer_1:TimerUDB:trig_reg\[363] +Removing Lhs of wire \Timer_1:TimerUDB:cs_addr_0\[376] = \Timer_1:TimerUDB:per_zero\[354] +Removing Lhs of wire \SPIM:BSPIM:dpcounter_one_reg\\D\[461] = \SPIM:BSPIM:dpcounter_one\[54] +Removing Lhs of wire \SPIM:BSPIM:so_send_reg\\D\[462] = \SPIM:BSPIM:so_send\[34] +Removing Lhs of wire \SPIM:BSPIM:mosi_reg\\D\[469] = \SPIM:BSPIM:mosi_pre_reg\[51] +Removing Lhs of wire \SPIM:BSPIM:mosi_from_dp_reg\\D\[471] = \SPIM:BSPIM:mosi_from_dp\[41] +Removing Lhs of wire \UART_1:BUART:reset_reg\\D\[475] = zero[3] +Removing Lhs of wire \UART_1:BUART:tx_bitclk\\D\[480] = \UART_1:BUART:tx_bitclk_enable_pre\[173] +Removing Lhs of wire Net_256D[481] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:capture_last\\D\[485] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:hwEnable_reg\\D\[486] = \Timer_1:TimerUDB:control_7\[330] +Removing Lhs of wire \Timer_1:TimerUDB:tc_reg_i\\D\[487] = \Timer_1:TimerUDB:status_tc\[352] +Removing Lhs of wire \Timer_1:TimerUDB:capture_out_reg_i\\D\[488] = \Timer_1:TimerUDB:capt_fifo_load\[348] ------------------------------------------------------ -Aliased 0 equations, 62 wires. +Aliased 0 equations, 89 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -332,17 +398,26 @@ Note: Expanding virtual equation for '\UART_1:BUART:tx_counter_tc\' (cost = 0): Note: Expanding virtual equation for 'Net_438' (cost = 0): Net_438 <= (not Net_439); -Note: Expanding virtual equation for 'Net_444' (cost = 3): -Net_444 <= ((not Net_439 and not mywire_1_1 and not mywire_1_0)); +Note: Expanding virtual equation for 'Net_590' (cost = 4): +Net_590 <= ((not Net_439 and not mywire_1_2 and not mywire_1_1 and not mywire_1_0)); + +Note: Expanding virtual equation for 'Net_591' (cost = 4): +Net_591 <= ((not Net_439 and not mywire_1_2 and not mywire_1_1 and mywire_1_0)); -Note: Expanding virtual equation for 'Net_441' (cost = 3): -Net_441 <= ((not Net_439 and not mywire_1_1 and mywire_1_0)); +Note: Expanding virtual equation for 'Net_592' (cost = 4): +Net_592 <= ((not Net_439 and not mywire_1_2 and not mywire_1_0 and mywire_1_1)); -Note: Expanding virtual equation for 'Net_449' (cost = 3): -Net_449 <= ((not Net_439 and not mywire_1_0 and mywire_1_1)); +Note: Expanding virtual equation for 'Net_594' (cost = 4): +Net_594 <= ((not Net_439 and not mywire_1_2 and mywire_1_1 and mywire_1_0)); -Note: Expanding virtual equation for 'Net_443' (cost = 3): -Net_443 <= ((not Net_439 and mywire_1_1 and mywire_1_0)); +Note: Expanding virtual equation for 'Net_596' (cost = 4): +Net_596 <= ((not Net_439 and not mywire_1_1 and not mywire_1_0 and mywire_1_2)); + +Note: Expanding virtual equation for '\Timer_1:TimerUDB:fifo_load_polarized\' (cost = 0): +\Timer_1:TimerUDB:fifo_load_polarized\ <= ('0') ; + +Note: Expanding virtual equation for '\Timer_1:TimerUDB:status_tc\' (cost = 3): +\Timer_1:TimerUDB:status_tc\ <= ((\Timer_1:TimerUDB:run_mode\ and \Timer_1:TimerUDB:per_zero\)); Substituting virtuals - pass 2: @@ -351,7 +426,7 @@ Substituting virtuals - pass 2: ---------------------------------------------------------- Circuit simplification results: - Expanded 10 signals. + Expanded 13 signals. Turned 0 signals into soft nodes. Maximum default expansion cost was set at 5. ---------------------------------------------------------- @@ -359,10 +434,13 @@ Circuit simplification results: ------------------------------------------------------ Alias Detection ------------------------------------------------------ -Removing Lhs of wire \UART_1:BUART:tx_ctrl_mark_last\\D\[327] = \UART_1:BUART:tx_ctrl_mark_last\[231] +Aliasing \Timer_1:TimerUDB:capt_fifo_load\ to zero +Removing Lhs of wire \Timer_1:TimerUDB:capt_fifo_load\[348] = zero[3] +Removing Lhs of wire \Timer_1:TimerUDB:trig_reg\[363] = \Timer_1:TimerUDB:timer_enable\[349] +Removing Lhs of wire \UART_1:BUART:tx_ctrl_mark_last\\D\[482] = \UART_1:BUART:tx_ctrl_mark_last\[231] ------------------------------------------------------ -Aliased 0 equations, 1 wires. +Aliased 0 equations, 3 wires. ------------------------------------------------------ ---------------------------------------------------------- @@ -390,21 +468,24 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog +Warp Arguments : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -dcpsoc3 PSOC5_SPI_LSM303D.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.794ms +Warp synthesis phase: Elapsed time ==> 2s.217ms -cyp3fit: V2.2.0.293, Family: PSoC3, Started at: Friday, 22 March 2013 10:33:25 -Options: -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 PSOC5_SPI_LSM303D.v -verilog +cyp3fit: V2.2.0.572, Family: PSoC3, Started at: Thursday, 25 July 2013 16:48:55 +Options: -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -d CY8C5568AXI-060 PSOC5_SPI_LSM303D.v -verilog -Design parsing phase: Elapsed time ==> 0s.020ms +Design parsing phase: Elapsed time ==> 0s.025ms Converted constant MacroCell: Net_256 from registered to combinatorial + Converted constant MacroCell: \Timer_1:TimerUDB:capture_last\ from registered to combinatorial + Converted constant MacroCell: \Timer_1:TimerUDB:capture_out_reg_i\ from registered to combinatorial Converted constant MacroCell: \UART_1:BUART:reset_reg\ from registered to combinatorial +Assigning clock timer_clock to clock ILO because it is a pass-through Digital Clock 0: Automatic-assigning clock 'SPIM_IntClock'. Fanout=1, Signal=\SPIM:Net_276\ Digital Clock 1: Automatic-assigning clock 'Clock_1'. Fanout=1, Signal=Net_191 @@ -414,6 +495,9 @@ Removing unused cells resulting from optimization Removed unused cell/equation 'Net_256:macrocell' Removed unused cell/equation '\SPIM:BSPIM:mosi_reg\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:so_send_reg\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:capture_last\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:capture_out_reg_i\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:tc_reg_i\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:so_send\:macrocell' Done removing unused cells. @@ -421,6 +505,10 @@ Done removing unused cells. ClockIn: SPIM_IntClock was determined to be a global clock that is synchronous to BUS_CLK EnableIn: Constant 1 was determined to be synchronous to ClockIn ClockOut: SPIM_IntClock, EnableOut: Constant 1 + UDB Clk/Enable \Timer_1:TimerUDB:clock_enable_block\: with output requested to be synchronous + ClockIn: ILO was determined to be a routed clock that is asynchronous + EnableIn: Constant 1 was determined to be synchronous to ClockIn + ClockOut: BUS_CLK, EnableOut: ClockBlock_1k__SYNC:synccell.out UDB Clk/Enable \UART_1:BUART:ClkSync\: with output requested to be synchronous ClockIn: Clock_1 was determined to be a global clock that is synchronous to BUS_CLK EnableIn: Constant 1 was determined to be synchronous to ClockIn @@ -439,6 +527,8 @@ Removing unused cells resulting from optimization Removed unused cell/equation '\SPIM:BSPIM:state_0\\D\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:state_1\\D\:macrocell' Removed unused cell/equation '\SPIM:BSPIM:state_2\\D\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:runmode_enable\\D\:macrocell' + Removed unused cell/equation '\Timer_1:TimerUDB:trig_disable\\D\:macrocell' Removed unused cell/equation '\UART_1:BUART:reset_reg\:macrocell' Removed unused cell/equation '\UART_1:BUART:tx_mark\\D\:macrocell' Removed unused cell/equation '\UART_1:BUART:tx_parity_bit\\D\:macrocell' @@ -653,6 +743,45 @@ Design Equations { } + Pin : Name = Pin_5(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Pin_5(0)__PA , + input => Net_585 , + pad => Pin_5(0)_PAD ); + Properties: + { + } + Pin : Name = Tx_1(0) Attributes: In Group/Port: True @@ -1102,42 +1231,42 @@ Design Equations Output = Net_30 (fanout=1) MacroCell: Name=Net_419, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * !mywire_1_1 * !mywire_1_0 + !Net_439 * !mywire_1_2 * !mywire_1_1 * !mywire_1_0 ); Output = Net_419 (fanout=1) MacroCell: Name=Net_422, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * !mywire_1_1 * mywire_1_0 + !Net_439 * !mywire_1_2 * !mywire_1_1 * mywire_1_0 ); Output = Net_422 (fanout=1) MacroCell: Name=Net_425, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * mywire_1_1 * mywire_1_0 + !Net_439 * !mywire_1_2 * mywire_1_1 * mywire_1_0 ); Output = Net_425 (fanout=1) MacroCell: Name=Net_428, Mode=(Combinatorial) - Total # of inputs : 3 + Total # of inputs : 4 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm !( - !Net_439 * mywire_1_1 * !mywire_1_0 + !Net_439 * !mywire_1_2 * mywire_1_1 * !mywire_1_0 ); Output = Net_428 (fanout=1) @@ -1156,7 +1285,7 @@ Design Equations + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * !Net_439 ); - Output = Net_439 (fanout=6) + Output = Net_439 (fanout=7) MacroCell: Name=Net_479, Mode=(D-Register) Total # of inputs : 4 @@ -1174,6 +1303,16 @@ Design Equations ); Output = Net_479 (fanout=2) + MacroCell: Name=Net_585, Mode=(Combinatorial) + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_585 (fanout=1) + MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) Total # of inputs : 10 Total # of product terms : 4 @@ -1435,6 +1574,58 @@ Design Equations ); Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) + MacroCell: Name=\Timer_1:TimerUDB:run_mode\, Mode=(D-Register) + Total # of inputs : 1 + Total # of product terms : 1 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:control_7\ + ); + Output = \Timer_1:TimerUDB:run_mode\ (fanout=3) + + MacroCell: Name=\Timer_1:TimerUDB:status_tc\, Mode=(Combinatorial) + Total # of inputs : 2 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:run_mode\ * \Timer_1:TimerUDB:per_zero\ + ); + Output = \Timer_1:TimerUDB:status_tc\ (fanout=1) + + MacroCell: Name=\Timer_1:TimerUDB:timer_enable\, Mode=(D-Register) + Total # of inputs : 5 + Total # of product terms : 3 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 3 pterms + ( + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:timer_enable\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:run_mode\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:per_zero\ * + !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:timer_enable\ (fanout=4) + + MacroCell: Name=\Timer_1:TimerUDB:trig_disable\, Mode=(T-Register) + Total # of inputs : 4 + Total # of product terms : 1 + List of special equations: + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:timer_enable\ * \Timer_1:TimerUDB:run_mode\ * + \Timer_1:TimerUDB:per_zero\ * !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:trig_disable\ (fanout=2) + MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) Total # of inputs : 4 Total # of product terms : 2 @@ -1612,6 +1803,79 @@ Design Equations Clock Polarity: Active High Clock Enable: True + datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u0\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + chain_out => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Next in chain : \Timer_1:TimerUDB:sT16:timerdp:u1\ + + datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u1\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + z0_comb => \Timer_1:TimerUDB:per_zero\ , + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\ , + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\ , + chain_in => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Previous in chain : \Timer_1:TimerUDB:sT16:timerdp:u0\ + datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ PORT MAP ( clock => Net_191 , @@ -1721,6 +1985,22 @@ Design Equations Clock Polarity: Active High Clock Enable: True + statusicell: Name =\Timer_1:TimerUDB:nrstSts:stsreg\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + status_3 => \Timer_1:TimerUDB:status_3\ , + status_2 => \Timer_1:TimerUDB:status_2\ , + status_0 => \Timer_1:TimerUDB:status_tc\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "1111111" + cy_md_select = "0000011" + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + statusicell: Name =\UART_1:BUART:sTX:TxSts\ PORT MAP ( clock => Net_191 , @@ -1738,6 +2018,18 @@ Design Equations Clock Enable: True + + ------------------------------------------------------------ + Sync listing + ------------------------------------------------------------ + + synccell: Name =ClockBlock_1k__SYNC + PORT MAP ( + in => ClockBlock_1k , + out => ClockBlock_1k__SYNC_OUT , + clock => ClockBlock_BUS_CLK ); + Clock Polarity: Active High + Clock Enable: True @@ -1752,7 +2044,7 @@ Design Equations control_5 => \SS:control_5\ , control_4 => \SS:control_4\ , control_3 => \SS:control_3\ , - control_2 => \SS:control_2\ , + control_2 => mywire_1_2 , control_1 => mywire_1_1 , control_0 => mywire_1_0 ); Properties: @@ -1764,6 +2056,26 @@ Design Equations cy_init_value = "00000000" } Clock Enable: True + + controlcell: Name =\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ + PORT MAP ( + control_7 => \Timer_1:TimerUDB:control_7\ , + control_6 => \Timer_1:TimerUDB:control_6\ , + control_5 => \Timer_1:TimerUDB:control_5\ , + control_4 => \Timer_1:TimerUDB:control_4\ , + control_3 => \Timer_1:TimerUDB:control_3\ , + control_2 => \Timer_1:TimerUDB:control_2\ , + control_1 => \Timer_1:TimerUDB:control_1\ , + control_0 => \Timer_1:TimerUDB:control_0\ ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True @@ -1809,15 +2121,16 @@ Resource Type : Used : Free : Max : % Used ============================================================ Digital domain clock dividers : 2 : 6 : 8 : 25.00% Analog domain clock dividers : 0 : 4 : 4 : 0.00% -Pins : 18 : 52 : 70 : 25.71% -UDB Macrocells : 32 : 160 : 192 : 16.67% -UDB Unique Pterms : 67 : 317 : 384 : 17.45% -UDB Total Pterms : 74 : : : -UDB Datapath Cells : 3 : 21 : 24 : 12.50% -UDB Status Cells : 3 : 21 : 24 : 12.50% - StatusI Registers : 3 -UDB Control Cells : 2 : 22 : 24 : 8.33% - Control Registers : 1 +Pins : 19 : 51 : 70 : 27.14% +UDB Macrocells : 37 : 155 : 192 : 19.27% +UDB Unique Pterms : 74 : 310 : 384 : 19.27% +UDB Total Pterms : 81 : : : +UDB Datapath Cells : 5 : 19 : 24 : 20.83% +UDB Status Cells : 5 : 19 : 24 : 20.83% + StatusI Registers : 4 + Sync Cells : 1 (in 1 status cell) +UDB Control Cells : 3 : 21 : 24 : 12.50% + Control Registers : 2 Count7 Cells : 1 DMA Channels : 0 : 24 : 24 : 0.00% Interrupts : 0 : 32 : 32 : 0.00% @@ -1838,9 +2151,9 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 2 : 2 : 0.00% -Technology Mapping: Elapsed time ==> 0s.099ms +Technology Mapping: Elapsed time ==> 0s.051ms Info: mpr.M0037: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details. (App=cydsfit) -Tech mapping phase: Elapsed time ==> 0s.210ms +Tech mapping phase: Elapsed time ==> 0s.220ms Initial Analog Placement Results: @@ -1848,6 +2161,7 @@ IO_0@[IOP=(3)][IoId=(0)] : Pin_1(0) (fixed) IO_1@[IOP=(3)][IoId=(1)] : Pin_2(0) (fixed) IO_2@[IOP=(3)][IoId=(2)] : Pin_3(0) (fixed) IO_3@[IOP=(3)][IoId=(3)] : Pin_4(0) (fixed) +IO_4@[IOP=(3)][IoId=(4)] : Pin_5(0) (fixed) IO_7@[IOP=(3)][IoId=(7)] : Tx_1(0) (fixed) IO_0@[IOP=(2)][IoId=(0)] : \LCD:LCDPort(0)\ (fixed) IO_1@[IOP=(2)][IoId=(1)] : \LCD:LCDPort(1)\ (fixed) @@ -1859,10 +2173,10 @@ IO_6@[IOP=(2)][IoId=(6)] : \LCD:LCDPort(6)\ (fixed) IO_0@[IOP=(0)][IoId=(0)] : m_miso_pin(0) (fixed) IO_5@[IOP=(0)][IoId=(5)] : m_mosi_pin(0) (fixed) IO_6@[IOP=(0)][IoId=(6)] : m_sclk_pin(0) (fixed) -Analog Placement phase: Elapsed time ==> 0s.053ms +Analog Placement phase: Elapsed time ==> 0s.052ms -Analog Routing phase: Elapsed time ==> 0s.000ms +Analog Routing phase: Elapsed time ==> 0s.001ms ============ Analog Final Answer Routes ============ @@ -1877,7 +2191,7 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 0s.435ms +Analog Code Generation phase: Elapsed time ==> 0s.614ms @@ -1888,33 +2202,33 @@ PLD Packing Summary ------------------------------------------------------------ Resource Type : Used : Free : Max : % Used ==================================================== - PLDs : 11 : 37 : 48 : 22.92% + PLDs : 13 : 35 : 48 : 27.08% PLD Resource Type : Average/LAB ======================================= - Inputs : 7.82 - Pterms : 6.36 - Macrocells : 2.91 + Inputs : 7.46 + Pterms : 6.00 + Macrocells : 2.85 Packed PLD Contents not displayed at this verbose level. -PLD Packing: Elapsed time ==> 0s.001ms +PLD Packing: Elapsed time ==> 0s.003ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.043ms +Partitioning: Elapsed time ==> 0s.059ms Annealing: Elapsed time ==> 0s.002ms The seed used for moves was 114161200. -Inital cost was 248, final cost is 248 (0.00% improvement). +Inital cost was 261, final cost is 261 (0.00% improvement). @@ -1924,7 +2238,7 @@ Final Placement Summary Resource Type : Count : Avg Inputs : Avg Outputs ======================================================== - UDB : 6 : 10.50 : 5.33 + UDB : 8 : 9.13 : 4.63 @@ -1943,174 +2257,297 @@ UDB [UDB=(1,2)] is empty. UDB [UDB=(1,3)] is empty. UDB [UDB=(1,4)] is empty. UDB [UDB=(1,5)] is empty. -UDB [UDB=(2,0)] is empty. -UDB [UDB=(2,1)] is empty. -UDB [UDB=(2,2)] is empty. -UDB [UDB=(2,3)] contents: -LAB@[UDB=(2,3)][LB=0] #macrocells=3, #inputs=11, #pterms=8 +UDB [UDB=(2,0)] contents: +LAB@[UDB=(2,0)][LB=0] #macrocells=4, #inputs=5, #pterms=6 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(2,3)][LB=0][MC=0] - Total # of inputs : 10 - Total # of product terms : 4 + [McSlotId=0]: MacroCell: Name=\Timer_1:TimerUDB:timer_enable\, Mode=(D-Register) @ [UDB=(2,0)][LB=0][MC=0] + Total # of inputs : 5 + Total # of product terms : 3 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 3 pterms ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:cnt_enable\ - ); - Output = \SPIM:BSPIM:cnt_enable\ (fanout=3) + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:timer_enable\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:run_mode\ * + !\Timer_1:TimerUDB:trig_disable\ + + \Timer_1:TimerUDB:control_7\ * !\Timer_1:TimerUDB:per_zero\ * + !\Timer_1:TimerUDB:trig_disable\ + ); + Output = \Timer_1:TimerUDB:timer_enable\ (fanout=4) Properties : { } - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(2,3)][LB=0][MC=1] - Total # of inputs : 10 - Total # of product terms : 4 + [McSlotId=1]: MacroCell: Name=\Timer_1:TimerUDB:trig_disable\, Mode=(T-Register) @ [UDB=(2,0)][LB=0][MC=1] + Total # of inputs : 4 + Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - \SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm + ( + \Timer_1:TimerUDB:timer_enable\ * \Timer_1:TimerUDB:run_mode\ * + \Timer_1:TimerUDB:per_zero\ * !\Timer_1:TimerUDB:trig_disable\ ); - Output = \SPIM:BSPIM:state_1\ (fanout=14) + Output = \Timer_1:TimerUDB:trig_disable\ (fanout=2) Properties : { } - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=2] - Total # of inputs : 3 + [McSlotId=2]: MacroCell: Name=\Timer_1:TimerUDB:status_tc\, Mode=(Combinatorial) @ [UDB=(2,0)][LB=0][MC=2] + Total # of inputs : 2 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ + \Timer_1:TimerUDB:run_mode\ * \Timer_1:TimerUDB:per_zero\ ); - Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) + Output = \Timer_1:TimerUDB:status_tc\ (fanout=1) Properties : { } - [McSlotId=3]: (empty) -} - -LAB@[UDB=(2,3)][LB=1] #macrocells=4, #inputs=10, #pterms=8 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(2,3)][LB=1][MC=0] - Total # of inputs : 9 - Total # of product terms : 4 + [McSlotId=3]: MacroCell: Name=\Timer_1:TimerUDB:run_mode\, Mode=(D-Register) @ [UDB=(2,0)][LB=0][MC=3] + Total # of inputs : 1 + Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms + Clock = (ClockBlock_BUS_CLK) => Global + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Main Equation : 1 pterm ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ + \Timer_1:TimerUDB:control_7\ ); - Output = \SPIM:BSPIM:load_cond\ (fanout=1) + Output = \Timer_1:TimerUDB:run_mode\ (fanout=3) Properties : { } +} - [McSlotId=1]: MacroCell: Name=Net_479, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=1] - Total # of inputs : 4 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - !( - !Net_479 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = Net_479 (fanout=2) +datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u0\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + chain_out => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Next in chain : \Timer_1:TimerUDB:sT16:timerdp:u1\ + +statusicell: Name =\Timer_1:TimerUDB:nrstSts:stsreg\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + status_3 => \Timer_1:TimerUDB:status_3\ , + status_2 => \Timer_1:TimerUDB:status_2\ , + status_0 => \Timer_1:TimerUDB:status_tc\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "1111111" + cy_md_select = "0000011" + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + +controlcell: Name =\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ + PORT MAP ( + control_7 => \Timer_1:TimerUDB:control_7\ , + control_6 => \Timer_1:TimerUDB:control_6\ , + control_5 => \Timer_1:TimerUDB:control_5\ , + control_4 => \Timer_1:TimerUDB:control_4\ , + control_3 => \Timer_1:TimerUDB:control_3\ , + control_2 => \Timer_1:TimerUDB:control_2\ , + control_1 => \Timer_1:TimerUDB:control_1\ , + control_0 => \Timer_1:TimerUDB:control_0\ ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True + +UDB [UDB=(2,1)] is empty. +UDB [UDB=(2,2)] is empty. +UDB [UDB=(2,3)] contents: +LAB@[UDB=(2,3)][LB=0] #macrocells=3, #inputs=11, #pterms=6 +{ + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=0] + Total # of inputs : 6 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ + ); + Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) Properties : { } - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=2] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_0\, Mode=(T-Register) @ [UDB=(2,3)][LB=0][MC=1] + Total # of inputs : 5 + Total # of product terms : 4 + List of special equations: + Clock = (Net_191) => Global + Clock Enable: True + Main Equation : 4 pterms + ( + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + !\UART_1:BUART:tx_fifo_empty\ * !\UART_1:BUART:tx_state_2\ + + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + !\UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ + ); + Output = \UART_1:BUART:tx_state_0\ (fanout=7) + Properties : + { + } + + [McSlotId=2]: (empty) + [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_0\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=0][MC=3] Total # of inputs : 5 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ + ); + Output = \UART_1:BUART:tx_status_0\ (fanout=1) + Properties : + { + } +} + +LAB@[UDB=(2,3)][LB=1] #macrocells=3, #inputs=2, #pterms=2 +{ + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_bitclk\, Mode=(D-Register) @ [UDB=(2,3)][LB=1][MC=0] + Total # of inputs : 1 Total # of product terms : 1 List of special equations: - Clock = (\SPIM:Net_276\) => Global + Clock = (Net_191) => Global Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ + !\UART_1:BUART:tx_bitclk_dp\ ); - Output = \SPIM:BSPIM:load_rx_data\ (fanout=1) + Output = \UART_1:BUART:tx_bitclk\ (fanout=6) Properties : { } - [McSlotId=3]: MacroCell: Name=\SPIM:BSPIM:dpcounter_one\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=3] - Total # of inputs : 5 + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_bitclk_enable_pre\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=1] + Total # of inputs : 1 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ + !\UART_1:BUART:tx_bitclk_dp\ ); - Output = \SPIM:BSPIM:dpcounter_one\ (fanout=1) + Output = \UART_1:BUART:tx_bitclk_enable_pre\ (fanout=1) + Properties : + { + } + + [McSlotId=2]: (empty) + [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_2\, Mode=(Combinatorial) @ [UDB=(2,3)][LB=1][MC=3] + Total # of inputs : 1 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:tx_fifo_notfull\ + ); + Output = \UART_1:BUART:tx_status_2\ (fanout=1) Properties : { } } -statusicell: Name =\SPIM:BSPIM:TxStsReg\ +datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ PORT MAP ( - clock => \SPIM:Net_276\ , - status_4 => \SPIM:BSPIM:tx_status_4\ , - status_3 => \SPIM:BSPIM:dpcounter_one\ , - status_2 => \SPIM:BSPIM:tx_status_2\ , - status_1 => \SPIM:BSPIM:tx_status_1\ , - status_0 => \SPIM:BSPIM:tx_status_0\ ); + clock => Net_191 , + cs_addr_2 => \UART_1:BUART:tx_state_1\ , + cs_addr_1 => \UART_1:BUART:tx_state_0\ , + cs_addr_0 => \UART_1:BUART:tx_bitclk_enable_pre\ , + so_comb => \UART_1:BUART:tx_shift_out\ , + f0_bus_stat_comb => \UART_1:BUART:tx_fifo_notfull\ , + f0_blk_stat_comb => \UART_1:BUART:tx_fifo_empty\ ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000000000000000000000000000000000000000000000000000011000000000000000000000000000010010000000000000000000000000000000000000011111111000000001111111111111111000000000000000001000100111100000000000000001100" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: True + +statusicell: Name =\UART_1:BUART:sTX:TxSts\ + PORT MAP ( + clock => Net_191 , + status_3 => \UART_1:BUART:tx_fifo_notfull\ , + status_2 => \UART_1:BUART:tx_status_2\ , + status_1 => \UART_1:BUART:tx_fifo_empty\ , + status_0 => \UART_1:BUART:tx_status_0\ ); Properties: { cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "0001001" + cy_int_mask = "1111111" + cy_md_select = "0000001" } Clock Polarity: Active High Clock Enable: True @@ -2298,190 +2735,106 @@ count7cell: Name =\SPIM:BSPIM:BitCounter\ Clock Enable: True UDB [UDB=(2,5)] contents: -LAB@[UDB=(2,5)][LB=0] #macrocells=4, #inputs=12, #pterms=8 +LAB@[UDB=(2,5)][LB=0] #macrocells=3, #inputs=11, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=0] - Total # of inputs : 6 - Total # of product terms : 1 + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=0] + Total # of inputs : 10 + Total # of product terms : 4 + List of special equations: + Clock = (\SPIM:Net_276\) => Global Clock Enable: True - Main Equation : 1 pterm + Main Equation : 4 pterms ( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ * + \SPIM:BSPIM:cnt_enable\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * + \SPIM:BSPIM:cnt_enable\ ); - Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) + Output = \SPIM:BSPIM:cnt_enable\ (fanout=3) Properties : { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_0\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=1] - Total # of inputs : 5 + [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(2,5)][LB=0][MC=1] + Total # of inputs : 10 Total # of product terms : 4 List of special equations: - Clock = (Net_191) => Global + Clock = (\SPIM:Net_276\) => Global Clock Enable: True Main Equation : 4 pterms - ( - !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - !\UART_1:BUART:tx_fifo_empty\ * !\UART_1:BUART:tx_state_2\ - + !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - !\UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_state_0\ (fanout=7) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\UART_1:BUART:tx_state_1\, Mode=(T-Register) @ [UDB=(2,5)][LB=0][MC=2] - Total # of inputs : 5 - Total # of product terms : 3 - List of special equations: - Clock = (Net_191) => Global - Clock Enable: True - Main Equation : 3 pterms - ( - \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_bitclk\ - + \UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ * !\UART_1:BUART:tx_counter_dp\ - + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_state_1\ (fanout=7) - Properties : - { - } - - [McSlotId=3]: MacroCell: Name=\UART_1:BUART:tx_status_0\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=3] - Total # of inputs : 5 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_0\ * - \UART_1:BUART:tx_fifo_empty\ * \UART_1:BUART:tx_state_2\ * - \UART_1:BUART:tx_bitclk\ - ); - Output = \UART_1:BUART:tx_status_0\ (fanout=1) - Properties : - { - } -} - -LAB@[UDB=(2,5)][LB=1] #macrocells=2, #inputs=1, #pterms=1 -{ - [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_bitclk\, Mode=(D-Register) @ [UDB=(2,5)][LB=1][MC=0] - Total # of inputs : 1 - Total # of product terms : 1 - List of special equations: - Clock = (Net_191) => Global - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:tx_bitclk_dp\ + !( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:is_spi_done\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ + + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + \SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ ); - Output = \UART_1:BUART:tx_bitclk\ (fanout=6) + Output = \SPIM:BSPIM:state_1\ (fanout=14) Properties : { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_bitclk_enable_pre\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=1][MC=1] - Total # of inputs : 1 + [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=0][MC=2] + Total # of inputs : 3 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm ( - !\UART_1:BUART:tx_bitclk_dp\ + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ ); - Output = \UART_1:BUART:tx_bitclk_enable_pre\ (fanout=1) + Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) Properties : { } - [McSlotId=2]: (empty) [McSlotId=3]: (empty) } -datapathcell: Name =\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ - PORT MAP ( - clock => Net_191 , - cs_addr_0 => \UART_1:BUART:counter_load_not\ , - cl0_comb => \UART_1:BUART:tx_bitclk_dp\ , - cl1_comb => \UART_1:BUART:tx_counter_dp\ ); - Properties: - { - a0_init = "00000000" - a1_init = "00000000" - ce0_sync = 1 - ce1_sync = 1 - cl0_sync = 1 - cl1_sync = 1 - cmsb_sync = 1 - co_msb_sync = 1 - cy_dpconfig = "1010100001000000001000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000001111111100000111001000000100000000000101111100000000000000001000" - d0_init = "00000000" - d1_init = "00000000" - f0_blk_sync = 1 - f0_bus_sync = 1 - f1_blk_sync = 1 - f1_bus_sync = 1 - ff0_sync = 1 - ff1_sync = 1 - ov_msb_sync = 1 - so_sync = 1 - z0_sync = 1 - z1_sync = 1 - } - Clock Polarity: Active High - Clock Enable: True - -statusicell: Name =\SPIM:BSPIM:RxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_6 => \SPIM:BSPIM:rx_status_6\ , - status_5 => \SPIM:BSPIM:rx_status_5\ , - status_4 => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "1000000" - } - Clock Polarity: Active High - Clock Enable: True - -UDB [UDB=(3,0)] is empty. -UDB [UDB=(3,1)] is empty. -UDB [UDB=(3,2)] is empty. -UDB [UDB=(3,3)] contents: -LAB@[UDB=(3,3)][LB=0] #macrocells=4, #inputs=8, #pterms=7 +LAB@[UDB=(2,5)][LB=1] #macrocells=4, #inputs=10, #pterms=7 { - [McSlotId=0]: MacroCell: Name=Net_439, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=0] - Total # of inputs : 4 - Total # of product terms : 3 + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(2,5)][LB=1][MC=0] + Total # of inputs : 9 + Total # of product terms : 4 List of special equations: Clock = (\SPIM:Net_276\) => Global Clock Enable: True - Main Equation : 3 pterms + Main Equation : 4 pterms ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !Net_439 - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * Net_439 - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !Net_439 + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ + + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * + !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * + !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * + \SPIM:BSPIM:load_cond\ ); - Output = Net_439 (fanout=6) + Output = \SPIM:BSPIM:load_cond\ (fanout=1) Properties : { } - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:ld_ident\, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=1] + [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:ld_ident\, Mode=(T-Register) @ [UDB=(2,5)][LB=1][MC=1] Total # of inputs : 4 Total # of product terms : 2 List of special equations: @@ -2499,164 +2852,139 @@ LAB@[UDB=(3,3)][LB=0] #macrocells=4, #inputs=8, #pterms=7 { } - [McSlotId=2]: MacroCell: Name=Net_30, Mode=(Combinatorial) @ [UDB=(3,3)][LB=0][MC=2] - Total # of inputs : 2 + [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(D-Register) @ [UDB=(2,5)][LB=1][MC=2] + Total # of inputs : 5 Total # of product terms : 1 + List of special equations: + Clock = (\SPIM:Net_276\) => Global Clock Enable: True Main Equation : 1 pterm ( - !Net_439 * \SPIM:BSPIM:mosi_hs_reg\ - ); - Output = Net_30 (fanout=1) - Properties : - { - } - - [McSlotId=3]: MacroCell: Name=Net_419, Mode=(Combinatorial) @ [UDB=(3,3)][LB=0][MC=3] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * !mywire_1_1 * !mywire_1_0 - ); - Output = Net_419 (fanout=1) - Properties : - { - } -} - -LAB@[UDB=(3,3)][LB=1] #macrocells=3, #inputs=3, #pterms=3 -{ - [McSlotId=0]: MacroCell: Name=Net_422, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=0] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * !mywire_1_1 * mywire_1_0 - ); - Output = Net_422 (fanout=1) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_425, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=1] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - !( - !Net_439 * mywire_1_1 * mywire_1_0 + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ ); - Output = Net_425 (fanout=1) + Output = \SPIM:BSPIM:load_rx_data\ (fanout=1) Properties : { } - [McSlotId=2]: MacroCell: Name=Net_428, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=2] - Total # of inputs : 3 + [McSlotId=3]: MacroCell: Name=\SPIM:BSPIM:dpcounter_one\, Mode=(Combinatorial) @ [UDB=(2,5)][LB=1][MC=3] + Total # of inputs : 5 Total # of product terms : 1 Clock Enable: True Main Equation : 1 pterm - !( - !Net_439 * mywire_1_1 * !mywire_1_0 + ( + !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * + !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * + \SPIM:BSPIM:count_0\ ); - Output = Net_428 (fanout=1) + Output = \SPIM:BSPIM:dpcounter_one\ (fanout=1) Properties : { } - - [McSlotId=3]: (empty) } -controlcell: Name =\SS:Async:ctrl_reg\ +statusicell: Name =\SPIM:BSPIM:TxStsReg\ PORT MAP ( - control_7 => \SS:control_7\ , - control_6 => \SS:control_6\ , - control_5 => \SS:control_5\ , - control_4 => \SS:control_4\ , - control_3 => \SS:control_3\ , - control_2 => \SS:control_2\ , - control_1 => mywire_1_1 , - control_0 => mywire_1_0 ); + clock => \SPIM:Net_276\ , + status_4 => \SPIM:BSPIM:tx_status_4\ , + status_3 => \SPIM:BSPIM:dpcounter_one\ , + status_2 => \SPIM:BSPIM:tx_status_2\ , + status_1 => \SPIM:BSPIM:tx_status_1\ , + status_0 => \SPIM:BSPIM:tx_status_0\ ); Properties: { - cy_ctrl_mode_0 = "00000000" - cy_ctrl_mode_1 = "00000000" - cy_ext_reset = 0 cy_force_order = 1 - cy_init_value = "00000000" + cy_int_mask = "0000000" + cy_md_select = "0001001" } + Clock Polarity: Active High Clock Enable: True -UDB [UDB=(3,4)] contents: -LAB@[UDB=(3,4)][LB=0] #macrocells=3, #inputs=3, #pterms=3 +UDB [UDB=(3,0)] contents: +LAB@[UDB=(3,0)][LB=1] #macrocells=1, #inputs=5, #pterms=3 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_from_dp_reg\, Mode=(D-Register) @ [UDB=(3,4)][LB=0][MC=0] - Total # of inputs : 1 - Total # of product terms : 1 + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:tx_state_1\, Mode=(T-Register) @ [UDB=(3,0)][LB=1][MC=0] + Total # of inputs : 5 + Total # of product terms : 3 List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 1 pterm - ( - \SPIM:BSPIM:mosi_from_dp\ - ); - Output = \SPIM:BSPIM:mosi_from_dp_reg\ (fanout=1) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_234, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=1] - Total # of inputs : 1 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\UART_1:BUART:txn\ - ); - Output = Net_234 (fanout=1) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\UART_1:BUART:tx_status_2\, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=2] - Total # of inputs : 1 - Total # of product terms : 1 + Clock = (Net_191) => Global Clock Enable: True - Main Equation : 1 pterm + Main Equation : 3 pterms ( - !\UART_1:BUART:tx_fifo_notfull\ + \UART_1:BUART:tx_state_1\ * \UART_1:BUART:tx_state_0\ * + \UART_1:BUART:tx_bitclk\ + + \UART_1:BUART:tx_state_1\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ * !\UART_1:BUART:tx_counter_dp\ + + \UART_1:BUART:tx_state_0\ * !\UART_1:BUART:tx_state_2\ * + \UART_1:BUART:tx_bitclk\ ); - Output = \UART_1:BUART:tx_status_2\ (fanout=1) + Output = \UART_1:BUART:tx_state_1\ (fanout=7) Properties : { } + [McSlotId=1]: (empty) + [McSlotId=2]: (empty) [McSlotId=3]: (empty) } -statusicell: Name =\UART_1:BUART:sTX:TxSts\ +datapathcell: Name =\Timer_1:TimerUDB:sT16:timerdp:u1\ + PORT MAP ( + clock => ClockBlock_BUS_CLK , + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\ , + cs_addr_0 => \Timer_1:TimerUDB:per_zero\ , + z0_comb => \Timer_1:TimerUDB:per_zero\ , + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\ , + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\ , + chain_in => \Timer_1:TimerUDB:sT16:timerdp:carry\ , + clk_en => ClockBlock_1k__SYNC_OUT ); + Properties: + { + a0_init = "00000000" + a1_init = "00000000" + ce0_sync = 1 + ce1_sync = 1 + cl0_sync = 1 + cl1_sync = 1 + cmsb_sync = 1 + co_msb_sync = 1 + cy_dpconfig = "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000" + d0_init = "00000000" + d1_init = "00000000" + f0_blk_sync = 1 + f0_bus_sync = 1 + f1_blk_sync = 1 + f1_bus_sync = 1 + ff0_sync = 1 + ff1_sync = 1 + ov_msb_sync = 1 + so_sync = 1 + z0_sync = 1 + z1_sync = 1 + } + Clock Polarity: Active High + Clock Enable: PosEdge(ClockBlock_1k__SYNC_OUT) + Previous in chain : \Timer_1:TimerUDB:sT16:timerdp:u0\ + +synccell: Name =ClockBlock_1k__SYNC PORT MAP ( - clock => Net_191 , - status_3 => \UART_1:BUART:tx_fifo_notfull\ , - status_2 => \UART_1:BUART:tx_status_2\ , - status_1 => \UART_1:BUART:tx_fifo_empty\ , - status_0 => \UART_1:BUART:tx_status_0\ ); + in => ClockBlock_1k , + out => ClockBlock_1k__SYNC_OUT , + clock => ClockBlock_BUS_CLK ); Properties: { - cy_force_order = 1 - cy_int_mask = "1111111" - cy_md_select = "0000001" } Clock Polarity: Active High Clock Enable: True -UDB [UDB=(3,5)] contents: -LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 +UDB [UDB=(3,1)] is empty. +UDB [UDB=(3,2)] is empty. +UDB [UDB=(3,3)] contents: +LAB@[UDB=(3,3)][LB=0] #macrocells=2, #inputs=7, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\UART_1:BUART:txn\, Mode=(D-Register) @ [UDB=(3,5)][LB=0][MC=0] + [McSlotId=0]: MacroCell: Name=\UART_1:BUART:txn\, Mode=(D-Register) @ [UDB=(3,3)][LB=0][MC=0] Total # of inputs : 7 Total # of product terms : 5 List of special equations: @@ -2680,7 +3008,7 @@ LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_2\, Mode=(T-Register) @ [UDB=(3,5)][LB=0][MC=1] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:tx_state_2\, Mode=(T-Register) @ [UDB=(3,3)][LB=0][MC=1] Total # of inputs : 5 Total # of product terms : 3 List of special equations: @@ -2704,9 +3032,9 @@ LAB@[UDB=(3,5)][LB=0] #macrocells=2, #inputs=7, #pterms=8 [McSlotId=3]: (empty) } -LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 +LAB@[UDB=(3,3)][LB=1] #macrocells=2, #inputs=10, #pterms=8 { - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_hs_reg\, Mode=(D-Register) @ [UDB=(3,5)][LB=1][MC=0] + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_hs_reg\, Mode=(D-Register) @ [UDB=(3,3)][LB=1][MC=0] Total # of inputs : 6 Total # of product terms : 6 List of special equations: @@ -2732,7 +3060,7 @@ LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 { } - [McSlotId=1]: MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=1] + [McSlotId=1]: MacroCell: Name=\UART_1:BUART:counter_load_not\, Mode=(Combinatorial) @ [UDB=(3,3)][LB=1][MC=1] Total # of inputs : 4 Total # of product terms : 2 Clock Enable: True @@ -2752,15 +3080,12 @@ LAB@[UDB=(3,5)][LB=1] #macrocells=2, #inputs=10, #pterms=8 [McSlotId=3]: (empty) } -datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ +datapathcell: Name =\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ PORT MAP ( clock => Net_191 , - cs_addr_2 => \UART_1:BUART:tx_state_1\ , - cs_addr_1 => \UART_1:BUART:tx_state_0\ , - cs_addr_0 => \UART_1:BUART:tx_bitclk_enable_pre\ , - so_comb => \UART_1:BUART:tx_shift_out\ , - f0_bus_stat_comb => \UART_1:BUART:tx_fifo_notfull\ , - f0_blk_stat_comb => \UART_1:BUART:tx_fifo_empty\ ); + cs_addr_0 => \UART_1:BUART:counter_load_not\ , + cl0_comb => \UART_1:BUART:tx_bitclk_dp\ , + cl1_comb => \UART_1:BUART:tx_counter_dp\ ); Properties: { a0_init = "00000000" @@ -2771,7 +3096,7 @@ datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ cl1_sync = 1 cmsb_sync = 1 co_msb_sync = 1 - cy_dpconfig = "0000000000000000000000000000000000000000000000000000000011000000000000000000000000000010010000000000000000000000000000000000000011111111000000001111111111111111000000000000000001000100111100000000000000001100" + cy_dpconfig = "1010100001000000001000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111000000001111111100000111001000000100000000000101111100000000000000001000" d0_init = "00000000" d1_init = "00000000" f0_blk_sync = 1 @@ -2788,6 +3113,200 @@ datapathcell: Name =\UART_1:BUART:sTX:TxShifter:u0\ Clock Polarity: Active High Clock Enable: True +UDB [UDB=(3,4)] contents: +LAB@[UDB=(3,4)][LB=0] #macrocells=2, #inputs=2, #pterms=2 +{ + [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:mosi_from_dp_reg\, Mode=(D-Register) @ [UDB=(3,4)][LB=0][MC=0] + Total # of inputs : 1 + Total # of product terms : 1 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 1 pterm + ( + \SPIM:BSPIM:mosi_from_dp\ + ); + Output = \SPIM:BSPIM:mosi_from_dp_reg\ (fanout=1) + Properties : + { + } + + [McSlotId=1]: (empty) + [McSlotId=2]: MacroCell: Name=Net_234, Mode=(Combinatorial) @ [UDB=(3,4)][LB=0][MC=2] + Total # of inputs : 1 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !\UART_1:BUART:txn\ + ); + Output = Net_234 (fanout=1) + Properties : + { + } + + [McSlotId=3]: (empty) +} + +statusicell: Name =\SPIM:BSPIM:RxStsReg\ + PORT MAP ( + clock => \SPIM:Net_276\ , + status_6 => \SPIM:BSPIM:rx_status_6\ , + status_5 => \SPIM:BSPIM:rx_status_5\ , + status_4 => \SPIM:BSPIM:rx_status_4\ ); + Properties: + { + cy_force_order = 1 + cy_int_mask = "0000000" + cy_md_select = "1000000" + } + Clock Polarity: Active High + Clock Enable: True + +UDB [UDB=(3,5)] contents: +LAB@[UDB=(3,5)][LB=0] #macrocells=4, #inputs=9, #pterms=8 +{ + [McSlotId=0]: MacroCell: Name=Net_479, Mode=(D-Register) @ [UDB=(3,5)][LB=0][MC=0] + Total # of inputs : 4 + Total # of product terms : 3 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 3 pterms + !( + !Net_479 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ + + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ + ); + Output = Net_479 (fanout=2) + Properties : + { + } + + [McSlotId=1]: MacroCell: Name=Net_439, Mode=(T-Register) @ [UDB=(3,5)][LB=0][MC=1] + Total # of inputs : 4 + Total # of product terms : 3 + List of special equations: + Clock = (\SPIM:Net_276\) => Global + Clock Enable: True + Main Equation : 3 pterms + ( + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + !\SPIM:BSPIM:state_0\ * !Net_439 + + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * Net_439 + + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * + \SPIM:BSPIM:state_0\ * !Net_439 + ); + Output = Net_439 (fanout=7) + Properties : + { + } + + [McSlotId=2]: MacroCell: Name=Net_30, Mode=(Combinatorial) @ [UDB=(3,5)][LB=0][MC=2] + Total # of inputs : 2 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + ( + !Net_439 * \SPIM:BSPIM:mosi_hs_reg\ + ); + Output = Net_30 (fanout=1) + Properties : + { + } + + [McSlotId=3]: MacroCell: Name=Net_419, Mode=(Combinatorial) @ [UDB=(3,5)][LB=0][MC=3] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_419 (fanout=1) + Properties : + { + } +} + +LAB@[UDB=(3,5)][LB=1] #macrocells=4, #inputs=4, #pterms=4 +{ + [McSlotId=0]: MacroCell: Name=Net_422, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=0] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * !mywire_1_1 * mywire_1_0 + ); + Output = Net_422 (fanout=1) + Properties : + { + } + + [McSlotId=1]: MacroCell: Name=Net_425, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=1] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * mywire_1_1 * mywire_1_0 + ); + Output = Net_425 (fanout=1) + Properties : + { + } + + [McSlotId=2]: MacroCell: Name=Net_428, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=2] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * !mywire_1_2 * mywire_1_1 * !mywire_1_0 + ); + Output = Net_428 (fanout=1) + Properties : + { + } + + [McSlotId=3]: MacroCell: Name=Net_585, Mode=(Combinatorial) @ [UDB=(3,5)][LB=1][MC=3] + Total # of inputs : 4 + Total # of product terms : 1 + Clock Enable: True + Main Equation : 1 pterm + !( + !Net_439 * mywire_1_2 * !mywire_1_1 * !mywire_1_0 + ); + Output = Net_585 (fanout=1) + Properties : + { + } +} + +controlcell: Name =\SS:Async:ctrl_reg\ + PORT MAP ( + control_7 => \SS:control_7\ , + control_6 => \SS:control_6\ , + control_5 => \SS:control_5\ , + control_4 => \SS:control_4\ , + control_3 => \SS:control_3\ , + control_2 => mywire_1_2 , + control_1 => mywire_1_1 , + control_0 => mywire_1_0 ); + Properties: + { + cy_ctrl_mode_0 = "00000000" + cy_ctrl_mode_1 = "00000000" + cy_ext_reset = 0 + cy_force_order = 1 + cy_init_value = "00000000" + } + Clock Enable: True + Intr hod @ [IntrHod=(0)]: empty Drq hod @ [DrqHod=(0)]: empty Port 0 contains the following IO cells: @@ -3347,6 +3866,46 @@ Pin : Name = Pin_4(0) { } +[IoId=4]: +Pin : Name = Pin_5(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO RefSel: VCC_IO + Required Capabilitites: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => Pin_5(0)__PA , + input => Net_585 , + pad => Pin_5(0)_PAD ); + Properties: + { + } + [IoId=7]: Pin : Name = Tx_1(0) Attributes: @@ -3462,37 +4021,38 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connectio | 1 | * | NONE | RES_PULL_UP | Pin_2(0) | In(Net_422) | 2 | * | NONE | RES_PULL_UP | Pin_3(0) | In(Net_428) | 3 | * | NONE | RES_PULL_UP | Pin_4(0) | In(Net_425) + | 4 | * | NONE | RES_PULL_UP | Pin_5(0) | In(Net_585) | 7 | * | NONE | CMOS_OUT | Tx_1(0) | In(Net_234) ---------------------------------------------------------------------------------- -Digital component placer commit/Report: Elapsed time ==> 0s.003ms -Digital Placement phase: Elapsed time ==> 1s.395ms +Digital component placer commit/Report: Elapsed time ==> 0s.005ms +Digital Placement phase: Elapsed time ==> 1s.451ms Routing successful. -Digital Routing phase: Elapsed time ==> 2s.255ms +Digital Routing phase: Elapsed time ==> 3s.163ms -Bitstream and API generation phase: Elapsed time ==> 0s.215ms +Bitstream and API generation phase: Elapsed time ==> 0s.247ms -Bitstream verification phase: Elapsed time ==> 0s.073ms +Bitstream verification phase: Elapsed time ==> 0s.088ms Timing report is in PSOC5_SPI_LSM303D_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.512ms +Static timing analysis phase: Elapsed time ==> 0s.652ms -Data reporting phase: Elapsed time ==> 0s.001ms +Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.220ms +Design database save phase: Elapsed time ==> 0s.331ms -cydsfit: Elapsed time ==> 5s.413ms +cydsfit: Elapsed time ==> 6s.878ms -Fitter phase: Elapsed time ==> 5s.453ms -API generation phase: Elapsed time ==> 0s.801ms -Dependency generation phase: Elapsed time ==> 0s.004ms -Cleanup phase: Elapsed time ==> 0s.001ms +Fitter phase: Elapsed time ==> 6s.922ms +API generation phase: Elapsed time ==> 1s.277ms +Dependency generation phase: Elapsed time ==> 0s.015ms +Cleanup phase: Elapsed time ==> 0s.002ms diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rt_log b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rt_log index 7c75389..85a91b8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rt_log +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.rt_log @@ -13,19 +13,15 @@ I1206: Completed Reading of file PSOC5_SPI_LSM303D.sdc I1204: Reading architecture from file C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\dev/psoc5/route_arch-rrg.cydata I1206: Completed Reading of file C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\dev/psoc5/route_arch-rrg.cydata I1209: Started routing -I1223: Total Nets : 53 -I1212: Iteration 1 : 45 unrouted : 1 seconds -I1212: Iteration 2 : 19 unrouted : 0 seconds -I1212: Iteration 3 : 8 unrouted : 0 seconds -I1212: Iteration 4 : 6 unrouted : 0 seconds -I1212: Iteration 5 : 4 unrouted : 0 seconds -I1212: Iteration 6 : 4 unrouted : 0 seconds -I1212: Iteration 7 : 2 unrouted : 0 seconds -I1212: Iteration 8 : 2 unrouted : 0 seconds -I1212: Iteration 9 : 2 unrouted : 0 seconds -I1212: Iteration 10 : 0 unrouted : 0 seconds +I1223: Total Nets : 78 +I1212: Iteration 1 : 49 unrouted : 0 seconds +I1212: Iteration 2 : 20 unrouted : 1 seconds +I1212: Iteration 3 : 5 unrouted : 0 seconds +I1212: Iteration 4 : 4 unrouted : 0 seconds +I1212: Iteration 5 : 2 unrouted : 0 seconds +I1212: Iteration 6 : 0 unrouted : 0 seconds I1215: Routing is successful I1207: Completed routing I1210: Writing routes I1218: Exiting the router -I1224: Total Time : 2 seconds +I1224: Total Time : 3 seconds diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.sdc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.sdc index 0ace657..80b21de 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.sdc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.sdc @@ -1,6 +1,6 @@ # THIS FILE IS AUTOMATICALLY GENERATED -# Project: C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -# Date: Fri, 22 Mar 2013 09:33:30 GMT +# Project: C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj +# Date: Thu, 25 Jul 2013 14:49:01 GMT #set_units -time ns create_clock -name {CyIMO} -period 333.33333333333331 -waveform {0 166.666666666667} [list [get_pins {ClockBlock/imo}]] create_clock -name {CyPLL_OUT} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/pllout}]] @@ -11,6 +11,6 @@ create_generated_clock -name {Clock_1} -source [get_pins {ClockBlock/clk_sync}] create_generated_clock -name {CyBUS_CLK} -source [get_pins {ClockBlock/clk_sync}] -edges {1 2 3} [list [get_pins {ClockBlock/clk_bus_glb}]] -# Component constraints for C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch -# Project: C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -# Date: Fri, 22 Mar 2013 09:33:23 GMT +# Component constraints for C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch +# Project: C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj +# Date: Thu, 25 Jul 2013 14:48:52 GMT diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.svd b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.svd index 478d670..57e21c2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.svd +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.svd @@ -7,33 +7,252 @@ 32 - SS + Timer_1 No description available - 0x40006475 + 0x40006504 0 - 0x1 + 0x91 registers - SS_CONTROL_REG - No description available + Timer_1_COUNTER + UDB.A0 - Current Down Counter Value 0x0 + 16 + read-write + 0 + 0 + + + Timer_1_PERIOD + UDB.D0 - Assigned Period + 0x20 + 16 + read-write + 0 + 0 + + + Timer_1_Control_Reg + UDB Control Register - Assigned Control Register Value + 0x70 8 read-write 0 0 + + + CTRL_ENABLE + Enable the Timer + 7 + 7 + read-write + + + CTRL_CMODE + Capture Mode + 5 + 6 + read-write + + + CTRL_TEN + Trigger Enable Bit + 4 + 4 + read-write + + + CTRL_TMODE + Trigger Mode + 2 + 3 + read-write + + + CTRL_IC + Interrupt Count + 0 + 1 + read-write + + + + + Timer_1_STATUS_MASK + UDB Status bits Interrupt Mask Enable Register + 0x80 + 8 + read-write + 0 + 0 + + + TIMER_STS_TC + Enables the Interrupt on TC + 0 + 0 + read-only + + + TIMER_STS_CAPT + Enables the Interrupt on Capture + 1 + 1 + read-only + + + TIMER_STS_FIFO_FULL + FIFO Full Status + 2 + 2 + read-only + + + TIMER_STS_FIFO_NEMPTY + FIFO Empty status + 3 + 3 + read-only + + + + + Timer_1_STATUS_AUX_CTRL + UDB Auxilliary Control Register + 0x90 + 8 + read-write + 0 + 0 + + + FIFO0_CLR + FIFO0 clear + 0 + 0 + read-write + + + E_FIFO_CLR_0 + Normal FIFO operation + 0 + + + E_FIFO_CLR_1 + Clear FIFO state + 1 + + + + + FIFO1_CLR + FIFO1 clear + 1 + 1 + read-write + + + E_FIFO_CLR_0 + Normal FIFO operation + 0 + + + E_FIFO_CLR_1 + Clear FIFO state + 1 + + + + + FIFO0_LVL + FIFO level + 2 + 2 + read-write + + + E_FIFO_LVL_0 + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + E_FIFO_LVL_1 + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + + + FIFO1_LVL + FIFO level + 3 + 3 + read-write + + + E_FIFO_LVL_0 + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + E_FIFO_LVL_1 + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + + + INT_EN + No description available + 4 + 4 + read-write + + + E_INT_EN0 + Interrupt disabled + 0 + + + E_INT_EN1 + Interrupt enabled + 1 + + + + + CNT_START + FIFO0 clear + 5 + 5 + read-write + + + E_CNT_START0 + Disable counter + 0 + + + E_CNT_START1 + Enable counter + 1 + + + + UART_1 UART - 0x40006441 + 0x40006444 0 - 0x22 + 0x21 registers @@ -49,7 +268,7 @@ TX_UART_1_TX_STATUS TX status register - 0x21 + 0x20 8 read-write 0 @@ -87,5 +306,26 @@ + + SS + No description available + 0x40006471 + + 0 + 0x1 + registers + + + + SS_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.tr b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.tr index b20202f..6f44570 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.tr +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.tr @@ -9,10 +9,12 @@ 3.3::Pad to Pad 4::Path Details for Clock Frequency Summary 4.1::Critical Path Report for Clock_1 - 4.2::Critical Path Report for SPIM_IntClock + 4.2::Critical Path Report for CyBUS_CLK + 4.3::Critical Path Report for SPIM_IntClock 5::Path Details for Clock Relationship Summary 5.1::Critical Path Report for (SPIM_IntClock:R vs. SPIM_IntClock:R) 5.2::Critical Path Report for (Clock_1:R vs. Clock_1:R) + 5.3::Critical Path Report for (CyBUS_CLK:R vs. CyBUS_CLK:R) ===================================================================== End of Table of Contents ##################################################################### @@ -21,13 +23,13 @@ 1::Clock Frequency Summary ===================================================================== Number of clocks: 7 -Clock: Clock_1 | Frequency: 43.85 MHz | Target: 0.92 MHz | -Clock: CyBUS_CLK | N/A | Target: 24.00 MHz | +Clock: Clock_1 | Frequency: 42.47 MHz | Target: 0.92 MHz | +Clock: CyBUS_CLK | Frequency: 43.36 MHz | Target: 24.00 MHz | Clock: CyILO | N/A | Target: 0.00 MHz | Clock: CyIMO | N/A | Target: 3.00 MHz | Clock: CyMASTER_CLK | N/A | Target: 24.00 MHz | Clock: CyPLL_OUT | N/A | Target: 24.00 MHz | -Clock: SPIM_IntClock | Frequency: 61.38 MHz | Target: 2.00 MHz | +Clock: SPIM_IntClock | Frequency: 52.40 MHz | Target: 2.00 MHz | ===================================================================== End of Clock Frequency Summary @@ -40,8 +42,9 @@ Clock: SPIM_IntClock | Frequency: 61.38 MHz | Target: 2.00 MHz | Launch Clock Capture Clock Constraint(R-R) Slack(R-R) Constraint(R-F) Slack(R-F) Constraint(F-F) Slack(F-F) Constraint(F-R) Slack(F-R) ------------- ------------- --------------- ---------- --------------- ---------- --------------- ---------- --------------- ---------- -Clock_1 Clock_1 1.08333e+006 1060528 N/A N/A N/A N/A N/A N/A -SPIM_IntClock SPIM_IntClock 500000 483708 N/A N/A N/A N/A N/A N/A +Clock_1 Clock_1 1.08333e+006 1059785 N/A N/A N/A N/A N/A N/A +CyBUS_CLK CyBUS_CLK 41666.7 18605 N/A N/A N/A N/A N/A N/A +SPIM_IntClock SPIM_IntClock 500000 480914 N/A N/A N/A N/A N/A N/A ===================================================================== End of Clock Relationship Summary @@ -59,7 +62,7 @@ All values are in Picoseconds Port Name Setup to Clk Clock Name:Phase ----------------- ------------ ---------------- -m_miso_pin(0)_PAD 41682 SPIM_IntClock:R +m_miso_pin(0)_PAD 41683 SPIM_IntClock:R 3.2::Clock to Out @@ -67,17 +70,19 @@ m_miso_pin(0)_PAD 41682 SPIM_IntClock:R Port Name Clock to Out Clock Name:Phase ----------------- ------------ ---------------- -Pin_1(0)_PAD 33745 CyBUS_CLK:R -Pin_1(0)_PAD 32210 SPIM_IntClock:R -Pin_2(0)_PAD 33907 CyBUS_CLK:R -Pin_2(0)_PAD 32381 SPIM_IntClock:R -Pin_3(0)_PAD 33472 CyBUS_CLK:R -Pin_3(0)_PAD 31946 SPIM_IntClock:R -Pin_4(0)_PAD 32133 CyBUS_CLK:R -Pin_4(0)_PAD 30607 SPIM_IntClock:R -Tx_1(0)_PAD 34023 Clock_1:R -m_mosi_pin(0)_PAD 36766 SPIM_IntClock:R -m_sclk_pin(0)_PAD 28375 SPIM_IntClock:R +Pin_1(0)_PAD 32702 CyBUS_CLK:R +Pin_1(0)_PAD 31153 SPIM_IntClock:R +Pin_2(0)_PAD 31990 CyBUS_CLK:R +Pin_2(0)_PAD 30464 SPIM_IntClock:R +Pin_3(0)_PAD 33095 CyBUS_CLK:R +Pin_3(0)_PAD 31569 SPIM_IntClock:R +Pin_4(0)_PAD 31860 CyBUS_CLK:R +Pin_4(0)_PAD 30334 SPIM_IntClock:R +Pin_5(0)_PAD 32580 CyBUS_CLK:R +Pin_5(0)_PAD 31053 SPIM_IntClock:R +Tx_1(0)_PAD 32135 Clock_1:R +m_mosi_pin(0)_PAD 35727 SPIM_IntClock:R +m_sclk_pin(0)_PAD 27466 SPIM_IntClock:R 3.3::Pad to Pad @@ -95,14 +100,14 @@ Port Name (Source) Port Name (Destination) Delay 4.1::Critical Path Report for Clock_1 ************************************* Clock: Clock_1 -Frequency: 43.85 MHz | Target: 0.92 MHz +Frequency: 42.47 MHz | Target: 0.92 MHz ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q +Path Begin : \UART_1:BUART:tx_state_1\/q Path End : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 Capture Clock : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock -Path slack : 1060528p +Path slack : 1059785p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -113,43 +118,92 @@ End-of-path required time (ps) 1071813 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 11285 ++ Data path delay 12028 ------------------------------------- ----- -End-of-path arrival time (ps) 11285 +End-of-path arrival time (ps) 12028 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ----------------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/main_1 macrocell24 4383 5633 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/q macrocell24 3350 8983 1060528 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell3 2302 11285 1060528 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/main_0 macrocell29 5136 6386 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/q macrocell29 3350 9736 1059785 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell5 2292 12028 1059785 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell3 0 0 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell5 0 0 RISE 1 + + +===================================================================== +4.2::Critical Path Report for CyBUS_CLK +*************************************** +Clock: CyBUS_CLK +Frequency: 43.36 MHz | Target: 24.00 MHz + +++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/ci +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 18605p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -5090 +------------------------------------------------ ----- +End-of-path required time (ps) 36577 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 17972 +------------------------------------- ----- +End-of-path arrival time (ps) 17972 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 datapathcell2 2982 8262 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb datapathcell2 9710 17972 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/ci datapathcell3 0 17972 18605 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 ===================================================================== -4.2::Critical Path Report for SPIM_IntClock +4.3::Critical Path Report for SPIM_IntClock ******************************************* Clock: SPIM_IntClock -Frequency: 61.38 MHz | Target: 2.00 MHz +Frequency: 52.40 MHz | Target: 2.00 MHz ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483708p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:TxStsReg\/status_3 +Capture Clock : \SPIM:BSPIM:TxStsReg\/clock +Path slack : 480914p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -160,29 +214,29 @@ End-of-path required time (ps) 498430 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 14722 ++ Data path delay 17516 ------------------------------------- ----- -End-of-path arrival time (ps) 14722 +End-of-path arrival time (ps) 17516 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell18 3784 9064 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell18 3350 12414 483708 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14722 483708 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------- ------------ ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/main_2 macrocell11 6477 8587 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/q macrocell11 3350 11937 480914 RISE 1 +\SPIM:BSPIM:TxStsReg\/status_3 statusicell2 5578 17516 480914 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 +\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 @@ -200,10 +254,10 @@ ClockBlock/dclk_glb_0 clockblockcell 0 ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483708p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:TxStsReg\/status_3 +Capture Clock : \SPIM:BSPIM:TxStsReg\/clock +Path slack : 480914p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -214,29 +268,29 @@ End-of-path required time (ps) 498430 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 14722 ++ Data path delay 17516 ------------------------------------- ----- -End-of-path arrival time (ps) 14722 +End-of-path arrival time (ps) 17516 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell18 3784 9064 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell18 3350 12414 483708 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14722 483708 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------- ------------ ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/main_2 macrocell11 6477 8587 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/q macrocell11 3350 11937 480914 RISE 1 +\SPIM:BSPIM:TxStsReg\/status_3 statusicell2 5578 17516 480914 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 +\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 5.2::Critical Path Report for (Clock_1:R vs. Clock_1:R) @@ -244,10 +298,10 @@ ClockBlock/dclk_glb_0 clockblockcell 0 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q +Path Begin : \UART_1:BUART:tx_state_1\/q Path End : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 Capture Clock : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock -Path slack : 1060528p +Path slack : 1059785p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -258,29 +312,75 @@ End-of-path required time (ps) 1071813 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 11285 ++ Data path delay 12028 ------------------------------------- ----- -End-of-path arrival time (ps) 11285 +End-of-path arrival time (ps) 12028 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ----------------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/main_1 macrocell24 4383 5633 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/q macrocell24 3350 8983 1060528 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell3 2302 11285 1060528 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/main_0 macrocell29 5136 6386 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/q macrocell29 3350 9736 1059785 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell5 2292 12028 1059785 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell3 0 0 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell5 0 0 RISE 1 + + +5.3::Critical Path Report for (CyBUS_CLK:R vs. CyBUS_CLK:R) +*********************************************************** + +++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/ci +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 18605p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -5090 +------------------------------------------------ ----- +End-of-path required time (ps) 36577 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 17972 +------------------------------------- ----- +End-of-path arrival time (ps) 17972 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 datapathcell2 2982 8262 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb datapathcell2 9710 17972 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/ci datapathcell3 0 17972 18605 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 @@ -294,416 +394,1312 @@ ClockBlock/dclk_glb_1 clockblockcell 0 ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483708p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/ci +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 18605p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -5090 +------------------------------------------------ ----- +End-of-path required time (ps) 36577 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 14722 ++ Data path delay 17972 ------------------------------------- ----- -End-of-path arrival time (ps) 14722 +End-of-path arrival time (ps) 17972 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell18 3784 9064 483708 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell18 3350 12414 483708 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14722 483708 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 datapathcell2 2982 8262 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb datapathcell2 9710 17972 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/ci datapathcell3 0 17972 18605 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb -Path End : \SPIM:BSPIM:mosi_hs_reg\/main_3 -Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 484477p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u0\/clock +Path slack : 21885p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -11520 +------------------------------------------------ ------ +End-of-path required time (ps) 30147 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 12013 -------------------------------------- ----- -End-of-path arrival time (ps) 12013 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 8262 +------------------------------------- ---- +End-of-path arrival time (ps) 8262 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484477 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_3 macrocell16 3713 12013 484477 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 datapathcell2 2982 8262 21885 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_3 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 485360p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 21887p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -11520 +------------------------------------------------ ------ +End-of-path required time (ps) 30147 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 11130 -------------------------------------- ----- -End-of-path arrival time (ps) 11130 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 8259 +------------------------------------- ---- +End-of-path arrival time (ps) 8259 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484477 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_3 macrocell17 2830 11130 485360 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 datapathcell3 2979 8259 21887 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb -Path End : \SPIM:BSPIM:mosi_from_dp_reg\/main_0 -Capture Clock : \SPIM:BSPIM:mosi_from_dp_reg\/clock_0 -Path slack : 485370p +Path Begin : \Timer_1:TimerUDB:timer_enable\/q +Path End : \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u0\/clock +Path slack : 25922p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -11520 +------------------------------------------------ ------ +End-of-path required time (ps) 30147 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 11120 -------------------------------------- ----- -End-of-path arrival time (ps) 11120 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4224 +------------------------------------- ---- +End-of-path arrival time (ps) 4224 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484477 RISE 1 -\SPIM:BSPIM:mosi_from_dp_reg\/main_0 macrocell15 2820 11120 485370 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:timer_enable\/q macrocell27 1250 1250 22642 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 datapathcell2 2974 4224 25922 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_from_dp_reg\/clock_0 macrocell15 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:TxStsReg\/status_0 -Capture Clock : \SPIM:BSPIM:TxStsReg\/clock -Path slack : 486427p +Path Begin : \Timer_1:TimerUDB:timer_enable\/q +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 26029p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -11520 +------------------------------------------------ ------ +End-of-path required time (ps) 30147 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 12003 -------------------------------------- ----- -End-of-path arrival time (ps) 12003 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4117 +------------------------------------- ---- +End-of-path arrival time (ps) 4117 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ------------ ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:tx_status_0\/main_0 macrocell22 4486 5736 486427 RISE 1 -\SPIM:BSPIM:tx_status_0\/q macrocell22 3350 9086 486427 RISE 1 -\SPIM:BSPIM:TxStsReg\/status_0 statusicell2 2917 12003 486427 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------------------- ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:timer_enable\/q macrocell27 1250 1250 22642 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 datapathcell3 2867 4117 26029 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:TxStsReg\/status_3 -Capture Clock : \SPIM:BSPIM:TxStsReg\/clock -Path slack : 486627p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:nrstSts:stsreg\/status_0 +Capture Clock : \Timer_1:TimerUDB:nrstSts:stsreg\/clock +Path slack : 26330p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -1570 +------------------------------------------------ ----- +End-of-path required time (ps) 40097 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 11803 ++ Data path delay 13767 ------------------------------------- ----- -End-of-path arrival time (ps) 11803 +End-of-path arrival time (ps) 13767 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------- ------------ ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:dpcounter_one\/main_3 macrocell10 4028 6138 486627 RISE 1 -\SPIM:BSPIM:dpcounter_one\/q macrocell10 3350 9488 486627 RISE 1 -\SPIM:BSPIM:TxStsReg\/status_3 statusicell2 2316 11803 486627 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------------------ ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:status_tc\/main_1 macrocell26 2872 8152 26330 RISE 1 +\Timer_1:TimerUDB:status_tc\/q macrocell26 3350 11502 26330 RISE 1 +\Timer_1:TimerUDB:nrstSts:stsreg\/status_0 statusicell3 2265 13767 26330 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:nrstSts:stsreg\/clock statusicell3 0 0 RISE 1 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_1\/main_8 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 486838p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:timer_enable\/main_3 +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 30005p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 9652 ++ Data path delay 8152 ------------------------------------- ---- -End-of-path arrival time (ps) 9652 +End-of-path arrival time (ps) 8152 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486838 RISE 1 -\SPIM:BSPIM:state_1\/main_8 macrocell20 4372 9652 486838 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------------------ ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:timer_enable\/main_3 macrocell27 2872 8152 30005 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 487379p +Path Begin : \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 +Path End : \Timer_1:TimerUDB:trig_disable\/main_2 +Capture Clock : \Timer_1:TimerUDB:trig_disable\/clock_0 +Path slack : 30005p -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 --------------------------------------------------------- ------ -End-of-path required time (ps) 492830 +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5451 ++ Data path delay 8152 ------------------------------------- ---- -End-of-path arrival time (ps) 5451 +End-of-path arrival time (ps) 8152 Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 datapathcell1 4201 5451 487379 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------------------ ------------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 datapathcell2 2320 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i datapathcell3 0 2320 18605 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb datapathcell3 2960 5280 18605 RISE 1 +\Timer_1:TimerUDB:trig_disable\/main_2 macrocell28 2872 8152 30005 RISE 1 Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 487556p +Path Begin : \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 +Path End : \Timer_1:TimerUDB:run_mode\/main_0 +Capture Clock : \Timer_1:TimerUDB:run_mode\/clock_0 +Path slack : 33326p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4831 +------------------------------------- ---- +End-of-path arrival time (ps) 4831 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk controlcell2 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +------------------------------------------------------ ------------ ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 controlcell2 2580 2580 33326 RISE 1 +\Timer_1:TimerUDB:run_mode\/main_0 macrocell25 2251 4831 33326 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:run_mode\/clock_0 macrocell25 0 0 RISE 1 + + + +++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 +Path End : \Timer_1:TimerUDB:timer_enable\/main_0 +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 33326p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4831 +------------------------------------- ---- +End-of-path arrival time (ps) 4831 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/busclk controlcell2 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +------------------------------------------------------ ------------ ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\/control_7 controlcell2 2580 2580 33326 RISE 1 +\Timer_1:TimerUDB:timer_enable\/main_0 macrocell27 2251 4831 33326 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + + + +++++ Path 11 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:timer_enable\/q +Path End : \Timer_1:TimerUDB:timer_enable\/main_1 +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 33941p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4215 +------------------------------------- ---- +End-of-path arrival time (ps) 4215 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:timer_enable\/q macrocell27 1250 1250 22642 RISE 1 +\Timer_1:TimerUDB:timer_enable\/main_1 macrocell27 2965 4215 33941 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + + + +++++ Path 12 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:timer_enable\/q +Path End : \Timer_1:TimerUDB:trig_disable\/main_0 +Capture Clock : \Timer_1:TimerUDB:trig_disable\/clock_0 +Path slack : 33941p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4215 +------------------------------------- ---- +End-of-path arrival time (ps) 4215 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:timer_enable\/q macrocell27 1250 1250 22642 RISE 1 +\Timer_1:TimerUDB:trig_disable\/main_0 macrocell28 2965 4215 33941 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + + + +++++ Path 13 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:trig_disable\/q +Path End : \Timer_1:TimerUDB:timer_enable\/main_4 +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 34663p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 3493 +------------------------------------- ---- +End-of-path arrival time (ps) 3493 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:trig_disable\/q macrocell28 1250 1250 34663 RISE 1 +\Timer_1:TimerUDB:timer_enable\/main_4 macrocell27 2243 3493 34663 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + + + +++++ Path 14 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:trig_disable\/q +Path End : \Timer_1:TimerUDB:trig_disable\/main_3 +Capture Clock : \Timer_1:TimerUDB:trig_disable\/clock_0 +Path slack : 34663p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 3493 +------------------------------------- ---- +End-of-path arrival time (ps) 3493 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:trig_disable\/q macrocell28 1250 1250 34663 RISE 1 +\Timer_1:TimerUDB:trig_disable\/main_3 macrocell28 2243 3493 34663 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + + + +++++ Path 15 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:run_mode\/q +Path End : \Timer_1:TimerUDB:timer_enable\/main_2 +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 34666p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 3490 +------------------------------------- ---- +End-of-path arrival time (ps) 3490 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:run_mode\/clock_0 macrocell25 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:run_mode\/q macrocell25 1250 1250 30991 RISE 1 +\Timer_1:TimerUDB:timer_enable\/main_2 macrocell27 2240 3490 34666 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + + + +++++ Path 16 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \Timer_1:TimerUDB:run_mode\/q +Path End : \Timer_1:TimerUDB:trig_disable\/main_1 +Capture Clock : \Timer_1:TimerUDB:trig_disable\/clock_0 +Path slack : 34666p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -3510 +------------------------------------------------ ----- +End-of-path required time (ps) 38157 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 3490 +------------------------------------- ---- +End-of-path arrival time (ps) 3490 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:run_mode\/clock_0 macrocell25 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +\Timer_1:TimerUDB:run_mode\/q macrocell25 1250 1250 30991 RISE 1 +\Timer_1:TimerUDB:trig_disable\/main_1 macrocell28 2240 3490 34666 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + + + +++++ Path 17 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:nrstSts:stsreg\/clk_en +Capture Clock : \Timer_1:TimerUDB:nrstSts:stsreg\/clock +Path slack : 35381p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4185 +------------------------------------- ---- +End-of-path arrival time (ps) 4185 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +---------------------------------------- ------------ ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:nrstSts:stsreg\/clk_en statusicell3 2705 4185 35381 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:nrstSts:stsreg\/clock statusicell3 0 0 RISE 1 + + + +++++ Path 18 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:run_mode\/clk_en +Capture Clock : \Timer_1:TimerUDB:run_mode\/clock_0 +Path slack : 35381p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4185 +------------------------------------- ---- +End-of-path arrival time (ps) 4185 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +---------------------------------- ----------- ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:run_mode\/clk_en macrocell25 2705 4185 35381 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:run_mode\/clock_0 macrocell25 0 0 RISE 1 + + + +++++ Path 19 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u0\/clock +Path slack : 35381p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4185 +------------------------------------- ---- +End-of-path arrival time (ps) 4185 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +----------------------------------------- ------------- ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en datapathcell2 2705 4185 35381 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u0\/clock datapathcell2 0 0 RISE 1 + + + +++++ Path 20 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:timer_enable\/clk_en +Capture Clock : \Timer_1:TimerUDB:timer_enable\/clock_0 +Path slack : 35381p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4185 +------------------------------------- ---- +End-of-path arrival time (ps) 4185 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clk_en macrocell27 2705 4185 35381 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:timer_enable\/clock_0 macrocell27 0 0 RISE 1 + + + +++++ Path 21 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:trig_disable\/clk_en +Capture Clock : \Timer_1:TimerUDB:trig_disable\/clock_0 +Path slack : 35381p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4185 +------------------------------------- ---- +End-of-path arrival time (ps) 4185 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------------- ----------- ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clk_en macrocell28 2705 4185 35381 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:trig_disable\/clock_0 macrocell28 0 0 RISE 1 + + + +++++ Path 22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : ClockBlock_1k__SYNC/out +Path End : \Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en +Capture Clock : \Timer_1:TimerUDB:sT16:timerdp:u1\/clock +Path slack : 35404p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (CyBUS_CLK:R#1 vs. CyBUS_CLK:R#2) 41667 +- Setup time -2100 +------------------------------------------------ ----- +End-of-path required time (ps) 39567 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 4162 +------------------------------------- ---- +End-of-path arrival time (ps) 4162 + +Launch Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +ClockBlock_1k__SYNC/clock synccell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +----------------------------------------- ------------- ----- ----- ----- ---- ------ +ClockBlock_1k__SYNC/out synccell 1480 1480 35381 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en datapathcell3 2682 4162 35404 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +---------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/clk_bus_glb clockblockcell 0 0 RISE 1 +\Timer_1:TimerUDB:sT16:timerdp:u1\/clock datapathcell3 0 0 RISE 1 + + + +++++ Path 23 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:TxStsReg\/status_3 +Capture Clock : \SPIM:BSPIM:TxStsReg\/clock +Path slack : 480914p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -1570 +-------------------------------------------------------- ------ +End-of-path required time (ps) 498430 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 17516 +------------------------------------- ----- +End-of-path arrival time (ps) 17516 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +--------------------------------- ------------ ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/main_2 macrocell11 6477 8587 480914 RISE 1 +\SPIM:BSPIM:dpcounter_one\/q macrocell11 3350 11937 480914 RISE 1 +\SPIM:BSPIM:TxStsReg\/status_3 statusicell2 5578 17516 480914 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 + + + +++++ Path 24 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:TxStsReg\/status_0 +Capture Clock : \SPIM:BSPIM:TxStsReg\/clock +Path slack : 482386p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -1570 +-------------------------------------------------------- ------ +End-of-path required time (ps) 498430 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 16044 +------------------------------------- ----- +End-of-path arrival time (ps) 16044 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +------------------------------- ------------ ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:tx_status_0\/main_1 macrocell23 8507 9757 482386 RISE 1 +\SPIM:BSPIM:tx_status_0\/q macrocell23 3350 13107 482386 RISE 1 +\SPIM:BSPIM:TxStsReg\/status_0 statusicell2 2937 16044 482386 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 + + + +++++ Path 25 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 +Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock +Path slack : 482507p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -7170 +-------------------------------------------------------- ------ +End-of-path required time (ps) 492830 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10323 +------------------------------------- ----- +End-of-path arrival time (ps) 10323 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 datapathcell1 9073 10323 482507 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 + + + +++++ Path 26 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb +Path End : \SPIM:BSPIM:RxStsReg\/status_6 +Capture Clock : \SPIM:BSPIM:RxStsReg\/clock +Path slack : 483626p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -1570 +-------------------------------------------------------- ------ +End-of-path required time (ps) 498430 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 14804 +------------------------------------- ----- +End-of-path arrival time (ps) 14804 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +--------------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483626 RISE 1 +\SPIM:BSPIM:rx_status_6\/main_5 macrocell19 3241 8521 483626 RISE 1 +\SPIM:BSPIM:rx_status_6\/q macrocell19 3350 11871 483626 RISE 1 +\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2933 14804 483626 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 + + + +++++ Path 27 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:mosi_hs_reg\/main_0 +Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 +Path slack : 484163p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -3510 +-------------------------------------------------------- ------ +End-of-path required time (ps) 496490 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 12327 +------------------------------------- ----- +End-of-path arrival time (ps) 12327 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_0 macrocell17 11077 12327 484163 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 + + + +++++ Path 28 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb +Path End : \SPIM:BSPIM:mosi_hs_reg\/main_3 +Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 +Path slack : 484278p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -3510 +-------------------------------------------------------- ------ +End-of-path required time (ps) 496490 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 12212 +------------------------------------- ----- +End-of-path arrival time (ps) 12212 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484278 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_3 macrocell17 3912 12212 484278 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 + + + +++++ Path 29 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 +Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock +Path slack : 484556p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -7170 +-------------------------------------------------------- ------ +End-of-path required time (ps) 492830 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 8274 +------------------------------------- ---- +End-of-path arrival time (ps) 8274 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 datapathcell1 7024 8274 484556 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 + + + +++++ Path 30 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_3 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 485037p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -3510 +-------------------------------------------------------- ------ +End-of-path required time (ps) 496490 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 11453 +------------------------------------- ----- +End-of-path arrival time (ps) 11453 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +-------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484278 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_3 macrocell18 3153 11453 485037 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 + + + +++++ Path 31 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb +Path End : \SPIM:BSPIM:mosi_from_dp_reg\/main_0 +Capture Clock : \SPIM:BSPIM:mosi_from_dp_reg\/clock_0 +Path slack : 485050p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 +- Setup time -3510 -------------------------------------------------------- ------ -End-of-path required time (ps) 492830 +End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5274 -------------------------------------- ---- -End-of-path arrival time (ps) 5274 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 11440 +------------------------------------- ----- +End-of-path arrival time (ps) 11440 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 datapathcell1 4024 5274 487556 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------------ ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 484278 RISE 1 +\SPIM:BSPIM:mosi_from_dp_reg\/main_0 macrocell16 3140 11440 485050 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:mosi_from_dp_reg\/clock_0 macrocell16 0 0 RISE 1 -++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 32 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 488004p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_0 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 485083p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 +- Setup time -3510 -------------------------------------------------------- ------ -End-of-path required time (ps) 492830 +End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4826 -------------------------------------- ---- -End-of-path arrival time (ps) 4826 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 11407 +------------------------------------- ----- +End-of-path arrival time (ps) 11407 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 datapathcell1 3576 4826 488004 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_0 macrocell18 10157 11407 485083 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 11 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 33 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:is_spi_done\/main_8 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 488572p +Path End : \SPIM:BSPIM:state_1\/main_8 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 485279p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -712,11 +1708,11 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7918 -------------------------------------- ---- -End-of-path arrival time (ps) 7918 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 11211 +------------------------------------- ----- +End-of-path arrival time (ps) 11211 Launch Clock Path pin name model name delay AT edge Fanout @@ -727,23 +1723,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout --------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486838 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_8 macrocell11 2638 7918 488572 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 485279 RISE 1 +\SPIM:BSPIM:state_1\/main_8 macrocell21 5931 11211 485279 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 12 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 34 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_0\/main_3 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 488572p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:mosi_hs_reg\/main_1 +Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 +Path slack : 485377p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -752,38 +1748,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7918 -------------------------------------- ---- -End-of-path arrival time (ps) 7918 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 11113 +------------------------------------- ----- +End-of-path arrival time (ps) 11113 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486838 RISE 1 -\SPIM:BSPIM:state_0\/main_3 macrocell19 2638 7918 488572 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_1 macrocell17 9863 11113 485377 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 -++++ Path 13 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 35 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_2\/main_8 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 488572p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:ld_ident\/main_0 +Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 +Path slack : 485558p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -792,38 +1788,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7918 -------------------------------------- ---- -End-of-path arrival time (ps) 7918 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10932 +------------------------------------- ----- +End-of-path arrival time (ps) 10932 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486838 RISE 1 -\SPIM:BSPIM:state_2\/main_8 macrocell21 2638 7918 488572 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:ld_ident\/main_0 macrocell13 9682 10932 485558 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 -++++ Path 14 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 36 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_2\/q -Path End : Net_479/main_1 -Capture Clock : Net_479/clock_0 -Path slack : 489416p +Path End : \SPIM:BSPIM:load_cond\/main_0 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 485558p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -832,38 +1828,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7074 -------------------------------------- ---- -End-of-path arrival time (ps) 7074 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10932 +------------------------------------- ----- +End-of-path arrival time (ps) 10932 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -Net_479/main_1 macrocell8 5824 7074 489416 RISE 1 +pin name model name delay AT slack edge Fanout +----------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:load_cond\/main_0 macrocell14 9682 10932 485558 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_479/clock_0 macrocell8 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 15 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:load_cond\/main_0 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 489416p +Path End : \SPIM:BSPIM:cnt_enable\/main_0 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 485571p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -872,38 +1868,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7074 -------------------------------------- ---- -End-of-path arrival time (ps) 7074 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10919 +------------------------------------- ----- +End-of-path arrival time (ps) 10919 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:load_cond\/main_0 macrocell13 5824 7074 489416 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------ ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_0 macrocell10 9669 10919 485571 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 16 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 38 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:load_cond\/q -Path End : \SPIM:BSPIM:load_cond\/main_8 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 489718p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:state_1\/main_0 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 485571p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -912,38 +1908,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 6772 -------------------------------------- ---- -End-of-path arrival time (ps) 6772 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10919 +------------------------------------- ----- +End-of-path arrival time (ps) 10919 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:load_cond\/q macrocell13 1250 1250 489718 RISE 1 -\SPIM:BSPIM:load_cond\/main_8 macrocell13 5522 6772 489718 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:state_1\/main_0 macrocell21 9669 10919 485571 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 17 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 39 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:mosi_hs_reg\/main_1 -Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 490127p +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_1 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 486156p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -952,38 +1948,38 @@ Capture Clock Arrival Time 0 -------------------------------------------------------- ------ End-of-path required time (ps) 496490 -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 6363 -------------------------------------- ---- -End-of-path arrival time (ps) 6363 +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 10334 +------------------------------------- ----- +End-of-path arrival time (ps) 10334 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_1 macrocell16 5113 6363 490127 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_1 macrocell18 9084 10334 486156 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 18 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 40 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:cnt_enable\/main_6 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490337p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:is_spi_done\/main_1 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 486733p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -994,36 +1990,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6153 ++ Data path delay 9757 ------------------------------------- ---- -End-of-path arrival time (ps) 6153 +End-of-path arrival time (ps) 9757 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_6 macrocell9 4043 6153 490337 RISE 1 +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_1 macrocell12 8507 9757 486733 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 19 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 41 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:state_1\/main_6 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490337p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:state_0\/main_1 +Capture Clock : \SPIM:BSPIM:state_0\/clock_0 +Path slack : 486733p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1034,36 +2030,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6153 ++ Data path delay 9757 ------------------------------------- ---- -End-of-path arrival time (ps) 6153 +End-of-path arrival time (ps) 9757 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:state_1\/main_6 macrocell20 4043 6153 490337 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:state_0\/main_1 macrocell20 8507 9757 486733 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 -++++ Path 20 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 42 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:load_cond\/main_6 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490352p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:state_2\/main_1 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 486733p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1074,36 +2070,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6138 ++ Data path delay 9757 ------------------------------------- ---- -End-of-path arrival time (ps) 6138 +End-of-path arrival time (ps) 9757 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:load_cond\/main_6 macrocell13 4028 6138 490352 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:state_2\/main_1 macrocell22 8507 9757 486733 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 21 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 43 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:load_rx_data\/main_3 -Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 -Path slack : 490352p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:cnt_enable\/main_5 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 487352p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1114,9 +2110,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6138 ++ Data path delay 9138 ------------------------------------- ---- -End-of-path arrival time (ps) 6138 +End-of-path arrival time (ps) 9138 Launch Clock Path pin name model name delay AT edge Fanout @@ -1125,25 +2121,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_3 macrocell14 4028 6138 490352 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_5 macrocell10 7028 9138 487352 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 44 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_0 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490517p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:state_1\/main_5 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 487352p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1154,76 +2150,76 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5973 ++ Data path delay 9138 ------------------------------------- ---- -End-of-path arrival time (ps) 5973 +End-of-path arrival time (ps) 9138 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_0 macrocell9 4723 5973 490517 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:state_1\/main_5 macrocell21 7028 9138 487352 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 23 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 45 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_1\/main_0 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490517p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 +Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock +Path slack : 487379p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 +- Setup time -7170 -------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +End-of-path required time (ps) 492830 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5973 ++ Data path delay 5451 ------------------------------------- ---- -End-of-path arrival time (ps) 5973 +End-of-path arrival time (ps) 5451 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:state_1\/main_0 macrocell20 4723 5973 490517 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 datapathcell1 4201 5451 487379 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 -++++ Path 24 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 46 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:mosi_hs_reg\/main_0 -Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 490524p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:load_cond\/main_5 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 487903p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1234,36 +2230,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5966 ++ Data path delay 8587 ------------------------------------- ---- -End-of-path arrival time (ps) 5966 +End-of-path arrival time (ps) 8587 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_0 macrocell16 4716 5966 490524 RISE 1 +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:load_cond\/main_5 macrocell14 6477 8587 487903 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 - +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 25 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : Net_439/main_0 -Capture Clock : Net_439/clock_0 -Path slack : 490539p +++++ Path 47 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:load_rx_data\/main_2 +Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 +Path slack : 487903p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1274,36 +2270,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5951 ++ Data path delay 8587 ------------------------------------- ---- -End-of-path arrival time (ps) 5951 +End-of-path arrival time (ps) 8587 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -Net_439/main_0 macrocell7 4701 5951 490539 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:load_rx_data\/main_2 macrocell15 6477 8587 487903 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_439/clock_0 macrocell7 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 -++++ Path 26 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 48 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:ld_ident\/main_0 -Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 -Path slack : 490539p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : Net_439/main_1 +Capture Clock : Net_439/clock_0 +Path slack : 488393p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1314,36 +2310,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5951 ++ Data path delay 8097 ------------------------------------- ---- -End-of-path arrival time (ps) 5951 +End-of-path arrival time (ps) 8097 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:ld_ident\/main_0 macrocell12 4701 5951 490539 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +Net_439/main_1 macrocell7 6847 8097 488393 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 +Net_439/clock_0 macrocell7 0 0 RISE 1 -++++ Path 27 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 49 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:cnt_enable\/main_4 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490597p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : Net_479/main_2 +Capture Clock : Net_479/clock_0 +Path slack : 488393p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1354,36 +2350,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5893 ++ Data path delay 8097 ------------------------------------- ---- -End-of-path arrival time (ps) 5893 +End-of-path arrival time (ps) 8097 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_4 macrocell9 3783 5893 490597 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +Net_479/main_2 macrocell8 6847 8097 488393 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +Net_479/clock_0 macrocell8 0 0 RISE 1 -++++ Path 28 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 50 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:state_1\/main_4 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490597p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : Net_439/main_0 +Capture Clock : Net_439/clock_0 +Path slack : 488705p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1394,36 +2390,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5893 ++ Data path delay 7785 ------------------------------------- ---- -End-of-path arrival time (ps) 5893 +End-of-path arrival time (ps) 7785 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:state_1\/main_4 macrocell20 3783 5893 490597 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +Net_439/main_0 macrocell7 6535 7785 488705 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +Net_439/clock_0 macrocell7 0 0 RISE 1 -++++ Path 29 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 51 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:load_cond\/main_4 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490609p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : Net_479/main_1 +Capture Clock : Net_479/clock_0 +Path slack : 488705p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1434,36 +2430,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5881 ++ Data path delay 7785 ------------------------------------- ---- -End-of-path arrival time (ps) 5881 +End-of-path arrival time (ps) 7785 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:load_cond\/main_4 macrocell13 3771 5881 490609 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +Net_479/main_1 macrocell8 6535 7785 488705 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +Net_479/clock_0 macrocell8 0 0 RISE 1 -++++ Path 30 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:load_rx_data\/main_1 -Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 -Path slack : 490609p +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb +Path End : \SPIM:BSPIM:is_spi_done\/main_8 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 488894p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1474,36 +2470,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5881 ++ Data path delay 7596 ------------------------------------- ---- -End-of-path arrival time (ps) 5881 +End-of-path arrival time (ps) 7596 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_1 macrocell14 3771 5881 490609 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 485279 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_8 macrocell12 2316 7596 488894 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 31 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:cnt_enable\/main_3 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490624p +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb +Path End : \SPIM:BSPIM:state_0\/main_3 +Capture Clock : \SPIM:BSPIM:state_0\/clock_0 +Path slack : 488894p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1514,36 +2510,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5866 ++ Data path delay 7596 ------------------------------------- ---- -End-of-path arrival time (ps) 5866 +End-of-path arrival time (ps) 7596 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_3 macrocell9 3756 5866 490624 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 485279 RISE 1 +\SPIM:BSPIM:state_0\/main_3 macrocell20 2316 7596 488894 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 -++++ Path 32 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:state_1\/main_3 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490624p +Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb +Path End : \SPIM:BSPIM:state_2\/main_8 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 488894p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1554,36 +2550,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5866 ++ Data path delay 7596 ------------------------------------- ---- -End-of-path arrival time (ps) 5866 +End-of-path arrival time (ps) 7596 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:state_1\/main_3 macrocell20 3756 5866 490624 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------------- ------------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 485279 RISE 1 +\SPIM:BSPIM:state_2\/main_8 macrocell22 2316 7596 488894 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 33 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:load_cond\/main_3 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490646p +Path End : \SPIM:BSPIM:cnt_enable\/main_3 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 489270p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1594,9 +2590,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5844 ++ Data path delay 7220 ------------------------------------- ---- -End-of-path arrival time (ps) 5844 +End-of-path arrival time (ps) 7220 Launch Clock Path pin name model name delay AT edge Fanout @@ -1607,23 +2603,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:load_cond\/main_3 macrocell13 3734 5844 490646 RISE 1 +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_3 macrocell10 5110 7220 489270 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 34 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:load_rx_data\/main_0 -Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 -Path slack : 490646p +Path End : \SPIM:BSPIM:state_1\/main_3 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 489270p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1634,9 +2630,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5844 ++ Data path delay 7220 ------------------------------------- ---- -End-of-path arrival time (ps) 5844 +End-of-path arrival time (ps) 7220 Launch Clock Path pin name model name delay AT edge Fanout @@ -1645,25 +2641,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_0 macrocell14 3734 5844 490646 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:state_1\/main_3 macrocell21 5110 7220 489270 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 35 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : Net_439/main_2 -Capture Clock : Net_439/clock_0 -Path slack : 490654p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:cnt_enable\/main_7 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 489335p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1674,36 +2670,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5836 ++ Data path delay 7155 ------------------------------------- ---- -End-of-path arrival time (ps) 5836 +End-of-path arrival time (ps) 7155 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -Net_439/main_2 macrocell7 4586 5836 490654 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_7 macrocell10 5045 7155 489335 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_439/clock_0 macrocell7 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 36 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:ld_ident\/main_2 -Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 -Path slack : 490654p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:state_1\/main_7 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 489335p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1714,36 +2710,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5836 ++ Data path delay 7155 ------------------------------------- ---- -End-of-path arrival time (ps) 5836 +End-of-path arrival time (ps) 7155 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:ld_ident\/main_2 macrocell12 4586 5836 490654 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:state_1\/main_7 macrocell21 5045 7155 489335 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_2 +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:cnt_enable\/main_4 Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490654p +Path slack : 489421p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1754,36 +2750,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5836 ++ Data path delay 7069 ------------------------------------- ---- -End-of-path arrival time (ps) 5836 +End-of-path arrival time (ps) 7069 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_2 macrocell9 4586 5836 490654 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_4 macrocell10 4959 7069 489421 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 38 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_1\/main_2 +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:state_1\/main_4 Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490654p +Path slack : 489421p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1794,36 +2790,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5836 ++ Data path delay 7069 ------------------------------------- ---- -End-of-path arrival time (ps) 5836 +End-of-path arrival time (ps) 7069 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:state_1\/main_2 macrocell20 4586 5836 490654 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:state_1\/main_4 macrocell21 4959 7069 489421 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 39 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:cnt_enable\/main_5 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490656p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:mosi_hs_reg\/main_2 +Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 +Path slack : 489615p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1834,36 +2830,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5834 ++ Data path delay 6875 ------------------------------------- ---- -End-of-path arrival time (ps) 5834 +End-of-path arrival time (ps) 6875 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_5 macrocell9 3724 5834 490656 RISE 1 +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_2 macrocell17 5625 6875 489615 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 -++++ Path 40 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:state_1\/main_5 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490656p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:is_spi_done\/main_0 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 489635p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1874,36 +2870,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5834 ++ Data path delay 6855 ------------------------------------- ---- -End-of-path arrival time (ps) 5834 +End-of-path arrival time (ps) 6855 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:state_1\/main_5 macrocell20 3724 5834 490656 RISE 1 +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_0 macrocell12 5605 6855 489635 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 41 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:cnt_enable\/main_7 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490657p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:state_0\/main_0 +Capture Clock : \SPIM:BSPIM:state_0\/clock_0 +Path slack : 489635p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1914,36 +2910,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5833 ++ Data path delay 6855 ------------------------------------- ---- -End-of-path arrival time (ps) 5833 +End-of-path arrival time (ps) 6855 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_7 macrocell9 3723 5833 490657 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:state_0\/main_0 macrocell20 5605 6855 489635 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 -++++ Path 42 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:state_1\/main_7 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490657p +Path Begin : \SPIM:BSPIM:state_2\/q +Path End : \SPIM:BSPIM:state_2\/main_0 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 489635p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1954,36 +2950,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5833 ++ Data path delay 6855 ------------------------------------- ---- -End-of-path arrival time (ps) 5833 +End-of-path arrival time (ps) 6855 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:state_1\/main_7 macrocell20 3723 5833 490657 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_2\/q macrocell22 1250 1250 484163 RISE 1 +\SPIM:BSPIM:state_2\/main_0 macrocell22 5605 6855 489635 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 43 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:load_cond\/main_7 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490667p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:is_spi_done\/main_5 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 489693p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -1994,9 +2990,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5823 ++ Data path delay 6797 ------------------------------------- ---- -End-of-path arrival time (ps) 5823 +End-of-path arrival time (ps) 6797 Launch Clock Path pin name model name delay AT edge Fanout @@ -2007,23 +3003,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:load_cond\/main_7 macrocell13 3713 5823 490667 RISE 1 +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_5 macrocell12 4687 6797 489693 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 44 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:load_rx_data\/main_4 -Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 -Path slack : 490667p +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:state_2\/main_5 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 489693p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2034,9 +3030,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5823 ++ Data path delay 6797 ------------------------------------- ---- -End-of-path arrival time (ps) 5823 +End-of-path arrival time (ps) 6797 Launch Clock Path pin name model name delay AT edge Fanout @@ -2045,25 +3041,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_4 macrocell14 3713 5823 490667 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:state_2\/main_5 macrocell22 4687 6797 489693 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 45 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:load_cond\/main_5 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490672p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : Net_439/main_2 +Capture Clock : Net_439/clock_0 +Path slack : 489737p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2074,36 +3070,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5818 ++ Data path delay 6753 ------------------------------------- ---- -End-of-path arrival time (ps) 5818 +End-of-path arrival time (ps) 6753 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:load_cond\/main_5 macrocell13 3708 5818 490672 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +Net_439/main_2 macrocell7 5503 6753 489737 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 - +Net_439/clock_0 macrocell7 0 0 RISE 1 -++++ Path 46 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:load_rx_data\/main_2 -Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 -Path slack : 490672p +++++ Path 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : Net_479/main_3 +Capture Clock : Net_479/clock_0 +Path slack : 489737p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2114,36 +3110,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5818 ++ Data path delay 6753 ------------------------------------- ---- -End-of-path arrival time (ps) 5818 +End-of-path arrival time (ps) 6753 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_2 macrocell14 3708 5818 490672 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +Net_479/main_3 macrocell8 5503 6753 489737 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +Net_479/clock_0 macrocell8 0 0 RISE 1 -++++ Path 47 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:is_spi_done\/main_0 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 490754p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:load_cond\/main_7 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 489892p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2154,36 +3150,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5736 ++ Data path delay 6598 ------------------------------------- ---- -End-of-path arrival time (ps) 5736 +End-of-path arrival time (ps) 6598 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_0 macrocell11 4486 5736 490754 RISE 1 +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:load_cond\/main_7 macrocell14 4488 6598 489892 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 48 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_0\/main_0 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 490754p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:load_rx_data\/main_4 +Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 +Path slack : 489892p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2194,36 +3190,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5736 ++ Data path delay 6598 ------------------------------------- ---- -End-of-path arrival time (ps) 5736 +End-of-path arrival time (ps) 6598 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:state_0\/main_0 macrocell19 4486 5736 490754 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:load_rx_data\/main_4 macrocell15 4488 6598 489892 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 -++++ Path 49 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_2\/main_0 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 490754p +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:load_cond\/main_4 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 489973p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2234,36 +3230,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5736 ++ Data path delay 6517 ------------------------------------- ---- -End-of-path arrival time (ps) 5736 +End-of-path arrival time (ps) 6517 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:state_2\/main_0 macrocell21 4486 5736 490754 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:load_cond\/main_4 macrocell14 4407 6517 489973 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 50 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:mosi_hs_reg\/main_2 -Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 490842p +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:load_rx_data\/main_1 +Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 +Path slack : 489973p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2274,36 +3270,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5648 ++ Data path delay 6517 ------------------------------------- ---- -End-of-path arrival time (ps) 5648 +End-of-path arrival time (ps) 6517 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_2 macrocell16 4398 5648 490842 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:load_rx_data\/main_1 macrocell15 4407 6517 489973 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 -++++ Path 51 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : Net_479/main_3 -Capture Clock : Net_479/clock_0 -Path slack : 490844p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:ld_ident\/main_1 +Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 +Path slack : 490069p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2314,36 +3310,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5646 ++ Data path delay 6421 ------------------------------------- ---- -End-of-path arrival time (ps) 5646 +End-of-path arrival time (ps) 6421 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -Net_479/main_3 macrocell8 4396 5646 490844 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:ld_ident\/main_1 macrocell13 5171 6421 490069 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_479/clock_0 macrocell8 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 -++++ Path 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:load_cond\/main_2 +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:load_cond\/main_1 Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490844p +Path slack : 490069p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2354,36 +3350,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5646 ++ Data path delay 6421 ------------------------------------- ---- -End-of-path arrival time (ps) 5646 +End-of-path arrival time (ps) 6421 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ----------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:load_cond\/main_2 macrocell13 4396 5646 490844 RISE 1 +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:load_cond\/main_1 macrocell14 5171 6421 490069 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:is_spi_done\/main_1 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491050p +Path Begin : \SPIM:BSPIM:BitCounter\/count_4 +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_4 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 490154p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2394,36 +3390,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5440 ++ Data path delay 6336 ------------------------------------- ---- -End-of-path arrival time (ps) 5440 +End-of-path arrival time (ps) 6336 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_1 macrocell11 4190 5440 491050 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_4 macrocell18 4226 6336 490154 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_0\/main_1 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491050p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:ld_ident\/main_2 +Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 +Path slack : 490244p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2434,36 +3430,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5440 ++ Data path delay 6246 ------------------------------------- ---- -End-of-path arrival time (ps) 5440 +End-of-path arrival time (ps) 6246 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:state_0\/main_1 macrocell19 4190 5440 491050 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:ld_ident\/main_2 macrocell13 4996 6246 490244 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 -++++ Path 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_2\/main_1 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491050p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:load_cond\/main_2 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 490244p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2474,36 +3470,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5440 ++ Data path delay 6246 ------------------------------------- ---- -End-of-path arrival time (ps) 5440 +End-of-path arrival time (ps) 6246 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:state_2\/main_1 macrocell21 4190 5440 491050 RISE 1 +pin name model name delay AT slack edge Fanout +----------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:load_cond\/main_2 macrocell14 4996 6246 490244 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_1 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491073p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:cnt_enable\/main_2 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 490259p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2514,36 +3510,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5417 ++ Data path delay 6231 ------------------------------------- ---- -End-of-path arrival time (ps) 5417 +End-of-path arrival time (ps) 6231 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_1 macrocell17 4167 5417 491073 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------ ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_2 macrocell10 4981 6231 490259 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_0 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491220p +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:state_1\/main_2 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 490259p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2554,36 +3550,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5270 ++ Data path delay 6231 ------------------------------------- ---- -End-of-path arrival time (ps) 5270 +End-of-path arrival time (ps) 6231 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell21 1250 1250 486427 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_0 macrocell17 4020 5270 491220 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:state_1\/main_2 macrocell21 4981 6231 490259 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_7 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491268p +Path Begin : \SPIM:BSPIM:BitCounter\/count_4 +Path End : \SPIM:BSPIM:load_cond\/main_3 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 490277p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2594,9 +3590,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5222 ++ Data path delay 6213 ------------------------------------- ---- -End-of-path arrival time (ps) 5222 +End-of-path arrival time (ps) 6213 Launch Clock Path pin name model name delay AT edge Fanout @@ -2605,25 +3601,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_7 macrocell17 3112 5222 491268 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:load_cond\/main_3 macrocell14 4103 6213 490277 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:is_spi_done\/main_6 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491270p +Path Begin : \SPIM:BSPIM:BitCounter\/count_4 +Path End : \SPIM:BSPIM:load_rx_data\/main_0 +Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 +Path slack : 490277p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2634,9 +3630,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5220 ++ Data path delay 6213 ------------------------------------- ---- -End-of-path arrival time (ps) 5220 +End-of-path arrival time (ps) 6213 Launch Clock Path pin name model name delay AT edge Fanout @@ -2645,25 +3641,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_6 macrocell11 3110 5220 491270 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:load_rx_data\/main_0 macrocell15 4103 6213 490277 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 -++++ Path 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:state_2\/main_6 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491270p +Path End : \SPIM:BSPIM:load_cond\/main_6 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 490389p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2674,9 +3670,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5220 ++ Data path delay 6101 ------------------------------------- ---- -End-of-path arrival time (ps) 5220 +End-of-path arrival time (ps) 6101 Launch Clock Path pin name model name delay AT edge Fanout @@ -2687,23 +3683,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 486627 RISE 1 -\SPIM:BSPIM:state_2\/main_6 macrocell21 3110 5220 491270 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:load_cond\/main_6 macrocell14 3991 6101 490389 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 -++++ Path 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_5 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491415p +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:load_rx_data\/main_3 +Capture Clock : \SPIM:BSPIM:load_rx_data\/clock_0 +Path slack : 490389p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2714,9 +3710,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5075 ++ Data path delay 6101 ------------------------------------- ---- -End-of-path arrival time (ps) 5075 +End-of-path arrival time (ps) 6101 Launch Clock Path pin name model name delay AT edge Fanout @@ -2727,23 +3723,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_5 macrocell17 2965 5075 491415 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:load_rx_data\/main_3 macrocell15 3991 6101 490389 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 -++++ Path 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:is_spi_done\/main_4 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491426p +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:cnt_enable\/main_6 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 490547p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2754,9 +3750,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5064 ++ Data path delay 5943 ------------------------------------- ---- -End-of-path arrival time (ps) 5064 +End-of-path arrival time (ps) 5943 Launch Clock Path pin name model name delay AT edge Fanout @@ -2767,23 +3763,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_4 macrocell11 2954 5064 491426 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_6 macrocell10 3833 5943 490547 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:state_2\/main_4 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491426p +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:state_1\/main_6 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 490547p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2794,9 +3790,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5064 ++ Data path delay 5943 ------------------------------------- ---- -End-of-path arrival time (ps) 5064 +End-of-path arrival time (ps) 5943 Launch Clock Path pin name model name delay AT edge Fanout @@ -2807,23 +3803,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486847 RISE 1 -\SPIM:BSPIM:state_2\/main_4 macrocell21 2954 5064 491426 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:state_1\/main_6 macrocell21 3833 5943 490547 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : Net_479/q -Path End : Net_479/main_0 -Capture Clock : Net_479/clock_0 -Path slack : 491459p +Path Begin : \SPIM:BSPIM:BitCounter\/count_4 +Path End : \SPIM:BSPIM:is_spi_done\/main_3 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 490709p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2834,36 +3830,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5031 ++ Data path delay 5781 ------------------------------------- ---- -End-of-path arrival time (ps) 5031 +End-of-path arrival time (ps) 5781 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_479/clock_0 macrocell8 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------- ----------- ----- ----- ------ ---- ------ -Net_479/q macrocell8 1250 1250 491459 RISE 1 -Net_479/main_0 macrocell8 3781 5031 491459 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_3 macrocell12 3671 5781 490709 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_479/clock_0 macrocell8 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 87 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:is_spi_done\/main_2 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491497p +Path Begin : \SPIM:BSPIM:BitCounter\/count_4 +Path End : \SPIM:BSPIM:state_2\/main_3 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 490709p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2874,36 +3870,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4993 ++ Data path delay 5781 ------------------------------------- ---- -End-of-path arrival time (ps) 4993 +End-of-path arrival time (ps) 5781 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_2 macrocell11 3743 4993 491497 RISE 1 +\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 483289 RISE 1 +\SPIM:BSPIM:state_2\/main_3 macrocell22 3671 5781 490709 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_0\/main_2 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491497p +Path End : \SPIM:BSPIM:is_spi_done\/main_2 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 490956p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2914,36 +3910,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4993 ++ Data path delay 5534 ------------------------------------- ---- -End-of-path arrival time (ps) 4993 +End-of-path arrival time (ps) 5534 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:state_0\/main_2 macrocell19 3743 4993 491497 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_2 macrocell12 4284 5534 490956 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_2\/main_2 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491497p +Path End : \SPIM:BSPIM:state_0\/main_2 +Capture Clock : \SPIM:BSPIM:state_0\/clock_0 +Path slack : 490956p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2954,36 +3950,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4993 ++ Data path delay 5534 ------------------------------------- ---- -End-of-path arrival time (ps) 4993 +End-of-path arrival time (ps) 5534 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout --------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:state_2\/main_2 macrocell21 3743 4993 491497 RISE 1 +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:state_0\/main_2 macrocell20 4284 5534 490956 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 -++++ Path 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_2 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491497p +Path End : \SPIM:BSPIM:state_2\/main_2 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 490956p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -2994,36 +3990,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4993 ++ Data path delay 5534 ------------------------------------- ---- -End-of-path arrival time (ps) 4993 +End-of-path arrival time (ps) 5534 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell19 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell19 1250 1250 487170 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_2 macrocell17 3743 4993 491497 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:state_2\/main_2 macrocell22 4284 5534 490956 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_4 +Path Begin : \SPIM:BSPIM:BitCounter\/count_2 +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_6 Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491549p +Path slack : 491102p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3034,9 +4030,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4941 ++ Data path delay 5388 ------------------------------------- ---- -End-of-path arrival time (ps) 4941 +End-of-path arrival time (ps) 5388 Launch Clock Path pin name model name delay AT edge Fanout @@ -3047,23 +4043,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_4 macrocell17 2831 4941 491549 RISE 1 +\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 480914 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_6 macrocell18 3278 5388 491102 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:is_spi_done\/main_3 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491567p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:cnt_enable\/main_1 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 491187p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3074,36 +4070,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4923 ++ Data path delay 5303 ------------------------------------- ---- -End-of-path arrival time (ps) 4923 +End-of-path arrival time (ps) 5303 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_3 macrocell11 2813 4923 491567 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------ ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_1 macrocell10 4053 5303 491187 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:state_2\/main_3 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491567p +Path Begin : \SPIM:BSPIM:state_1\/q +Path End : \SPIM:BSPIM:state_1\/main_1 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 491187p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3114,36 +4110,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4923 ++ Data path delay 5303 ------------------------------------- ---- -End-of-path arrival time (ps) 4923 +End-of-path arrival time (ps) 5303 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486920 RISE 1 -\SPIM:BSPIM:state_2\/main_3 macrocell21 2813 4923 491567 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:state_1\/q macrocell21 1250 1250 482386 RISE 1 +\SPIM:BSPIM:state_1\/main_1 macrocell21 4053 5303 491187 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_8 +Path Begin : \SPIM:BSPIM:state_0\/q +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_2 Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491754p +Path slack : 491235p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3154,36 +4150,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4736 ++ Data path delay 5255 ------------------------------------- ---- -End-of-path arrival time (ps) 4736 +End-of-path arrival time (ps) 5255 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:state_0\/clock_0 macrocell20 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_8 macrocell17 2626 4736 491754 RISE 1 +\SPIM:BSPIM:state_0\/q macrocell20 1250 1250 486610 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_2 macrocell18 4005 5255 491235 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 95 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_6 +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_7 Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491757p +Path slack : 491268p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3194,9 +4190,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4733 ++ Data path delay 5222 ------------------------------------- ---- -End-of-path arrival time (ps) 4733 +End-of-path arrival time (ps) 5222 Launch Clock Path pin name model name delay AT edge Fanout @@ -3207,23 +4203,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_6 macrocell17 2623 4733 491757 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_7 macrocell18 3112 5222 491268 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:is_spi_done\/main_7 +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:is_spi_done\/main_6 Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491764p +Path slack : 491270p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3234,9 +4230,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4726 ++ Data path delay 5220 ------------------------------------- ---- -End-of-path arrival time (ps) 4726 +End-of-path arrival time (ps) 5220 Launch Clock Path pin name model name delay AT edge Fanout @@ -3247,23 +4243,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_7 macrocell11 2616 4726 491764 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_6 macrocell12 3110 5220 491270 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:state_2\/main_7 +Path Begin : \SPIM:BSPIM:BitCounter\/count_1 +Path End : \SPIM:BSPIM:state_2\/main_6 Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491764p +Path slack : 491270p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3274,9 +4270,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4726 ++ Data path delay 5220 ------------------------------------- ---- -End-of-path arrival time (ps) 4726 +End-of-path arrival time (ps) 5220 Launch Clock Path pin name model name delay AT edge Fanout @@ -3287,23 +4283,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486941 RISE 1 -\SPIM:BSPIM:state_2\/main_7 macrocell21 2616 4726 491764 RISE 1 +\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 483401 RISE 1 +\SPIM:BSPIM:state_2\/main_6 macrocell22 3110 5220 491270 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:is_spi_done\/main_5 -Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 491769p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_8 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 491427p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3314,9 +4310,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4721 ++ Data path delay 5063 ------------------------------------- ---- -End-of-path arrival time (ps) 4721 +End-of-path arrival time (ps) 5063 Launch Clock Path pin name model name delay AT edge Fanout @@ -3325,25 +4321,25 @@ ClockBlock/dclk_glb_0 clockblockcell 0 \SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_5 macrocell11 2611 4721 491769 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_8 macrocell18 2953 5063 491427 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:state_2\/main_5 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491769p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:is_spi_done\/main_7 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 491437p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3354,9 +4350,9 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4721 ++ Data path delay 5053 ------------------------------------- ---- -End-of-path arrival time (ps) 4721 +End-of-path arrival time (ps) 5053 Launch Clock Path pin name model name delay AT edge Fanout @@ -3367,23 +4363,23 @@ ClockBlock/dclk_glb_0 clockblockcell 0 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 486946 RISE 1 -\SPIM:BSPIM:state_2\/main_5 macrocell21 2611 4721 491769 RISE 1 +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_7 macrocell12 2943 5053 491437 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:ld_ident\/q -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_10 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 491866p +Path Begin : \SPIM:BSPIM:BitCounter\/count_0 +Path End : \SPIM:BSPIM:state_2\/main_7 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 491437p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3394,36 +4390,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4624 ++ Data path delay 5053 ------------------------------------- ---- -End-of-path arrival time (ps) 4624 +End-of-path arrival time (ps) 5053 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:ld_ident\/q macrocell12 1250 1250 491866 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_10 macrocell17 3374 4624 491866 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 482904 RISE 1 +\SPIM:BSPIM:state_2\/main_7 macrocell22 2943 5053 491437 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 101 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:is_spi_done\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_8 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 492007p +Path Begin : Net_479/q +Path End : Net_479/main_0 +Capture Clock : Net_479/clock_0 +Path slack : 491718p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3434,36 +4430,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4483 ++ Data path delay 4772 ------------------------------------- ---- -End-of-path arrival time (ps) 4483 +End-of-path arrival time (ps) 4772 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +Net_479/clock_0 macrocell8 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:is_spi_done\/q macrocell11 1250 1250 492007 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_8 macrocell9 3233 4483 492007 RISE 1 +pin name model name delay AT slack edge Fanout +-------------- ----------- ----- ----- ------ ---- ------ +Net_479/q macrocell8 1250 1250 491718 RISE 1 +Net_479/main_0 macrocell8 3522 4772 491718 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +Net_479/clock_0 macrocell8 0 0 RISE 1 -++++ Path 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:is_spi_done\/q -Path End : \SPIM:BSPIM:state_1\/main_9 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 492007p +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_5 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 491757p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3474,36 +4470,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4483 ++ Data path delay 4733 ------------------------------------- ---- -End-of-path arrival time (ps) 4483 +End-of-path arrival time (ps) 4733 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:is_spi_done\/q macrocell11 1250 1250 492007 RISE 1 -\SPIM:BSPIM:state_1\/main_9 macrocell20 3233 4483 492007 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_5 macrocell18 2623 4733 491757 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 103 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:mosi_hs_reg\/q -Path End : \SPIM:BSPIM:mosi_hs_reg\/main_4 -Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 492087p +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:is_spi_done\/main_4 +Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 +Path slack : 491765p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3514,36 +4510,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4403 ++ Data path delay 4725 ------------------------------------- ---- -End-of-path arrival time (ps) 4403 +End-of-path arrival time (ps) 4725 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:mosi_hs_reg\/q macrocell16 1250 1250 492087 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_4 macrocell16 3153 4403 492087 RISE 1 +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_4 macrocell12 2615 4725 491765 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 104 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_1 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 492150p +Path Begin : \SPIM:BSPIM:BitCounter\/count_3 +Path End : \SPIM:BSPIM:state_2\/main_4 +Capture Clock : \SPIM:BSPIM:state_2\/clock_0 +Path slack : 491765p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3554,76 +4550,76 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4340 ++ Data path delay 4725 ------------------------------------- ---- -End-of-path arrival time (ps) 4340 +End-of-path arrival time (ps) 4725 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_1 macrocell9 3090 4340 492150 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 482985 RISE 1 +\SPIM:BSPIM:state_2\/main_4 macrocell22 2615 4725 491765 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_1\/main_1 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 492150p +Path Begin : \SPIM:BSPIM:cnt_enable\/q +Path End : \SPIM:BSPIM:BitCounter\/enable +Capture Clock : \SPIM:BSPIM:BitCounter\/clock +Path slack : 492008p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 +- Setup time -3340 -------------------------------------------------------- ------ -End-of-path required time (ps) 496490 +End-of-path required time (ps) 496660 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4340 ++ Data path delay 4652 ------------------------------------- ---- -End-of-path arrival time (ps) 4340 +End-of-path arrival time (ps) 4652 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:state_1\/main_1 macrocell20 3090 4340 492150 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------ ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:cnt_enable\/q macrocell10 1250 1250 492008 RISE 1 +\SPIM:BSPIM:BitCounter\/enable count7cell 3402 4652 492008 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 -++++ Path 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : Net_439/main_1 -Capture Clock : Net_439/clock_0 -Path slack : 492151p +Path Begin : \SPIM:BSPIM:ld_ident\/q +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_10 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 +Path slack : 492011p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3634,36 +4630,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4339 ++ Data path delay 4479 ------------------------------------- ---- -End-of-path arrival time (ps) 4339 +End-of-path arrival time (ps) 4479 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -Net_439/main_1 macrocell7 3089 4339 492151 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:ld_ident\/q macrocell13 1250 1250 492011 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_10 macrocell18 3229 4479 492011 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_439/clock_0 macrocell7 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:ld_ident\/main_1 -Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 -Path slack : 492151p +Path Begin : \SPIM:BSPIM:is_spi_done\/q +Path End : \SPIM:BSPIM:cnt_enable\/main_8 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 492033p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3674,76 +4670,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4339 -------------------------------------- ---- -End-of-path arrival time (ps) 4339 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:ld_ident\/main_1 macrocell12 3089 4339 492151 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 - - - -++++ Path 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:cnt_enable\/q -Path End : \SPIM:BSPIM:BitCounter\/enable -Capture Clock : \SPIM:BSPIM:BitCounter\/clock -Path slack : 492188p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3340 --------------------------------------------------------- ------ -End-of-path required time (ps) 496660 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4472 ++ Data path delay 4457 ------------------------------------- ---- -End-of-path arrival time (ps) 4472 +End-of-path arrival time (ps) 4457 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:cnt_enable\/q macrocell9 1250 1250 492188 RISE 1 -\SPIM:BSPIM:BitCounter\/enable count7cell 3222 4472 492188 RISE 1 +\SPIM:BSPIM:is_spi_done\/q macrocell12 1250 1250 492033 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_8 macrocell10 3207 4457 492033 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 87 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : Net_479/main_2 -Capture Clock : Net_479/clock_0 -Path slack : 492292p +Path Begin : \SPIM:BSPIM:is_spi_done\/q +Path End : \SPIM:BSPIM:state_1\/main_9 +Capture Clock : \SPIM:BSPIM:state_1\/clock_0 +Path slack : 492033p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3754,36 +4710,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4198 ++ Data path delay 4457 ------------------------------------- ---- -End-of-path arrival time (ps) 4198 +End-of-path arrival time (ps) 4457 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -Net_479/main_2 macrocell8 2948 4198 492292 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:is_spi_done\/q macrocell12 1250 1250 492033 RISE 1 +\SPIM:BSPIM:state_1\/main_9 macrocell21 3207 4457 492033 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_479/clock_0 macrocell8 0 0 RISE 1 +\SPIM:BSPIM:state_1\/clock_0 macrocell21 0 0 RISE 1 -++++ Path 88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:load_cond\/main_1 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 492292p +Path Begin : \SPIM:BSPIM:mosi_hs_reg\/q +Path End : \SPIM:BSPIM:mosi_hs_reg\/main_4 +Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 +Path slack : 492044p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3794,36 +4750,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4198 ++ Data path delay 4446 ------------------------------------- ---- -End-of-path arrival time (ps) 4198 +End-of-path arrival time (ps) 4446 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell20 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell20 1250 1250 486723 RISE 1 -\SPIM:BSPIM:load_cond\/main_1 macrocell13 2948 4198 492292 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:mosi_hs_reg\/q macrocell17 1250 1250 492044 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_4 macrocell17 3196 4446 492044 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell13 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 -++++ Path 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:mosi_from_dp_reg\/q Path End : \SPIM:BSPIM:mosi_hs_reg\/main_5 Capture Clock : \SPIM:BSPIM:mosi_hs_reg\/clock_0 -Path slack : 492317p +Path slack : 492330p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3834,36 +4790,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4173 ++ Data path delay 4160 ------------------------------------- ---- -End-of-path arrival time (ps) 4173 +End-of-path arrival time (ps) 4160 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_from_dp_reg\/clock_0 macrocell15 0 0 RISE 1 +\SPIM:BSPIM:mosi_from_dp_reg\/clock_0 macrocell16 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:mosi_from_dp_reg\/q macrocell15 1250 1250 492317 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/main_5 macrocell16 2923 4173 492317 RISE 1 +\SPIM:BSPIM:mosi_from_dp_reg\/q macrocell16 1250 1250 492330 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/main_5 macrocell17 2910 4160 492330 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell16 0 0 RISE 1 +\SPIM:BSPIM:mosi_hs_reg\/clock_0 macrocell17 0 0 RISE 1 -++++ Path 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 111 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:ld_ident\/q -Path End : \SPIM:BSPIM:ld_ident\/main_3 -Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 -Path slack : 492613p +Path Begin : \SPIM:BSPIM:cnt_enable\/q +Path End : \SPIM:BSPIM:cnt_enable\/main_9 +Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path slack : 492602p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3874,31 +4830,31 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 3877 ++ Data path delay 3888 ------------------------------------- ---- -End-of-path arrival time (ps) 3877 +End-of-path arrival time (ps) 3888 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:ld_ident\/q macrocell12 1250 1250 491866 RISE 1 -\SPIM:BSPIM:ld_ident\/main_3 macrocell12 2627 3877 492613 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------------ ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:cnt_enable\/q macrocell10 1250 1250 492008 RISE 1 +\SPIM:BSPIM:cnt_enable\/main_9 macrocell10 2638 3888 492602 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:ld_ident\/clock_0 macrocell12 0 0 RISE 1 +\SPIM:BSPIM:cnt_enable\/clock_0 macrocell10 0 0 RISE 1 -++++ Path 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : Net_439/q Path End : Net_439/main_3 @@ -3938,12 +4894,12 @@ Net_439/clock_0 macrocell7 0 -++++ Path 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:mosi_pre_reg\/q -Path End : \SPIM:BSPIM:mosi_pre_reg\/main_9 -Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 -Path slack : 492919p +Path Begin : \SPIM:BSPIM:ld_ident\/q +Path End : \SPIM:BSPIM:ld_ident\/main_3 +Capture Clock : \SPIM:BSPIM:ld_ident\/clock_0 +Path slack : 492931p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3954,36 +4910,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 3571 ++ Data path delay 3559 ------------------------------------- ---- -End-of-path arrival time (ps) 3571 +End-of-path arrival time (ps) 3559 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:mosi_pre_reg\/q macrocell17 1250 1250 492919 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/main_9 macrocell17 2321 3571 492919 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:ld_ident\/q macrocell13 1250 1250 492011 RISE 1 +\SPIM:BSPIM:ld_ident\/main_3 macrocell13 2309 3559 492931 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell17 0 0 RISE 1 +\SPIM:BSPIM:ld_ident\/clock_0 macrocell13 0 0 RISE 1 -++++ Path 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:is_spi_done\/q Path End : \SPIM:BSPIM:is_spi_done\/main_9 Capture Clock : \SPIM:BSPIM:is_spi_done\/clock_0 -Path slack : 492930p +Path slack : 492936p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -3994,36 +4950,36 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 3560 ++ Data path delay 3554 ------------------------------------- ---- -End-of-path arrival time (ps) 3560 +End-of-path arrival time (ps) 3554 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:is_spi_done\/q macrocell11 1250 1250 492007 RISE 1 -\SPIM:BSPIM:is_spi_done\/main_9 macrocell11 2310 3560 492930 RISE 1 +\SPIM:BSPIM:is_spi_done\/q macrocell12 1250 1250 492033 RISE 1 +\SPIM:BSPIM:is_spi_done\/main_9 macrocell12 2304 3554 492936 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 -++++ Path 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:is_spi_done\/q Path End : \SPIM:BSPIM:state_2\/main_9 Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 492930p +Path slack : 492936p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4034,35 +4990,75 @@ End-of-path required time (ps) 496490 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 3560 ++ Data path delay 3554 ------------------------------------- ---- -End-of-path arrival time (ps) 3560 +End-of-path arrival time (ps) 3554 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:is_spi_done\/clock_0 macrocell11 0 0 RISE 1 +\SPIM:BSPIM:is_spi_done\/clock_0 macrocell12 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout --------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:is_spi_done\/q macrocell11 1250 1250 492007 RISE 1 -\SPIM:BSPIM:state_2\/main_9 macrocell21 2310 3560 492930 RISE 1 +\SPIM:BSPIM:is_spi_done\/q macrocell12 1250 1250 492033 RISE 1 +\SPIM:BSPIM:state_2\/main_9 macrocell22 2304 3554 492936 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell21 0 0 RISE 1 +\SPIM:BSPIM:state_2\/clock_0 macrocell22 0 0 RISE 1 -++++ Path 95 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \SPIM:BSPIM:cnt_enable\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_9 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 +Path Begin : \SPIM:BSPIM:load_cond\/q +Path End : \SPIM:BSPIM:load_cond\/main_8 +Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 +Path slack : 492943p + +Capture Clock Arrival Time 0 ++ Clock path delay 0 ++ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 +- Setup time -3510 +-------------------------------------------------------- ------ +End-of-path required time (ps) 496490 + +Launch Clock Arrival Time 0 ++ Clock path delay 0 ++ Data path delay 3547 +------------------------------------- ---- +End-of-path arrival time (ps) 3547 + +Launch Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 + +Data path +pin name model name delay AT slack edge Fanout +----------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:load_cond\/q macrocell14 1250 1250 492943 RISE 1 +\SPIM:BSPIM:load_cond\/main_8 macrocell14 2297 3547 492943 RISE 1 + +Capture Clock Path +pin name model name delay AT edge Fanout +--------------------------------------------------------- -------------- ----- ----- ---- ------ +ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 +\SPIM:BSPIM:load_cond\/clock_0 macrocell14 0 0 RISE 1 + + + +++++ Path 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +Path Begin : \SPIM:BSPIM:mosi_pre_reg\/q +Path End : \SPIM:BSPIM:mosi_pre_reg\/main_9 +Capture Clock : \SPIM:BSPIM:mosi_pre_reg\/clock_0 Path slack : 492951p Capture Clock Arrival Time 0 @@ -4082,28 +5078,28 @@ Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:cnt_enable\/q macrocell9 1250 1250 492188 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_9 macrocell9 2289 3539 492951 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------ ---- ------ +\SPIM:BSPIM:mosi_pre_reg\/q macrocell18 1250 1250 492951 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/main_9 macrocell18 2289 3539 492951 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell9 0 0 RISE 1 +\SPIM:BSPIM:mosi_pre_reg\/clock_0 macrocell18 0 0 RISE 1 -++++ Path 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \SPIM:BSPIM:load_rx_data\/q Path End : \SPIM:BSPIM:sR8:Dp:u0\/f1_load Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 493987p +Path slack : 494004p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4114,21 +5110,21 @@ End-of-path required time (ps) 498150 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4163 ++ Data path delay 4146 ------------------------------------- ---- -End-of-path arrival time (ps) 4163 +End-of-path arrival time (ps) 4146 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_rx_data\/clock_0 macrocell14 0 0 RISE 1 +\SPIM:BSPIM:load_rx_data\/clock_0 macrocell15 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------ ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:load_rx_data\/q macrocell14 1250 1250 493987 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/f1_load datapathcell1 2913 4163 493987 RISE 1 +\SPIM:BSPIM:load_rx_data\/q macrocell15 1250 1250 494004 RISE 1 +\SPIM:BSPIM:sR8:Dp:u0\/f1_load datapathcell1 2896 4146 494004 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout @@ -4138,12 +5134,12 @@ ClockBlock/dclk_glb_0 clockblockcell 0 -++++ Path 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 119 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q +Path Begin : \UART_1:BUART:tx_state_1\/q Path End : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 Capture Clock : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock -Path slack : 1060528p +Path slack : 1059785p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4154,38 +5150,38 @@ End-of-path required time (ps) 1071813 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 11285 ++ Data path delay 12028 ------------------------------------- ----- -End-of-path arrival time (ps) 11285 +End-of-path arrival time (ps) 12028 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ----------------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/main_1 macrocell24 4383 5633 1060528 RISE 1 -\UART_1:BUART:counter_load_not\/q macrocell24 3350 8983 1060528 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell3 2302 11285 1060528 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/main_0 macrocell29 5136 6386 1059785 RISE 1 +\UART_1:BUART:counter_load_not\/q macrocell29 3350 9736 1059785 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 datapathcell5 2292 12028 1059785 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell3 0 0 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell5 0 0 RISE 1 -++++ Path 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb Path End : \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 Capture Clock : \UART_1:BUART:sTX:TxShifter:u0\/clock -Path slack : 1063403p +Path slack : 1063406p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4196,38 +5192,38 @@ End-of-path required time (ps) 1077043 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 13640 ++ Data path delay 13638 ------------------------------------- ----- -End-of-path arrival time (ps) 13640 +End-of-path arrival time (ps) 13638 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell3 0 0 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell5 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ---------------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb datapathcell3 5680 5680 1063403 RISE 1 -\UART_1:BUART:tx_bitclk_enable_pre\/main_0 macrocell26 2290 7970 1063403 RISE 1 -\UART_1:BUART:tx_bitclk_enable_pre\/q macrocell26 3350 11320 1063403 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 datapathcell2 2320 13640 1063403 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb datapathcell5 5680 5680 1063406 RISE 1 +\UART_1:BUART:tx_bitclk_enable_pre\/main_0 macrocell31 2301 7981 1063406 RISE 1 +\UART_1:BUART:tx_bitclk_enable_pre\/q macrocell31 3350 11331 1063406 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 datapathcell4 2307 13638 1063406 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 -++++ Path 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 121 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb Path End : \UART_1:BUART:sTX:TxSts\/status_0 Capture Clock : \UART_1:BUART:sTX:TxSts\/clock -Path slack : 1067003p +Path slack : 1067180p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4238,38 +5234,38 @@ End-of-path required time (ps) 1081763 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 14760 ++ Data path delay 14583 ------------------------------------- ----- -End-of-path arrival time (ps) 14760 +End-of-path arrival time (ps) 14583 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------------------------ ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb datapathcell2 5280 5280 1067003 RISE 1 -\UART_1:BUART:tx_status_0\/main_2 macrocell30 3228 8508 1067003 RISE 1 -\UART_1:BUART:tx_status_0\/q macrocell30 3350 11858 1067003 RISE 1 -\UART_1:BUART:sTX:TxSts\/status_0 statusicell3 2902 14760 1067003 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb datapathcell4 5280 5280 1067180 RISE 1 +\UART_1:BUART:tx_status_0\/main_2 macrocell35 3638 8918 1067180 RISE 1 +\UART_1:BUART:tx_status_0\/q macrocell35 3350 12268 1067180 RISE 1 +\UART_1:BUART:sTX:TxSts\/status_0 statusicell4 2314 14583 1067180 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxSts\/clock statusicell3 0 0 RISE 1 +\UART_1:BUART:sTX:TxSts\/clock statusicell4 0 0 RISE 1 -++++ Path 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:sTX:TxShifter:u0\/so_comb Path End : \UART_1:BUART:txn\/main_3 Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1070235p +Path slack : 1070231p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4280,36 +5276,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 9588 ++ Data path delay 9592 ------------------------------------- ---- -End-of-path arrival time (ps) 9588 +End-of-path arrival time (ps) 9592 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout --------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:sTX:TxShifter:u0\/so_comb datapathcell2 7280 7280 1070235 RISE 1 -\UART_1:BUART:txn\/main_3 macrocell32 2308 9588 1070235 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/so_comb datapathcell4 7280 7280 1070231 RISE 1 +\UART_1:BUART:txn\/main_3 macrocell37 2312 9592 1070231 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 101 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 123 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q -Path End : \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 +Path Begin : \UART_1:BUART:tx_state_1\/q +Path End : \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 Capture Clock : \UART_1:BUART:sTX:TxShifter:u0\/clock -Path slack : 1070727p +Path slack : 1070649p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4320,36 +5316,36 @@ End-of-path required time (ps) 1077043 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6316 ++ Data path delay 6394 ------------------------------------- ---- -End-of-path arrival time (ps) 6316 +End-of-path arrival time (ps) 6394 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ----------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 datapathcell2 5066 6316 1070727 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 datapathcell4 5144 6394 1070649 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 -++++ Path 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 124 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb Path End : \UART_1:BUART:tx_state_0\/main_2 Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 -Path slack : 1071316p +Path slack : 1070905p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4360,116 +5356,116 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 8508 ++ Data path delay 8918 ------------------------------------- ---- -End-of-path arrival time (ps) 8508 +End-of-path arrival time (ps) 8918 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout ------------------------------------------------ ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb datapathcell2 5280 5280 1067003 RISE 1 -\UART_1:BUART:tx_state_0\/main_2 macrocell27 3228 8508 1071316 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb datapathcell4 5280 5280 1067180 RISE 1 +\UART_1:BUART:tx_state_0\/main_2 macrocell32 3638 8918 1070905 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 -++++ Path 103 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 125 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb -Path End : \UART_1:BUART:tx_bitclk\/main_0 -Capture Clock : \UART_1:BUART:tx_bitclk\/clock_0 -Path slack : 1071854p +Path Begin : \UART_1:BUART:tx_state_0\/q +Path End : \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 +Capture Clock : \UART_1:BUART:sTX:TxShifter:u0\/clock +Path slack : 1070921p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (Clock_1:R#1 vs. Clock_1:R#2) 1083333 -- Setup time -3510 +- Setup time -6290 -------------------------------------------- ------- -End-of-path required time (ps) 1079823 +End-of-path required time (ps) 1077043 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 7970 ++ Data path delay 6122 ------------------------------------- ---- -End-of-path arrival time (ps) 7970 +End-of-path arrival time (ps) 6122 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell3 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ----------------------------------------------- ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb datapathcell3 5680 5680 1063403 RISE 1 -\UART_1:BUART:tx_bitclk\/main_0 macrocell25 2290 7970 1071854 RISE 1 +pin name model name delay AT slack edge Fanout +----------------------------------------- ------------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_0\/q macrocell32 1250 1250 1060627 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 datapathcell4 4872 6122 1070921 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_bitclk\/clock_0 macrocell25 0 0 RISE 1 +\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell4 0 0 RISE 1 -++++ Path 104 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 126 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_1\/q -Path End : \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 -Capture Clock : \UART_1:BUART:sTX:TxShifter:u0\/clock -Path slack : 1072006p +Path Begin : \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb +Path End : \UART_1:BUART:tx_bitclk\/main_0 +Capture Clock : \UART_1:BUART:tx_bitclk\/clock_0 +Path slack : 1071842p Capture Clock Arrival Time 0 + Clock path delay 0 + Cycle adjust (Clock_1:R#1 vs. Clock_1:R#2) 1083333 -- Setup time -6290 +- Setup time -3510 -------------------------------------------- ------- -End-of-path required time (ps) 1077043 +End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5038 ++ Data path delay 7981 ------------------------------------- ---- -End-of-path arrival time (ps) 5038 +End-of-path arrival time (ps) 7981 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock datapathcell5 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ------------------------------------------ ------------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_1\/q macrocell28 1250 1250 1061125 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 datapathcell2 3788 5038 1072006 RISE 1 +pin name model name delay AT slack edge Fanout +---------------------------------------------- ------------- ----- ----- ------- ---- ------ +\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb datapathcell5 5680 5680 1063406 RISE 1 +\UART_1:BUART:tx_bitclk\/main_0 macrocell30 2301 7981 1071842 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:sTX:TxShifter:u0\/clock datapathcell2 0 0 RISE 1 +\UART_1:BUART:tx_bitclk\/clock_0 macrocell30 0 0 RISE 1 -++++ Path 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 127 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:tx_state_0\/q -Path End : \UART_1:BUART:tx_state_2\/main_1 -Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 -Path slack : 1073497p +Path End : \UART_1:BUART:tx_state_1\/main_1 +Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 +Path slack : 1072326p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4480,36 +5476,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6326 ++ Data path delay 7498 ------------------------------------- ---- -End-of-path arrival time (ps) 6326 +End-of-path arrival time (ps) 7498 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:tx_state_2\/main_1 macrocell29 5076 6326 1073497 RISE 1 +\UART_1:BUART:tx_state_0\/q macrocell32 1250 1250 1060627 RISE 1 +\UART_1:BUART:tx_state_1\/main_1 macrocell33 6248 7498 1072326 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 -++++ Path 106 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q -Path End : \UART_1:BUART:txn\/main_2 -Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1073497p +Path Begin : \UART_1:BUART:tx_bitclk\/q +Path End : \UART_1:BUART:tx_state_1\/main_3 +Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 +Path slack : 1073098p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4520,36 +5516,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 6326 ++ Data path delay 6726 ------------------------------------- ---- -End-of-path arrival time (ps) 6326 +End-of-path arrival time (ps) 6726 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_bitclk\/clock_0 macrocell30 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:txn\/main_2 macrocell32 5076 6326 1073497 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_bitclk\/q macrocell30 1250 1250 1061821 RISE 1 +\UART_1:BUART:tx_state_1\/main_3 macrocell33 5476 6726 1073098 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 -++++ Path 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 129 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q -Path End : \UART_1:BUART:tx_state_0\/main_1 -Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 -Path slack : 1074765p +Path Begin : \UART_1:BUART:tx_state_2\/q +Path End : \UART_1:BUART:tx_state_1\/main_2 +Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 +Path slack : 1073140p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4560,36 +5556,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5058 ++ Data path delay 6684 ------------------------------------- ---- -End-of-path arrival time (ps) 5058 +End-of-path arrival time (ps) 6684 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:tx_state_0\/main_1 macrocell27 3808 5058 1074765 RISE 1 +\UART_1:BUART:tx_state_2\/q macrocell34 1250 1250 1061861 RISE 1 +\UART_1:BUART:tx_state_1\/main_2 macrocell33 5434 6684 1073140 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 -++++ Path 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_0\/q -Path End : \UART_1:BUART:tx_state_1\/main_1 -Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 -Path slack : 1074765p +Path Begin : \UART_1:BUART:tx_state_1\/q +Path End : \UART_1:BUART:tx_state_0\/main_0 +Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 +Path slack : 1073463p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4600,36 +5596,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5058 ++ Data path delay 6360 ------------------------------------- ---- -End-of-path arrival time (ps) 5058 +End-of-path arrival time (ps) 6360 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_0\/q macrocell27 1250 1250 1060528 RISE 1 -\UART_1:BUART:tx_state_1\/main_1 macrocell28 3808 5058 1074765 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:tx_state_0\/main_0 macrocell32 5110 6360 1073463 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 -++++ Path 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 131 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:tx_state_1\/q -Path End : \UART_1:BUART:tx_state_0\/main_0 -Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 -Path slack : 1074800p +Path End : \UART_1:BUART:tx_state_2\/main_0 +Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 +Path slack : 1073465p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4640,36 +5636,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5023 ++ Data path delay 6359 ------------------------------------- ---- -End-of-path arrival time (ps) 5023 +End-of-path arrival time (ps) 6359 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_1\/q macrocell28 1250 1250 1061125 RISE 1 -\UART_1:BUART:tx_state_0\/main_0 macrocell27 3773 5023 1074800 RISE 1 +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:tx_state_2\/main_0 macrocell34 5109 6359 1073465 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 -++++ Path 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 132 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:tx_state_1\/q -Path End : \UART_1:BUART:tx_state_1\/main_0 -Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 -Path slack : 1074800p +Path End : \UART_1:BUART:txn\/main_1 +Capture Clock : \UART_1:BUART:txn\/clock_0 +Path slack : 1073465p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4680,36 +5676,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5023 ++ Data path delay 6359 ------------------------------------- ---- -End-of-path arrival time (ps) 5023 +End-of-path arrival time (ps) 6359 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_1\/q macrocell28 1250 1250 1061125 RISE 1 -\UART_1:BUART:tx_state_1\/main_0 macrocell28 3773 5023 1074800 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:txn\/main_1 macrocell37 5109 6359 1073465 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 111 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 133 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_1\/q -Path End : \UART_1:BUART:tx_state_2\/main_0 -Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 -Path slack : 1074813p +Path Begin : \UART_1:BUART:tx_state_0\/q +Path End : \UART_1:BUART:tx_state_0\/main_1 +Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 +Path slack : 1074975p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4720,36 +5716,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5010 ++ Data path delay 4849 ------------------------------------- ---- -End-of-path arrival time (ps) 5010 +End-of-path arrival time (ps) 4849 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_1\/q macrocell28 1250 1250 1061125 RISE 1 -\UART_1:BUART:tx_state_2\/main_0 macrocell29 3760 5010 1074813 RISE 1 +\UART_1:BUART:tx_state_0\/q macrocell32 1250 1250 1060627 RISE 1 +\UART_1:BUART:tx_state_0\/main_1 macrocell32 3599 4849 1074975 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 -++++ Path 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_1\/q -Path End : \UART_1:BUART:txn\/main_1 -Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1074813p +Path Begin : \UART_1:BUART:tx_state_0\/q +Path End : \UART_1:BUART:tx_state_2\/main_1 +Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 +Path slack : 1074977p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4760,36 +5756,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 5010 ++ Data path delay 4847 ------------------------------------- ---- -End-of-path arrival time (ps) 5010 +End-of-path arrival time (ps) 4847 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_1\/q macrocell28 1250 1250 1061125 RISE 1 -\UART_1:BUART:txn\/main_1 macrocell32 3760 5010 1074813 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_0\/q macrocell32 1250 1250 1060627 RISE 1 +\UART_1:BUART:tx_state_2\/main_1 macrocell34 3597 4847 1074977 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 -++++ Path 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:txn\/q -Path End : \UART_1:BUART:txn\/main_0 +Path Begin : \UART_1:BUART:tx_state_0\/q +Path End : \UART_1:BUART:txn\/main_2 Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1075397p +Path slack : 1074977p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4800,36 +5796,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4426 ++ Data path delay 4847 ------------------------------------- ---- -End-of-path arrival time (ps) 4426 +End-of-path arrival time (ps) 4847 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout -------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:txn\/q macrocell32 1250 1250 1075397 RISE 1 -\UART_1:BUART:txn\/main_0 macrocell32 3176 4426 1075397 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_0\/q macrocell32 1250 1250 1060627 RISE 1 +\UART_1:BUART:txn\/main_2 macrocell37 3597 4847 1074977 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 136 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : \UART_1:BUART:tx_bitclk\/q Path End : \UART_1:BUART:tx_state_0\/main_4 Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 -Path slack : 1075478p +Path slack : 1075470p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4840,36 +5836,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4346 ++ Data path delay 4354 ------------------------------------- ---- -End-of-path arrival time (ps) 4346 +End-of-path arrival time (ps) 4354 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_bitclk\/clock_0 macrocell25 0 0 RISE 1 +\UART_1:BUART:tx_bitclk\/clock_0 macrocell30 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_bitclk\/q macrocell25 1250 1250 1061814 RISE 1 -\UART_1:BUART:tx_state_0\/main_4 macrocell27 3096 4346 1075478 RISE 1 +\UART_1:BUART:tx_bitclk\/q macrocell30 1250 1250 1061821 RISE 1 +\UART_1:BUART:tx_state_0\/main_4 macrocell32 3104 4354 1075470 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 -++++ Path 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 137 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_bitclk\/q -Path End : \UART_1:BUART:tx_state_1\/main_3 -Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 -Path slack : 1075478p +Path Begin : \UART_1:BUART:tx_state_2\/q +Path End : \UART_1:BUART:tx_state_0\/main_3 +Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 +Path slack : 1075511p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4880,36 +5876,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4346 ++ Data path delay 4312 ------------------------------------- ---- -End-of-path arrival time (ps) 4346 +End-of-path arrival time (ps) 4312 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_bitclk\/clock_0 macrocell25 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_bitclk\/q macrocell25 1250 1250 1061814 RISE 1 -\UART_1:BUART:tx_state_1\/main_3 macrocell28 3096 4346 1075478 RISE 1 +\UART_1:BUART:tx_state_2\/q macrocell34 1250 1250 1061861 RISE 1 +\UART_1:BUART:tx_state_0\/main_3 macrocell32 3062 4312 1075511 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:tx_state_0\/clock_0 macrocell32 0 0 RISE 1 -++++ Path 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_2\/q -Path End : \UART_1:BUART:tx_state_0\/main_3 -Capture Clock : \UART_1:BUART:tx_state_0\/clock_0 -Path slack : 1075508p +Path Begin : \UART_1:BUART:tx_bitclk\/q +Path End : \UART_1:BUART:tx_state_2\/main_3 +Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 +Path slack : 1075605p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4920,36 +5916,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4316 ++ Data path delay 4218 ------------------------------------- ---- -End-of-path arrival time (ps) 4316 +End-of-path arrival time (ps) 4218 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_bitclk\/clock_0 macrocell30 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_2\/q macrocell29 1250 1250 1061848 RISE 1 -\UART_1:BUART:tx_state_0\/main_3 macrocell27 3066 4316 1075508 RISE 1 +\UART_1:BUART:tx_bitclk\/q macrocell30 1250 1250 1061821 RISE 1 +\UART_1:BUART:tx_state_2\/main_3 macrocell34 2968 4218 1075605 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_0\/clock_0 macrocell27 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 -++++ Path 117 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 139 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_2\/q -Path End : \UART_1:BUART:tx_state_1\/main_2 -Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 -Path slack : 1075508p +Path Begin : \UART_1:BUART:tx_bitclk\/q +Path End : \UART_1:BUART:txn\/main_5 +Capture Clock : \UART_1:BUART:txn\/clock_0 +Path slack : 1075605p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -4960,36 +5956,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4316 ++ Data path delay 4218 ------------------------------------- ---- -End-of-path arrival time (ps) 4316 +End-of-path arrival time (ps) 4218 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_bitclk\/clock_0 macrocell30 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_2\/q macrocell29 1250 1250 1061848 RISE 1 -\UART_1:BUART:tx_state_1\/main_2 macrocell28 3066 4316 1075508 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_bitclk\/q macrocell30 1250 1250 1061821 RISE 1 +\UART_1:BUART:txn\/main_5 macrocell37 2968 4218 1075605 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_1\/clock_0 macrocell28 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_bitclk\/q -Path End : \UART_1:BUART:tx_state_2\/main_3 +Path Begin : \UART_1:BUART:tx_state_2\/q +Path End : \UART_1:BUART:tx_state_2\/main_2 Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 -Path slack : 1075606p +Path slack : 1075618p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -5000,36 +5996,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4218 ++ Data path delay 4206 ------------------------------------- ---- -End-of-path arrival time (ps) 4218 +End-of-path arrival time (ps) 4206 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_bitclk\/clock_0 macrocell25 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 Data path pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_bitclk\/q macrocell25 1250 1250 1061814 RISE 1 -\UART_1:BUART:tx_state_2\/main_3 macrocell29 2968 4218 1075606 RISE 1 +\UART_1:BUART:tx_state_2\/q macrocell34 1250 1250 1061861 RISE 1 +\UART_1:BUART:tx_state_2\/main_2 macrocell34 2956 4206 1075618 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 -++++ Path 119 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_bitclk\/q -Path End : \UART_1:BUART:txn\/main_5 +Path Begin : \UART_1:BUART:tx_state_2\/q +Path End : \UART_1:BUART:txn\/main_4 Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1075606p +Path slack : 1075618p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -5040,36 +6036,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4218 ++ Data path delay 4206 ------------------------------------- ---- -End-of-path arrival time (ps) 4218 +End-of-path arrival time (ps) 4206 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_bitclk\/clock_0 macrocell25 0 0 RISE 1 +\UART_1:BUART:tx_state_2\/clock_0 macrocell34 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_bitclk\/q macrocell25 1250 1250 1061814 RISE 1 -\UART_1:BUART:txn\/main_5 macrocell32 2968 4218 1075606 RISE 1 +pin name model name delay AT slack edge Fanout +--------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_2\/q macrocell34 1250 1250 1061861 RISE 1 +\UART_1:BUART:txn\/main_4 macrocell37 2956 4206 1075618 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 142 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_2\/q -Path End : \UART_1:BUART:tx_state_2\/main_2 -Capture Clock : \UART_1:BUART:tx_state_2\/clock_0 -Path slack : 1075640p +Path Begin : \UART_1:BUART:txn\/q +Path End : \UART_1:BUART:txn\/main_0 +Capture Clock : \UART_1:BUART:txn\/clock_0 +Path slack : 1076279p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -5080,36 +6076,36 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4184 ++ Data path delay 3545 ------------------------------------- ---- -End-of-path arrival time (ps) 4184 +End-of-path arrival time (ps) 3545 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout --------------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_2\/q macrocell29 1250 1250 1061848 RISE 1 -\UART_1:BUART:tx_state_2\/main_2 macrocell29 2934 4184 1075640 RISE 1 +pin name model name delay AT slack edge Fanout +------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:txn\/q macrocell37 1250 1250 1076279 RISE 1 +\UART_1:BUART:txn\/main_0 macrocell37 2295 3545 1076279 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:txn\/clock_0 macrocell37 0 0 RISE 1 -++++ Path 121 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++ Path 143 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -Path Begin : \UART_1:BUART:tx_state_2\/q -Path End : \UART_1:BUART:txn\/main_4 -Capture Clock : \UART_1:BUART:txn\/clock_0 -Path slack : 1075640p +Path Begin : \UART_1:BUART:tx_state_1\/q +Path End : \UART_1:BUART:tx_state_1\/main_0 +Capture Clock : \UART_1:BUART:tx_state_1\/clock_0 +Path slack : 1076338p Capture Clock Arrival Time 0 + Clock path delay 0 @@ -5120,27 +6116,27 @@ End-of-path required time (ps) 1079823 Launch Clock Arrival Time 0 + Clock path delay 0 -+ Data path delay 4184 ++ Data path delay 3485 ------------------------------------- ---- -End-of-path arrival time (ps) 4184 +End-of-path arrival time (ps) 3485 Launch Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:tx_state_2\/clock_0 macrocell29 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------- ---- ------ -\UART_1:BUART:tx_state_2\/q macrocell29 1250 1250 1061848 RISE 1 -\UART_1:BUART:txn\/main_4 macrocell32 2934 4184 1075640 RISE 1 +pin name model name delay AT slack edge Fanout +-------------------------------- ----------- ----- ----- ------- ---- ------ +\UART_1:BUART:tx_state_1\/q macrocell33 1250 1250 1059785 RISE 1 +\UART_1:BUART:tx_state_1\/main_0 macrocell33 2235 3485 1076338 RISE 1 Capture Clock Path pin name model name delay AT edge Fanout --------------------------------------------------------- -------------- ----- ----- ---- ------ ClockBlock/dclk_glb_1 clockblockcell 0 0 RISE 1 -\UART_1:BUART:txn\/clock_0 macrocell32 0 0 RISE 1 +\UART_1:BUART:tx_state_1\/clock_0 macrocell33 0 0 RISE 1 ===================================================================== diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.v b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.v index 510c768..8e3bfb5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.v +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.v @@ -1,6 +1,6 @@ // ====================================================================== // PSOC5_SPI_LSM303D.v generated from TopDesign.cysch -// 03/22/2013 at 10:33 +// 07/25/2013 at 16:48 // This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! // ====================================================================== @@ -10,16 +10,19 @@ `define CYDEV_CHIP_REV_LEOPARD_ES3 3 `define CYDEV_CHIP_REV_LEOPARD_ES2 1 `define CYDEV_CHIP_REV_LEOPARD_ES1 0 -`define CYDEV_CHIP_DIE_PANTHER 2 +`define CYDEV_CHIP_DIE_PSOC4A 2 +`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17 +`define CYDEV_CHIP_REV_PSOC4A_ES0 17 +`define CYDEV_CHIP_DIE_PANTHER 3 `define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1 `define CYDEV_CHIP_REV_PANTHER_ES1 1 `define CYDEV_CHIP_REV_PANTHER_ES0 0 -`define CYDEV_CHIP_DIE_PSOC5LP 3 +`define CYDEV_CHIP_DIE_PSOC5LP 4 `define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0 `define CYDEV_CHIP_REV_PSOC5LP_ES0 0 -`define CYDEV_CHIP_DIE_EXPECT 2 +`define CYDEV_CHIP_DIE_EXPECT 3 `define CYDEV_CHIP_REV_EXPECT 1 -`define CYDEV_CHIP_DIE_ACTUAL 2 +`define CYDEV_CHIP_DIE_ACTUAL 3 /* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */ `define CYDEV_CHIP_FAMILY_UNKNOWN 0 `define CYDEV_CHIP_MEMBER_UNKNOWN 0 @@ -29,16 +32,20 @@ `define CYDEV_CHIP_REVISION_3A_ES3 3 `define CYDEV_CHIP_REVISION_3A_ES2 1 `define CYDEV_CHIP_REVISION_3A_ES1 0 -`define CYDEV_CHIP_FAMILY_PSOC5 2 -`define CYDEV_CHIP_MEMBER_5A 2 +`define CYDEV_CHIP_FAMILY_PSOC4 2 +`define CYDEV_CHIP_MEMBER_4A 2 +`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17 +`define CYDEV_CHIP_REVISION_4A_ES0 17 +`define CYDEV_CHIP_FAMILY_PSOC5 3 +`define CYDEV_CHIP_MEMBER_5A 3 `define CYDEV_CHIP_REVISION_5A_PRODUCTION 1 `define CYDEV_CHIP_REVISION_5A_ES1 1 `define CYDEV_CHIP_REVISION_5A_ES0 0 -`define CYDEV_CHIP_MEMBER_5B 3 +`define CYDEV_CHIP_MEMBER_5B 4 `define CYDEV_CHIP_REVISION_5B_PRODUCTION 0 `define CYDEV_CHIP_REVISION_5B_ES0 0 -`define CYDEV_CHIP_FAMILY_USED 2 -`define CYDEV_CHIP_MEMBER_USED 2 +`define CYDEV_CHIP_FAMILY_USED 3 +`define CYDEV_CHIP_MEMBER_USED 3 `define CYDEV_CHIP_REVISION_USED 1 // Component: ZeroTerminal `ifdef CY_BLK_DIR @@ -159,8 +166,8 @@ module SPI_Master_v2_40_0 ( endmodule -// CharLCD_v1_80(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, CY_COMPONENT_NAME=CharLCD_v1_80, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=80, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD, ) -module CharLCD_v1_80_1 ; +// CharLCD_v1_90(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, TypeReplacementString=uint8, CY_COMPONENT_NAME=CharLCD_v1_90, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=90, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD, ) +module CharLCD_v1_90_1 ; @@ -377,9 +384,115 @@ endmodule `include "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v" `endif +// Component: B_Timer_v2_50 +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50" +`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v" +`endif + +// Component: OneTerminal +`ifdef CY_BLK_DIR +`undef CY_BLK_DIR +`endif + +`ifdef WARP +`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal" +`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v" +`else +`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal" +`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v" +`endif + +// Timer_v2_50(CaptureAlternatingFall=false, CaptureAlternatingRise=false, CaptureCount=2, CaptureCounterEnabled=false, CaptureInputEnabled=false, CaptureMode=0, CONTROL3=0, ControlRegRemoved=0, CtlModeReplacementString=AsyncCtl, CyGetRegReplacementString=CY_GET_REG16, CySetRegReplacementString=CY_SET_REG16, DeviceFamily=PSoC5, EnableMode=0, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, HWCaptureCounterEnabled=false, InterruptOnCapture=false, InterruptOnFIFOFull=false, InterruptOnTC=false, IntOnCapture=0, IntOnFIFOFull=0, IntOnTC=0, NumberOfCaptures=1, param45=1, Period=499, RegDefReplacementString=reg16, RegSizeReplacementString=uint16, Resolution=16, RstStatusReplacementString=nrstSts, RunMode=1, SiliconRevision=1, SoftwareCaptureModeEnabled=false, SoftwareTriggerModeEnabled=false, TriggerInputEnabled=false, TriggerMode=0, UDB16=true, UDB24=false, UDB32=false, UDB8=false, UDBControlReg=true, UsesHWEnable=0, VerilogSectionReplacementString=sT16, CY_COMPONENT_NAME=Timer_v2_50, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=Timer_1, CY_INSTANCE_SHORT_NAME=Timer_1, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=50, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=Timer_1, ) +module Timer_v2_50_3 ( + clock, + reset, + interrupt, + enable, + capture, + trigger, + capture_out, + tc); + input clock; + input reset; + output interrupt; + input enable; + input capture; + input trigger; + output capture_out; + output tc; + + parameter CaptureCount = 2; + parameter CaptureCounterEnabled = 0; + parameter DeviceFamily = "PSoC5"; + parameter InterruptOnCapture = 0; + parameter InterruptOnTC = 0; + parameter Resolution = 16; + parameter SiliconRevision = "1"; + + wire Net_260; + wire Net_261; + wire Net_266; + wire Net_102; + wire Net_55; + wire Net_57; + wire Net_53; + wire Net_51; + + ZeroTerminal ZeroTerminal_1 ( + .z(Net_260)); + + // VirtualMux_2 (cy_virtualmux_v1_0) + assign interrupt = Net_55; + + // VirtualMux_3 (cy_virtualmux_v1_0) + assign tc = Net_53; + + B_Timer_v2_50 TimerUDB ( + .reset(reset), + .interrupt(Net_55), + .enable(enable), + .trigger(trigger), + .capture_in(capture), + .capture_out(capture_out), + .tc(Net_53), + .clock(clock)); + defparam TimerUDB.Capture_Count = 2; + defparam TimerUDB.CaptureCounterEnabled = 0; + defparam TimerUDB.CaptureMode = 0; + defparam TimerUDB.EnableMode = 0; + defparam TimerUDB.InterruptOnCapture = 0; + defparam TimerUDB.Resolution = 16; + defparam TimerUDB.RunMode = 1; + defparam TimerUDB.TriggerMode = 0; + + OneTerminal OneTerminal_1 ( + .o(Net_102)); + + // VirtualMux_1 (cy_virtualmux_v1_0) + assign Net_266 = Net_102; + + + +endmodule + // top module top ; + wire Net_656; + wire Net_668; + wire Net_667; + wire Net_666; + wire Net_665; + wire Net_664; + wire Net_663; wire Net_583; wire Net_582; wire Net_581; @@ -390,6 +503,9 @@ module top ; wire Net_576; wire Net_575; wire Net_574; + wire Net_589; + wire Net_588; + wire Net_443; wire Net_400; wire Net_263; wire Net_262; @@ -400,23 +516,27 @@ module top ; wire Net_257; wire Net_256; wire Net_255; + wire [2:0] mywire_1; wire Net_254; wire Net_573; wire Net_572; wire Net_571; - wire [1:0] mywire_1; wire Net_570; + wire Net_12; + wire Net_10; + wire Net_596; + wire Net_585; + wire Net_594; + wire Net_592; + wire Net_591; + wire Net_590; wire Net_479; wire Net_425; wire Net_428; wire Net_422; wire Net_419; - wire Net_449; wire Net_438; wire Net_439; - wire Net_443; - wire Net_441; - wire Net_444; wire Net_161; wire Net_191; wire Net_234; @@ -648,7 +768,7 @@ module top ; defparam SPIM.NumberOfDataBits = 8; defparam SPIM.ShiftDir = 0; - CharLCD_v1_80_1 LCD (); + CharLCD_v1_90_1 LCD (); UART_v2_30_2 UART_1 ( .cts_n(1'b0), @@ -768,43 +888,111 @@ module top ; reg tmp__demux_1_1_reg; reg tmp__demux_1_2_reg; reg tmp__demux_1_3_reg; + reg tmp__demux_1_4_reg; + reg tmp__demux_1_5_reg; + reg tmp__demux_1_6_reg; + reg tmp__demux_1_7_reg; always @(Net_438 or mywire_1) begin - case (mywire_1[1:0]) - 2'b00: + case (mywire_1[2:0]) + 3'b000: begin tmp__demux_1_0_reg = Net_438; tmp__demux_1_1_reg = 1'b0; tmp__demux_1_2_reg = 1'b0; tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; end - 2'b01: + 3'b001: begin tmp__demux_1_0_reg = 1'b0; tmp__demux_1_1_reg = Net_438; tmp__demux_1_2_reg = 1'b0; tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; end - 2'b10: + 3'b010: begin tmp__demux_1_0_reg = 1'b0; tmp__demux_1_1_reg = 1'b0; tmp__demux_1_2_reg = Net_438; tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; end - 2'b11: + 3'b011: begin tmp__demux_1_0_reg = 1'b0; tmp__demux_1_1_reg = 1'b0; tmp__demux_1_2_reg = 1'b0; tmp__demux_1_3_reg = Net_438; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; + end + 3'b100: + begin + tmp__demux_1_0_reg = 1'b0; + tmp__demux_1_1_reg = 1'b0; + tmp__demux_1_2_reg = 1'b0; + tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = Net_438; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; + end + 3'b101: + begin + tmp__demux_1_0_reg = 1'b0; + tmp__demux_1_1_reg = 1'b0; + tmp__demux_1_2_reg = 1'b0; + tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = Net_438; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = 1'b0; + end + 3'b110: + begin + tmp__demux_1_0_reg = 1'b0; + tmp__demux_1_1_reg = 1'b0; + tmp__demux_1_2_reg = 1'b0; + tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = Net_438; + tmp__demux_1_7_reg = 1'b0; + end + 3'b111: + begin + tmp__demux_1_0_reg = 1'b0; + tmp__demux_1_1_reg = 1'b0; + tmp__demux_1_2_reg = 1'b0; + tmp__demux_1_3_reg = 1'b0; + tmp__demux_1_4_reg = 1'b0; + tmp__demux_1_5_reg = 1'b0; + tmp__demux_1_6_reg = 1'b0; + tmp__demux_1_7_reg = Net_438; end endcase end - assign Net_444 = tmp__demux_1_0_reg; - assign Net_441 = tmp__demux_1_1_reg; - assign Net_449 = tmp__demux_1_2_reg; - assign Net_443 = tmp__demux_1_3_reg; + assign Net_590 = tmp__demux_1_0_reg; + assign Net_591 = tmp__demux_1_1_reg; + assign Net_592 = tmp__demux_1_2_reg; + assign Net_594 = tmp__demux_1_3_reg; + assign Net_596 = tmp__demux_1_4_reg; + assign Net_443 = tmp__demux_1_5_reg; + assign Net_588 = tmp__demux_1_6_reg; + assign Net_589 = tmp__demux_1_7_reg; end // -- De Mux end -- @@ -819,7 +1007,7 @@ module top ; .control_7(Net_581), .clock(1'b0), .reset(1'b0), - .control_bus(mywire_1[1:0])); + .control_bus(mywire_1[2:0])); defparam SS.Bit0Mode = 0; defparam SS.Bit1Mode = 0; defparam SS.Bit2Mode = 0; @@ -831,7 +1019,7 @@ module top ; defparam SS.BitValue = 0; defparam SS.BusDisplay = 1; defparam SS.ExtrReset = 0; - defparam SS.NumOutputs = 2; + defparam SS.NumOutputs = 3; wire [0:0] tmpOE__Pin_1_net; wire [0:0] tmpFB_0__Pin_1_net; @@ -1113,16 +1301,120 @@ module top ; assign Net_438 = ~Net_439; - assign Net_419 = ~Net_444; + assign Net_419 = ~Net_590; + + assign Net_422 = ~Net_591; - assign Net_422 = ~Net_441; + assign Net_428 = ~Net_592; - assign Net_428 = ~Net_449; + assign Net_425 = ~Net_594; + + wire [0:0] tmpOE__Pin_5_net; + wire [0:0] tmpFB_0__Pin_5_net; + wire [0:0] tmpIO_0__Pin_5_net; + wire [0:0] tmpINTERRUPT_0__Pin_5_net; + electrical [0:0] tmpSIOVREF__Pin_5_net; + + cy_psoc3_pins_v1_10 + #(.id("f04dd9ba-954e-4352-a3f2-4deb8634d958"), + .drive_mode(3'b010), + .ibuf_enabled(1'b1), + .init_dr_st(1'b1), + .input_clk_en(0), + .input_sync(1'b1), + .input_sync_mode(1'b0), + .intr_mode(2'b00), + .invert_in_clock(0), + .invert_in_clock_en(0), + .invert_in_reset(0), + .invert_out_clock(0), + .invert_out_clock_en(0), + .invert_out_reset(0), + .io_voltage(""), + .layout_mode("CONTIGUOUS"), + .oe_conn(1'b0), + .oe_reset(0), + .oe_sync(1'b0), + .output_clk_en(0), + .output_clock_mode(1'b0), + .output_conn(1'b1), + .output_mode(1'b0), + .output_reset(0), + .output_sync(1'b0), + .pa_in_clock(-1), + .pa_in_clock_en(-1), + .pa_in_reset(-1), + .pa_out_clock(-1), + .pa_out_clock_en(-1), + .pa_out_reset(-1), + .pin_aliases(""), + .pin_mode("O"), + .por_state(4), + .use_annotation(1'b0), + .sio_group_cnt(0), + .sio_hyst(1'b0), + .sio_ibuf(""), + .sio_info(2'b00), + .sio_obuf(""), + .sio_refsel(""), + .sio_vtrip(""), + .slew_rate(1'b0), + .spanning(0), + .vtrip(2'b10), + .width(1)) + Pin_5 + (.oe(tmpOE__Pin_5_net), + .y({Net_585}), + .fb({tmpFB_0__Pin_5_net[0:0]}), + .io({tmpIO_0__Pin_5_net[0:0]}), + .siovref(tmpSIOVREF__Pin_5_net), + .interrupt({tmpINTERRUPT_0__Pin_5_net[0:0]}), + .in_clock({1'b0}), + .in_clock_en({1'b1}), + .in_reset({1'b0}), + .out_clock({1'b0}), + .out_clock_en({1'b1}), + .out_reset({1'b0})); + + assign tmpOE__Pin_5_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; + + + assign Net_585 = ~Net_596; + + ZeroTerminal ZeroTerminal_3 ( + .z(Net_12)); + + Timer_v2_50_3 Timer_1 ( + .reset(Net_12), + .interrupt(Net_663), + .enable(1'b1), + .trigger(1'b0), + .capture(1'b0), + .capture_out(Net_667), + .tc(Net_668), + .clock(Net_10)); + defparam Timer_1.CaptureCount = 2; + defparam Timer_1.CaptureCounterEnabled = 0; + defparam Timer_1.DeviceFamily = "PSoC5"; + defparam Timer_1.InterruptOnCapture = 0; + defparam Timer_1.InterruptOnTC = 0; + defparam Timer_1.Resolution = 16; + defparam Timer_1.SiliconRevision = "1"; + + + cy_clock_v1_0 + #(.id("c0fb34bd-1044-4931-9788-16b01ce89812"), + .source_clock_id("315365C3-2E3E-4f04-84A2-BB564A173261"), + .divisor(0), + .period("0"), + .is_direct(1), + .is_digital(1)) + timer_clock + (.clock_out(Net_10)); - assign Net_425 = ~Net_443; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.vh2 index e00e88a..caee1c5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.vh2 +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.vh2 @@ -2,7 +2,7 @@ -- Conversion of PSOC5_SPI_LSM303D.v to vh2: -- -- Cypress Semiconductor - WARP Version 6.3 IR 41 --- Fri Mar 22 10:33:25 2013 +-- Thu Jul 25 16:48:54 2013 -- USE cypress.cypress.all; @@ -294,16 +294,25 @@ SIGNAL tmpIO_0__Tx_1_net_0 : bit; TERMINAL tmpSIOVREF__Tx_1_net_0 : bit; SIGNAL tmpINTERRUPT_0__Tx_1_net_0 : bit; SIGNAL \demux_1:tmp__demux_1_0_reg\ : bit; +SIGNAL mywire_1_2 : bit; SIGNAL mywire_1_1 : bit; SIGNAL mywire_1_0 : bit; SIGNAL Net_438 : bit; SIGNAL \demux_1:tmp__demux_1_1_reg\ : bit; SIGNAL \demux_1:tmp__demux_1_2_reg\ : bit; SIGNAL \demux_1:tmp__demux_1_3_reg\ : bit; -SIGNAL Net_444 : bit; -SIGNAL Net_441 : bit; -SIGNAL Net_449 : bit; +SIGNAL \demux_1:tmp__demux_1_4_reg\ : bit; +SIGNAL \demux_1:tmp__demux_1_5_reg\ : bit; +SIGNAL \demux_1:tmp__demux_1_6_reg\ : bit; +SIGNAL \demux_1:tmp__demux_1_7_reg\ : bit; +SIGNAL Net_590 : bit; +SIGNAL Net_591 : bit; +SIGNAL Net_592 : bit; +SIGNAL Net_594 : bit; +SIGNAL Net_596 : bit; SIGNAL Net_443 : bit; +SIGNAL Net_588 : bit; +SIGNAL Net_589 : bit; SIGNAL \SS:clk\ : bit; SIGNAL \SS:rst\ : bit; SIGNAL \SS:control_bus_7\ : bit; @@ -321,8 +330,6 @@ SIGNAL \SS:control_out_4\ : bit; SIGNAL \SS:control_bus_3\ : bit; ATTRIBUTE port_state_att of \SS:control_bus_3\:SIGNAL IS 2; SIGNAL \SS:control_out_3\ : bit; -SIGNAL \SS:control_bus_2\ : bit; -ATTRIBUTE port_state_att of \SS:control_bus_2\:SIGNAL IS 2; SIGNAL \SS:control_out_2\ : bit; SIGNAL \SS:control_out_1\ : bit; SIGNAL \SS:control_out_0\ : bit; @@ -358,6 +365,204 @@ SIGNAL tmpFB_0__Pin_4_net_0 : bit; SIGNAL tmpIO_0__Pin_4_net_0 : bit; TERMINAL tmpSIOVREF__Pin_4_net_0 : bit; SIGNAL tmpINTERRUPT_0__Pin_4_net_0 : bit; +SIGNAL tmpOE__Pin_5_net_0 : bit; +SIGNAL Net_585 : bit; +SIGNAL tmpFB_0__Pin_5_net_0 : bit; +SIGNAL tmpIO_0__Pin_5_net_0 : bit; +TERMINAL tmpSIOVREF__Pin_5_net_0 : bit; +SIGNAL tmpINTERRUPT_0__Pin_5_net_0 : bit; +SIGNAL Net_12 : bit; +SIGNAL \Timer_1:Net_260\ : bit; +SIGNAL Net_663 : bit; +SIGNAL \Timer_1:Net_55\ : bit; +SIGNAL Net_668 : bit; +SIGNAL \Timer_1:Net_53\ : bit; +SIGNAL Net_10 : bit; +SIGNAL \Timer_1:TimerUDB:ClockOutFromEnBlock\ : bit; +SIGNAL \Timer_1:TimerUDB:control_7\ : bit; +SIGNAL \Timer_1:TimerUDB:control_6\ : bit; +SIGNAL \Timer_1:TimerUDB:control_5\ : bit; +SIGNAL \Timer_1:TimerUDB:control_4\ : bit; +SIGNAL \Timer_1:TimerUDB:control_3\ : bit; +SIGNAL \Timer_1:TimerUDB:control_2\ : bit; +SIGNAL \Timer_1:TimerUDB:control_1\ : bit; +SIGNAL \Timer_1:TimerUDB:control_0\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_enable\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_ten\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_cmode_1\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_cmode_0\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_tmode_1\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_tmode_0\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_ic_1\ : bit; +SIGNAL \Timer_1:TimerUDB:ctrl_ic_0\ : bit; +SIGNAL \Timer_1:TimerUDB:fifo_load_polarized\ : bit; +SIGNAL \Timer_1:TimerUDB:capture_last\ : bit; +SIGNAL \Timer_1:TimerUDB:capt_fifo_load\ : bit; +SIGNAL \Timer_1:TimerUDB:timer_enable\ : bit; +SIGNAL \Timer_1:TimerUDB:run_mode\ : bit; +SIGNAL \Timer_1:TimerUDB:hwEnable_reg\ : bit; +SIGNAL \Timer_1:TimerUDB:status_tc\ : bit; +SIGNAL \Timer_1:TimerUDB:trigger_enable\ : bit; +SIGNAL \Timer_1:TimerUDB:per_zero\ : bit; +SIGNAL \Timer_1:TimerUDB:tc_i\ : bit; +SIGNAL \Timer_1:TimerUDB:tc_reg_i\ : bit; +SIGNAL \Timer_1:TimerUDB:hwEnable\ : bit; +SIGNAL \Timer_1:TimerUDB:capture_out_reg_i\ : bit; +SIGNAL Net_667 : bit; +SIGNAL \Timer_1:TimerUDB:capt_fifo_load_int\ : bit; +SIGNAL \Timer_1:TimerUDB:runmode_enable\ : bit; +SIGNAL \Timer_1:TimerUDB:trig_disable\ : bit; +SIGNAL \Timer_1:TimerUDB:trig_reg\ : bit; +SIGNAL \Timer_1:TimerUDB:status_6\ : bit; +SIGNAL \Timer_1:TimerUDB:status_5\ : bit; +SIGNAL \Timer_1:TimerUDB:status_4\ : bit; +SIGNAL \Timer_1:TimerUDB:status_0\ : bit; +SIGNAL \Timer_1:TimerUDB:status_1\ : bit; +SIGNAL \Timer_1:TimerUDB:status_2\ : bit; +SIGNAL \Timer_1:TimerUDB:fifo_full\ : bit; +SIGNAL \Timer_1:TimerUDB:status_3\ : bit; +SIGNAL \Timer_1:TimerUDB:fifo_nempty\ : bit; +SIGNAL \Timer_1:TimerUDB:cs_addr_2\ : bit; +SIGNAL \Timer_1:TimerUDB:cs_addr_1\ : bit; +SIGNAL \Timer_1:TimerUDB:cs_addr_0\ : bit; +SIGNAL \Timer_1:TimerUDB:zeros_3\ : bit; +SIGNAL \Timer_1:TimerUDB:zeros_2\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce0_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce0_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl0_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl0_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:nc0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff0_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff0_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce1_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce1_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl1_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl1_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z1_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z1_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff1_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff1_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ov_msb_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ov_msb_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:co_msb_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:co_msb_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmsb_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cmsb_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:so_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:so_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:nc3\ : bit; +SIGNAL \Timer_1:TimerUDB:nc4\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce0_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce0_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl0_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl0_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z0_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z0_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff0_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff0_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce1_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce1_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl1_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl1_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z1_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z1_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff1_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff1_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ov_msb_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ov_msb_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:co_msb_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:co_msb_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmsb_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cmsb_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:so_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:so_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f0_bus_stat_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f0_bus_stat_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f0_blk_stat_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f0_blk_stat_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_reg_0\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_reg_0\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:carry\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:sh_right\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:sh_left\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:msb\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_eq_1\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_eq_0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_lt_1\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_lt_0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_zero_1\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_zero_0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_ff_1\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmp_ff_0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cap_1\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cap_0\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cfb\ : bit; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce0_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce0_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl0_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl0_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff0_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff0_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce1_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce1_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl1_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl1_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z1_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z1_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff1_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff1_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ov_msb_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ov_msb_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:co_msb_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:co_msb_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmsb_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cmsb_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:so_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:so_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce0_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce0_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl0_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl0_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z0_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z0_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff0_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff0_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ce1_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ce1_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cl1_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cl1_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:z1_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:z1_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ff1_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ff1_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:ov_msb_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:ov_msb_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:co_msb_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:co_msb_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:cmsb_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:cmsb_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:so_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:so_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f0_bus_stat_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f0_bus_stat_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f0_blk_stat_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f0_blk_stat_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_bus_stat_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_reg_1\ : bit; +ATTRIBUTE port_state_att of \Timer_1:TimerUDB:sT16:timerdp:f1_blk_stat_reg_1\:SIGNAL IS 2; +SIGNAL \Timer_1:Net_102\ : bit; +SIGNAL \Timer_1:Net_266\ : bit; SIGNAL Net_479D : bit; SIGNAL \SPIM:BSPIM:dpcounter_one_reg\\D\ : bit; SIGNAL \SPIM:BSPIM:so_send_reg\\D\ : bit; @@ -383,6 +588,12 @@ SIGNAL Net_256D : bit; SIGNAL \UART_1:BUART:tx_ctrl_mark_last\\D\ : bit; SIGNAL \UART_1:BUART:tx_mark\\D\ : bit; SIGNAL \UART_1:BUART:tx_parity_bit\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:capture_last\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:hwEnable_reg\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:tc_reg_i\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:capture_out_reg_i\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:runmode_enable\\D\ : bit; +SIGNAL \Timer_1:TimerUDB:trig_disable\\D\ : bit; BEGIN zero <= ('0') ; @@ -518,20 +729,38 @@ Net_234 <= (not \UART_1:BUART:txn\); Net_419 <= (mywire_1_0 OR mywire_1_1 + OR mywire_1_2 OR Net_439); Net_422 <= (not mywire_1_0 OR mywire_1_1 + OR mywire_1_2 OR Net_439); Net_428 <= (mywire_1_0 OR not mywire_1_1 + OR mywire_1_2 OR Net_439); Net_425 <= (not mywire_1_0 OR not mywire_1_1 + OR mywire_1_2 OR Net_439); +Net_585 <= (mywire_1_0 + OR mywire_1_1 + OR not mywire_1_2 + OR Net_439); + +\Timer_1:TimerUDB:status_tc\ <= ((\Timer_1:TimerUDB:run_mode\ and \Timer_1:TimerUDB:per_zero\)); + +\Timer_1:TimerUDB:runmode_enable\\D\ <= ((not \Timer_1:TimerUDB:per_zero\ and not \Timer_1:TimerUDB:trig_disable\ and \Timer_1:TimerUDB:control_7\) + OR (not \Timer_1:TimerUDB:run_mode\ and not \Timer_1:TimerUDB:trig_disable\ and \Timer_1:TimerUDB:control_7\) + OR (not \Timer_1:TimerUDB:timer_enable\ and not \Timer_1:TimerUDB:trig_disable\ and \Timer_1:TimerUDB:control_7\)); + +\Timer_1:TimerUDB:trig_disable\\D\ <= ((\Timer_1:TimerUDB:timer_enable\ and \Timer_1:TimerUDB:run_mode\ and \Timer_1:TimerUDB:per_zero\) + OR \Timer_1:TimerUDB:trig_disable\); + m_miso_pin:cy_psoc3_pins_v1_10 GENERIC MAP(id=>"1425177d-0d0e-4468-8bcc-e638e5509a9b", drive_mode=>"010", @@ -1201,7 +1430,7 @@ Tx_1:cy_psoc3_pins_v1_10 PORT MAP(reset=>zero, clock=>zero, control=>(\SS:control_7\, \SS:control_6\, \SS:control_5\, \SS:control_4\, - \SS:control_3\, \SS:control_2\, mywire_1_1, mywire_1_0)); + \SS:control_3\, mywire_1_2, mywire_1_1, mywire_1_0)); Pin_1:cy_psoc3_pins_v1_10 GENERIC MAP(id=>"52f31aa9-2f0a-497d-9a1f-1424095e13e6", drive_mode=>"010", @@ -1462,6 +1691,277 @@ Pin_4:cy_psoc3_pins_v1_10 out_clock_en=>tmpOE__m_miso_pin_net_0, out_reset=>zero, interrupt=>tmpINTERRUPT_0__Pin_4_net_0); +Pin_5:cy_psoc3_pins_v1_10 + GENERIC MAP(id=>"f04dd9ba-954e-4352-a3f2-4deb8634d958", + drive_mode=>"010", + ibuf_enabled=>"1", + init_dr_st=>"1", + input_sync=>"1", + input_clk_en=>'0', + input_sync_mode=>"0", + intr_mode=>"00", + invert_in_clock=>'0', + invert_in_clock_en=>'0', + invert_in_reset=>'0', + invert_out_clock=>'0', + invert_out_clock_en=>'0', + invert_out_reset=>'0', + io_voltage=>"", + layout_mode=>"CONTIGUOUS", + output_conn=>"1", + output_sync=>"0", + output_clk_en=>'0', + output_mode=>"0", + output_reset=>'0', + output_clock_mode=>"0", + oe_sync=>"0", + oe_conn=>"0", + oe_reset=>'0', + pin_aliases=>"", + pin_mode=>"O", + por_state=>4, + sio_group_cnt=>0, + sio_hifreq=>"", + sio_hyst=>"0", + sio_ibuf=>"00000000", + sio_info=>"00", + sio_obuf=>"00000000", + sio_refsel=>"00000000", + sio_vtrip=>"00000000", + slew_rate=>"0", + spanning=>'0', + sw_only=>'0', + vtrip=>"10", + width=>1, + port_alias_required=>'0', + port_alias_group=>"", + use_annotation=>"0", + pa_in_clock=>-1, + pa_in_clock_en=>-1, + pa_in_reset=>-1, + pa_out_clock=>-1, + pa_out_clock_en=>-1, + pa_out_reset=>-1) + PORT MAP(oe=>(tmpOE__m_miso_pin_net_0), + y=>Net_585, + fb=>(tmpFB_0__Pin_5_net_0), + analog=>(open), + io=>(tmpIO_0__Pin_5_net_0), + siovref=>(tmpSIOVREF__Pin_5_net_0), + annotation=>(open), + in_clock=>zero, + in_clock_en=>tmpOE__m_miso_pin_net_0, + in_reset=>zero, + out_clock=>zero, + out_clock_en=>tmpOE__m_miso_pin_net_0, + out_reset=>zero, + interrupt=>tmpINTERRUPT_0__Pin_5_net_0); +\Timer_1:TimerUDB:clock_enable_block\:cy_psoc3_udb_clock_enable_v1_0 + GENERIC MAP(sync_mode=>'1') + PORT MAP(clock_in=>Net_10, + enable=>tmpOE__m_miso_pin_net_0, + clock_out=>\Timer_1:TimerUDB:ClockOutFromEnBlock\); +\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\:cy_psoc3_control + GENERIC MAP(cy_init_value=>"00000000", + cy_force_order=>'1', + cy_ctrl_mode_1=>"00000000", + cy_ctrl_mode_0=>"00000000", + cy_ext_reset=>'0') + PORT MAP(reset=>zero, + clock=>zero, + control=>(\Timer_1:TimerUDB:control_7\, \Timer_1:TimerUDB:control_6\, \Timer_1:TimerUDB:control_5\, \Timer_1:TimerUDB:control_4\, + \Timer_1:TimerUDB:control_3\, \Timer_1:TimerUDB:control_2\, \Timer_1:TimerUDB:control_1\, \Timer_1:TimerUDB:control_0\)); +\Timer_1:TimerUDB:nrstSts:stsreg\:cy_psoc3_statusi + GENERIC MAP(cy_force_order=>'1', + cy_md_select=>"0000011", + cy_int_mask=>"1111111") + PORT MAP(reset=>zero, + clock=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + status=>(zero, zero, zero, \Timer_1:TimerUDB:status_3\, + \Timer_1:TimerUDB:status_2\, zero, \Timer_1:TimerUDB:status_tc\), + interrupt=>\Timer_1:Net_55\); +\Timer_1:TimerUDB:sT16:timerdp:u0\:cy_psoc3_dp + GENERIC MAP(cy_dpconfig=>"0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000", + d0_init=>"00000000", + d1_init=>"00000000", + a0_init=>"00000000", + a1_init=>"00000000", + ce0_sync=>'1', + cl0_sync=>'1', + z0_sync=>'1', + ff0_sync=>'1', + ce1_sync=>'1', + cl1_sync=>'1', + z1_sync=>'1', + ff1_sync=>'1', + ov_msb_sync=>'1', + co_msb_sync=>'1', + cmsb_sync=>'1', + so_sync=>'1', + f0_bus_sync=>'1', + f0_blk_sync=>'1', + f1_bus_sync=>'1', + f1_blk_sync=>'1') + PORT MAP(reset=>zero, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + cs_addr=>(zero, \Timer_1:TimerUDB:timer_enable\, \Timer_1:TimerUDB:per_zero\), + route_si=>zero, + route_ci=>zero, + f0_load=>zero, + f1_load=>zero, + d0_load=>zero, + d1_load=>zero, + ce0=>open, + cl0=>open, + z0=>\Timer_1:TimerUDB:nc0\, + ff0=>open, + ce1=>open, + cl1=>open, + z1=>open, + ff1=>open, + ov_msb=>open, + co_msb=>open, + cmsb=>open, + so=>open, + f0_bus_stat=>\Timer_1:TimerUDB:nc3\, + f0_blk_stat=>\Timer_1:TimerUDB:nc4\, + f1_bus_stat=>open, + f1_blk_stat=>open, + ce0_reg=>open, + cl0_reg=>open, + z0_reg=>open, + ff0_reg=>open, + ce1_reg=>open, + cl1_reg=>open, + z1_reg=>open, + ff1_reg=>open, + ov_msb_reg=>open, + co_msb_reg=>open, + cmsb_reg=>open, + so_reg=>open, + f0_bus_stat_reg=>open, + f0_blk_stat_reg=>open, + f1_bus_stat_reg=>open, + f1_blk_stat_reg=>open, + ci=>zero, + co=>\Timer_1:TimerUDB:sT16:timerdp:carry\, + sir=>zero, + sor=>open, + sil=>\Timer_1:TimerUDB:sT16:timerdp:sh_right\, + sol=>\Timer_1:TimerUDB:sT16:timerdp:sh_left\, + msbi=>\Timer_1:TimerUDB:sT16:timerdp:msb\, + msbo=>open, + cei=>(zero, zero), + ceo=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_eq_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_eq_0\), + cli=>(zero, zero), + clo=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_lt_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_lt_0\), + zi=>(zero, zero), + zo=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_zero_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_zero_0\), + fi=>(zero, zero), + fo=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_ff_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_ff_0\), + capi=>(zero, zero), + capo=>(\Timer_1:TimerUDB:sT16:timerdp:cap_1\, \Timer_1:TimerUDB:sT16:timerdp:cap_0\), + cfbi=>zero, + cfbo=>\Timer_1:TimerUDB:sT16:timerdp:cfb\, + pi=>(zero, zero, zero, zero, + zero, zero, zero, zero), + po=>open); +\Timer_1:TimerUDB:sT16:timerdp:u1\:cy_psoc3_dp + GENERIC MAP(cy_dpconfig=>"0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000", + d0_init=>"00000000", + d1_init=>"00000000", + a0_init=>"00000000", + a1_init=>"00000000", + ce0_sync=>'1', + cl0_sync=>'1', + z0_sync=>'1', + ff0_sync=>'1', + ce1_sync=>'1', + cl1_sync=>'1', + z1_sync=>'1', + ff1_sync=>'1', + ov_msb_sync=>'1', + co_msb_sync=>'1', + cmsb_sync=>'1', + so_sync=>'1', + f0_bus_sync=>'1', + f0_blk_sync=>'1', + f1_bus_sync=>'1', + f1_blk_sync=>'1') + PORT MAP(reset=>zero, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + cs_addr=>(zero, \Timer_1:TimerUDB:timer_enable\, \Timer_1:TimerUDB:per_zero\), + route_si=>zero, + route_ci=>zero, + f0_load=>zero, + f1_load=>zero, + d0_load=>zero, + d1_load=>zero, + ce0=>open, + cl0=>open, + z0=>\Timer_1:TimerUDB:per_zero\, + ff0=>open, + ce1=>open, + cl1=>open, + z1=>open, + ff1=>open, + ov_msb=>open, + co_msb=>open, + cmsb=>open, + so=>open, + f0_bus_stat=>\Timer_1:TimerUDB:status_3\, + f0_blk_stat=>\Timer_1:TimerUDB:status_2\, + f1_bus_stat=>open, + f1_blk_stat=>open, + ce0_reg=>open, + cl0_reg=>open, + z0_reg=>open, + ff0_reg=>open, + ce1_reg=>open, + cl1_reg=>open, + z1_reg=>open, + ff1_reg=>open, + ov_msb_reg=>open, + co_msb_reg=>open, + cmsb_reg=>open, + so_reg=>open, + f0_bus_stat_reg=>open, + f0_blk_stat_reg=>open, + f1_bus_stat_reg=>open, + f1_blk_stat_reg=>open, + ci=>\Timer_1:TimerUDB:sT16:timerdp:carry\, + co=>open, + sir=>\Timer_1:TimerUDB:sT16:timerdp:sh_left\, + sor=>\Timer_1:TimerUDB:sT16:timerdp:sh_right\, + sil=>zero, + sol=>open, + msbi=>zero, + msbo=>\Timer_1:TimerUDB:sT16:timerdp:msb\, + cei=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_eq_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_eq_0\), + ceo=>open, + cli=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_lt_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_lt_0\), + clo=>open, + zi=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_zero_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_zero_0\), + zo=>open, + fi=>(\Timer_1:TimerUDB:sT16:timerdp:cmp_ff_1\, \Timer_1:TimerUDB:sT16:timerdp:cmp_ff_0\), + fo=>open, + capi=>(\Timer_1:TimerUDB:sT16:timerdp:cap_1\, \Timer_1:TimerUDB:sT16:timerdp:cap_0\), + capo=>open, + cfbi=>\Timer_1:TimerUDB:sT16:timerdp:cfb\, + cfbo=>open, + pi=>(zero, zero, zero, zero, + zero, zero, zero, zero), + po=>open); +timer_clock:cy_clock_v1_0 + GENERIC MAP(cy_registers=>"", + id=>"c0fb34bd-1044-4931-9788-16b01ce89812", + source_clock_id=>"315365C3-2E3E-4f04-84A2-BB564A173261", + divisor=>0, + period=>"0", + is_direct=>'1', + is_digital=>'1') + PORT MAP(clock_out=>Net_10, + dig_domain_out=>open); Net_479:cy_dff PORT MAP(d=>Net_479D, clk=>\SPIM:BSPIM:clk_fin\, @@ -1562,5 +2062,29 @@ Net_256:cy_dff PORT MAP(d=>\UART_1:BUART:tx_parity_bit\\D\, clk=>\UART_1:BUART:clock_op\, q=>\UART_1:BUART:tx_parity_bit\); +\Timer_1:TimerUDB:capture_last\:cy_dff + PORT MAP(d=>zero, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:capture_last\); +\Timer_1:TimerUDB:hwEnable_reg\:cy_dff + PORT MAP(d=>\Timer_1:TimerUDB:control_7\, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:run_mode\); +\Timer_1:TimerUDB:tc_reg_i\:cy_dff + PORT MAP(d=>\Timer_1:TimerUDB:status_tc\, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:tc_reg_i\); +\Timer_1:TimerUDB:capture_out_reg_i\:cy_dff + PORT MAP(d=>zero, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:capture_out_reg_i\); +\Timer_1:TimerUDB:runmode_enable\:cy_dff + PORT MAP(d=>\Timer_1:TimerUDB:runmode_enable\\D\, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:timer_enable\); +\Timer_1:TimerUDB:trig_disable\:cy_dff + PORT MAP(d=>\Timer_1:TimerUDB:trig_disable\\D\, + clk=>\Timer_1:TimerUDB:ClockOutFromEnBlock\, + q=>\Timer_1:TimerUDB:trig_disable\); END R_T_L; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.wde b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.wde index 6c8bf7e..ae2d2d1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.wde +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D.wde @@ -11,5 +11,7 @@ C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\conten C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\demux_v1_10\demux_v1_10.v C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\CyControlReg_v1_70.v C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.lib index 7621965..7df65f1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.lib +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.lib @@ -247,7 +247,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -257,7 +257,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -335,7 +335,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -345,7 +345,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -423,7 +423,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -433,7 +433,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -511,7 +511,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -521,7 +521,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -726,6 +726,94 @@ library (timing) { } } } + cell (macrocell9) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } cell (iocell1) { pin (in_clock) { direction : input; @@ -999,6 +1087,74 @@ library (timing) { } } cell (iocell5) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.839; + intrinsic_fall : 16.839; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 16.918; + intrinsic_fall : 16.918; + } + } + } + cell (iocell6) { pin (in_clock) { direction : input; clock : true; @@ -1066,7 +1222,7 @@ library (timing) { } } } - cell (iocell6) { + cell (iocell7) { pin (in_clock) { direction : input; clock : true; @@ -1134,7 +1290,7 @@ library (timing) { } } } - cell (iocell7) { + cell (iocell8) { pin (in_clock) { direction : input; clock : true; @@ -1202,7 +1358,7 @@ library (timing) { } } } - cell (iocell8) { + cell (iocell9) { pin (in_clock) { direction : input; clock : true; @@ -1270,7 +1426,7 @@ library (timing) { } } } - cell (iocell9) { + cell (iocell10) { pin (in_clock) { direction : input; clock : true; @@ -1338,7 +1494,7 @@ library (timing) { } } } - cell (iocell10) { + cell (iocell11) { pin (in_clock) { direction : input; clock : true; @@ -1406,7 +1562,7 @@ library (timing) { } } } - cell (iocell11) { + cell (iocell12) { pin (in_clock) { direction : input; clock : true; @@ -1474,7 +1630,7 @@ library (timing) { } } } - cell (iocell12) { + cell (iocell13) { pin (in_clock) { direction : input; clock : true; @@ -1694,7 +1850,7 @@ library (timing) { direction : output; } } - cell (macrocell9) { + cell (macrocell10) { pin (cin) { direction : input; } @@ -1792,7 +1948,7 @@ library (timing) { } } } - cell (macrocell10) { + cell (macrocell11) { pin (cin) { direction : input; } @@ -1880,7 +2036,7 @@ library (timing) { } } } - cell (macrocell11) { + cell (macrocell12) { pin (cin) { direction : input; } @@ -1978,7 +2134,7 @@ library (timing) { } } } - cell (macrocell12) { + cell (macrocell13) { pin (cin) { direction : input; } @@ -2076,7 +2232,7 @@ library (timing) { } } } - cell (macrocell13) { + cell (macrocell14) { pin (cin) { direction : input; } @@ -2174,7 +2330,7 @@ library (timing) { } } } - cell (macrocell14) { + cell (macrocell15) { pin (cin) { direction : input; } @@ -2272,7 +2428,7 @@ library (timing) { } } } - cell (macrocell15) { + cell (macrocell16) { pin (cin) { direction : input; } @@ -2370,7 +2526,7 @@ library (timing) { } } } - cell (macrocell16) { + cell (macrocell17) { pin (cin) { direction : input; } @@ -2468,7 +2624,7 @@ library (timing) { } } } - cell (macrocell17) { + cell (macrocell18) { pin (cin) { direction : input; } @@ -2566,7 +2722,7 @@ library (timing) { } } } - cell (macrocell18) { + cell (macrocell19) { pin (cin) { direction : input; } @@ -3159,7 +3315,7 @@ library (timing) { direction : output; } } - cell (macrocell19) { + cell (macrocell20) { pin (cin) { direction : input; } @@ -3257,7 +3413,7 @@ library (timing) { } } } - cell (macrocell20) { + cell (macrocell21) { pin (cin) { direction : input; } @@ -3355,7 +3511,7 @@ library (timing) { } } } - cell (macrocell21) { + cell (macrocell22) { pin (cin) { direction : input; } @@ -3453,7 +3609,7 @@ library (timing) { } } } - cell (macrocell22) { + cell (macrocell23) { pin (cin) { direction : input; } @@ -3541,7 +3697,7 @@ library (timing) { } } } - cell (macrocell23) { + cell (macrocell24) { pin (cin) { direction : input; } @@ -3787,24 +3943,8 @@ library (timing) { } } } - cell (macrocell24) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); + cell (statusicell3) { + pin (clock) { direction : input; clock : true; } @@ -3812,59 +3952,1778 @@ library (timing) { direction : input; timing () { timing_type : setup_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 2.100; intrinsic_fall : 2.100; } timing () { timing_type : hold_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 0.000; intrinsic_fall : 0.000; } } - bundle (ar) { - members (ar_0); + pin (reset) { direction : input; timing () { timing_type : recovery_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } timing () { timing_type : removal_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } } - bundle (ap) { - members (ap_0); + pin (status_0) { direction : input; timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; } } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + pin (status_1) { + direction : input; timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } - } - pin (q_fixed) { + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; + } + } + pin (status_2) { + direction : input; + } + pin (status_3) { + direction : input; + } + pin (status_4) { + direction : input; + } + pin (status_5) { + direction : input; + } + pin (status_6) { + direction : input; + } + pin (interrupt) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.030; + intrinsic_fall : 4.030; + } + timing () { + timing_sense : negative_unate; + timing_type : clear; + related_pin : "reset"; + intrinsic_rise : 8.260; + intrinsic_fall : 8.260; + } + } + } + cell (macrocell25) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (controlcell2) { + pin (clock) { + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + } + pin (busclk) { + direction : input; + clock : true; + } + pin (control_0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_2) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_3) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_4) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_5) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_6) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_7) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + } + cell (datapathcell2) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + } + pin (f0_blk_stat_comb) { + direction : output; + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + } + pin (cl0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + } + pin (z0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.32; + intrinsic_fall : 2.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.74; + intrinsic_fall : 1.74; + } + } + pin (ff0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.73; + intrinsic_fall : 2.73; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.32; + intrinsic_fall : 1.32; + } + } + pin (ce1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + } + pin (cl1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + } + pin (z1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.29; + intrinsic_fall : 2.29; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.53; + intrinsic_fall : 1.53; + } + } + pin (ff1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.17; + intrinsic_fall : 2.17; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.18; + intrinsic_fall : 1.18; + } + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.21; + intrinsic_fall : 3.21; + } + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.84; + intrinsic_fall : 4.84; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.63; + intrinsic_fall : 3.63; + } + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + } + } + cell (datapathcell3) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.09; + intrinsic_fall : 5.09; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 4.57; + intrinsic_fall : 4.57; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.96; + intrinsic_fall : 2.96; + } + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.74; + intrinsic_fall : 2.74; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.85; + intrinsic_fall : 3.85; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.27; + intrinsic_fall : 3.27; + } + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + } + pin (f0_blk_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + } + pin (cl0) { + direction : output; + } + pin (z0) { + direction : output; + } + pin (ff0) { + direction : output; + } + pin (ce1) { + direction : output; + } + pin (cl1) { + direction : output; + } + pin (z1) { + direction : output; + } + pin (ff1) { + direction : output; + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.32; + intrinsic_fall : 3.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.25; + intrinsic_fall : 2.25; + } + } + } + cell (macrocell26) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } + cell (macrocell27) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell28) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell29) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { direction : output; function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; timing () { @@ -3875,7 +5734,7 @@ library (timing) { } } } - cell (datapathcell2) { + cell (datapathcell4) { pin (clk_en) { direction : input; } @@ -4260,7 +6119,7 @@ library (timing) { direction : output; } } - cell (statusicell3) { + cell (statusicell4) { pin (clock) { direction : input; clock : true; @@ -4427,7 +6286,7 @@ library (timing) { } } } - cell (datapathcell3) { + cell (datapathcell5) { pin (clk_en) { direction : input; } @@ -4752,7 +6611,7 @@ library (timing) { direction : output; } } - cell (macrocell25) { + cell (macrocell30) { pin (cin) { direction : input; } @@ -4850,7 +6709,7 @@ library (timing) { } } } - cell (macrocell26) { + cell (macrocell31) { pin (cin) { direction : input; } @@ -4938,7 +6797,7 @@ library (timing) { } } } - cell (macrocell27) { + cell (macrocell32) { pin (cin) { direction : input; } @@ -5036,7 +6895,7 @@ library (timing) { } } } - cell (macrocell28) { + cell (macrocell33) { pin (cin) { direction : input; } @@ -5134,7 +6993,7 @@ library (timing) { } } } - cell (macrocell29) { + cell (macrocell34) { pin (cin) { direction : input; } @@ -5232,7 +7091,7 @@ library (timing) { } } } - cell (macrocell30) { + cell (macrocell35) { pin (cin) { direction : input; } @@ -5320,7 +7179,7 @@ library (timing) { } } } - cell (macrocell31) { + cell (macrocell36) { pin (cin) { direction : input; } @@ -5408,7 +7267,7 @@ library (timing) { } } } - cell (macrocell32) { + cell (macrocell37) { pin (cin) { direction : input; } @@ -5506,7 +7365,7 @@ library (timing) { } } } - cell (iocell13) { + cell (iocell14) { pin (in_clock) { direction : input; clock : true; @@ -5574,7 +7433,7 @@ library (timing) { } } } - cell (iocell14) { + cell (iocell15) { pin (in_clock) { direction : input; clock : true; @@ -5642,7 +7501,7 @@ library (timing) { } } } - cell (iocell15) { + cell (iocell16) { pin (in_clock) { direction : input; clock : true; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.pco b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.pco index 958ab94..cf8d711 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.pco +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.pco @@ -1,59 +1,70 @@ dont_use_io iocell 1 0 dont_use_io iocell 1 1 dont_use_io iocell 1 3 -set_location "\UART_1:BUART:tx_state_2\" macrocell 3 5 0 1 -set_location "\SPIM:BSPIM:tx_status_4\" macrocell 2 3 0 2 -set_location "\SPIM:BSPIM:state_1\" macrocell 2 3 0 1 -set_location "\SPIM:BSPIM:RxStsReg\" statusicell 2 5 4 +set_location "\UART_1:BUART:tx_state_2\" macrocell 3 3 0 1 +set_location "Net_439" macrocell 3 5 0 1 +set_location "\SPIM:BSPIM:tx_status_4\" macrocell 2 5 0 2 +set_location "\SPIM:BSPIM:state_1\" macrocell 2 5 0 1 +set_location "\SPIM:BSPIM:RxStsReg\" statusicell 3 4 4 set_location "\SPIM:BSPIM:state_0\" macrocell 2 4 1 3 -set_location "\UART_1:BUART:sTX:TxShifter:u0\" datapathcell 3 5 2 -set_location "\SPIM:BSPIM:ld_ident\" macrocell 3 3 0 1 -set_location "\SPIM:BSPIM:cnt_enable\" macrocell 2 3 0 0 -set_location "\UART_1:BUART:tx_status_0\" macrocell 2 5 0 3 -set_location "\UART_1:BUART:txn\" macrocell 3 5 0 0 +set_location "\UART_1:BUART:sTX:TxShifter:u0\" datapathcell 2 3 2 +set_location "\SPIM:BSPIM:ld_ident\" macrocell 2 5 1 1 +set_location "\SPIM:BSPIM:cnt_enable\" macrocell 2 5 0 0 +set_location "\UART_1:BUART:tx_status_0\" macrocell 2 3 0 3 +set_location "\UART_1:BUART:txn\" macrocell 3 3 0 0 set_location "\SPIM:BSPIM:sR8:Dp:u0\" datapathcell 2 4 2 set_location "\SPIM:BSPIM:tx_status_0\" macrocell 2 4 1 2 -set_location "\UART_1:BUART:tx_status_2\" macrocell 3 4 0 2 -set_location "Net_439" macrocell 3 3 0 0 +set_location "\Timer_1:TimerUDB:status_tc\" macrocell 2 0 0 2 set_location "\SPIM:BSPIM:state_2\" macrocell 2 4 1 1 -set_location "Net_479" macrocell 2 3 1 1 -set_location "\SPIM:BSPIM:mosi_hs_reg\" macrocell 3 5 1 0 -set_location "\UART_1:BUART:counter_load_not\" macrocell 3 5 1 1 -set_location "\UART_1:BUART:tx_bitclk\" macrocell 2 5 1 0 -set_location "\SPIM:BSPIM:TxStsReg\" statusicell 2 3 4 -set_location "\UART_1:BUART:tx_state_1\" macrocell 2 5 0 2 -set_location "\SPIM:BSPIM:mosi_from_dp_reg\" macrocell 3 4 0 0 -set_location "Net_422" macrocell 3 3 1 0 -set_location "Net_30" macrocell 3 3 0 2 -set_location "\UART_1:BUART:tx_state_0\" macrocell 2 5 0 1 -set_location "\UART_1:BUART:sTX:TxSts\" statusicell 3 4 4 -set_location "\SPIM:BSPIM:load_cond\" macrocell 2 3 1 0 +set_location "\Timer_1:TimerUDB:timer_enable\" macrocell 2 0 0 0 +set_location "Net_479" macrocell 3 5 0 0 +set_location "\SPIM:BSPIM:mosi_hs_reg\" macrocell 3 3 1 0 +set_location "\UART_1:BUART:counter_load_not\" macrocell 3 3 1 1 +set_location "Net_30" macrocell 3 5 0 2 +set_location "\SPIM:BSPIM:TxStsReg\" statusicell 2 5 4 +set_location "\UART_1:BUART:tx_state_1\" macrocell 3 0 1 0 +set_location "\UART_1:BUART:tx_bitclk_enable_pre\" macrocell 2 3 1 1 +set_location "Net_234" macrocell 3 4 0 2 +set_location "Net_419" macrocell 3 5 0 3 +set_location "Net_428" macrocell 3 5 1 2 +set_location "\Timer_1:TimerUDB:nrstSts:stsreg\" statusicell 2 0 4 +set_location "\Timer_1:TimerUDB:run_mode\" macrocell 2 0 0 3 +set_location "\UART_1:BUART:tx_state_0\" macrocell 2 3 0 1 +set_location "Net_422" macrocell 3 5 1 0 +set_location "\UART_1:BUART:sTX:TxSts\" statusicell 2 3 4 +set_location "\SPIM:BSPIM:load_cond\" macrocell 2 5 1 0 set_location "\SPIM:BSPIM:BitCounter\" count7cell 2 4 7 set_location "\SPIM:BSPIM:mosi_pre_reg\" macrocell 2 4 0 0 -set_location "\SPIM:BSPIM:dpcounter_one\" macrocell 2 3 1 3 -set_location "\SPIM:BSPIM:load_rx_data\" macrocell 2 3 1 2 -set_location "\SPIM:BSPIM:rx_status_6\" macrocell 2 5 0 0 -set_location "\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\" datapathcell 2 5 2 -set_location "Net_428" macrocell 3 3 1 2 -set_location "\UART_1:BUART:tx_bitclk_enable_pre\" macrocell 2 5 1 1 +set_location "\SPIM:BSPIM:dpcounter_one\" macrocell 2 5 1 3 +set_location "\SPIM:BSPIM:load_rx_data\" macrocell 2 5 1 2 +set_location "\UART_1:BUART:tx_status_2\" macrocell 2 3 1 3 +set_location "\Timer_1:TimerUDB:sT16:timerdp:u1\" datapathcell 3 0 2 +set_location "\Timer_1:TimerUDB:trig_disable\" macrocell 2 0 0 1 +set_location "\SPIM:BSPIM:rx_status_6\" macrocell 2 3 0 0 +set_location "Net_585" macrocell 3 5 1 3 +set_location "\UART_1:BUART:tx_bitclk\" macrocell 2 3 1 0 +set_location "Net_425" macrocell 3 5 1 1 +set_location "\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\" datapathcell 3 3 2 +set_location "\Timer_1:TimerUDB:sT16:timerdp:u0\" datapathcell 2 0 2 set_location "\SPIM:BSPIM:is_spi_done\" macrocell 2 4 1 0 -set_location "Net_425" macrocell 3 3 1 1 -set_location "Net_419" macrocell 3 3 0 3 -set_location "Net_234" macrocell 3 4 0 1 +set_location "\SPIM:BSPIM:mosi_from_dp_reg\" macrocell 3 4 0 0 set_io "\LCD:LCDPort(4)\" iocell 2 4 +set_location "ClockBlock" clockblockcell -1 -1 0 +set_location "\SS:Async:ctrl_reg\" controlcell 3 5 6 set_io "m_miso_pin(0)" iocell 0 0 set_io "Pin_4(0)" iocell 3 3 +set_location "\Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\" controlcell 2 0 6 set_io "\LCD:LCDPort(6)\" iocell 2 6 set_io "\LCD:LCDPort(5)\" iocell 2 5 set_io "\LCD:LCDPort(2)\" iocell 2 2 set_io "Tx_1(0)" iocell 3 7 set_io "m_sclk_pin(0)" iocell 0 6 set_io "Pin_2(0)" iocell 3 1 +set_location "ClockBlock_1k__SYNC" synccell 3 0 5 0 set_io "Pin_1(0)" iocell 3 0 -set_location "ClockBlock" clockblockcell -1 -1 0 set_io "m_mosi_pin(0)" iocell 0 5 set_io "\LCD:LCDPort(1)\" iocell 2 1 set_io "\LCD:LCDPort(0)\" iocell 2 0 set_io "\LCD:LCDPort(3)\" iocell 2 3 set_io "Pin_3(0)" iocell 3 2 -set_location "\SS:Async:ctrl_reg\" controlcell 3 3 6 +set_io "Pin_5(0)" iocell 3 4 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.vh2 index 588b5a8..218d7af 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.vh2 +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_p.vh2 @@ -1,5 +1,5 @@ -- Project: PSOC5_SPI_LSM303D --- Generated: 03/22/2013 10:33:26 +-- Generated: 07/25/2013 16:48:56 -- ENTITY PSOC5_SPI_LSM303D IS @@ -8,6 +8,7 @@ ENTITY PSOC5_SPI_LSM303D IS Pin_2(0)_PAD : OUT std_ulogic; Pin_3(0)_PAD : OUT std_ulogic; Pin_4(0)_PAD : OUT std_ulogic; + Pin_5(0)_PAD : OUT std_ulogic; Tx_1(0)_PAD : OUT std_ulogic; \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; @@ -31,6 +32,7 @@ END PSOC5_SPI_LSM303D; ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL ClockBlock_100k : bit; SIGNAL ClockBlock_1k : bit; + SIGNAL ClockBlock_1k__SYNC_OUT : bit; SIGNAL ClockBlock_32k : bit; SIGNAL ClockBlock_BUS_CLK : bit; ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; @@ -53,10 +55,12 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL Net_428 : bit; SIGNAL Net_439 : bit; SIGNAL Net_479 : bit; + SIGNAL Net_585 : bit; SIGNAL Pin_1(0)__PA : bit; SIGNAL Pin_2(0)__PA : bit; SIGNAL Pin_3(0)__PA : bit; SIGNAL Pin_4(0)__PA : bit; + SIGNAL Pin_5(0)__PA : bit; SIGNAL Tx_1(0)__PA : bit; SIGNAL \\\LCD:LCDPort(0)\\__PA\ : bit; SIGNAL \\\LCD:LCDPort(1)\\__PA\ : bit; @@ -96,12 +100,26 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \SPIM:Net_276\ : bit; ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL \SS:control_2\ : bit; SIGNAL \SS:control_3\ : bit; SIGNAL \SS:control_4\ : bit; SIGNAL \SS:control_5\ : bit; SIGNAL \SS:control_6\ : bit; SIGNAL \SS:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:control_0\ : bit; + SIGNAL \Timer_1:TimerUDB:control_1\ : bit; + SIGNAL \Timer_1:TimerUDB:control_2\ : bit; + SIGNAL \Timer_1:TimerUDB:control_3\ : bit; + SIGNAL \Timer_1:TimerUDB:control_4\ : bit; + SIGNAL \Timer_1:TimerUDB:control_5\ : bit; + SIGNAL \Timer_1:TimerUDB:control_6\ : bit; + SIGNAL \Timer_1:TimerUDB:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:per_zero\ : bit; + SIGNAL \Timer_1:TimerUDB:run_mode\ : bit; + SIGNAL \Timer_1:TimerUDB:status_2\ : bit; + SIGNAL \Timer_1:TimerUDB:status_3\ : bit; + SIGNAL \Timer_1:TimerUDB:status_tc\ : bit; + SIGNAL \Timer_1:TimerUDB:timer_enable\ : bit; + SIGNAL \Timer_1:TimerUDB:trig_disable\ : bit; SIGNAL \UART_1:BUART:counter_load_not\ : bit; SIGNAL \UART_1:BUART:tx_bitclk\ : bit; SIGNAL \UART_1:BUART:tx_bitclk_dp\ : bit; @@ -125,10 +143,24 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL m_sclk_pin(0)__PA : bit; SIGNAL mywire_1_0 : bit; SIGNAL mywire_1_1 : bit; + SIGNAL mywire_1_2 : bit; SIGNAL tmpOE__m_miso_pin_net_0 : bit; ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; SIGNAL zero : bit; ATTRIBUTE GROUND OF zero : SIGNAL IS true; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\ : bit; ATTRIBUTE lib_model OF Net_234 : LABEL IS "macrocell1"; ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; ATTRIBUTE lib_model OF Net_419 : LABEL IS "macrocell3"; @@ -137,6 +169,7 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS ATTRIBUTE lib_model OF Net_428 : LABEL IS "macrocell6"; ATTRIBUTE lib_model OF Net_439 : LABEL IS "macrocell7"; ATTRIBUTE lib_model OF Net_479 : LABEL IS "macrocell8"; + ATTRIBUTE lib_model OF Net_585 : LABEL IS "macrocell9"; ATTRIBUTE lib_model OF Pin_1(0) : LABEL IS "iocell1"; ATTRIBUTE Location OF Pin_1(0) : LABEL IS "P3[0]"; ATTRIBUTE lib_model OF Pin_2(0) : LABEL IS "iocell2"; @@ -145,58 +178,68 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS ATTRIBUTE Location OF Pin_3(0) : LABEL IS "P3[2]"; ATTRIBUTE lib_model OF Pin_4(0) : LABEL IS "iocell4"; ATTRIBUTE Location OF Pin_4(0) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell5"; + ATTRIBUTE lib_model OF Pin_5(0) : LABEL IS "iocell5"; + ATTRIBUTE Location OF Pin_5(0) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell6"; ATTRIBUTE Location OF Tx_1(0) : LABEL IS "P3[7]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell6"; + ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell7"; ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell7"; + ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell8"; ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell8"; + ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell9"; ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell9"; + ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell10"; ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell10"; + ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell11"; ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell11"; + ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell12"; ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell12"; + ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell13"; ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell9"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell10"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell11"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell12"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell13"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell14"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell15"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell16"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell17"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell18"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell10"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell11"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell12"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell13"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell14"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell15"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell16"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell17"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell18"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell19"; ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell19"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell20"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell21"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell22"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell23"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell20"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell21"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell22"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell23"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell24"; ATTRIBUTE lib_model OF \SS:Async:ctrl_reg\ : LABEL IS "controlcell1"; - ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell24"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell2"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell3"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell3"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell25"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell26"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell27"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell28"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell29"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell30"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell31"; - ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell32"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell13"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:nrstSts:stsreg\ : LABEL IS "statusicell3"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:run_mode\ : LABEL IS "macrocell25"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ : LABEL IS "controlcell2"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u0\ : LABEL IS "datapathcell2"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u1\ : LABEL IS "datapathcell3"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:status_tc\ : LABEL IS "macrocell26"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:timer_enable\ : LABEL IS "macrocell27"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:trig_disable\ : LABEL IS "macrocell28"; + ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell29"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell4"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell4"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell5"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell30"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell31"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell32"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell33"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell34"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell35"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell36"; + ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell37"; + ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell14"; ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell14"; + ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell15"; ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell15"; + ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell16"; ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; COMPONENT abufcell END COMPONENT; @@ -1143,6 +1186,15 @@ BEGIN dclk_glb_1 => Net_191, dclk_1 => Net_191_local); + ClockBlock_1k__SYNC:synccell + GENERIC MAP( + clk_inv => '0') + PORT MAP( + in => ClockBlock_1k, + out => ClockBlock_1k__SYNC_OUT, + clock => ClockBlock_BUS_CLK, + clk_en => open); + Net_234:macrocell GENERIC MAP( eqn_main => "(!main_0)") @@ -1160,39 +1212,43 @@ BEGIN Net_419:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3)") PORT MAP( q => Net_419, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_422:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * main_3)") PORT MAP( q => Net_422, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_425:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * main_3)") PORT MAP( q => Net_425, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_428:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * !main_3)") PORT MAP( q => Net_428, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_439:macrocell GENERIC MAP( @@ -1218,6 +1274,16 @@ BEGIN main_2 => \SPIM:BSPIM:state_1\, main_3 => \SPIM:BSPIM:state_0\); + Net_585:macrocell + GENERIC MAP( + eqn_main => "(!main_0 * main_1 * !main_2 * !main_3)") + PORT MAP( + q => Net_585, + main_0 => Net_439, + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); + Pin_1:logicalport GENERIC MAP( drive_mode => "010", @@ -1566,6 +1632,93 @@ BEGIN out_clock_en => '1', out_reset => '0'); + Pin_5:logicalport + GENERIC MAP( + drive_mode => "010", + ibuf_enabled => "1", + id => "f04dd9ba-954e-4352-a3f2-4deb8634d958", + init_dr_st => "1", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "0", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Pin_5(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Pin_5", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000100000000000000000000000000000000000000001") + PORT MAP( + pa_out => Pin_5(0)__PA, + oe => open, + pin_input => Net_585, + pad_out => Pin_5(0)_PAD, + pad_in => Pin_5(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + Tx_1:logicalport GENERIC MAP( drive_mode => "110", @@ -2167,11 +2320,192 @@ BEGIN control_5 => \SS:control_5\, control_4 => \SS:control_4\, control_3 => \SS:control_3\, - control_2 => \SS:control_2\, + control_2 => mywire_1_2, control_1 => mywire_1_1, control_0 => mywire_1_0, busclk => ClockBlock_BUS_CLK); + \Timer_1:TimerUDB:nrstSts:stsreg\:statusicell + GENERIC MAP( + cy_force_order => 1, + cy_int_mask => "1111111", + cy_md_select => "0000011", + clk_inv => '0', + clken_inv => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + status_6 => open, + status_5 => open, + status_4 => open, + status_3 => \Timer_1:TimerUDB:status_3\, + status_2 => \Timer_1:TimerUDB:status_2\, + status_1 => open, + status_0 => \Timer_1:TimerUDB:status_tc\, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:run_mode\:macrocell + GENERIC MAP( + eqn_main => "(main_0)", + clk_inv => '0', + clken_inv => '0') + PORT MAP( + q => \Timer_1:TimerUDB:run_mode\, + main_0 => \Timer_1:TimerUDB:control_7\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\:controlcell + GENERIC MAP( + cy_ctrl_mode_0 => "00000000", + cy_ctrl_mode_1 => "00000000", + cy_ext_reset => 0, + cy_force_order => 1, + cy_init_value => "00000000") + PORT MAP( + control_7 => \Timer_1:TimerUDB:control_7\, + control_6 => \Timer_1:TimerUDB:control_6\, + control_5 => \Timer_1:TimerUDB:control_5\, + control_4 => \Timer_1:TimerUDB:control_4\, + control_3 => \Timer_1:TimerUDB:control_3\, + control_2 => \Timer_1:TimerUDB:control_2\, + control_1 => \Timer_1:TimerUDB:control_1\, + control_0 => \Timer_1:TimerUDB:control_0\, + busclk => ClockBlock_BUS_CLK); + + \Timer_1:TimerUDB:sT16:timerdp:u0\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0', + clk_inv => '0', + clken_inv => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + clk_en => ClockBlock_1k__SYNC_OUT, + busclk => ClockBlock_BUS_CLK, + ce0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0 => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1 => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + co_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sol_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbo => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sil => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbi => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:sT16:timerdp:u1\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0', + clk_inv => '0', + clken_inv => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + z0_comb => \Timer_1:TimerUDB:per_zero\, + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\, + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\, + busclk => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + ce0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0i => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1i => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + ci => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sir => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbi => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sor => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbo => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:status_tc\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1)") + PORT MAP( + q => \Timer_1:TimerUDB:status_tc\, + main_0 => \Timer_1:TimerUDB:run_mode\, + main_1 => \Timer_1:TimerUDB:per_zero\); + + \Timer_1:TimerUDB:timer_enable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * !main_1 * !main_4) + (main_0 * !main_2 * !main_4) + (main_0 * !main_3 * !main_4)", + clk_inv => '0', + clken_inv => '0') + PORT MAP( + q => \Timer_1:TimerUDB:timer_enable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:control_7\, + main_1 => \Timer_1:TimerUDB:timer_enable\, + main_2 => \Timer_1:TimerUDB:run_mode\, + main_3 => \Timer_1:TimerUDB:per_zero\, + main_4 => \Timer_1:TimerUDB:trig_disable\); + + \Timer_1:TimerUDB:trig_disable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1 * main_2 * !main_3)", + clk_inv => '0', + clken_inv => '0') + PORT MAP( + q => \Timer_1:TimerUDB:trig_disable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:timer_enable\, + main_1 => \Timer_1:TimerUDB:run_mode\, + main_2 => \Timer_1:TimerUDB:per_zero\, + main_3 => \Timer_1:TimerUDB:trig_disable\); + \UART_1:BUART:counter_load_not\:macrocell GENERIC MAP( eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)") diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.lib index 7621965..7df65f1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.lib +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.lib @@ -247,7 +247,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -257,7 +257,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -335,7 +335,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -345,7 +345,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -423,7 +423,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -433,7 +433,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -511,7 +511,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -521,7 +521,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -726,6 +726,94 @@ library (timing) { } } } + cell (macrocell9) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } cell (iocell1) { pin (in_clock) { direction : input; @@ -999,6 +1087,74 @@ library (timing) { } } cell (iocell5) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.839; + intrinsic_fall : 16.839; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 16.918; + intrinsic_fall : 16.918; + } + } + } + cell (iocell6) { pin (in_clock) { direction : input; clock : true; @@ -1066,7 +1222,7 @@ library (timing) { } } } - cell (iocell6) { + cell (iocell7) { pin (in_clock) { direction : input; clock : true; @@ -1134,7 +1290,7 @@ library (timing) { } } } - cell (iocell7) { + cell (iocell8) { pin (in_clock) { direction : input; clock : true; @@ -1202,7 +1358,7 @@ library (timing) { } } } - cell (iocell8) { + cell (iocell9) { pin (in_clock) { direction : input; clock : true; @@ -1270,7 +1426,7 @@ library (timing) { } } } - cell (iocell9) { + cell (iocell10) { pin (in_clock) { direction : input; clock : true; @@ -1338,7 +1494,7 @@ library (timing) { } } } - cell (iocell10) { + cell (iocell11) { pin (in_clock) { direction : input; clock : true; @@ -1406,7 +1562,7 @@ library (timing) { } } } - cell (iocell11) { + cell (iocell12) { pin (in_clock) { direction : input; clock : true; @@ -1474,7 +1630,7 @@ library (timing) { } } } - cell (iocell12) { + cell (iocell13) { pin (in_clock) { direction : input; clock : true; @@ -1694,7 +1850,7 @@ library (timing) { direction : output; } } - cell (macrocell9) { + cell (macrocell10) { pin (cin) { direction : input; } @@ -1792,7 +1948,7 @@ library (timing) { } } } - cell (macrocell10) { + cell (macrocell11) { pin (cin) { direction : input; } @@ -1880,7 +2036,7 @@ library (timing) { } } } - cell (macrocell11) { + cell (macrocell12) { pin (cin) { direction : input; } @@ -1978,7 +2134,7 @@ library (timing) { } } } - cell (macrocell12) { + cell (macrocell13) { pin (cin) { direction : input; } @@ -2076,7 +2232,7 @@ library (timing) { } } } - cell (macrocell13) { + cell (macrocell14) { pin (cin) { direction : input; } @@ -2174,7 +2330,7 @@ library (timing) { } } } - cell (macrocell14) { + cell (macrocell15) { pin (cin) { direction : input; } @@ -2272,7 +2428,7 @@ library (timing) { } } } - cell (macrocell15) { + cell (macrocell16) { pin (cin) { direction : input; } @@ -2370,7 +2526,7 @@ library (timing) { } } } - cell (macrocell16) { + cell (macrocell17) { pin (cin) { direction : input; } @@ -2468,7 +2624,7 @@ library (timing) { } } } - cell (macrocell17) { + cell (macrocell18) { pin (cin) { direction : input; } @@ -2566,7 +2722,7 @@ library (timing) { } } } - cell (macrocell18) { + cell (macrocell19) { pin (cin) { direction : input; } @@ -3159,7 +3315,7 @@ library (timing) { direction : output; } } - cell (macrocell19) { + cell (macrocell20) { pin (cin) { direction : input; } @@ -3257,7 +3413,7 @@ library (timing) { } } } - cell (macrocell20) { + cell (macrocell21) { pin (cin) { direction : input; } @@ -3355,7 +3511,7 @@ library (timing) { } } } - cell (macrocell21) { + cell (macrocell22) { pin (cin) { direction : input; } @@ -3453,7 +3609,7 @@ library (timing) { } } } - cell (macrocell22) { + cell (macrocell23) { pin (cin) { direction : input; } @@ -3541,7 +3697,7 @@ library (timing) { } } } - cell (macrocell23) { + cell (macrocell24) { pin (cin) { direction : input; } @@ -3787,24 +3943,8 @@ library (timing) { } } } - cell (macrocell24) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); + cell (statusicell3) { + pin (clock) { direction : input; clock : true; } @@ -3812,59 +3952,1778 @@ library (timing) { direction : input; timing () { timing_type : setup_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 2.100; intrinsic_fall : 2.100; } timing () { timing_type : hold_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 0.000; intrinsic_fall : 0.000; } } - bundle (ar) { - members (ar_0); + pin (reset) { direction : input; timing () { timing_type : recovery_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } timing () { timing_type : removal_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } } - bundle (ap) { - members (ap_0); + pin (status_0) { direction : input; timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; } } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + pin (status_1) { + direction : input; timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } - } - pin (q_fixed) { + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; + } + } + pin (status_2) { + direction : input; + } + pin (status_3) { + direction : input; + } + pin (status_4) { + direction : input; + } + pin (status_5) { + direction : input; + } + pin (status_6) { + direction : input; + } + pin (interrupt) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.030; + intrinsic_fall : 4.030; + } + timing () { + timing_sense : negative_unate; + timing_type : clear; + related_pin : "reset"; + intrinsic_rise : 8.260; + intrinsic_fall : 8.260; + } + } + } + cell (macrocell25) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (controlcell2) { + pin (clock) { + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + } + pin (busclk) { + direction : input; + clock : true; + } + pin (control_0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_2) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_3) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_4) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_5) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_6) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_7) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + } + cell (datapathcell2) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + } + pin (f0_blk_stat_comb) { + direction : output; + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + } + pin (cl0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + } + pin (z0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.32; + intrinsic_fall : 2.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.74; + intrinsic_fall : 1.74; + } + } + pin (ff0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.73; + intrinsic_fall : 2.73; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.32; + intrinsic_fall : 1.32; + } + } + pin (ce1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + } + pin (cl1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + } + pin (z1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.29; + intrinsic_fall : 2.29; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.53; + intrinsic_fall : 1.53; + } + } + pin (ff1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.17; + intrinsic_fall : 2.17; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.18; + intrinsic_fall : 1.18; + } + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.21; + intrinsic_fall : 3.21; + } + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.84; + intrinsic_fall : 4.84; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.63; + intrinsic_fall : 3.63; + } + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + } + } + cell (datapathcell3) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.09; + intrinsic_fall : 5.09; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 4.57; + intrinsic_fall : 4.57; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.96; + intrinsic_fall : 2.96; + } + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.74; + intrinsic_fall : 2.74; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.85; + intrinsic_fall : 3.85; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.27; + intrinsic_fall : 3.27; + } + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + } + pin (f0_blk_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + } + pin (cl0) { + direction : output; + } + pin (z0) { + direction : output; + } + pin (ff0) { + direction : output; + } + pin (ce1) { + direction : output; + } + pin (cl1) { + direction : output; + } + pin (z1) { + direction : output; + } + pin (ff1) { + direction : output; + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.32; + intrinsic_fall : 3.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.25; + intrinsic_fall : 2.25; + } + } + } + cell (macrocell26) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } + cell (macrocell27) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell28) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell29) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { direction : output; function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; timing () { @@ -3875,7 +5734,7 @@ library (timing) { } } } - cell (datapathcell2) { + cell (datapathcell4) { pin (clk_en) { direction : input; } @@ -4260,7 +6119,7 @@ library (timing) { direction : output; } } - cell (statusicell3) { + cell (statusicell4) { pin (clock) { direction : input; clock : true; @@ -4427,7 +6286,7 @@ library (timing) { } } } - cell (datapathcell3) { + cell (datapathcell5) { pin (clk_en) { direction : input; } @@ -4752,7 +6611,7 @@ library (timing) { direction : output; } } - cell (macrocell25) { + cell (macrocell30) { pin (cin) { direction : input; } @@ -4850,7 +6709,7 @@ library (timing) { } } } - cell (macrocell26) { + cell (macrocell31) { pin (cin) { direction : input; } @@ -4938,7 +6797,7 @@ library (timing) { } } } - cell (macrocell27) { + cell (macrocell32) { pin (cin) { direction : input; } @@ -5036,7 +6895,7 @@ library (timing) { } } } - cell (macrocell28) { + cell (macrocell33) { pin (cin) { direction : input; } @@ -5134,7 +6993,7 @@ library (timing) { } } } - cell (macrocell29) { + cell (macrocell34) { pin (cin) { direction : input; } @@ -5232,7 +7091,7 @@ library (timing) { } } } - cell (macrocell30) { + cell (macrocell35) { pin (cin) { direction : input; } @@ -5320,7 +7179,7 @@ library (timing) { } } } - cell (macrocell31) { + cell (macrocell36) { pin (cin) { direction : input; } @@ -5408,7 +7267,7 @@ library (timing) { } } } - cell (macrocell32) { + cell (macrocell37) { pin (cin) { direction : input; } @@ -5506,7 +7365,7 @@ library (timing) { } } } - cell (iocell13) { + cell (iocell14) { pin (in_clock) { direction : input; clock : true; @@ -5574,7 +7433,7 @@ library (timing) { } } } - cell (iocell14) { + cell (iocell15) { pin (in_clock) { direction : input; clock : true; @@ -5642,7 +7501,7 @@ library (timing) { } } } - cell (iocell15) { + cell (iocell16) { pin (in_clock) { direction : input; clock : true; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.vh2 index e5c3302..e3a6b40 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.vh2 +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_r.vh2 @@ -1,5 +1,5 @@ -- Project: PSOC5_SPI_LSM303D --- Generated: 03/22/2013 10:33:27 +-- Generated: 07/25/2013 16:48:57 -- ENTITY PSOC5_SPI_LSM303D IS @@ -8,6 +8,7 @@ ENTITY PSOC5_SPI_LSM303D IS Pin_2(0)_PAD : OUT std_ulogic; Pin_3(0)_PAD : OUT std_ulogic; Pin_4(0)_PAD : OUT std_ulogic; + Pin_5(0)_PAD : OUT std_ulogic; Tx_1(0)_PAD : OUT std_ulogic; \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; @@ -31,6 +32,7 @@ END PSOC5_SPI_LSM303D; ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL ClockBlock_100k : bit; SIGNAL ClockBlock_1k : bit; + SIGNAL ClockBlock_1k__SYNC_OUT : bit; SIGNAL ClockBlock_32k : bit; SIGNAL ClockBlock_BUS_CLK : bit; ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; @@ -46,25 +48,28 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL Net_191_local : bit; SIGNAL Net_20 : bit; SIGNAL Net_234 : bit; - ATTRIBUTE placement_force OF Net_234 : SIGNAL IS "U(3,4,A)1"; + ATTRIBUTE placement_force OF Net_234 : SIGNAL IS "U(3,4,A)2"; SIGNAL Net_30 : bit; - ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(3,3,A)2"; + ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(3,5,A)2"; SIGNAL Net_419 : bit; - ATTRIBUTE placement_force OF Net_419 : SIGNAL IS "U(3,3,A)3"; + ATTRIBUTE placement_force OF Net_419 : SIGNAL IS "U(3,5,A)3"; SIGNAL Net_422 : bit; - ATTRIBUTE placement_force OF Net_422 : SIGNAL IS "U(3,3,B)0"; + ATTRIBUTE placement_force OF Net_422 : SIGNAL IS "U(3,5,B)0"; SIGNAL Net_425 : bit; - ATTRIBUTE placement_force OF Net_425 : SIGNAL IS "U(3,3,B)1"; + ATTRIBUTE placement_force OF Net_425 : SIGNAL IS "U(3,5,B)1"; SIGNAL Net_428 : bit; - ATTRIBUTE placement_force OF Net_428 : SIGNAL IS "U(3,3,B)2"; + ATTRIBUTE placement_force OF Net_428 : SIGNAL IS "U(3,5,B)2"; SIGNAL Net_439 : bit; - ATTRIBUTE placement_force OF Net_439 : SIGNAL IS "U(3,3,A)0"; + ATTRIBUTE placement_force OF Net_439 : SIGNAL IS "U(3,5,A)1"; SIGNAL Net_479 : bit; - ATTRIBUTE placement_force OF Net_479 : SIGNAL IS "U(2,3,B)1"; + ATTRIBUTE placement_force OF Net_479 : SIGNAL IS "U(3,5,A)0"; + SIGNAL Net_585 : bit; + ATTRIBUTE placement_force OF Net_585 : SIGNAL IS "U(3,5,B)3"; SIGNAL Pin_1(0)__PA : bit; SIGNAL Pin_2(0)__PA : bit; SIGNAL Pin_3(0)__PA : bit; SIGNAL Pin_4(0)__PA : bit; + SIGNAL Pin_5(0)__PA : bit; SIGNAL Tx_1(0)__PA : bit; SIGNAL \\\LCD:LCDPort(0)\\__PA\ : bit; SIGNAL \\\LCD:LCDPort(1)\\__PA\ : bit; @@ -74,7 +79,7 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \\\LCD:LCDPort(5)\\__PA\ : bit; SIGNAL \\\LCD:LCDPort(6)\\__PA\ : bit; SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(2,3,A)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(2,5,A)0"; SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; SIGNAL \SPIM:BSPIM:count_0\ : bit; SIGNAL \SPIM:BSPIM:count_1\ : bit; @@ -84,30 +89,30 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \SPIM:BSPIM:count_5\ : bit; SIGNAL \SPIM:BSPIM:count_6\ : bit; SIGNAL \SPIM:BSPIM:dpcounter_one\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:dpcounter_one\ : SIGNAL IS "U(2,3,B)3"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:dpcounter_one\ : SIGNAL IS "U(2,5,B)3"; SIGNAL \SPIM:BSPIM:is_spi_done\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:is_spi_done\ : SIGNAL IS "U(2,4,B)0"; SIGNAL \SPIM:BSPIM:ld_ident\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:ld_ident\ : SIGNAL IS "U(3,3,A)1"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:ld_ident\ : SIGNAL IS "U(2,5,B)1"; SIGNAL \SPIM:BSPIM:load_cond\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(2,3,B)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(2,5,B)0"; SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(2,3,B)2"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(2,5,B)2"; SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; SIGNAL \SPIM:BSPIM:mosi_from_dp_reg\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_from_dp_reg\ : SIGNAL IS "U(3,4,A)0"; SIGNAL \SPIM:BSPIM:mosi_hs_reg\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_hs_reg\ : SIGNAL IS "U(3,5,B)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_hs_reg\ : SIGNAL IS "U(3,3,B)0"; SIGNAL \SPIM:BSPIM:mosi_pre_reg\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_pre_reg\ : SIGNAL IS "U(2,4,A)0"; SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(2,5,A)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(2,3,A)0"; SIGNAL \SPIM:BSPIM:state_0\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:state_0\ : SIGNAL IS "U(2,4,B)3"; SIGNAL \SPIM:BSPIM:state_1\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(2,3,A)1"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(2,5,A)1"; SIGNAL \SPIM:BSPIM:state_2\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:state_2\ : SIGNAL IS "U(2,4,B)1"; SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; @@ -115,39 +120,57 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(2,3,A)2"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(2,5,A)2"; SIGNAL \SPIM:Net_276\ : bit; ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL \SS:control_2\ : bit; SIGNAL \SS:control_3\ : bit; SIGNAL \SS:control_4\ : bit; SIGNAL \SS:control_5\ : bit; SIGNAL \SS:control_6\ : bit; SIGNAL \SS:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:control_0\ : bit; + SIGNAL \Timer_1:TimerUDB:control_1\ : bit; + SIGNAL \Timer_1:TimerUDB:control_2\ : bit; + SIGNAL \Timer_1:TimerUDB:control_3\ : bit; + SIGNAL \Timer_1:TimerUDB:control_4\ : bit; + SIGNAL \Timer_1:TimerUDB:control_5\ : bit; + SIGNAL \Timer_1:TimerUDB:control_6\ : bit; + SIGNAL \Timer_1:TimerUDB:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:per_zero\ : bit; + SIGNAL \Timer_1:TimerUDB:run_mode\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:run_mode\ : SIGNAL IS "U(2,0,A)3"; + SIGNAL \Timer_1:TimerUDB:status_2\ : bit; + SIGNAL \Timer_1:TimerUDB:status_3\ : bit; + SIGNAL \Timer_1:TimerUDB:status_tc\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:status_tc\ : SIGNAL IS "U(2,0,A)2"; + SIGNAL \Timer_1:TimerUDB:timer_enable\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:timer_enable\ : SIGNAL IS "U(2,0,A)0"; + SIGNAL \Timer_1:TimerUDB:trig_disable\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:trig_disable\ : SIGNAL IS "U(2,0,A)1"; SIGNAL \UART_1:BUART:counter_load_not\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:counter_load_not\ : SIGNAL IS "U(3,5,B)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:counter_load_not\ : SIGNAL IS "U(3,3,B)1"; SIGNAL \UART_1:BUART:tx_bitclk\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk\ : SIGNAL IS "U(2,5,B)0"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk\ : SIGNAL IS "U(2,3,B)0"; SIGNAL \UART_1:BUART:tx_bitclk_dp\ : bit; SIGNAL \UART_1:BUART:tx_bitclk_enable_pre\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk_enable_pre\ : SIGNAL IS "U(2,5,B)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk_enable_pre\ : SIGNAL IS "U(2,3,B)1"; SIGNAL \UART_1:BUART:tx_counter_dp\ : bit; SIGNAL \UART_1:BUART:tx_fifo_empty\ : bit; SIGNAL \UART_1:BUART:tx_fifo_notfull\ : bit; SIGNAL \UART_1:BUART:tx_shift_out\ : bit; SIGNAL \UART_1:BUART:tx_state_0\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_0\ : SIGNAL IS "U(2,5,A)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_0\ : SIGNAL IS "U(2,3,A)1"; SIGNAL \UART_1:BUART:tx_state_1\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_1\ : SIGNAL IS "U(2,5,A)2"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_1\ : SIGNAL IS "U(3,0,B)0"; SIGNAL \UART_1:BUART:tx_state_2\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_2\ : SIGNAL IS "U(3,5,A)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_2\ : SIGNAL IS "U(3,3,A)1"; SIGNAL \UART_1:BUART:tx_status_0\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_0\ : SIGNAL IS "U(2,5,A)3"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_0\ : SIGNAL IS "U(2,3,A)3"; SIGNAL \UART_1:BUART:tx_status_2\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_2\ : SIGNAL IS "U(3,4,A)2"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_2\ : SIGNAL IS "U(2,3,B)3"; SIGNAL \UART_1:BUART:txn\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:txn\ : SIGNAL IS "U(3,5,A)0"; + ATTRIBUTE placement_force OF \UART_1:BUART:txn\ : SIGNAL IS "U(3,3,A)0"; SIGNAL __ONE__ : bit; ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; SIGNAL __ZERO__ : bit; @@ -157,27 +180,44 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL m_sclk_pin(0)__PA : bit; SIGNAL mywire_1_0 : bit; SIGNAL mywire_1_1 : bit; + SIGNAL mywire_1_2 : bit; SIGNAL tmpOE__m_miso_pin_net_0 : bit; ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; SIGNAL zero : bit; ATTRIBUTE GROUND OF zero : SIGNAL IS true; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\ : bit; ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; + ATTRIBUTE Location OF ClockBlock_1k__SYNC : LABEL IS "U(3,0)"; ATTRIBUTE lib_model OF Net_234 : LABEL IS "macrocell1"; ATTRIBUTE Location OF Net_234 : LABEL IS "U(3,4)"; ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; - ATTRIBUTE Location OF Net_30 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_30 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_419 : LABEL IS "macrocell3"; - ATTRIBUTE Location OF Net_419 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_419 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_422 : LABEL IS "macrocell4"; - ATTRIBUTE Location OF Net_422 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_422 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_425 : LABEL IS "macrocell5"; - ATTRIBUTE Location OF Net_425 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_425 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_428 : LABEL IS "macrocell6"; - ATTRIBUTE Location OF Net_428 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_428 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_439 : LABEL IS "macrocell7"; - ATTRIBUTE Location OF Net_439 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_439 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_479 : LABEL IS "macrocell8"; - ATTRIBUTE Location OF Net_479 : LABEL IS "U(2,3)"; + ATTRIBUTE Location OF Net_479 : LABEL IS "U(3,5)"; + ATTRIBUTE lib_model OF Net_585 : LABEL IS "macrocell9"; + ATTRIBUTE Location OF Net_585 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Pin_1(0) : LABEL IS "iocell1"; ATTRIBUTE Location OF Pin_1(0) : LABEL IS "P3[0]"; ATTRIBUTE lib_model OF Pin_2(0) : LABEL IS "iocell2"; @@ -186,90 +226,108 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS ATTRIBUTE Location OF Pin_3(0) : LABEL IS "P3[2]"; ATTRIBUTE lib_model OF Pin_4(0) : LABEL IS "iocell4"; ATTRIBUTE Location OF Pin_4(0) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell5"; + ATTRIBUTE lib_model OF Pin_5(0) : LABEL IS "iocell5"; + ATTRIBUTE Location OF Pin_5(0) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell6"; ATTRIBUTE Location OF Tx_1(0) : LABEL IS "P3[7]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell6"; + ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell7"; ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell7"; + ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell8"; ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell8"; + ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell9"; ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell9"; + ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell10"; ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell10"; + ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell11"; ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell11"; + ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell12"; ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell12"; + ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell13"; ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; ATTRIBUTE Location OF \SPIM:BSPIM:BitCounter\ : LABEL IS "U(2,4)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(2,5)"; + ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(3,4)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell9"; - ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell10"; - ATTRIBUTE Location OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell11"; + ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell10"; + ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell11"; + ATTRIBUTE Location OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell12"; ATTRIBUTE Location OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell12"; - ATTRIBUTE Location OF \SPIM:BSPIM:ld_ident\ : LABEL IS "U(3,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell13"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell14"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell15"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell13"; + ATTRIBUTE Location OF \SPIM:BSPIM:ld_ident\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell14"; + ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell15"; + ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell16"; ATTRIBUTE Location OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell16"; - ATTRIBUTE Location OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell17"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell17"; + ATTRIBUTE Location OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell18"; ATTRIBUTE Location OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell18"; - ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell19"; + ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(2,3)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; ATTRIBUTE Location OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell19"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell20"; ATTRIBUTE Location OF \SPIM:BSPIM:state_0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell20"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell21"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell21"; + ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell22"; ATTRIBUTE Location OF \SPIM:BSPIM:state_2\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell22"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell23"; ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell23"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell24"; + ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(2,5)"; ATTRIBUTE lib_model OF \SS:Async:ctrl_reg\ : LABEL IS "controlcell1"; - ATTRIBUTE Location OF \SS:Async:ctrl_reg\ : LABEL IS "U(3,3)"; - ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell24"; - ATTRIBUTE Location OF \UART_1:BUART:counter_load_not\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell2"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell3"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell3"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell25"; - ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell26"; - ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell27"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_0\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell28"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_1\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell29"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_2\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell30"; - ATTRIBUTE Location OF \UART_1:BUART:tx_status_0\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell31"; - ATTRIBUTE Location OF \UART_1:BUART:tx_status_2\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell32"; - ATTRIBUTE Location OF \UART_1:BUART:txn\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell13"; + ATTRIBUTE Location OF \SS:Async:ctrl_reg\ : LABEL IS "U(3,5)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:nrstSts:stsreg\ : LABEL IS "statusicell3"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:nrstSts:stsreg\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:run_mode\ : LABEL IS "macrocell25"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:run_mode\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ : LABEL IS "controlcell2"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u0\ : LABEL IS "datapathcell2"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u1\ : LABEL IS "datapathcell3"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sT16:timerdp:u1\ : LABEL IS "U(3,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:status_tc\ : LABEL IS "macrocell26"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:status_tc\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:timer_enable\ : LABEL IS "macrocell27"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:timer_enable\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:trig_disable\ : LABEL IS "macrocell28"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:trig_disable\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell29"; + ATTRIBUTE Location OF \UART_1:BUART:counter_load_not\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell4"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell4"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell5"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell30"; + ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell31"; + ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell32"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell33"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_1\ : LABEL IS "U(3,0)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell34"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_2\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell35"; + ATTRIBUTE Location OF \UART_1:BUART:tx_status_0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell36"; + ATTRIBUTE Location OF \UART_1:BUART:tx_status_2\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell37"; + ATTRIBUTE Location OF \UART_1:BUART:txn\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell14"; ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell14"; + ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell15"; ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell15"; + ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell16"; ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; COMPONENT abufcell END COMPONENT; @@ -1189,6 +1247,13 @@ BEGIN dclk_glb_1 => Net_191, dclk_1 => Net_191_local); + ClockBlock_1k__SYNC:synccell + PORT MAP( + in => ClockBlock_1k, + out => ClockBlock_1k__SYNC_OUT, + clock => ClockBlock_BUS_CLK, + clk_en => open); + Net_234:macrocell GENERIC MAP( eqn_main => "(!main_0)") @@ -1206,39 +1271,43 @@ BEGIN Net_419:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3)") PORT MAP( q => Net_419, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_422:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * main_3)") PORT MAP( q => Net_422, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_425:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * main_3)") PORT MAP( q => Net_425, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_428:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * !main_3)") PORT MAP( q => Net_428, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_439:macrocell GENERIC MAP( @@ -1262,6 +1331,16 @@ BEGIN main_2 => \SPIM:BSPIM:state_1\, main_3 => \SPIM:BSPIM:state_0\); + Net_585:macrocell + GENERIC MAP( + eqn_main => "(!main_0 * main_1 * !main_2 * !main_3)") + PORT MAP( + q => Net_585, + main_0 => Net_439, + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); + Pin_1:logicalport GENERIC MAP( drive_mode => "010", @@ -1610,6 +1689,93 @@ BEGIN out_clock_en => '1', out_reset => '0'); + Pin_5:logicalport + GENERIC MAP( + drive_mode => "010", + ibuf_enabled => "1", + id => "f04dd9ba-954e-4352-a3f2-4deb8634d958", + init_dr_st => "1", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "0", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Pin_5(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Pin_5", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000100000000000000000000000000000000000000001") + PORT MAP( + pa_out => Pin_5(0)__PA, + oe => open, + pin_input => Net_585, + pad_out => Pin_5(0)_PAD, + pad_in => Pin_5(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + Tx_1:logicalport GENERIC MAP( drive_mode => "110", @@ -2196,11 +2362,180 @@ BEGIN control_5 => \SS:control_5\, control_4 => \SS:control_4\, control_3 => \SS:control_3\, - control_2 => \SS:control_2\, + control_2 => mywire_1_2, control_1 => mywire_1_1, control_0 => mywire_1_0, busclk => ClockBlock_BUS_CLK); + \Timer_1:TimerUDB:nrstSts:stsreg\:statusicell + GENERIC MAP( + cy_force_order => 1, + cy_int_mask => "1111111", + cy_md_select => "0000011") + PORT MAP( + clock => ClockBlock_BUS_CLK, + status_6 => open, + status_5 => open, + status_4 => open, + status_3 => \Timer_1:TimerUDB:status_3\, + status_2 => \Timer_1:TimerUDB:status_2\, + status_1 => open, + status_0 => \Timer_1:TimerUDB:status_tc\, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:run_mode\:macrocell + GENERIC MAP( + eqn_main => "(main_0)") + PORT MAP( + q => \Timer_1:TimerUDB:run_mode\, + main_0 => \Timer_1:TimerUDB:control_7\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\:controlcell + GENERIC MAP( + cy_ctrl_mode_0 => "00000000", + cy_ctrl_mode_1 => "00000000", + cy_ext_reset => 0, + cy_force_order => 1, + cy_init_value => "00000000") + PORT MAP( + control_7 => \Timer_1:TimerUDB:control_7\, + control_6 => \Timer_1:TimerUDB:control_6\, + control_5 => \Timer_1:TimerUDB:control_5\, + control_4 => \Timer_1:TimerUDB:control_4\, + control_3 => \Timer_1:TimerUDB:control_3\, + control_2 => \Timer_1:TimerUDB:control_2\, + control_1 => \Timer_1:TimerUDB:control_1\, + control_0 => \Timer_1:TimerUDB:control_0\, + busclk => ClockBlock_BUS_CLK); + + \Timer_1:TimerUDB:sT16:timerdp:u0\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + clk_en => ClockBlock_1k__SYNC_OUT, + busclk => ClockBlock_BUS_CLK, + ce0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0 => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1 => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + co_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sol_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbo => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sil => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbi => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:sT16:timerdp:u1\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + z0_comb => \Timer_1:TimerUDB:per_zero\, + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\, + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\, + busclk => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + ce0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0i => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1i => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + ci => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sir => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbi => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sor => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbo => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:status_tc\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1)") + PORT MAP( + q => \Timer_1:TimerUDB:status_tc\, + main_0 => \Timer_1:TimerUDB:run_mode\, + main_1 => \Timer_1:TimerUDB:per_zero\); + + \Timer_1:TimerUDB:timer_enable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * !main_1 * !main_4) + (main_0 * !main_2 * !main_4) + (main_0 * !main_3 * !main_4)") + PORT MAP( + q => \Timer_1:TimerUDB:timer_enable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:control_7\, + main_1 => \Timer_1:TimerUDB:timer_enable\, + main_2 => \Timer_1:TimerUDB:run_mode\, + main_3 => \Timer_1:TimerUDB:per_zero\, + main_4 => \Timer_1:TimerUDB:trig_disable\); + + \Timer_1:TimerUDB:trig_disable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1 * main_2 * !main_3)") + PORT MAP( + q => \Timer_1:TimerUDB:trig_disable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:timer_enable\, + main_1 => \Timer_1:TimerUDB:run_mode\, + main_2 => \Timer_1:TimerUDB:per_zero\, + main_3 => \Timer_1:TimerUDB:trig_disable\); + \UART_1:BUART:counter_load_not\:macrocell GENERIC MAP( eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)") diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.lib index 7621965..7df65f1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.lib +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.lib @@ -247,7 +247,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -257,7 +257,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -335,7 +335,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -345,7 +345,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * !main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * !main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -423,7 +423,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -433,7 +433,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -511,7 +511,7 @@ library (timing) { } pin (q) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -521,7 +521,7 @@ library (timing) { } pin (q_fixed) { direction : output; - function : "((!main_0 * main_1 * !main_2)) ^ 1"; + function : "((!main_0 * !main_1 * main_2 * !main_3)) ^ 1"; timing () { timing_type : combinational; related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; @@ -726,6 +726,94 @@ library (timing) { } } } + cell (macrocell9) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((!main_0 * main_1 * !main_2 * !main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } cell (iocell1) { pin (in_clock) { direction : input; @@ -999,6 +1087,74 @@ library (timing) { } } cell (iocell5) { + pin (in_clock) { + direction : input; + clock : true; + } + pin (in_clock_en) { + direction : input; + } + pin (in_reset) { + direction : input; + } + pin (out_clock) { + direction : input; + clock : true; + } + pin (out_clock_en) { + direction : input; + } + pin (out_reset) { + direction : input; + } + pin (pin_input) { + direction : input; + } + pin (pa_out) { + direction : output; + } + pin (oe) { + direction : input; + } + pin (pad_in) { + direction : input; + } + pin (pad_out) { + direction : output; + timing () { + timing_sense : negative_unate; + timing_type : three_state_disable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : three_state_enable; + related_pin : "oe"; + intrinsic_rise : 16.870; + intrinsic_fall : 16.870; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pin_input"; + intrinsic_rise : 16.839; + intrinsic_fall : 16.839; + } + } + pin (fb) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "pad_in"; + intrinsic_rise : 16.918; + intrinsic_fall : 16.918; + } + } + } + cell (iocell6) { pin (in_clock) { direction : input; clock : true; @@ -1066,7 +1222,7 @@ library (timing) { } } } - cell (iocell6) { + cell (iocell7) { pin (in_clock) { direction : input; clock : true; @@ -1134,7 +1290,7 @@ library (timing) { } } } - cell (iocell7) { + cell (iocell8) { pin (in_clock) { direction : input; clock : true; @@ -1202,7 +1358,7 @@ library (timing) { } } } - cell (iocell8) { + cell (iocell9) { pin (in_clock) { direction : input; clock : true; @@ -1270,7 +1426,7 @@ library (timing) { } } } - cell (iocell9) { + cell (iocell10) { pin (in_clock) { direction : input; clock : true; @@ -1338,7 +1494,7 @@ library (timing) { } } } - cell (iocell10) { + cell (iocell11) { pin (in_clock) { direction : input; clock : true; @@ -1406,7 +1562,7 @@ library (timing) { } } } - cell (iocell11) { + cell (iocell12) { pin (in_clock) { direction : input; clock : true; @@ -1474,7 +1630,7 @@ library (timing) { } } } - cell (iocell12) { + cell (iocell13) { pin (in_clock) { direction : input; clock : true; @@ -1694,7 +1850,7 @@ library (timing) { direction : output; } } - cell (macrocell9) { + cell (macrocell10) { pin (cin) { direction : input; } @@ -1792,7 +1948,7 @@ library (timing) { } } } - cell (macrocell10) { + cell (macrocell11) { pin (cin) { direction : input; } @@ -1880,7 +2036,7 @@ library (timing) { } } } - cell (macrocell11) { + cell (macrocell12) { pin (cin) { direction : input; } @@ -1978,7 +2134,7 @@ library (timing) { } } } - cell (macrocell12) { + cell (macrocell13) { pin (cin) { direction : input; } @@ -2076,7 +2232,7 @@ library (timing) { } } } - cell (macrocell13) { + cell (macrocell14) { pin (cin) { direction : input; } @@ -2174,7 +2330,7 @@ library (timing) { } } } - cell (macrocell14) { + cell (macrocell15) { pin (cin) { direction : input; } @@ -2272,7 +2428,7 @@ library (timing) { } } } - cell (macrocell15) { + cell (macrocell16) { pin (cin) { direction : input; } @@ -2370,7 +2526,7 @@ library (timing) { } } } - cell (macrocell16) { + cell (macrocell17) { pin (cin) { direction : input; } @@ -2468,7 +2624,7 @@ library (timing) { } } } - cell (macrocell17) { + cell (macrocell18) { pin (cin) { direction : input; } @@ -2566,7 +2722,7 @@ library (timing) { } } } - cell (macrocell18) { + cell (macrocell19) { pin (cin) { direction : input; } @@ -3159,7 +3315,7 @@ library (timing) { direction : output; } } - cell (macrocell19) { + cell (macrocell20) { pin (cin) { direction : input; } @@ -3257,7 +3413,7 @@ library (timing) { } } } - cell (macrocell20) { + cell (macrocell21) { pin (cin) { direction : input; } @@ -3355,7 +3511,7 @@ library (timing) { } } } - cell (macrocell21) { + cell (macrocell22) { pin (cin) { direction : input; } @@ -3453,7 +3609,7 @@ library (timing) { } } } - cell (macrocell22) { + cell (macrocell23) { pin (cin) { direction : input; } @@ -3541,7 +3697,7 @@ library (timing) { } } } - cell (macrocell23) { + cell (macrocell24) { pin (cin) { direction : input; } @@ -3787,24 +3943,8 @@ library (timing) { } } } - cell (macrocell24) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); + cell (statusicell3) { + pin (clock) { direction : input; clock : true; } @@ -3812,59 +3952,1778 @@ library (timing) { direction : input; timing () { timing_type : setup_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 2.100; intrinsic_fall : 2.100; } timing () { timing_type : hold_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_rise : 0.000; intrinsic_fall : 0.000; } } - bundle (ar) { - members (ar_0); + pin (reset) { direction : input; timing () { timing_type : recovery_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } timing () { timing_type : removal_rising; - related_pin : "clock_0"; + related_pin : "clock"; intrinsic_fall : 0.000; } } - bundle (ap) { - members (ap_0); + pin (status_0) { direction : input; timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; } } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + pin (status_1) { + direction : input; timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 1.570; + intrinsic_fall : 1.570; } - } - pin (q_fixed) { + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 2.000; + intrinsic_fall : 2.000; + } + } + pin (status_2) { + direction : input; + } + pin (status_3) { + direction : input; + } + pin (status_4) { + direction : input; + } + pin (status_5) { + direction : input; + } + pin (status_6) { + direction : input; + } + pin (interrupt) { + direction : output; + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_2"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_3"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_4"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_5"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 2.460; + intrinsic_fall : 2.460; + } + timing () { + timing_sense : positive_unate; + timing_type : combinational; + related_pin : "status_6"; + intrinsic_rise : 3.910; + intrinsic_fall : 3.910; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.030; + intrinsic_fall : 4.030; + } + timing () { + timing_sense : negative_unate; + timing_type : clear; + related_pin : "reset"; + intrinsic_rise : 8.260; + intrinsic_fall : 8.260; + } + } + } + cell (macrocell25) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (controlcell2) { + pin (clock) { + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + pin (reset) { + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock"; + intrinsic_fall : 0.000; + } + } + pin (busclk) { + direction : input; + clock : true; + } + pin (control_0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_2) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_3) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_4) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_5) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_6) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + pin (control_7) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.040; + intrinsic_fall : 2.040; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 2.580; + intrinsic_fall : 2.580; + } + } + } + cell (datapathcell2) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + } + pin (f0_blk_stat_comb) { + direction : output; + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.54; + intrinsic_fall : 3.54; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.90; + intrinsic_fall : 1.90; + } + } + pin (cl0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.14; + intrinsic_fall : 4.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.14; + intrinsic_fall : 2.14; + } + } + pin (z0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.32; + intrinsic_fall : 2.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.74; + intrinsic_fall : 1.74; + } + } + pin (ff0) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.73; + intrinsic_fall : 2.73; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.32; + intrinsic_fall : 1.32; + } + } + pin (ce1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.51; + intrinsic_fall : 3.51; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.03; + intrinsic_fall : 2.03; + } + } + pin (cl1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.90; + intrinsic_fall : 4.90; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.26; + intrinsic_fall : 2.26; + } + } + pin (z1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.29; + intrinsic_fall : 2.29; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.53; + intrinsic_fall : 1.53; + } + } + pin (ff1) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.17; + intrinsic_fall : 2.17; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 1.18; + intrinsic_fall : 1.18; + } + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_0"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : combinational; + related_pin : "cs_addr_1"; + intrinsic_rise : 9.71; + intrinsic_fall : 9.71; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.21; + intrinsic_fall : 3.21; + } + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 4.84; + intrinsic_fall : 4.84; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.63; + intrinsic_fall : 3.63; + } + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + } + } + cell (datapathcell3) { + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 2.10; + intrinsic_fall : 2.10; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (reset) { + direction : input; + } + pin (cs_addr_0) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_1) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 11.52; + intrinsic_fall : 11.52; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.31; + intrinsic_fall : 5.31; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 10.97; + intrinsic_fall : 10.97; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (cs_addr_2) { + direction : input; + } + pin (route_si) { + direction : input; + } + pin (route_ci) { + direction : input; + } + pin (f0_load) { + direction : input; + } + pin (f1_load) { + direction : input; + } + pin (d0_load) { + direction : input; + } + pin (d1_load) { + direction : input; + } + pin (p_in_0) { + direction : input; + } + pin (p_in_1) { + direction : input; + } + pin (p_in_2) { + direction : input; + } + pin (p_in_3) { + direction : input; + } + pin (p_in_4) { + direction : input; + } + pin (p_in_5) { + direction : input; + } + pin (p_in_6) { + direction : input; + } + pin (p_in_7) { + direction : input; + } + pin (ce0i) { + direction : input; + } + pin (cl0i) { + direction : input; + } + pin (z0i) { + direction : input; + } + pin (ff0i) { + direction : input; + } + pin (ce1i) { + direction : input; + } + pin (cl1i) { + direction : input; + } + pin (z1i) { + direction : input; + } + pin (ff1i) { + direction : input; + } + pin (cap0i) { + direction : input; + } + pin (cap1i) { + direction : input; + } + pin (ci) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 5.09; + intrinsic_fall : 5.09; + } + timing () { + timing_type : setup_rising; + related_pin : "clock"; + intrinsic_rise : 4.57; + intrinsic_fall : 4.57; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + timing () { + timing_type : hold_rising; + related_pin : "clock"; + intrinsic_rise : 0.00; + intrinsic_fall : 0.00; + } + } + pin (sir) { + direction : input; + } + pin (cfbi) { + direction : input; + } + pin (sil) { + direction : input; + } + pin (cmsbi) { + direction : input; + } + pin (busclk) { + direction : input; + clock : true; + } + pin (clock) { + direction : input; + clock : true; + } + pin (ce0_reg) { + direction : output; + } + pin (cl0_reg) { + direction : output; + } + pin (z0_reg) { + direction : output; + } + pin (f0_reg) { + direction : output; + } + pin (ce1_reg) { + direction : output; + } + pin (cl1_reg) { + direction : output; + } + pin (z1_reg) { + direction : output; + } + pin (f1_reg) { + direction : output; + } + pin (ov_msb_reg) { + direction : output; + } + pin (co_msb_reg) { + direction : output; + } + pin (cmsb_reg) { + direction : output; + } + pin (so_reg) { + direction : output; + } + pin (f0_bus_stat_reg) { + direction : output; + } + pin (f0_blk_stat_reg) { + direction : output; + } + pin (f1_bus_stat_reg) { + direction : output; + } + pin (f1_blk_stat_reg) { + direction : output; + } + pin (ce0_comb) { + direction : output; + } + pin (cl0_comb) { + direction : output; + } + pin (z0_comb) { + direction : output; + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.96; + intrinsic_fall : 2.96; + } + timing () { + timing_type : combinational; + related_pin : "z0i"; + intrinsic_rise : 2.74; + intrinsic_fall : 2.74; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.85; + intrinsic_fall : 3.85; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.27; + intrinsic_fall : 3.27; + } + } + pin (f0_comb) { + direction : output; + } + pin (ce1_comb) { + direction : output; + } + pin (cl1_comb) { + direction : output; + } + pin (z1_comb) { + direction : output; + } + pin (f1_comb) { + direction : output; + } + pin (ov_msb_comb) { + direction : output; + } + pin (co_msb_comb) { + direction : output; + } + pin (cmsb_comb) { + direction : output; + } + pin (so_comb) { + direction : output; + } + pin (f0_bus_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.21; + intrinsic_fall : 7.21; + } + } + pin (f0_blk_stat_comb) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + timing () { + timing_type : rising_edge; + related_pin : "busclk"; + intrinsic_rise : 7.34; + intrinsic_fall : 7.34; + } + } + pin (f1_bus_stat_comb) { + direction : output; + } + pin (f1_blk_stat_comb) { + direction : output; + } + pin (p_out_0) { + direction : output; + } + pin (p_out_1) { + direction : output; + } + pin (p_out_2) { + direction : output; + } + pin (p_out_3) { + direction : output; + } + pin (p_out_4) { + direction : output; + } + pin (p_out_5) { + direction : output; + } + pin (p_out_6) { + direction : output; + } + pin (p_out_7) { + direction : output; + } + pin (ce0) { + direction : output; + } + pin (cl0) { + direction : output; + } + pin (z0) { + direction : output; + } + pin (ff0) { + direction : output; + } + pin (ce1) { + direction : output; + } + pin (cl1) { + direction : output; + } + pin (z1) { + direction : output; + } + pin (ff1) { + direction : output; + } + pin (cap0) { + direction : output; + } + pin (cap1) { + direction : output; + } + pin (co_msb) { + direction : output; + } + pin (sol_msb) { + direction : output; + } + pin (cfbo) { + direction : output; + } + pin (sor) { + direction : output; + } + pin (cmsbo) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 3.32; + intrinsic_fall : 3.32; + } + timing () { + timing_type : rising_edge; + related_pin : "clock"; + intrinsic_rise : 2.25; + intrinsic_fall : 2.25; + } + } + } + cell (macrocell26) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { + direction : output; + function : "((main_0 * main_1)) ^ 0"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + } + cell (macrocell27) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell28) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 3.510; + intrinsic_fall : 3.510; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + pin (q_fixed) { + direction : output; + timing () { + timing_type : rising_edge; + related_pin : "clock_0"; + intrinsic_rise : 1.250; + intrinsic_fall : 1.250; + } + } + } + cell (macrocell29) { + pin (cin) { + direction : input; + } + bundle (cpt0) { + members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); + direction : input; + } + bundle (cpt1) { + members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); + direction : input; + } + bundle (main) { + members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); + direction : input; + } + bundle (clock) { + members (clock_0); + direction : input; + clock : true; + } + pin (clk_en) { + direction : input; + timing () { + timing_type : setup_rising; + related_pin : "clock_0"; + intrinsic_rise : 2.100; + intrinsic_fall : 2.100; + } + timing () { + timing_type : hold_rising; + related_pin : "clock_0"; + intrinsic_rise : 0.000; + intrinsic_fall : 0.000; + } + } + bundle (ar) { + members (ar_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + bundle (ap) { + members (ap_0); + direction : input; + timing () { + timing_type : recovery_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + timing () { + timing_type : removal_rising; + related_pin : "clock_0"; + intrinsic_fall : 0.000; + } + } + pin (cout) { + direction : output; + } + pin (q) { + direction : output; + function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; + timing () { + timing_type : combinational; + related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; + intrinsic_rise : 3.350; + intrinsic_fall : 3.350; + } + } + pin (q_fixed) { direction : output; function : "((!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)) ^ 1"; timing () { @@ -3875,7 +5734,7 @@ library (timing) { } } } - cell (datapathcell2) { + cell (datapathcell4) { pin (clk_en) { direction : input; } @@ -4260,7 +6119,7 @@ library (timing) { direction : output; } } - cell (statusicell3) { + cell (statusicell4) { pin (clock) { direction : input; clock : true; @@ -4427,7 +6286,7 @@ library (timing) { } } } - cell (datapathcell3) { + cell (datapathcell5) { pin (clk_en) { direction : input; } @@ -4752,7 +6611,7 @@ library (timing) { direction : output; } } - cell (macrocell25) { + cell (macrocell30) { pin (cin) { direction : input; } @@ -4850,7 +6709,7 @@ library (timing) { } } } - cell (macrocell26) { + cell (macrocell31) { pin (cin) { direction : input; } @@ -4938,7 +6797,7 @@ library (timing) { } } } - cell (macrocell27) { + cell (macrocell32) { pin (cin) { direction : input; } @@ -5036,7 +6895,7 @@ library (timing) { } } } - cell (macrocell28) { + cell (macrocell33) { pin (cin) { direction : input; } @@ -5134,7 +6993,7 @@ library (timing) { } } } - cell (macrocell29) { + cell (macrocell34) { pin (cin) { direction : input; } @@ -5232,7 +7091,7 @@ library (timing) { } } } - cell (macrocell30) { + cell (macrocell35) { pin (cin) { direction : input; } @@ -5320,7 +7179,7 @@ library (timing) { } } } - cell (macrocell31) { + cell (macrocell36) { pin (cin) { direction : input; } @@ -5408,7 +7267,7 @@ library (timing) { } } } - cell (macrocell32) { + cell (macrocell37) { pin (cin) { direction : input; } @@ -5506,7 +7365,7 @@ library (timing) { } } } - cell (iocell13) { + cell (iocell14) { pin (in_clock) { direction : input; clock : true; @@ -5574,7 +7433,7 @@ library (timing) { } } } - cell (iocell14) { + cell (iocell15) { pin (in_clock) { direction : input; clock : true; @@ -5642,7 +7501,7 @@ library (timing) { } } } - cell (iocell15) { + cell (iocell16) { pin (in_clock) { direction : input; clock : true; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.vh2 index 7d15c1a..e4a36b1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.vh2 +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_t.vh2 @@ -1,5 +1,5 @@ --- Project: C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj --- Generated: 03/22/2013 10:33:30 +-- Project: C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj +-- Generated: 07/25/2013 16:49:01 -- ENTITY PSOC5_SPI_LSM303D IS @@ -8,6 +8,7 @@ ENTITY PSOC5_SPI_LSM303D IS Pin_2(0)_PAD : OUT std_ulogic; Pin_3(0)_PAD : OUT std_ulogic; Pin_4(0)_PAD : OUT std_ulogic; + Pin_5(0)_PAD : OUT std_ulogic; Tx_1(0)_PAD : OUT std_ulogic; \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; @@ -31,6 +32,7 @@ END PSOC5_SPI_LSM303D; ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL ClockBlock_100k : bit; SIGNAL ClockBlock_1k : bit; + SIGNAL ClockBlock_1k__SYNC_OUT : bit; SIGNAL ClockBlock_32k : bit; SIGNAL ClockBlock_BUS_CLK : bit; ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; @@ -46,25 +48,28 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL Net_191_local : bit; SIGNAL Net_20 : bit; SIGNAL Net_234 : bit; - ATTRIBUTE placement_force OF Net_234 : SIGNAL IS "U(3,4,A)1"; + ATTRIBUTE placement_force OF Net_234 : SIGNAL IS "U(3,4,A)2"; SIGNAL Net_30 : bit; - ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(3,3,A)2"; + ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(3,5,A)2"; SIGNAL Net_419 : bit; - ATTRIBUTE placement_force OF Net_419 : SIGNAL IS "U(3,3,A)3"; + ATTRIBUTE placement_force OF Net_419 : SIGNAL IS "U(3,5,A)3"; SIGNAL Net_422 : bit; - ATTRIBUTE placement_force OF Net_422 : SIGNAL IS "U(3,3,B)0"; + ATTRIBUTE placement_force OF Net_422 : SIGNAL IS "U(3,5,B)0"; SIGNAL Net_425 : bit; - ATTRIBUTE placement_force OF Net_425 : SIGNAL IS "U(3,3,B)1"; + ATTRIBUTE placement_force OF Net_425 : SIGNAL IS "U(3,5,B)1"; SIGNAL Net_428 : bit; - ATTRIBUTE placement_force OF Net_428 : SIGNAL IS "U(3,3,B)2"; + ATTRIBUTE placement_force OF Net_428 : SIGNAL IS "U(3,5,B)2"; SIGNAL Net_439 : bit; - ATTRIBUTE placement_force OF Net_439 : SIGNAL IS "U(3,3,A)0"; + ATTRIBUTE placement_force OF Net_439 : SIGNAL IS "U(3,5,A)1"; SIGNAL Net_479 : bit; - ATTRIBUTE placement_force OF Net_479 : SIGNAL IS "U(2,3,B)1"; + ATTRIBUTE placement_force OF Net_479 : SIGNAL IS "U(3,5,A)0"; + SIGNAL Net_585 : bit; + ATTRIBUTE placement_force OF Net_585 : SIGNAL IS "U(3,5,B)3"; SIGNAL Pin_1(0)__PA : bit; SIGNAL Pin_2(0)__PA : bit; SIGNAL Pin_3(0)__PA : bit; SIGNAL Pin_4(0)__PA : bit; + SIGNAL Pin_5(0)__PA : bit; SIGNAL Tx_1(0)__PA : bit; SIGNAL \\\LCD:LCDPort(0)\\__PA\ : bit; SIGNAL \\\LCD:LCDPort(1)\\__PA\ : bit; @@ -74,7 +79,7 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \\\LCD:LCDPort(5)\\__PA\ : bit; SIGNAL \\\LCD:LCDPort(6)\\__PA\ : bit; SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(2,3,A)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(2,5,A)0"; SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; SIGNAL \SPIM:BSPIM:count_0\ : bit; SIGNAL \SPIM:BSPIM:count_1\ : bit; @@ -84,30 +89,30 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \SPIM:BSPIM:count_5\ : bit; SIGNAL \SPIM:BSPIM:count_6\ : bit; SIGNAL \SPIM:BSPIM:dpcounter_one\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:dpcounter_one\ : SIGNAL IS "U(2,3,B)3"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:dpcounter_one\ : SIGNAL IS "U(2,5,B)3"; SIGNAL \SPIM:BSPIM:is_spi_done\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:is_spi_done\ : SIGNAL IS "U(2,4,B)0"; SIGNAL \SPIM:BSPIM:ld_ident\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:ld_ident\ : SIGNAL IS "U(3,3,A)1"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:ld_ident\ : SIGNAL IS "U(2,5,B)1"; SIGNAL \SPIM:BSPIM:load_cond\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(2,3,B)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(2,5,B)0"; SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(2,3,B)2"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(2,5,B)2"; SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; SIGNAL \SPIM:BSPIM:mosi_from_dp_reg\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_from_dp_reg\ : SIGNAL IS "U(3,4,A)0"; SIGNAL \SPIM:BSPIM:mosi_hs_reg\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_hs_reg\ : SIGNAL IS "U(3,5,B)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_hs_reg\ : SIGNAL IS "U(3,3,B)0"; SIGNAL \SPIM:BSPIM:mosi_pre_reg\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:mosi_pre_reg\ : SIGNAL IS "U(2,4,A)0"; SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(2,5,A)0"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(2,3,A)0"; SIGNAL \SPIM:BSPIM:state_0\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:state_0\ : SIGNAL IS "U(2,4,B)3"; SIGNAL \SPIM:BSPIM:state_1\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(2,3,A)1"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(2,5,A)1"; SIGNAL \SPIM:BSPIM:state_2\ : bit; ATTRIBUTE placement_force OF \SPIM:BSPIM:state_2\ : SIGNAL IS "U(2,4,B)1"; SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; @@ -115,39 +120,57 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(2,3,A)2"; + ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(2,5,A)2"; SIGNAL \SPIM:Net_276\ : bit; ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL \SS:control_2\ : bit; SIGNAL \SS:control_3\ : bit; SIGNAL \SS:control_4\ : bit; SIGNAL \SS:control_5\ : bit; SIGNAL \SS:control_6\ : bit; SIGNAL \SS:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:control_0\ : bit; + SIGNAL \Timer_1:TimerUDB:control_1\ : bit; + SIGNAL \Timer_1:TimerUDB:control_2\ : bit; + SIGNAL \Timer_1:TimerUDB:control_3\ : bit; + SIGNAL \Timer_1:TimerUDB:control_4\ : bit; + SIGNAL \Timer_1:TimerUDB:control_5\ : bit; + SIGNAL \Timer_1:TimerUDB:control_6\ : bit; + SIGNAL \Timer_1:TimerUDB:control_7\ : bit; + SIGNAL \Timer_1:TimerUDB:per_zero\ : bit; + SIGNAL \Timer_1:TimerUDB:run_mode\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:run_mode\ : SIGNAL IS "U(2,0,A)3"; + SIGNAL \Timer_1:TimerUDB:status_2\ : bit; + SIGNAL \Timer_1:TimerUDB:status_3\ : bit; + SIGNAL \Timer_1:TimerUDB:status_tc\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:status_tc\ : SIGNAL IS "U(2,0,A)2"; + SIGNAL \Timer_1:TimerUDB:timer_enable\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:timer_enable\ : SIGNAL IS "U(2,0,A)0"; + SIGNAL \Timer_1:TimerUDB:trig_disable\ : bit; + ATTRIBUTE placement_force OF \Timer_1:TimerUDB:trig_disable\ : SIGNAL IS "U(2,0,A)1"; SIGNAL \UART_1:BUART:counter_load_not\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:counter_load_not\ : SIGNAL IS "U(3,5,B)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:counter_load_not\ : SIGNAL IS "U(3,3,B)1"; SIGNAL \UART_1:BUART:tx_bitclk\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk\ : SIGNAL IS "U(2,5,B)0"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk\ : SIGNAL IS "U(2,3,B)0"; SIGNAL \UART_1:BUART:tx_bitclk_dp\ : bit; SIGNAL \UART_1:BUART:tx_bitclk_enable_pre\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk_enable_pre\ : SIGNAL IS "U(2,5,B)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_bitclk_enable_pre\ : SIGNAL IS "U(2,3,B)1"; SIGNAL \UART_1:BUART:tx_counter_dp\ : bit; SIGNAL \UART_1:BUART:tx_fifo_empty\ : bit; SIGNAL \UART_1:BUART:tx_fifo_notfull\ : bit; SIGNAL \UART_1:BUART:tx_shift_out\ : bit; SIGNAL \UART_1:BUART:tx_state_0\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_0\ : SIGNAL IS "U(2,5,A)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_0\ : SIGNAL IS "U(2,3,A)1"; SIGNAL \UART_1:BUART:tx_state_1\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_1\ : SIGNAL IS "U(2,5,A)2"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_1\ : SIGNAL IS "U(3,0,B)0"; SIGNAL \UART_1:BUART:tx_state_2\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_2\ : SIGNAL IS "U(3,5,A)1"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_state_2\ : SIGNAL IS "U(3,3,A)1"; SIGNAL \UART_1:BUART:tx_status_0\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_0\ : SIGNAL IS "U(2,5,A)3"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_0\ : SIGNAL IS "U(2,3,A)3"; SIGNAL \UART_1:BUART:tx_status_2\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_2\ : SIGNAL IS "U(3,4,A)2"; + ATTRIBUTE placement_force OF \UART_1:BUART:tx_status_2\ : SIGNAL IS "U(2,3,B)3"; SIGNAL \UART_1:BUART:txn\ : bit; - ATTRIBUTE placement_force OF \UART_1:BUART:txn\ : SIGNAL IS "U(3,5,A)0"; + ATTRIBUTE placement_force OF \UART_1:BUART:txn\ : SIGNAL IS "U(3,3,A)0"; SIGNAL __ONE__ : bit; ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; SIGNAL __ZERO__ : bit; @@ -157,27 +180,44 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS SIGNAL m_sclk_pin(0)__PA : bit; SIGNAL mywire_1_0 : bit; SIGNAL mywire_1_1 : bit; + SIGNAL mywire_1_2 : bit; SIGNAL tmpOE__m_miso_pin_net_0 : bit; ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; SIGNAL zero : bit; ATTRIBUTE GROUND OF zero : SIGNAL IS true; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\ : bit; + SIGNAL \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\ : bit; ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; + ATTRIBUTE Location OF ClockBlock_1k__SYNC : LABEL IS "U(3,0)"; ATTRIBUTE lib_model OF Net_234 : LABEL IS "macrocell1"; ATTRIBUTE Location OF Net_234 : LABEL IS "U(3,4)"; ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; - ATTRIBUTE Location OF Net_30 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_30 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_419 : LABEL IS "macrocell3"; - ATTRIBUTE Location OF Net_419 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_419 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_422 : LABEL IS "macrocell4"; - ATTRIBUTE Location OF Net_422 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_422 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_425 : LABEL IS "macrocell5"; - ATTRIBUTE Location OF Net_425 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_425 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_428 : LABEL IS "macrocell6"; - ATTRIBUTE Location OF Net_428 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_428 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_439 : LABEL IS "macrocell7"; - ATTRIBUTE Location OF Net_439 : LABEL IS "U(3,3)"; + ATTRIBUTE Location OF Net_439 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Net_479 : LABEL IS "macrocell8"; - ATTRIBUTE Location OF Net_479 : LABEL IS "U(2,3)"; + ATTRIBUTE Location OF Net_479 : LABEL IS "U(3,5)"; + ATTRIBUTE lib_model OF Net_585 : LABEL IS "macrocell9"; + ATTRIBUTE Location OF Net_585 : LABEL IS "U(3,5)"; ATTRIBUTE lib_model OF Pin_1(0) : LABEL IS "iocell1"; ATTRIBUTE Location OF Pin_1(0) : LABEL IS "P3[0]"; ATTRIBUTE lib_model OF Pin_2(0) : LABEL IS "iocell2"; @@ -186,90 +226,108 @@ ARCHITECTURE __DEFAULT__ OF PSOC5_SPI_LSM303D IS ATTRIBUTE Location OF Pin_3(0) : LABEL IS "P3[2]"; ATTRIBUTE lib_model OF Pin_4(0) : LABEL IS "iocell4"; ATTRIBUTE Location OF Pin_4(0) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell5"; + ATTRIBUTE lib_model OF Pin_5(0) : LABEL IS "iocell5"; + ATTRIBUTE Location OF Pin_5(0) : LABEL IS "P3[4]"; + ATTRIBUTE lib_model OF Tx_1(0) : LABEL IS "iocell6"; ATTRIBUTE Location OF Tx_1(0) : LABEL IS "P3[7]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell6"; + ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell7"; ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell7"; + ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell8"; ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell8"; + ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell9"; ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell9"; + ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell10"; ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell10"; + ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell11"; ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell11"; + ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell12"; ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell12"; + ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell13"; ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; ATTRIBUTE Location OF \SPIM:BSPIM:BitCounter\ : LABEL IS "U(2,4)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(2,5)"; + ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(3,4)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell9"; - ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell10"; - ATTRIBUTE Location OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell11"; + ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell10"; + ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "macrocell11"; + ATTRIBUTE Location OF \SPIM:BSPIM:dpcounter_one\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "macrocell12"; ATTRIBUTE Location OF \SPIM:BSPIM:is_spi_done\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell12"; - ATTRIBUTE Location OF \SPIM:BSPIM:ld_ident\ : LABEL IS "U(3,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell13"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell14"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell15"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:ld_ident\ : LABEL IS "macrocell13"; + ATTRIBUTE Location OF \SPIM:BSPIM:ld_ident\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell14"; + ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell15"; + ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "macrocell16"; ATTRIBUTE Location OF \SPIM:BSPIM:mosi_from_dp_reg\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell16"; - ATTRIBUTE Location OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell17"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "macrocell17"; + ATTRIBUTE Location OF \SPIM:BSPIM:mosi_hs_reg\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "macrocell18"; ATTRIBUTE Location OF \SPIM:BSPIM:mosi_pre_reg\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell18"; - ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell19"; + ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(2,3)"; ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; ATTRIBUTE Location OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell19"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell20"; ATTRIBUTE Location OF \SPIM:BSPIM:state_0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell20"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(2,3)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell21"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell21"; + ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(2,5)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell22"; ATTRIBUTE Location OF \SPIM:BSPIM:state_2\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell22"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell23"; ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "U(2,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell23"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell24"; + ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(2,5)"; ATTRIBUTE lib_model OF \SS:Async:ctrl_reg\ : LABEL IS "controlcell1"; - ATTRIBUTE Location OF \SS:Async:ctrl_reg\ : LABEL IS "U(3,3)"; - ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell24"; - ATTRIBUTE Location OF \UART_1:BUART:counter_load_not\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell2"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell3"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell3"; - ATTRIBUTE Location OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell25"; - ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell26"; - ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell27"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_0\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell28"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_1\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell29"; - ATTRIBUTE Location OF \UART_1:BUART:tx_state_2\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell30"; - ATTRIBUTE Location OF \UART_1:BUART:tx_status_0\ : LABEL IS "U(2,5)"; - ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell31"; - ATTRIBUTE Location OF \UART_1:BUART:tx_status_2\ : LABEL IS "U(3,4)"; - ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell32"; - ATTRIBUTE Location OF \UART_1:BUART:txn\ : LABEL IS "U(3,5)"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell13"; + ATTRIBUTE Location OF \SS:Async:ctrl_reg\ : LABEL IS "U(3,5)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:nrstSts:stsreg\ : LABEL IS "statusicell3"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:nrstSts:stsreg\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:run_mode\ : LABEL IS "macrocell25"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:run_mode\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ : LABEL IS "controlcell2"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u0\ : LABEL IS "datapathcell2"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:sT16:timerdp:u1\ : LABEL IS "datapathcell3"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:sT16:timerdp:u1\ : LABEL IS "U(3,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:status_tc\ : LABEL IS "macrocell26"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:status_tc\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:timer_enable\ : LABEL IS "macrocell27"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:timer_enable\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \Timer_1:TimerUDB:trig_disable\ : LABEL IS "macrocell28"; + ATTRIBUTE Location OF \Timer_1:TimerUDB:trig_disable\ : LABEL IS "U(2,0)"; + ATTRIBUTE lib_model OF \UART_1:BUART:counter_load_not\ : LABEL IS "macrocell29"; + ATTRIBUTE Location OF \UART_1:BUART:counter_load_not\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "datapathcell4"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:TxShifter:u0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "statusicell4"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:TxSts\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "datapathcell5"; + ATTRIBUTE Location OF \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk\ : LABEL IS "macrocell30"; + ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "macrocell31"; + ATTRIBUTE Location OF \UART_1:BUART:tx_bitclk_enable_pre\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_0\ : LABEL IS "macrocell32"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_1\ : LABEL IS "macrocell33"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_1\ : LABEL IS "U(3,0)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_state_2\ : LABEL IS "macrocell34"; + ATTRIBUTE Location OF \UART_1:BUART:tx_state_2\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_0\ : LABEL IS "macrocell35"; + ATTRIBUTE Location OF \UART_1:BUART:tx_status_0\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:tx_status_2\ : LABEL IS "macrocell36"; + ATTRIBUTE Location OF \UART_1:BUART:tx_status_2\ : LABEL IS "U(2,3)"; + ATTRIBUTE lib_model OF \UART_1:BUART:txn\ : LABEL IS "macrocell37"; + ATTRIBUTE Location OF \UART_1:BUART:txn\ : LABEL IS "U(3,3)"; + ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell14"; ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell14"; + ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell15"; ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell15"; + ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell16"; ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; COMPONENT abufcell END COMPONENT; @@ -1189,6 +1247,13 @@ BEGIN dclk_glb_1 => Net_191, dclk_1 => Net_191_local); + ClockBlock_1k__SYNC:synccell + PORT MAP( + in => ClockBlock_1k, + out => ClockBlock_1k__SYNC_OUT, + clock => ClockBlock_BUS_CLK, + clk_en => open); + Net_234:macrocell GENERIC MAP( eqn_main => "(!main_0)") @@ -1206,39 +1271,43 @@ BEGIN Net_419:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3)") PORT MAP( q => Net_419, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_422:macrocell GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * !main_2 * main_3)") PORT MAP( q => Net_422, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_425:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * main_3)") PORT MAP( q => Net_425, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_428:macrocell GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)") + eqn_main => "(!main_0 * !main_1 * main_2 * !main_3)") PORT MAP( q => Net_428, main_0 => Net_439, - main_1 => mywire_1_1, - main_2 => mywire_1_0); + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); Net_439:macrocell GENERIC MAP( @@ -1262,6 +1331,16 @@ BEGIN main_2 => \SPIM:BSPIM:state_1\, main_3 => \SPIM:BSPIM:state_0\); + Net_585:macrocell + GENERIC MAP( + eqn_main => "(!main_0 * main_1 * !main_2 * !main_3)") + PORT MAP( + q => Net_585, + main_0 => Net_439, + main_1 => mywire_1_2, + main_2 => mywire_1_1, + main_3 => mywire_1_0); + Pin_1:logicalport GENERIC MAP( drive_mode => "010", @@ -1610,6 +1689,93 @@ BEGIN out_clock_en => '1', out_reset => '0'); + Pin_5:logicalport + GENERIC MAP( + drive_mode => "010", + ibuf_enabled => "1", + id => "f04dd9ba-954e-4352-a3f2-4deb8634d958", + init_dr_st => "1", + input_clk_en => 0, + input_sync => "1", + input_sync_mode => "0", + intr_mode => "00", + invert_in_clock => 0, + invert_in_clock_en => 0, + invert_in_reset => 0, + invert_out_clock => 0, + invert_out_clock_en => 0, + invert_out_reset => 0, + io_voltage => "", + layout_mode => "CONTIGUOUS", + oe_conn => "0", + oe_reset => 0, + oe_sync => "0", + output_clk_en => 0, + output_clock_mode => "0", + output_conn => "1", + output_mode => "0", + output_reset => 0, + output_sync => "0", + pa_in_clock => -1, + pa_in_clock_en => -1, + pa_in_reset => -1, + pa_out_clock => -1, + pa_out_clock_en => -1, + pa_out_reset => -1, + pin_aliases => "", + pin_mode => "O", + por_state => 4, + port_alias_group => "", + port_alias_required => 0, + sio_group_cnt => 0, + sio_hifreq => "", + sio_hyst => "0", + sio_ibuf => "00000000", + sio_info => "00", + sio_obuf => "00000000", + sio_refsel => "00000000", + sio_vtrip => "00000000", + slew_rate => "0", + spanning => 0, + sw_only => 0, + use_annotation => "0", + vtrip => "10", + width => 1, + in_clk_inv => 0, + in_clken_inv => 0, + in_clken_mode => 1, + in_rst_inv => 0, + out_clk_inv => 0, + out_clken_inv => 0, + out_clken_mode => 1, + out_rst_inv => 0) + PORT MAP( + in_clock_en => open, + in_reset => open, + out_clock_en => open, + out_reset => open); + + Pin_5(0):iocell + GENERIC MAP( + in_sync_mode => 0, + out_sync_mode => 0, + oe_sync_mode => 0, + logicalport => "Pin_5", + logicalport_pin_id => 0, + io_capabilities => "0000000000000000000000100000000000000000000000000000000000000001") + PORT MAP( + pa_out => Pin_5(0)__PA, + oe => open, + pin_input => Net_585, + pad_out => Pin_5(0)_PAD, + pad_in => Pin_5(0)_PAD, + in_clock => open, + in_clock_en => '1', + in_reset => '0', + out_clock => open, + out_clock_en => '1', + out_reset => '0'); + Tx_1:logicalport GENERIC MAP( drive_mode => "110", @@ -2196,11 +2362,180 @@ BEGIN control_5 => \SS:control_5\, control_4 => \SS:control_4\, control_3 => \SS:control_3\, - control_2 => \SS:control_2\, + control_2 => mywire_1_2, control_1 => mywire_1_1, control_0 => mywire_1_0, busclk => ClockBlock_BUS_CLK); + \Timer_1:TimerUDB:nrstSts:stsreg\:statusicell + GENERIC MAP( + cy_force_order => 1, + cy_int_mask => "1111111", + cy_md_select => "0000011") + PORT MAP( + clock => ClockBlock_BUS_CLK, + status_6 => open, + status_5 => open, + status_4 => open, + status_3 => \Timer_1:TimerUDB:status_3\, + status_2 => \Timer_1:TimerUDB:status_2\, + status_1 => open, + status_0 => \Timer_1:TimerUDB:status_tc\, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:run_mode\:macrocell + GENERIC MAP( + eqn_main => "(main_0)") + PORT MAP( + q => \Timer_1:TimerUDB:run_mode\, + main_0 => \Timer_1:TimerUDB:control_7\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT); + + \Timer_1:TimerUDB:sCTRLReg:AsyncCtl:ctrlreg\:controlcell + GENERIC MAP( + cy_ctrl_mode_0 => "00000000", + cy_ctrl_mode_1 => "00000000", + cy_ext_reset => 0, + cy_force_order => 1, + cy_init_value => "00000000") + PORT MAP( + control_7 => \Timer_1:TimerUDB:control_7\, + control_6 => \Timer_1:TimerUDB:control_6\, + control_5 => \Timer_1:TimerUDB:control_5\, + control_4 => \Timer_1:TimerUDB:control_4\, + control_3 => \Timer_1:TimerUDB:control_3\, + control_2 => \Timer_1:TimerUDB:control_2\, + control_1 => \Timer_1:TimerUDB:control_1\, + control_0 => \Timer_1:TimerUDB:control_0\, + busclk => ClockBlock_BUS_CLK); + + \Timer_1:TimerUDB:sT16:timerdp:u0\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111000000000000000000000001000000000000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + clk_en => ClockBlock_1k__SYNC_OUT, + busclk => ClockBlock_BUS_CLK, + ce0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0 => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1 => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1 => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1 => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + co_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sol_msb => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbo => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sil => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbi => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:sT16:timerdp:u1\:datapathcell + GENERIC MAP( + a0_init => "00000000", + a1_init => "00000000", + ce0_sync => 1, + ce1_sync => 1, + cl0_sync => 1, + cl1_sync => 1, + cmsb_sync => 1, + co_msb_sync => 1, + cy_dpconfig => "0000000001000000000000000100000001000000010000000000000010000000000000001000000000000000100000000000000010000000000000001000000011111111000000001111111111111111100000110000000000000001000000110000000000011000", + d0_init => "00000000", + d1_init => "00000000", + f0_blk_sync => 1, + f0_bus_sync => 1, + f1_blk_sync => 1, + f1_bus_sync => 1, + ff0_sync => 1, + ff1_sync => 1, + ov_msb_sync => 1, + so_sync => 1, + z0_sync => 1, + z1_sync => 1, + uses_p_in => '0', + uses_p_out => '0') + PORT MAP( + clock => ClockBlock_BUS_CLK, + cs_addr_1 => \Timer_1:TimerUDB:timer_enable\, + cs_addr_0 => \Timer_1:TimerUDB:per_zero\, + z0_comb => \Timer_1:TimerUDB:per_zero\, + f0_bus_stat_comb => \Timer_1:TimerUDB:status_3\, + f0_blk_stat_comb => \Timer_1:TimerUDB:status_2\, + busclk => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + ce0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce0__sig\, + cl0i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl0__sig\, + z0i => \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\, + ff0i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff0__sig\, + ce1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ce1__sig\, + cl1i => \Timer_1:TimerUDB:sT16:timerdp:u0.cl1__sig\, + z1i => \Timer_1:TimerUDB:sT16:timerdp:u0.z1__sig\, + ff1i => \Timer_1:TimerUDB:sT16:timerdp:u0.ff1__sig\, + ci => \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\, + sir => \Timer_1:TimerUDB:sT16:timerdp:u0.sol_msb__sig\, + cfbi => \Timer_1:TimerUDB:sT16:timerdp:u0.cfbo__sig\, + sor => \Timer_1:TimerUDB:sT16:timerdp:u1.sor__sig\, + cmsbo => \Timer_1:TimerUDB:sT16:timerdp:u1.cmsbo__sig\); + + \Timer_1:TimerUDB:status_tc\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1)") + PORT MAP( + q => \Timer_1:TimerUDB:status_tc\, + main_0 => \Timer_1:TimerUDB:run_mode\, + main_1 => \Timer_1:TimerUDB:per_zero\); + + \Timer_1:TimerUDB:timer_enable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * !main_1 * !main_4) + (main_0 * !main_2 * !main_4) + (main_0 * !main_3 * !main_4)") + PORT MAP( + q => \Timer_1:TimerUDB:timer_enable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:control_7\, + main_1 => \Timer_1:TimerUDB:timer_enable\, + main_2 => \Timer_1:TimerUDB:run_mode\, + main_3 => \Timer_1:TimerUDB:per_zero\, + main_4 => \Timer_1:TimerUDB:trig_disable\); + + \Timer_1:TimerUDB:trig_disable\:macrocell + GENERIC MAP( + eqn_main => "(main_0 * main_1 * main_2 * !main_3)") + PORT MAP( + q => \Timer_1:TimerUDB:trig_disable\, + clock_0 => ClockBlock_BUS_CLK, + clk_en => ClockBlock_1k__SYNC_OUT, + main_0 => \Timer_1:TimerUDB:timer_enable\, + main_1 => \Timer_1:TimerUDB:run_mode\, + main_2 => \Timer_1:TimerUDB:per_zero\, + main_3 => \Timer_1:TimerUDB:trig_disable\); + \UART_1:BUART:counter_load_not\:macrocell GENERIC MAP( eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_1 * main_3)") diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_timing.html b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_timing.html index 6ba435b..9f1c194 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_timing.html +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_timing.html @@ -539,7 +539,7 @@

Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

Path Delay Requirement : 500ns(2 MHz)
+
Path Delay Requirement : 41.6667ns(24 MHz)
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell7U(3,5)1Net_439Net_439/clock_0Net_439/q1.250
Route1Net_439Net_439/qNet_422/main_02.596
macrocell4U(3,5)1Net_422Net_422/main_0Net_422/q3.350
Route1Net_422Net_422/qPin_2(0)/pin_input5.506
iocell2P3[1]1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068
Route1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PAD 0.000
Net_439/q Pin_4(0)_PAD29.91529.632
@@ -4488,7 +6105,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell5U(3,3)U(3,5) 1 Net_425 Net_425/main_0 Net_425 Net_425/q Pin_4(0)/pin_input6.6136.330
iocell4
Net_479/q m_sclk_pin(0)_PAD27.67526.767
@@ -4575,7 +6192,7 @@

Static Timing Analysis

macrocell8U(2,3)U(3,5) 1 Net_479 Net_479/clock_0 Net_479 Net_479/q m_sclk_pin(0)/pin_input8.4437.535
iocell15iocell16 P0[6] 1 m_sclk_pin(0)
Project : PSOC5_SPI_LSM303D
Build Time : 03/22/13 10:33:30
07/25/13 16:49:01
Device : CY8C5568AXI-060
Temperature :CyMASTER_CLK 2.000 MHz 2.000 MHz61.376 MHz52.394 MHz
CyMASTER_CLK 923.077 kHz 923.077 kHz43.850 MHz42.472 MHz
CyMASTER_CLK 24.000 MHz 24.000 MHz N/A 43.373 MHz
CyPLL_OUT
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_043.850 MHz22.8051060.52842.472 MHz23.5451059.788
macrocell27U(2,5)macrocell33U(3,0) 1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q 1.250
Route 1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:counter_load_not\/main_14.383\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:counter_load_not\/main_05.133
macrocell24U(3,5)macrocell29U(3,3) 1 \UART_1:BUART:counter_load_not\\UART_1:BUART:counter_load_not\/main_1\UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_02.3022.292
datapathcell3U(2,5)datapathcell5U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_045.027 MHz22.2091061.12444.039 MHz22.7071060.626
macrocell28U(2,5)macrocell32U(2,3) 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q 1.250
Route 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:counter_load_not\/main_03.787\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:counter_load_not\/main_14.295
macrocell24U(3,5)macrocell29U(3,3) 1 \UART_1:BUART:counter_load_not\\UART_1:BUART:counter_load_not\/main_0\UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_02.3022.292
datapathcell3U(2,5)datapathcell5U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_046.471 MHz21.5191061.81446.484 MHz21.5131061.820
macrocell25U(2,5)macrocell30U(2,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_33.0973.101
macrocell24U(3,5)macrocell29U(3,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_02.3022.292
datapathcell3U(2,5)datapathcell5U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_046.544 MHz21.4851061.84846.572 MHz21.4721061.861
macrocell29U(3,5)macrocell34U(3,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_23.0633.060
macrocell24U(3,5)macrocell29U(3,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2\UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_02.3022.292
datapathcell3U(2,5)datapathcell5U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_050.176 MHz19.9301063.40350.181 MHz19.9281063.405
datapathcell3U(2,5)datapathcell5U(3,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock\UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_02.2902.301
macrocell26U(2,5)macrocell31U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0\UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_02.3202.307
datapathcell2U(3,5)datapathcell4U(2,3) 1 \UART_1:BUART:sTX:TxShifter:u0\
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_061.241 MHz16.3291067.00461.908 MHz16.1531067.180
datapathcell2U(3,5)datapathcell4U(2,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock\UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_23.2273.639
macrocell30U(2,5)macrocell35U(2,3) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2\UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_02.9022.314
statusicell3U(3,4)statusicell4U(2,3) 1 \UART_1:BUART:sTX:TxSts\
\UART_1:BUART:sTX:TxShifter:u0\/so_comb\UART_1:BUART:txn\/main_376.348 MHz13.0981070.235\UART_1:BUART:tx_state_1\/q\UART_1:BUART:sTX:TxSts\/status_073.578 MHz13.5911069.742
datapathcell2U(3,5)macrocell33U(3,0) 1\UART_1:BUART:sTX:TxShifter:u0\\UART_1:BUART:sTX:TxShifter:u0\/clock\UART_1:BUART:sTX:TxShifter:u0\/so_comb7.280\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q1.250
Route 1\UART_1:BUART:tx_shift_out\\UART_1:BUART:sTX:TxShifter:u0\/so_comb\UART_1:BUART:txn\/main_32.308\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_status_0\/main_05.107
macrocell32U(3,5)macrocell35U(2,3) 1\UART_1:BUART:txn\\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/main_0\UART_1:BUART:tx_status_0\/q3.350
Route 1\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/q\UART_1:BUART:sTX:TxSts\/status_02.314
statusicell4U(2,3)1\UART_1:BUART:sTX:TxSts\ SETUP3.5101.570
Clock
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:sTX:TxSts\/status_077.640 MHz12.8801070.453\UART_1:BUART:sTX:TxShifter:u0\/so_comb\UART_1:BUART:txn\/main_376.318 MHz13.1031070.230
macrocell27U(2,5)1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250
Route 1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_status_0\/main_13.808
macrocell30U(2,5)datapathcell4U(2,3) 1\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/main_1\UART_1:BUART:tx_status_0\/q3.350\UART_1:BUART:sTX:TxShifter:u0\\UART_1:BUART:sTX:TxShifter:u0\/clock\UART_1:BUART:sTX:TxShifter:u0\/so_comb7.280
Route 1\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/q\UART_1:BUART:sTX:TxSts\/status_02.902\UART_1:BUART:tx_shift_out\\UART_1:BUART:sTX:TxShifter:u0\/so_comb\UART_1:BUART:txn\/main_32.313
statusicell3U(3,4)macrocell37U(3,3) 1\UART_1:BUART:sTX:TxSts\\UART_1:BUART:txn\ SETUP1.5703.510
Clock
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:sTX:TxSts\/status_077.845 MHz12.8461070.487\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_278.858 MHz12.6811070.652
macrocell28U(2,5)macrocell33U(3,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_01 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_status_0\/main_03.774
macrocell30U(2,5)1\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/main_0\UART_1:BUART:tx_status_0\/q3.350
Route 1\UART_1:BUART:tx_status_0\\UART_1:BUART:tx_status_0\/q\UART_1:BUART:sTX:TxSts\/status_02.902\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_25.141
statusicell3U(3,4)datapathcell4U(2,3) 1\UART_1:BUART:sTX:TxSts\\UART_1:BUART:sTX:TxShifter:u0\ SETUP1.5706.290
Clock
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_179.327 MHz12.6061070.727\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb\UART_1:BUART:tx_state_0\/main_280.457 MHz12.4291070.904
macrocell27U(2,5)datapathcell4U(2,3) 1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250\UART_1:BUART:sTX:TxShifter:u0\\UART_1:BUART:sTX:TxShifter:u0\/clock\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb5.280
Route 1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:sTX:TxShifter:u0\/cs_addr_15.066\UART_1:BUART:tx_fifo_empty\\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb\UART_1:BUART:tx_state_0\/main_23.639
datapathcell2U(3,5)macrocell32U(2,3) 1\UART_1:BUART:sTX:TxShifter:u0\\UART_1:BUART:tx_state_0\ SETUP6.2903.510
Clock
@@ -1497,11 +1479,11 @@

Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

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Static Timing Analysis

- -
-
Path Delay Requirement : 500ns(2 MHz)
+
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:RxStsReg\/status_661.376 MHz16.293483.707\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/ci43.373 MHz23.05618.611
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb5.280\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:rx_status_4\\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:rx_status_6\/main_53.785\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell18U(2,5)datapathcell3U(3,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_5\SPIM:BSPIM:rx_status_6\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
statusicell1U(2,5)datapathcell2U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.5705.090
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_364.416 MHz15.524484.476\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci46.241 MHz21.62620.041
datapathcell1U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_33.714\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
macrocell16U(3,5)datapathcell2U(2,0) 1\SPIM:BSPIM:mosi_hs_reg\\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.5105.090
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_pre_reg\/main_368.306 MHz14.640485.360\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_050.566 MHz19.77621.891
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_pre_reg\/main_32.830\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell17U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:mosi_pre_reg\\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
datapathcell2U(2,0)1\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP3.51011.520
Clock
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_from_dp_reg\/main_068.353 MHz14.630485.370\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_050.571 MHz19.77421.893
datapathcell1U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_from_dp_reg\/main_02.820\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell15U(3,4)datapathcell3U(3,0) 1\SPIM:BSPIM:mosi_from_dp_reg\\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_02.974
datapathcell3U(3,0)1\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.51011.520
Clock
\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:TxStsReg\/status_073.676 MHz13.573486.427\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/ci52.576 MHz19.02022.647
macrocell21U(2,4)macrocell27U(2,0) 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/clock_0\SPIM:BSPIM:state_2\/q\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q 1.250
Route 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:tx_status_0\/main_04.486\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_12.970
macrocell22U(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_0\SPIM:BSPIM:tx_status_0\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb9.710
Route 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.917\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
statusicell2U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.5705.090
Clock
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:TxStsReg\/status_374.772 MHz13.374486.626\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_054.508 MHz18.34623.321
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:dpcounter_one\/main_34.028
macrocell10U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_3\SPIM:BSPIM:dpcounter_one\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_32.316\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_02.976
statusicell2U(2,3)datapathcell2U(2,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP1.57011.520
Clock
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:TxStsReg\/status_075.313 MHz13.278486.722\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_054.514 MHz18.34423.323
macrocell20U(2,3)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:tx_status_0\/main_14.191
macrocell22U(2,4)datapathcell3U(3,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_1\SPIM:BSPIM:tx_status_0\/q3.350\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/clock\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb3.850
Route datapathcell3U(3,0) 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.917\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_02.974
statusicell2U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:TxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP1.57011.520
Clock
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:RxStsReg\/status_675.919 MHz13.172486.828\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_163.532 MHz15.74025.927
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:rx_status_6\/main_33.834
macrocell18U(2,5)macrocell27U(2,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_3\SPIM:BSPIM:rx_status_6\/q3.350\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q1.250
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_12.970
statusicell1U(2,5)datapathcell2U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP1.57011.520
Clock
\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_875.976 MHz13.162486.838\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_163.971 MHz15.63226.035
datapathcell1U(2,4)macrocell27U(2,0) 1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb5.280\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/clock_0\Timer_1:TimerUDB:timer_enable\/q1.250
Route 1\SPIM:BSPIM:tx_status_1\\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_84.372\Timer_1:TimerUDB:timer_enable\\Timer_1:TimerUDB:timer_enable\/q\Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_12.862
macrocell20U(2,3)datapathcell3U(3,0) 1\SPIM:BSPIM:state_1\\Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP3.51011.520
Clock
\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:RxStsReg\/status_676.023 MHz13.154486.846\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:nrstSts:stsreg\/status_065.240 MHz15.32826.339
count7cellU(2,4)datapathcell2U(2,0) 1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_32.110\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/z02.320
Route 1\SPIM:BSPIM:count_3\\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:rx_status_6\/main_13.816\Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/z0\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i0.000
macrocell18U(2,5)datapathcell3U(3,0) 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_1\SPIM:BSPIM:rx_status_6\/q\Timer_1:TimerUDB:sT16:timerdp:u1\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0i\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb2.960
Route 1\Timer_1:TimerUDB:per_zero\\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb\Timer_1:TimerUDB:status_tc\/main_12.866
macrocell26U(2,0)1\Timer_1:TimerUDB:status_tc\\Timer_1:TimerUDB:status_tc\/main_1\Timer_1:TimerUDB:status_tc\/q 3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308\Timer_1:TimerUDB:status_tc\\Timer_1:TimerUDB:status_tc\/q\Timer_1:TimerUDB:nrstSts:stsreg\/status_02.262
statusicell1U(2,5)statusicell3U(2,0) 1\SPIM:BSPIM:RxStsReg\\Timer_1:TimerUDB:nrstSts:stsreg\ SETUP 1.570
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceDestinationFMaxDelay (ns)Slack (ns)Violation
\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:TxStsReg\/status_352.394 MHz19.086480.914
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_22.110
Route 1\SPIM:BSPIM:count_2\\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:dpcounter_one\/main_26.478
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_2\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:TxStsReg\/status_056.770 MHz17.615482.385
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell21U(2,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:tx_status_0\/main_18.508
macrocell23U(2,4)1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/main_1\SPIM:BSPIM:tx_status_0\/q3.350
Route 1\SPIM:BSPIM:tx_status_0\\SPIM:BSPIM:tx_status_0\/q\SPIM:BSPIM:TxStsReg\/status_02.937
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_157.166 MHz17.493482.507
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell21U(2,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_19.073
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\SETUP7.170
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:TxStsReg\/status_358.493 MHz17.096482.904
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_02.110
Route 1\SPIM:BSPIM:count_0\\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:dpcounter_one\/main_44.488
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_4\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:TxStsReg\/status_358.772 MHz17.015482.985
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_32.110
Route 1\SPIM:BSPIM:count_3\\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:dpcounter_one\/main_14.407
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_1\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:TxStsReg\/status_359.841 MHz16.711483.289
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_42.110
Route 1\SPIM:BSPIM:count_4\\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:dpcounter_one\/main_04.103
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_0\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:TxStsReg\/status_360.245 MHz16.599483.401
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(2,4)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:dpcounter_one\/main_33.991
macrocell11U(2,5)1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/main_3\SPIM:BSPIM:dpcounter_one\/q3.350
Route 1\SPIM:BSPIM:dpcounter_one\\SPIM:BSPIM:dpcounter_one\/q\SPIM:BSPIM:TxStsReg\/status_35.578
statusicell2U(2,5)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:RxStsReg\/status_661.072 MHz16.374483.626
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb5.280
Route 1\SPIM:BSPIM:rx_status_4\\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:rx_status_6\/main_53.241
macrocell19U(2,3)1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_5\SPIM:BSPIM:rx_status_6\/q3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.933
statusicell1U(3,4)1\SPIM:BSPIM:RxStsReg\SETUP1.570
Clock Skew0.000
+
\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:mosi_hs_reg\/main_063.147 MHz15.836484.164
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell22U(2,4)1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/clock_0\SPIM:BSPIM:state_2\/q1.250
Route 1\SPIM:BSPIM:state_2\\SPIM:BSPIM:state_2\/q\SPIM:BSPIM:mosi_hs_reg\/main_011.076
macrocell17U(3,3)1\SPIM:BSPIM:mosi_hs_reg\SETUP3.510
Clock Skew0.000
+
\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_363.605 MHz15.722484.278
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(2,4)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_comb\SPIM:BSPIM:mosi_hs_reg\/main_33.912
macrocell17U(3,3)1\SPIM:BSPIM:mosi_hs_reg\SETUP3.510
Clock Skew0.000
+
+
+
+
+
+
+
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceDestinationSlack (ns)Violation
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_1\/main_03.482
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q1.250
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_1\/main_02.232
macrocell33U(3,0)1\UART_1:BUART:tx_state_1\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_03.544
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell37U(3,3)1\UART_1:BUART:txn\\UART_1:BUART:txn\/clock_0\UART_1:BUART:txn\/q1.250
macrocell37U(3,3)1\UART_1:BUART:txn\\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_02.294
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_24.205
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_22.955
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_44.205
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
Route1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_42.955
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_34.218
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_32.968
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_54.218
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_52.968
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_34.312
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250
Route1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_33.062
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_44.354
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell30U(2,3)1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250
Route1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_43.104
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_2\/main_14.847
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250
Route1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:tx_state_2\/main_13.597
macrocell34U(3,3)1\UART_1:BUART:tx_state_2\ HOLD0.000
Clock Skew0.000
+
\UART_1:BUART:tx_state_0\/q\UART_1:BUART:txn\/main_24.847
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell32U(2,3)1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/clock_0\UART_1:BUART:tx_state_0\/q1.250
Route1\UART_1:BUART:tx_state_0\\UART_1:BUART:tx_state_0\/q\UART_1:BUART:txn\/main_23.597
macrocell37U(3,3)1\UART_1:BUART:txn\ HOLD0.000
Clock Skew0.000
+
+
+
+
+
+
+
+
@@ -2271,9 +3714,9 @@

Static Timing Analysis

- - - + + + @@ -2292,28 +3735,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - + + - - - - + + + + - - + + - + @@ -2332,9 +3775,9 @@

Static Timing Analysis

- - - + + + @@ -2353,28 +3796,28 @@

Static Timing Analysis

- - + + - - - + + + - - - - + + + + - - + + - + @@ -2393,9 +3836,9 @@

Static Timing Analysis

- - - + + + @@ -2415,27 +3858,27 @@

Static Timing Analysis

- + - - - + + + - - - - + + + + - - + + - + @@ -2454,9 +3897,9 @@

Static Timing Analysis

- - - + + + @@ -2475,28 +3918,28 @@

Static Timing Analysis

- - + + - - - + + + - - - - + + + + - - + + - + @@ -2515,9 +3958,9 @@

Static Timing Analysis

- - - + + + @@ -2536,28 +3979,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -2576,9 +4019,9 @@

Static Timing Analysis

- - - + + + @@ -2597,28 +4040,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2637,9 +4080,9 @@

Static Timing Analysis

- - - + + + @@ -2658,28 +4101,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2698,9 +4141,9 @@

Static Timing Analysis

- - - + + + @@ -2719,28 +4162,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2759,9 +4202,9 @@

Static Timing Analysis

- - - + + + @@ -2780,28 +4223,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - + + - - - - + + + + - - + + - + @@ -2820,9 +4263,9 @@

Static Timing Analysis

- - - + + + @@ -2841,28 +4284,28 @@

Static Timing Analysis

- - + + - - - - + + + + - - - - + + + + - - + + - + @@ -2909,8 +4352,8 @@

Static Timing Analysis

- - + + @@ -2930,28 +4373,89 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - + + + - - + + - + + + + + + + + + + + + + + + +
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_24.183\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci3.210
macrocell29U(3,5)datapathcell2U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250\Timer_1:TimerUDB:sT16:timerdp:u0\\Timer_1:TimerUDB:sT16:timerdp:u0\/clock\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb3.210
macrocell29U(3,5)Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_2\/main_22.933\Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb\Timer_1:TimerUDB:sT16:timerdp:u1\/ci0.000
macrocell29U(3,5)datapathcell3U(3,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_44.183\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:timer_enable\/main_23.487
macrocell29U(3,5)macrocell25U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/clock_0\Timer_1:TimerUDB:run_mode\/q 1.250
Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:txn\/main_42.933\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:timer_enable\/main_22.237
macrocell32U(3,5)macrocell27U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_34.218\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:trig_disable\/main_13.487
macrocell25U(2,5)U(2,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/clock_0\Timer_1:TimerUDB:run_mode\/q 1.250
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_2\/main_32.968\Timer_1:TimerUDB:run_mode\\Timer_1:TimerUDB:run_mode\/q\Timer_1:TimerUDB:trig_disable\/main_12.237
macrocell29U(3,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:trig_disable\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_54.218\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:timer_enable\/main_43.490
macrocell25U(2,5)macrocell28U(2,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/clock_0\Timer_1:TimerUDB:trig_disable\/q 1.250
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:txn\/main_52.968\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:timer_enable\/main_42.240
macrocell32U(3,5)macrocell27U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_34.315\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:trig_disable\/main_33.490
macrocell29U(3,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/clock_0\Timer_1:TimerUDB:trig_disable\/q 1.250
Routemacrocell28U(2,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_0\/main_33.065\Timer_1:TimerUDB:trig_disable\\Timer_1:TimerUDB:trig_disable\/q\Timer_1:TimerUDB:trig_disable\/main_32.240
macrocell27U(2,5)macrocell28U(2,0) 1\UART_1:BUART:tx_state_0\\Timer_1:TimerUDB:trig_disable\ HOLD 0.000
\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_1\/main_24.315ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en3.677
macrocell29U(3,5)synccellU(3,0) 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/clock_0\UART_1:BUART:tx_state_2\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_state_2\\UART_1:BUART:tx_state_2\/q\UART_1:BUART:tx_state_1\/main_23.065ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u1\/clk_en2.677
macrocell28U(2,5)datapathcell3U(3,0) 1\UART_1:BUART:tx_state_1\\Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_44.346ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:nrstSts:stsreg\/clk_en3.700
macrocell25U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_0\/main_43.096ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:nrstSts:stsreg\/clk_en2.700
macrocell27U(2,5)statusicell3U(2,0) 1\UART_1:BUART:tx_state_0\\Timer_1:TimerUDB:nrstSts:stsreg\ HOLD 0.000
\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_1\/main_34.346ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:run_mode\/clk_en3.700
macrocell25U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/clock_0\UART_1:BUART:tx_bitclk\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_bitclk\\UART_1:BUART:tx_bitclk\/q\UART_1:BUART:tx_state_1\/main_33.096ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:run_mode\/clk_en2.700
macrocell28U(2,5)macrocell25U(2,0) 1\UART_1:BUART:tx_state_1\\Timer_1:TimerUDB:run_mode\ HOLD 0.000
\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_04.426ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en3.700
macrocell32U(3,5)synccellU(3,0) 1\UART_1:BUART:txn\\UART_1:BUART:txn\/clock_0\UART_1:BUART:txn\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
macrocell32U(3,5)Route 1\UART_1:BUART:txn\\UART_1:BUART:txn\/q\UART_1:BUART:txn\/main_03.176ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:sT16:timerdp:u0\/clk_en2.700
macrocell32U(3,5)datapathcell2U(2,0) 1\UART_1:BUART:txn\\Timer_1:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_2\/main_05.011ClockBlock_1k__SYNC/out\Timer_1:TimerUDB:timer_enable\/clk_en3.700
macrocell28U(2,5)synccellU(3,0) 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/clock_0\UART_1:BUART:tx_state_1\/q1.250ClockBlock_1k__SYNCClockBlock_1k__SYNC/clockClockBlock_1k__SYNC/out1.000
Route 1\UART_1:BUART:tx_state_1\\UART_1:BUART:tx_state_1\/q\UART_1:BUART:tx_state_2\/main_03.761ClockBlock_1k__SYNC_OUTClockBlock_1k__SYNC/out\Timer_1:TimerUDB:timer_enable\/clk_en2.700
macrocell29U(3,5)macrocell27U(2,0) 1\UART_1:BUART:tx_state_2\\Timer_1:TimerUDB:timer_enable\ HOLD 0.000
\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_9\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_9 3.539
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/clock_0\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/clock_0\SPIM:BSPIM:mosi_pre_reg\/q 1.250
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_9\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_9 2.289
macrocell9U(2,3)macrocell18U(2,4) 1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:mosi_pre_reg\ HOLD0.000
Clock Skew0.000
+ + + + \SPIM:BSPIM:load_cond\/q + \SPIM:BSPIM:load_cond\/main_8 + 3.547 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2972,7 +4476,7 @@

Static Timing Analysis

- + @@ -2991,7 +4495,7 @@

Static Timing Analysis

- + @@ -3000,16 +4504,16 @@

Static Timing Analysis

- + - + - + @@ -3033,7 +4537,7 @@

Static Timing Analysis

- + @@ -3052,7 +4556,7 @@

Static Timing Analysis

- + @@ -3067,10 +4571,10 @@

Static Timing Analysis

- + - + @@ -3092,9 +4596,9 @@

Static Timing Analysis

- - - + + + @@ -3113,28 +4617,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3175,7 +4679,7 @@

Static Timing Analysis

- + @@ -3184,7 +4688,7 @@

Static Timing Analysis

- + @@ -3193,7 +4697,7 @@

Static Timing Analysis

- + @@ -3214,9 +4718,9 @@

Static Timing Analysis

- - - + + + @@ -3235,28 +4739,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3277,7 +4781,7 @@

Static Timing Analysis

- + @@ -3296,8 +4800,8 @@

Static Timing Analysis

- - + + @@ -3311,7 +4815,7 @@

Static Timing Analysis

- + @@ -3338,7 +4842,7 @@

Static Timing Analysis

- + @@ -3357,7 +4861,7 @@

Static Timing Analysis

- + @@ -3372,11 +4876,11 @@

Static Timing Analysis

- + - - + + @@ -3397,70 +4901,9 @@

Static Timing Analysis

- - - - - - - - - - - - + + + @@ -3479,28 +4922,28 @@

Static Timing Analysis

- - + + - - - + + + - - + + - - - - + + + + - - + + - + @@ -3552,7 +4995,7 @@

Static Timing Analysis

- + - + @@ -3594,7 +5037,7 @@

Static Timing Analysis

- + @@ -3648,7 +5091,7 @@

Static Timing Analysis

- + - - + + @@ -3681,7 +5124,7 @@

Static Timing Analysis

- + @@ -3699,10 +5142,10 @@

Static Timing Analysis

- + - + @@ -3752,9 +5195,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/clock_0\SPIM:BSPIM:load_cond\/q1.250
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/q\SPIM:BSPIM:load_cond\/main_82.297
macrocell14U(2,5)1\SPIM:BSPIM:load_cond\ HOLD 0.000
\SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:is_spi_done\/main_93.5603.554
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ 1.250
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:is_spi_done\/main_92.3102.304
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\
\SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:state_2\/main_93.5603.554
macrocell11macrocell12 U(2,4) 1 \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\ \SPIM:BSPIM:is_spi_done\/q \SPIM:BSPIM:state_2\/main_92.3102.304
macrocell21macrocell22 U(2,4) 1 \SPIM:BSPIM:state_2\
\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_93.571\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_33.559
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/clock_0\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/clock_0\SPIM:BSPIM:ld_ident\/q 1.250
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:mosi_pre_reg\/q\SPIM:BSPIM:mosi_pre_reg\/main_92.321\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_32.309
macrocell17U(2,4)macrocell13U(2,5) 1\SPIM:BSPIM:mosi_pre_reg\\SPIM:BSPIM:ld_ident\ HOLD 0.000
macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/q
macrocell7U(3,3)U(3,5) 1 Net_439
\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_33.876\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_93.888
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/clock_0\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/clock_0\SPIM:BSPIM:cnt_enable\/q 1.250
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:ld_ident\/q\SPIM:BSPIM:ld_ident\/main_32.626\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_92.638
macrocell12U(3,3)macrocell10U(2,5) 1\SPIM:BSPIM:ld_ident\\SPIM:BSPIM:cnt_enable\ HOLD 0.000
\SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load4.1634.146
macrocell14U(2,3)macrocell15U(2,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/clock_0 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load2.9132.896
datapathcell1
\SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_54.1734.160
macrocell15macrocell16 U(3,4) 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_52.9232.910
macrocell16U(3,5)macrocell17U(3,3) 1 \SPIM:BSPIM:mosi_hs_reg\
\SPIM:BSPIM:state_1\/qNet_479/main_24.198
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell20U(2,3)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/qNet_479/main_22.948
macrocell8U(2,3)1Net_479 HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:load_cond\/main_14.198\SPIM:BSPIM:mosi_hs_reg\/q\SPIM:BSPIM:mosi_hs_reg\/main_44.445
macrocell20U(2,3)macrocell17U(3,3) 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:mosi_hs_reg\\SPIM:BSPIM:mosi_hs_reg\/clock_0\SPIM:BSPIM:mosi_hs_reg\/q 1.250
Routemacrocell17U(3,3) 1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:load_cond\/main_12.948\SPIM:BSPIM:mosi_hs_reg\\SPIM:BSPIM:mosi_hs_reg\/q\SPIM:BSPIM:mosi_hs_reg\/main_43.195
macrocell13U(2,3)macrocell17U(3,3) 1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
m_miso_pin(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si41.67741.678
@@ -3579,7 +5022,7 @@

Static Timing Analysis

0.000
iocell13iocell14 P0[0] 1 m_miso_pin(0) Net_20 m_miso_pin(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si7.1877.188
datapathcell1
\UART_1:BUART:txn\/q Tx_1(0)_PAD33.32431.436
@@ -3666,8 +5109,8 @@

Static Timing Analysis

macrocell32U(3,5)macrocell37U(3,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_234/main_04.5213.195
macrocell1 Net_234 Net_234/q Tx_1(0)/pin_input6.3595.797
iocell5iocell6 P3[7] 1 Tx_1(0)
\SS:Async:ctrl_reg\/control_1Pin_2(0)_PAD33.212\SS:Async:ctrl_reg\/control_2Pin_3(0)_PAD32.395
@@ -3773,56 +5216,143 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_422/main_12.791mywire_1_2\SS:Async:ctrl_reg\/control_2Net_428/main_12.792
macrocell4U(3,3)macrocell6U(3,5) 1Net_422Net_422/main_1Net_422/qNet_428Net_428/main_1Net_428/q 3.350
Route 1Net_422Net_422/qPin_2(0)/pin_input7.423Net_428Net_428/qPin_3(0)/pin_input6.361
iocell3P3[2]1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312
Route1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PAD0.000
Clock Clock path delay0.000
+ + + + \SS:Async:ctrl_reg\/control_0 + Pin_1(0)_PAD + 32.006 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - - - + + + + - - - + + + @@ -3839,9 +5369,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -3926,9 +5456,9 @@

Static Timing Analysis

- - - + + + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -4013,9 +5543,9 @@

Static Timing Analysis

- + - + - + - + - - + + - + - + @@ -4066,7 +5596,7 @@

Static Timing Analysis

- + @@ -4121,7 +5651,7 @@

Static Timing Analysis

- + - - + + @@ -4154,11 +5684,11 @@

Static Timing Analysis

- + - + @@ -4172,10 +5702,10 @@

Static Timing Analysis

- + - + @@ -4207,8 +5737,8 @@

Static Timing Analysis

- - + + - + @@ -4240,43 +5770,43 @@

Static Timing Analysis

- + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + @@ -4295,7 +5825,7 @@

Static Timing Analysis

- + - + @@ -4332,7 +5862,7 @@

Static Timing Analysis

- + @@ -4346,7 +5876,7 @@

Static Timing Analysis

- + @@ -4381,8 +5911,8 @@

Static Timing Analysis

- - + + - + @@ -4414,43 +5944,130 @@

Static Timing Analysis

- + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - + + + + + + + + + + + + + + + +
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
controlcell1U(3,5)1\SS:Async:ctrl_reg\\SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_02.580
Route1mywire_1_0\SS:Async:ctrl_reg\/control_0Net_419/main_32.809
macrocell3U(3,5)1Net_419Net_419/main_3Net_419/q3.350
Route1Net_419Net_419/qPin_1(0)/pin_input6.356
iocell2P3[1]iocell1P3[0] 1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068Pin_1(0)Pin_1(0)/pin_inputPin_1(0)/pad_out16.911
Route 1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PADPin_1(0)_PADPin_1(0)/pad_outPin_1(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1Pin_1(0)_PAD33.047\SS:Async:ctrl_reg\/control_2Pin_5(0)_PAD31.882
@@ -3860,56 +5390,56 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_419/main_12.795mywire_1_2\SS:Async:ctrl_reg\/control_2Net_585/main_12.792
macrocell3U(3,3)macrocell9U(3,5) 1Net_419Net_419/main_1Net_419/qNet_585Net_585/main_1Net_585/q 3.350
Route 1Net_419Net_419/qPin_1(0)/pin_input7.411Net_585Net_585/qPin_5(0)/pin_input6.321
iocell1P3[0]iocell5P3[4] 1Pin_1(0)Pin_1(0)/pin_inputPin_1(0)/pad_out16.911Pin_5(0)Pin_5(0)/pin_inputPin_5(0)/pad_out16.839
Route 1Pin_1(0)_PADPin_1(0)/pad_outPin_1(0)_PADPin_5(0)_PADPin_5(0)/pad_outPin_5(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1Pin_3(0)_PAD32.781\SS:Async:ctrl_reg\/control_2Pin_2(0)_PAD31.296
@@ -3947,56 +5477,56 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1Net_428/main_12.791mywire_1_2\SS:Async:ctrl_reg\/control_2Net_422/main_12.792
macrocell6U(3,3)macrocell4U(3,5) 1Net_428Net_428/main_1Net_428/qNet_422Net_422/main_1Net_422/q 3.350
Route 1Net_428Net_428/qPin_3(0)/pin_input6.748Net_422Net_422/qPin_2(0)/pin_input5.506
iocell3P3[2]iocell2P3[1] 1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068
Route 1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PADPin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PAD 0.000
\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 Pin_4(0)_PAD31.44031.158
@@ -4034,25 +5564,25 @@

Static Timing Analysis

controlcell1U(3,3)U(3,5) 1 \SS:Async:ctrl_reg\ \SS:Async:ctrl_reg\/busclk\SS:Async:ctrl_reg\/control_1\SS:Async:ctrl_reg\/control_2 2.580
Route 1mywire_1_1\SS:Async:ctrl_reg\/control_1mywire_1_2\SS:Async:ctrl_reg\/control_2 Net_425/main_12.7912.792
macrocell5U(3,3)U(3,5) 1 Net_425 Net_425/main_1 Net_425 Net_425/q Pin_4(0)/pin_input6.6136.330
iocell4
\SPIM:BSPIM:mosi_hs_reg\/q m_mosi_pin(0)_PAD36.07435.028
@@ -4139,8 +5669,8 @@

Static Timing Analysis

macrocell16U(3,5)macrocell17U(3,3) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/clock_0 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/q Net_30/main_15.2575.244
macrocell2U(3,3)U(3,5) 1 Net_30 Net_30/main_1 Net_30 Net_30/q m_mosi_pin(0)/pin_input8.2467.213
iocell14iocell15 P0[5] 1 m_mosi_pin(0)
Net_439/qPin_2(0)_PAD31.687Pin_3(0)_PAD30.869
@@ -4227,7 +5757,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0 1 Net_439 Net_439/qNet_422/main_0Net_428/main_0 2.596
macrocell4U(3,3)macrocell6U(3,5) 1Net_422Net_422/main_0Net_422/qNet_428Net_428/main_0Net_428/q 3.350
Route 1Net_422Net_422/qPin_2(0)/pin_input7.423Net_428Net_428/qPin_3(0)/pin_input6.361
iocell2P3[1]iocell3P3[2] 1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312
Route 1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PADPin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PAD 0.000
Net_439/q Pin_1(0)_PAD31.51230.457
@@ -4314,7 +5844,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell3U(3,3)U(3,5) 1 Net_419 Net_419/main_0 Net_419 Net_419/q Pin_1(0)/pin_input7.4116.356
iocell1
Net_439/qPin_3(0)_PAD31.256Pin_5(0)_PAD30.356
@@ -4401,7 +5931,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0 1 Net_439 Net_439/qNet_428/main_0Net_585/main_0 2.596
macrocell6U(3,3)macrocell9U(3,5) 1Net_428Net_428/main_0Net_428/qNet_585Net_585/main_0Net_585/q 3.350
Route 1Net_428Net_428/qPin_3(0)/pin_input6.748Net_585Net_585/qPin_5(0)/pin_input6.321
iocell3P3[2]iocell5P3[4] 1Pin_3(0)Pin_3(0)/pin_inputPin_3(0)/pad_out17.312Pin_5(0)Pin_5(0)/pin_inputPin_5(0)/pad_out16.839
Route 1Pin_3(0)_PADPin_3(0)/pad_outPin_3(0)_PADPin_5(0)_PADPin_5(0)/pad_outPin_5(0)_PAD0.000
Clock Clock path delay0.000
+ + + + Net_439/q + Pin_2(0)_PAD + 29.770 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4469,7 +6086,7 @@

Static Timing Analysis

- + - + @@ -4506,7 +6123,7 @@

Static Timing Analysis

- + @@ -4520,7 +6137,7 @@

Static Timing Analysis

- + @@ -4556,7 +6173,7 @@

Static Timing Analysis

- + - + @@ -4589,10 +6206,10 @@

Static Timing Analysis

- + - + diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_u.sdc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_u.sdc index 928c5c6..7abfd7d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_u.sdc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSOC5_SPI_LSM303D_u.sdc @@ -1,3 +1,3 @@ -# Component constraints for C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch -# Project: C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj -# Date: Fri, 22 Mar 2013 09:33:23 GMT +# Component constraints for C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch +# Project: C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cyprj +# Date: Thu, 25 Jul 2013 14:48:52 GMT diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSoC5_Panther_100-TQFP.xml b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSoC5_Panther_100-TQFP.xml index cd7f928..3d5e4cc 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSoC5_Panther_100-TQFP.xml +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/PSoC5_Panther_100-TQFP.xml @@ -1,7 +1,6 @@ - @@ -45,6 +44,8 @@ + + diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.c index 6b2c354..2754a77 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.h index d8a146a..4170174 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1_aliases.h index b404d4a..13cc3b1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_1_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_1.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.c index 1f4385a..e8c68c4 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.h index b74bf90..4e73fa8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2_aliases.h index d6d8eba..ef19a3a 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_2_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_2.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.c index 4237a34..412803c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.h index 5268493..6b112e5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3_aliases.h index d3dcdea..fb8bc2d 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_3_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_3.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.c index 3bb6dd5..702a703 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.h index 3387667..cded03b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4_aliases.h index 08f796a..4f0894e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_4_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: Pin_4.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.c new file mode 100644 index 0000000..ee180d0 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: Pin_5.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "Pin_5.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + Pin_5__PORT == 15 && ((Pin_5__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: Pin_5_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void Pin_5_Write(uint8 value) +{ + uint8 staticBits = (Pin_5_DR & (uint8)(~Pin_5_MASK)); + Pin_5_DR = staticBits | ((uint8)(value << Pin_5_SHIFT) & Pin_5_MASK); +} + + +/******************************************************************************* +* Function Name: Pin_5_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void Pin_5_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(Pin_5_0, mode); +} + + +/******************************************************************************* +* Function Name: Pin_5_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro Pin_5_ReadPS calls this function. +* +*******************************************************************************/ +uint8 Pin_5_Read(void) +{ + return (Pin_5_PS & Pin_5_MASK) >> Pin_5_SHIFT; +} + + +/******************************************************************************* +* Function Name: Pin_5_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 Pin_5_ReadDataReg(void) +{ + return (Pin_5_DR & Pin_5_MASK) >> Pin_5_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(Pin_5_INTSTAT) + + /******************************************************************************* + * Function Name: Pin_5_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 Pin_5_ClearInterrupt(void) + { + return (Pin_5_INTSTAT & Pin_5_MASK) >> Pin_5_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.h new file mode 100644 index 0000000..8bc2e01 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: Pin_5.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Pin_5_H) /* Pins Pin_5_H */ +#define CY_PINS_Pin_5_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "Pin_5_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + Pin_5__PORT == 15 && ((Pin_5__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void Pin_5_Write(uint8 value) ; +void Pin_5_SetDriveMode(uint8 mode) ; +uint8 Pin_5_ReadDataReg(void) ; +uint8 Pin_5_Read(void) ; +uint8 Pin_5_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define Pin_5_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define Pin_5_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define Pin_5_DM_RES_UP PIN_DM_RES_UP +#define Pin_5_DM_RES_DWN PIN_DM_RES_DWN +#define Pin_5_DM_OD_LO PIN_DM_OD_LO +#define Pin_5_DM_OD_HI PIN_DM_OD_HI +#define Pin_5_DM_STRONG PIN_DM_STRONG +#define Pin_5_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define Pin_5_MASK Pin_5__MASK +#define Pin_5_SHIFT Pin_5__SHIFT +#define Pin_5_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define Pin_5_PS (* (reg8 *) Pin_5__PS) +/* Data Register */ +#define Pin_5_DR (* (reg8 *) Pin_5__DR) +/* Port Number */ +#define Pin_5_PRT_NUM (* (reg8 *) Pin_5__PRT) +/* Connect to Analog Globals */ +#define Pin_5_AG (* (reg8 *) Pin_5__AG) +/* Analog MUX bux enable */ +#define Pin_5_AMUX (* (reg8 *) Pin_5__AMUX) +/* Bidirectional Enable */ +#define Pin_5_BIE (* (reg8 *) Pin_5__BIE) +/* Bit-mask for Aliased Register Access */ +#define Pin_5_BIT_MASK (* (reg8 *) Pin_5__BIT_MASK) +/* Bypass Enable */ +#define Pin_5_BYP (* (reg8 *) Pin_5__BYP) +/* Port wide control signals */ +#define Pin_5_CTL (* (reg8 *) Pin_5__CTL) +/* Drive Modes */ +#define Pin_5_DM0 (* (reg8 *) Pin_5__DM0) +#define Pin_5_DM1 (* (reg8 *) Pin_5__DM1) +#define Pin_5_DM2 (* (reg8 *) Pin_5__DM2) +/* Input Buffer Disable Override */ +#define Pin_5_INP_DIS (* (reg8 *) Pin_5__INP_DIS) +/* LCD Common or Segment Drive */ +#define Pin_5_LCD_COM_SEG (* (reg8 *) Pin_5__LCD_COM_SEG) +/* Enable Segment LCD */ +#define Pin_5_LCD_EN (* (reg8 *) Pin_5__LCD_EN) +/* Slew Rate Control */ +#define Pin_5_SLW (* (reg8 *) Pin_5__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define Pin_5_PRTDSI__CAPS_SEL (* (reg8 *) Pin_5__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define Pin_5_PRTDSI__DBL_SYNC_IN (* (reg8 *) Pin_5__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define Pin_5_PRTDSI__OE_SEL0 (* (reg8 *) Pin_5__PRTDSI__OE_SEL0) +#define Pin_5_PRTDSI__OE_SEL1 (* (reg8 *) Pin_5__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define Pin_5_PRTDSI__OUT_SEL0 (* (reg8 *) Pin_5__PRTDSI__OUT_SEL0) +#define Pin_5_PRTDSI__OUT_SEL1 (* (reg8 *) Pin_5__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define Pin_5_PRTDSI__SYNC_OUT (* (reg8 *) Pin_5__PRTDSI__SYNC_OUT) + + +#if defined(Pin_5__INTSTAT) /* Interrupt Registers */ + + #define Pin_5_INTSTAT (* (reg8 *) Pin_5__INTSTAT) + #define Pin_5_SNAP (* (reg8 *) Pin_5__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_Pin_5_H */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5_aliases.h new file mode 100644 index 0000000..1f8e49d --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Pin_5_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: Pin_5.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_Pin_5_ALIASES_H) /* Pins Pin_5_ALIASES_H */ +#define CY_PINS_Pin_5_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define Pin_5_0 Pin_5__0__PC + +#endif /* End Pins Pin_5_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.c new file mode 100644 index 0000000..66ba383 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.c @@ -0,0 +1,754 @@ +/******************************************************************************* +* File Name: Timer_1.c +* Version 2.50 +* +* Description: +* The Timer component consists of a 8, 16, 24 or 32-bit timer with +* a selectable period between 2 and 2^Width - 1. The timer may free run +* or be used as a capture timer as well. The capture can be initiated +* by a positive or negative edge signal as well as via software. +* A trigger input can be programmed to enable the timer on rising edge +* falling edge, either edge or continous run. +* Interrupts may be generated due to a terminal count condition +* or a capture event. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Timer_1.h" + +uint8 Timer_1_initVar = 0u; + + +/******************************************************************************* +* Function Name: Timer_1_Init +******************************************************************************** +* +* Summary: +* Initialize to the schematic state +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_Init(void) +{ + #if(!Timer_1_UsingFixedFunction) + /* Interrupt State Backup for Critical Region*/ + uint8 Timer_1_interruptState; + #endif /* Interrupt state back up for Fixed Function only */ + + #if (Timer_1_UsingFixedFunction) + /* Clear all bits but the enable bit (if it's already set) for Timer operation */ + Timer_1_CONTROL &= Timer_1_CTRL_ENABLE; + + /* Clear the mode bits for continuous run mode */ + #if (CY_PSOC5A) + Timer_1_CONTROL2 &= ((uint8)(~Timer_1_CTRL_MODE_MASK)); + #endif /* Clear bits in CONTROL2 only in PSOC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_MODE_MASK)); + #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */ + + /* Check if One Shot mode is enabled i.e. RunMode !=0*/ + #if (Timer_1_RunModeUsed != 0x0u) + /* Set 3rd bit of Control register to enable one shot mode */ + Timer_1_CONTROL |= 0x04u; + #endif /* One Shot enabled only when RunModeUsed is not Continuous*/ + + #if (Timer_1_RunModeUsed == 2) + #if (CY_PSOC5A) + /* Set last 2 bits of control2 register if one shot(halt on + interrupt) is enabled*/ + Timer_1_CONTROL2 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Set last 2 bits of control3 register if one shot(halt on + interrupt) is enabled*/ + Timer_1_CONTROL3 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */ + + #endif /* Remove section if One Shot Halt on Interrupt is not enabled */ + + #if (Timer_1_UsingHWEnable != 0) + #if (CY_PSOC5A) + /* Set the default Run Mode of the Timer to Continuous */ + Timer_1_CONTROL2 |= Timer_1_CTRL_MODE_PULSEWIDTH; + #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Clear and Set ROD and COD bits of CFG2 register */ + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_RCOD_MASK)); + Timer_1_CONTROL3 |= Timer_1_CTRL_RCOD; + + /* Clear and Enable the HW enable bit in CFG2 register */ + Timer_1_CONTROL3 &= ((uint8)(~Timer_1_CTRL_ENBL_MASK)); + Timer_1_CONTROL3 |= Timer_1_CTRL_ENBL; + + /* Set the default Run Mode of the Timer to Continuous */ + Timer_1_CONTROL3 |= Timer_1_CTRL_MODE_CONTINUOUS; + #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */ + + #endif /* Configure Run Mode with hardware enable */ + + /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */ + Timer_1_RT1 &= ((uint8)(~Timer_1_RT1_MASK)); + Timer_1_RT1 |= Timer_1_SYNC; + + /*Enable DSI Sync all all inputs of the Timer*/ + Timer_1_RT1 &= ((uint8)(~Timer_1_SYNCDSI_MASK)); + Timer_1_RT1 |= Timer_1_SYNCDSI_EN; + + /* Set the IRQ to use the status register interrupts */ + Timer_1_CONTROL2 |= Timer_1_CTRL2_IRQ_SEL; + #endif /* Configuring registers of fixed function implementation */ + + /* Set Initial values from Configuration */ + Timer_1_WritePeriod(Timer_1_INIT_PERIOD); + Timer_1_WriteCounter(Timer_1_INIT_PERIOD); + + #if (Timer_1_UsingHWCaptureCounter)/* Capture counter is enabled */ + Timer_1_CAPTURE_COUNT_CTRL |= Timer_1_CNTR_ENABLE; + Timer_1_SetCaptureCount(Timer_1_INIT_CAPTURE_COUNT); + #endif /* Configure capture counter value */ + + #if (!Timer_1_UsingFixedFunction) + #if (Timer_1_SoftwareCaptureMode) + Timer_1_SetCaptureMode(Timer_1_INIT_CAPTURE_MODE); + #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */ + + #if (Timer_1_SoftwareTriggerMode) + if (0u == (Timer_1_CONTROL & Timer_1__B_TIMER__TM_SOFTWARE)) + { + Timer_1_SetTriggerMode(Timer_1_INIT_TRIGGER_MODE); + } + #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */ + + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Timer_1_interruptState = CyEnterCriticalSection(); + + /* Use the interrupt output of the status register for IRQ output */ + Timer_1_STATUS_AUX_CTRL |= Timer_1_STATUS_ACTL_INT_EN_MASK; + + /* Exit Critical Region*/ + CyExitCriticalSection(Timer_1_interruptState); + + #if (Timer_1_EnableTriggerMode) + Timer_1_EnableTrigger(); + #endif /* Set Trigger enable bit for UDB implementation in the control register*/ + + #if (Timer_1_InterruptOnCaptureCount) + #if (!Timer_1_ControlRegRemoved) + Timer_1_SetInterruptCount(Timer_1_INIT_INT_CAPTURE_COUNT); + #endif /* Set interrupt count in control register if control register is not removed */ + #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/ + + Timer_1_ClearFIFO(); + #endif /* Configure additional features of UDB implementation */ + + Timer_1_SetInterruptMode(Timer_1_INIT_INTERRUPT_MODE); +} + + +/******************************************************************************* +* Function Name: Timer_1_Enable +******************************************************************************** +* +* Summary: +* Enable the Timer +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_Enable(void) +{ + /* Globally Enable the Fixed Function Block chosen */ + #if (Timer_1_UsingFixedFunction) + Timer_1_GLOBAL_ENABLE |= Timer_1_BLOCK_EN_MASK; + Timer_1_GLOBAL_STBY_ENABLE |= Timer_1_BLOCK_STBY_EN_MASK; + #endif /* Set Enable bit for enabling Fixed function timer*/ + + /* Remove assignment if control register is removed */ + #if (!Timer_1_ControlRegRemoved || Timer_1_UsingFixedFunction) + Timer_1_CONTROL |= Timer_1_CTRL_ENABLE; + #endif /* Remove assignment if control register is removed */ +} + + +/******************************************************************************* +* Function Name: Timer_1_Start +******************************************************************************** +* +* Summary: +* The start function initializes the timer with the default values, the +* enables the timerto begin counting. It does not enable interrupts, +* the EnableInt command should be called if interrupt generation is required. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_initVar: Is modified when this function is called for the +* first time. Is used to ensure that initialization happens only once. +* +*******************************************************************************/ +void Timer_1_Start(void) +{ + if(Timer_1_initVar == 0u) + { + Timer_1_Init(); + + Timer_1_initVar = 1u; /* Clear this bit for Initialization */ + } + + /* Enable the Timer */ + Timer_1_Enable(); +} + + +/******************************************************************************* +* Function Name: Timer_1_Stop +******************************************************************************** +* +* Summary: +* The stop function halts the timer, but does not change any modes or disable +* interrupts. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: If the Enable mode is set to Hardware only then this function +* has no effect on the operation of the timer. +* +*******************************************************************************/ +void Timer_1_Stop(void) +{ + /* Disable Timer */ + #if(!Timer_1_ControlRegRemoved || Timer_1_UsingFixedFunction) + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_ENABLE)); + #endif /* Remove assignment if control register is removed */ + + /* Globally disable the Fixed Function Block chosen */ + #if (Timer_1_UsingFixedFunction) + Timer_1_GLOBAL_ENABLE &= ((uint8)(~Timer_1_BLOCK_EN_MASK)); + Timer_1_GLOBAL_STBY_ENABLE &= ((uint8)(~Timer_1_BLOCK_STBY_EN_MASK)); + #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/ +} + + +/******************************************************************************* +* Function Name: Timer_1_SetInterruptMode +******************************************************************************** +* +* Summary: +* This function selects which of the interrupt inputs may cause an interrupt. +* The twosources are caputure and terminal. One, both or neither may +* be selected. +* +* Parameters: +* interruptMode: This parameter is used to enable interrups on either/or +* terminal count or capture. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetInterruptMode(uint8 interruptMode) +{ + Timer_1_STATUS_MASK = interruptMode; +} + + +/******************************************************************************* +* Function Name: Timer_1_SoftwareCapture +******************************************************************************** +* +* Summary: +* This function forces a capture independent of the capture signal. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: +* An existing hardware capture could be overwritten. +* +*******************************************************************************/ +void Timer_1_SoftwareCapture(void) +{ + /* Generate a software capture by reading the counter register */ + (void)Timer_1_COUNTER_LSB; + /* Capture Data is now in the FIFO */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadStatusRegister +******************************************************************************** +* +* Summary: +* Reads the status register and returns it's state. This function should use +* defined types for the bit-field information as the bits in this register may +* be permuteable. +* +* Parameters: +* void +* +* Return: +* The contents of the status register +* +* Side Effects: +* Status register bits may be clear on read. +* +*******************************************************************************/ +uint8 Timer_1_ReadStatusRegister(void) +{ + return (Timer_1_STATUS); +} + + +#if (!Timer_1_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_ReadControlRegister +******************************************************************************** +* +* Summary: +* Reads the control register and returns it's value. +* +* Parameters: +* void +* +* Return: +* The contents of the control register +* +*******************************************************************************/ +uint8 Timer_1_ReadControlRegister(void) +{ + return ((uint8)Timer_1_CONTROL); +} + + +/******************************************************************************* +* Function Name: Timer_1_WriteControlRegister +******************************************************************************** +* +* Summary: +* Sets the bit-field of the control register. +* +* Parameters: +* control: The contents of the control register +* +* Return: +* +*******************************************************************************/ +void Timer_1_WriteControlRegister(uint8 control) +{ + Timer_1_CONTROL = control; +} +#endif /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_ReadPeriod +******************************************************************************** +* +* Summary: +* This function returns the current value of the Period. +* +* Parameters: +* void +* +* Return: +* The present value of the counter. +* +*******************************************************************************/ +uint16 Timer_1_ReadPeriod(void) +{ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_PERIOD_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_PERIOD_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_1_WritePeriod +******************************************************************************** +* +* Summary: +* This function is used to change the period of the counter. The new period +* will be loaded the next time terminal count is detected. +* +* Parameters: +* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will +* result in the counter remaining at zero. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_WritePeriod(uint16 period) +{ + #if(Timer_1_UsingFixedFunction) + uint16 period_temp = (uint16)period; + CY_SET_REG16(Timer_1_PERIOD_LSB_PTR, period_temp); + #else + CY_SET_REG16(Timer_1_PERIOD_LSB_PTR, period); + #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCapture +******************************************************************************** +* +* Summary: +* This function returns the last value captured. +* +* Parameters: +* void +* +* Return: +* Present Capture value. +* +*******************************************************************************/ +uint16 Timer_1_ReadCapture(void) +{ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Timer_1_WriteCounter +******************************************************************************** +* +* Summary: +* This funtion is used to set the counter to a specific value +* +* Parameters: +* counter: New counter value. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_WriteCounter(uint16 counter) \ + +{ + #if(Timer_1_UsingFixedFunction) + /* This functionality is removed until a FixedFunction HW update to + * allow this register to be written + */ + CY_SET_REG16(Timer_1_COUNTER_LSB_PTR, (uint16)counter); + + #else + CY_SET_REG16(Timer_1_COUNTER_LSB_PTR, counter); + #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */ +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCounter +******************************************************************************** +* +* Summary: +* This function returns the current counter value. +* +* Parameters: +* void +* +* Return: +* Present compare value. +* +*******************************************************************************/ +uint16 Timer_1_ReadCounter(void) +{ + + /* Force capture by reading Accumulator */ + /* Must first do a software capture to be able to read the counter */ + /* It is up to the user code to make sure there isn't already captured data in the FIFO */ + (void)Timer_1_COUNTER_LSB; + + /* Read the data from the FIFO (or capture register for Fixed Function)*/ + #if(Timer_1_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Timer_1_CAPTURE_LSB_PTR)); + #endif /* (Timer_1_UsingFixedFunction) */ +} + + +#if(!Timer_1_UsingFixedFunction) /* UDB Specific Functions */ + +/******************************************************************************* + * The functions below this point are only available using the UDB + * implementation. If a feature is selected, then the API is enabled. + ******************************************************************************/ + + +#if (Timer_1_SoftwareCaptureMode) + + +/******************************************************************************* +* Function Name: Timer_1_SetCaptureMode +******************************************************************************** +* +* Summary: +* This function sets the capture mode to either rising or falling edge. +* +* Parameters: +* captureMode: This parameter sets the capture mode of the UDB capture feature +* The parameter values are defined using the +* #define Timer_1__B_TIMER__CM_NONE 0 +#define Timer_1__B_TIMER__CM_RISINGEDGE 1 +#define Timer_1__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_1__B_TIMER__CM_EITHEREDGE 3 +#define Timer_1__B_TIMER__CM_SOFTWARE 4 + identifiers +* The following are the possible values of the parameter +* Timer_1__B_TIMER__CM_NONE - Set Capture mode to None +* Timer_1__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input +* Timer_1__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input +* Timer_1__B_TIMER__CM_EITHEREDGE - Either edge of Capture input +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetCaptureMode(uint8 captureMode) +{ + /* This must only set to two bits of the control register associated */ + captureMode = ((uint8)((uint8)captureMode << Timer_1_CTRL_CAP_MODE_SHIFT)); + captureMode &= (Timer_1_CTRL_CAP_MODE_MASK); + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_CAP_MODE_MASK)); + + /* Write The New Setting */ + Timer_1_CONTROL |= captureMode; +} +#endif /* Remove API if Capture Mode is not Software Controlled */ + + +#if (Timer_1_SoftwareTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_1_SetTriggerMode +******************************************************************************** +* +* Summary: +* This function sets the trigger input mode +* +* Parameters: +* triggerMode: Pass one of the pre-defined Trigger Modes (except Software) + #define Timer_1__B_TIMER__TM_NONE 0x00u + #define Timer_1__B_TIMER__TM_RISINGEDGE 0x04u + #define Timer_1__B_TIMER__TM_FALLINGEDGE 0x08u + #define Timer_1__B_TIMER__TM_EITHEREDGE 0x0Cu + #define Timer_1__B_TIMER__TM_SOFTWARE 0x10u +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetTriggerMode(uint8 triggerMode) +{ + /* This must only set to two bits of the control register associated */ + triggerMode &= Timer_1_CTRL_TRIG_MODE_MASK; + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_TRIG_MODE_MASK)); + + /* Write The New Setting */ + Timer_1_CONTROL |= (triggerMode | Timer_1__B_TIMER__TM_SOFTWARE); + +} +#endif /* Remove API if Trigger Mode is not Software Controlled */ + +#if (Timer_1_EnableTriggerMode) + + +/******************************************************************************* +* Function Name: Timer_1_EnableTrigger +******************************************************************************** +* +* Summary: +* Sets the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_EnableTrigger(void) +{ + #if (!Timer_1_ControlRegRemoved) /* Remove assignment if control register is removed */ + Timer_1_CONTROL |= Timer_1_CTRL_TRIG_EN; + #endif /* Remove code section if control register is not used */ +} + + +/******************************************************************************* +* Function Name: Timer_1_DisableTrigger +******************************************************************************** +* +* Summary: +* Clears the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_DisableTrigger(void) +{ + #if (!Timer_1_ControlRegRemoved) /* Remove assignment if control register is removed */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_TRIG_EN)); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API is Trigger Mode is set to None */ + + +#if(Timer_1_InterruptOnCaptureCount) +#if (!Timer_1_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: Timer_1_SetInterruptCount +******************************************************************************** +* +* Summary: +* This function sets the capture count before an interrupt is triggered. +* +* Parameters: +* interruptCount: A value between 0 and 3 is valid. If the value is 0, then +* an interrupt will occur each time a capture occurs. +* A value of 1 to 3 will cause the interrupt +* to delay by the same number of captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetInterruptCount(uint8 interruptCount) +{ + /* This must only set to two bits of the control register associated */ + interruptCount &= Timer_1_CTRL_INTCNT_MASK; + + /* Clear the Current Setting */ + Timer_1_CONTROL &= ((uint8)(~Timer_1_CTRL_INTCNT_MASK)); + /* Write The New Setting */ + Timer_1_CONTROL |= interruptCount; +} +#endif /* Remove API if control register is removed */ +#endif /* Timer_1_InterruptOnCaptureCount */ + + +#if (Timer_1_UsingHWCaptureCounter) + + +/******************************************************************************* +* Function Name: Timer_1_SetCaptureCount +******************************************************************************** +* +* Summary: +* This function sets the capture count +* +* Parameters: +* captureCount: A value between 2 and 127 inclusive is valid. A value of 1 +* to 127 will cause the interrupt to delay by the same number of +* captures. +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_SetCaptureCount(uint8 captureCount) +{ + Timer_1_CAP_COUNT = captureCount; +} + + +/******************************************************************************* +* Function Name: Timer_1_ReadCaptureCount +******************************************************************************** +* +* Summary: +* This function reads the capture count setting +* +* Parameters: +* void +* +* Return: +* Returns the Capture Count Setting +* +*******************************************************************************/ +uint8 Timer_1_ReadCaptureCount(void) +{ + return ((uint8)Timer_1_CAP_COUNT); +} +#endif /* Timer_1_UsingHWCaptureCounter */ + + +/******************************************************************************* +* Function Name: Timer_1_ClearFIFO +******************************************************************************** +* +* Summary: +* This function clears all capture data from the capture FIFO +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Timer_1_ClearFIFO(void) +{ + while(0u != (Timer_1_ReadStatusRegister() & Timer_1_STATUS_FIFONEMP)) + { + (void)Timer_1_ReadCapture(); + } +} + +#endif /* UDB Specific Functions */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.h new file mode 100644 index 0000000..9fbf5b6 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1.h @@ -0,0 +1,439 @@ +/******************************************************************************* +* File Name: Timer_1.h +* Version 2.50 +* +* Description: +* Contains the function prototypes and constants available to the timer +* user module. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CY_Timer_v2_30_Timer_1_H) +#define CY_Timer_v2_30_Timer_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + +extern uint8 Timer_1_initVar; + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Timer_v2_50 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5LP) */ + + +/************************************** +* Parameter Defaults +**************************************/ + +#define Timer_1_Resolution 16u +#define Timer_1_UsingFixedFunction 0u +#define Timer_1_UsingHWCaptureCounter 0u +#define Timer_1_SoftwareCaptureMode 0u +#define Timer_1_SoftwareTriggerMode 0u +#define Timer_1_UsingHWEnable 0u +#define Timer_1_EnableTriggerMode 0u +#define Timer_1_InterruptOnCaptureCount 0u +#define Timer_1_RunModeUsed 1u +#define Timer_1_ControlRegRemoved 0u + + +/*************************************** +* Type defines +***************************************/ + + +/************************************************************************** + * Sleep Wakeup Backup structure for Timer Component + *************************************************************************/ +typedef struct +{ + uint8 TimerEnableState; + #if(!Timer_1_UsingFixedFunction) + #if (CY_UDB_V0) + uint16 TimerUdb; /* Timer internal counter value */ + uint16 TimerPeriod; /* Timer Period value */ + uint8 InterruptMaskValue; /* Timer Compare Value */ + #if (Timer_1_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; /* Timer Capture Counter Value */ + #endif /* variable declaration for backing up Capture Counter value*/ + #endif /* variables for non retention registers in CY_UDB_V0 */ + + #if (CY_UDB_V1) + uint16 TimerUdb; + uint8 InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; + #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ + #endif /* (CY_UDB_V1) */ + + #if (!Timer_1_ControlRegRemoved) + uint8 TimerControlRegister; + #endif /* variable declaration for backing up enable state of the Timer */ + #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ +}Timer_1_backupStruct; + + +/*************************************** +* Function Prototypes +***************************************/ + +void Timer_1_Start(void) ; +void Timer_1_Stop(void) ; + +void Timer_1_SetInterruptMode(uint8 interruptMode) ; +uint8 Timer_1_ReadStatusRegister(void) ; +/* Deprecated function. Do not use this in future. Retained for backward compatibility */ +#define Timer_1_GetInterruptSource() Timer_1_ReadStatusRegister() + +#if(!Timer_1_ControlRegRemoved) + uint8 Timer_1_ReadControlRegister(void) ; + void Timer_1_WriteControlRegister(uint8 control) \ + ; +#endif /* (!Timer_1_ControlRegRemoved) */ + +uint16 Timer_1_ReadPeriod(void) ; +void Timer_1_WritePeriod(uint16 period) \ + ; +uint16 Timer_1_ReadCounter(void) ; +void Timer_1_WriteCounter(uint16 counter) \ + ; +uint16 Timer_1_ReadCapture(void) ; +void Timer_1_SoftwareCapture(void) ; + + +#if(!Timer_1_UsingFixedFunction) /* UDB Prototypes */ + #if (Timer_1_SoftwareCaptureMode) + void Timer_1_SetCaptureMode(uint8 captureMode) ; + #endif /* (!Timer_1_UsingFixedFunction) */ + + #if (Timer_1_SoftwareTriggerMode) + void Timer_1_SetTriggerMode(uint8 triggerMode) ; + #endif /* (Timer_1_SoftwareTriggerMode) */ + #if (Timer_1_EnableTriggerMode) + void Timer_1_EnableTrigger(void) ; + void Timer_1_DisableTrigger(void) ; + #endif /* (Timer_1_EnableTriggerMode) */ + + #if(Timer_1_InterruptOnCaptureCount) + #if(!Timer_1_ControlRegRemoved) + void Timer_1_SetInterruptCount(uint8 interruptCount) \ + ; + #endif /* (!Timer_1_ControlRegRemoved) */ + #endif /* (Timer_1_InterruptOnCaptureCount) */ + + #if (Timer_1_UsingHWCaptureCounter) + void Timer_1_SetCaptureCount(uint8 captureCount) \ + ; + uint8 Timer_1_ReadCaptureCount(void) ; + #endif /* (Timer_1_UsingHWCaptureCounter) */ + + void Timer_1_ClearFIFO(void) ; +#endif /* UDB Prototypes */ + +/* Sleep Retention APIs */ +void Timer_1_Init(void) ; +void Timer_1_Enable(void) ; +void Timer_1_SaveConfig(void) ; +void Timer_1_RestoreConfig(void) ; +void Timer_1_Sleep(void) ; +void Timer_1_Wakeup(void) ; + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ +#define Timer_1__B_TIMER__CM_NONE 0 +#define Timer_1__B_TIMER__CM_RISINGEDGE 1 +#define Timer_1__B_TIMER__CM_FALLINGEDGE 2 +#define Timer_1__B_TIMER__CM_EITHEREDGE 3 +#define Timer_1__B_TIMER__CM_SOFTWARE 4 + + + +/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ +#define Timer_1__B_TIMER__TM_NONE 0x00u +#define Timer_1__B_TIMER__TM_RISINGEDGE 0x04u +#define Timer_1__B_TIMER__TM_FALLINGEDGE 0x08u +#define Timer_1__B_TIMER__TM_EITHEREDGE 0x0Cu +#define Timer_1__B_TIMER__TM_SOFTWARE 0x10u + + +/*************************************** +* Initialial Parameter Constants +***************************************/ + +#define Timer_1_INIT_PERIOD 499u +#define Timer_1_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Timer_1_CTRL_CAP_MODE_SHIFT)) +#define Timer_1_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Timer_1_CTRL_TRIG_MODE_SHIFT)) +#if (Timer_1_UsingFixedFunction) + #define Timer_1_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT))) +#else + #define Timer_1_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Timer_1_STATUS_FIFOFULL_INT_MASK_SHIFT))) +#endif /* (Timer_1_UsingFixedFunction) */ +#define Timer_1_INIT_CAPTURE_COUNT (2u) +#define Timer_1_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Timer_1_CTRL_INTCNT_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#if (Timer_1_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ + + + /*************************************** + * Fixed Function Registers + ***************************************/ + + #define Timer_1_STATUS (*(reg8 *) Timer_1_TimerHW__SR0 ) + /* In Fixed Function Block Status and Mask are the same register */ + #define Timer_1_STATUS_MASK (*(reg8 *) Timer_1_TimerHW__SR0 ) + #define Timer_1_CONTROL (*(reg8 *) Timer_1_TimerHW__CFG0) + #define Timer_1_CONTROL2 (*(reg8 *) Timer_1_TimerHW__CFG1) + #define Timer_1_CONTROL2_PTR ( (reg8 *) Timer_1_TimerHW__CFG1) + #define Timer_1_RT1 (*(reg8 *) Timer_1_TimerHW__RT1) + #define Timer_1_RT1_PTR ( (reg8 *) Timer_1_TimerHW__RT1) + + #if (CY_PSOC3 || CY_PSOC5LP) + #define Timer_1_CONTROL3 (*(reg8 *) Timer_1_TimerHW__CFG2) + #define Timer_1_CONTROL3_PTR ( (reg8 *) Timer_1_TimerHW__CFG2) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #define Timer_1_GLOBAL_ENABLE (*(reg8 *) Timer_1_TimerHW__PM_ACT_CFG) + #define Timer_1_GLOBAL_STBY_ENABLE (*(reg8 *) Timer_1_TimerHW__PM_STBY_CFG) + + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerHW__CAP0 ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerHW__CAP0 ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerHW__PER0 ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerHW__PER0 ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerHW__CNT_CMP0 ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerHW__CNT_CMP0 ) + + + /*************************************** + * Register Constants + ***************************************/ + + /* Fixed Function Block Chosen */ + #define Timer_1_BLOCK_EN_MASK Timer_1_TimerHW__PM_ACT_MSK + #define Timer_1_BLOCK_STBY_EN_MASK Timer_1_TimerHW__PM_STBY_MSK + + /* Control Register Bit Locations */ + /* Interrupt Count - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_INTCNT_SHIFT 0x00u + /* Trigger Polarity - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_TRIG_MODE_SHIFT 0x00u + /* Trigger Enable - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_TRIG_EN_SHIFT 0x00u + /* Capture Polarity - Not valid for Fixed Function Block */ + #define Timer_1_CTRL_CAP_MODE_SHIFT 0x00u + /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ + #define Timer_1_CTRL_ENABLE_SHIFT 0x00u + + /* Control Register Bit Masks */ + #define Timer_1_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_1_CTRL_ENABLE_SHIFT)) + + /* Control2 Register Bit Masks */ + /* As defined in Register Map, Part of the TMRX_CFG1 register */ + #define Timer_1_CTRL2_IRQ_SEL_SHIFT 0x00u + #define Timer_1_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Timer_1_CTRL2_IRQ_SEL_SHIFT)) + + #if (CY_PSOC5A) + /* Use CFG1 Mode bits to set run mode */ + /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_MODE_SHIFT 0x01u + #define Timer_1_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Timer_1_CTRL_MODE_SHIFT)) + #endif /* (CY_PSOC5A) */ + #if (CY_PSOC3 || CY_PSOC5LP) + /* Control3 Register Bit Locations */ + #define Timer_1_CTRL_RCOD_SHIFT 0x02u + #define Timer_1_CTRL_ENBL_SHIFT 0x00u + #define Timer_1_CTRL_MODE_SHIFT 0x00u + + /* Control3 Register Bit Masks */ + #define Timer_1_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ + #define Timer_1_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Timer_1_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ + #define Timer_1_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_MODE_SHIFT)) /* Run mode bit mask */ + + #define Timer_1_CTRL_RCOD ((uint8)((uint8)0x03u << Timer_1_CTRL_RCOD_SHIFT)) + #define Timer_1_CTRL_ENBL ((uint8)((uint8)0x80u << Timer_1_CTRL_ENBL_SHIFT)) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ + #define Timer_1_RT1_SHIFT 0x04u + /* Sync TC and CMP bit masks */ + #define Timer_1_RT1_MASK ((uint8)((uint8)0x03u << Timer_1_RT1_SHIFT)) + #define Timer_1_SYNC ((uint8)((uint8)0x03u << Timer_1_RT1_SHIFT)) + #define Timer_1_SYNCDSI_SHIFT 0x00u + /* Sync all DSI inputs with Mask */ + #define Timer_1_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Timer_1_SYNCDSI_SHIFT)) + /* Sync all DSI inputs */ + #define Timer_1_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Timer_1_SYNCDSI_SHIFT)) + + #define Timer_1_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Timer_1_CTRL_MODE_SHIFT)) + #define Timer_1_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Timer_1_CTRL_MODE_SHIFT)) + #define Timer_1_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Timer_1_CTRL_MODE_SHIFT)) + + /* Status Register Bit Locations */ + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_1_STATUS_TC_SHIFT 0x07u + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_1_STATUS_CAPTURE_SHIFT 0x06u + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Timer_1_STATUS_TC_INT_MASK_SHIFT (Timer_1_STATUS_TC_SHIFT - 0x04u) + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT (Timer_1_STATUS_CAPTURE_SHIFT - 0x04u) + + /* Status Register Bit Masks */ + #define Timer_1_STATUS_TC ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + #define Timer_1_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on TC */ + #define Timer_1_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_INT_MASK_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on Capture */ + #define Timer_1_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT)) + +#else /* UDB Registers and Register Constants */ + + + /*************************************** + * UDB Registers + ***************************************/ + + #define Timer_1_STATUS (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG ) + #define Timer_1_STATUS_MASK (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG) + #define Timer_1_STATUS_AUX_CTRL (* (reg8 *) Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG) + #define Timer_1_CONTROL (* (reg8 *) Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG ) + + #if(Timer_1_Resolution <= 8u) /* 8-bit Timer */ + #define Timer_1_CAPTURE_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg8 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #elif(Timer_1_Resolution <= 16u) /* 8-bit Timer */ + #if(CY_PSOC3) /* 8-bit addres space */ + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 16-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg16 *) Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #endif /* CY_PSOC3 */ + #elif(Timer_1_Resolution <= 24u)/* 24-bit Timer */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit Timer */ + #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit address space */ + #define Timer_1_CAPTURE_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_1_CAPTURE_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Timer_1_PERIOD_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_1_PERIOD_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Timer_1_COUNTER_LSB (* (reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #define Timer_1_COUNTER_LSB_PTR ((reg32 *) Timer_1_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #endif /* CY_PSOC3 || CY_PSOC5 */ + #endif + + #if (Timer_1_UsingHWCaptureCounter) + #define Timer_1_CAP_COUNT (*(reg8 *) Timer_1_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_1_CAP_COUNT_PTR ( (reg8 *) Timer_1_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Timer_1_CAPTURE_COUNT_CTRL (*(reg8 *) Timer_1_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #define Timer_1_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Timer_1_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #endif /* (Timer_1_UsingHWCaptureCounter) */ + + + /*************************************** + * Register Constants + ***************************************/ + + /* Control Register Bit Locations */ + #define Timer_1_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ + #define Timer_1_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ + + /* Control Register Bit Masks */ + #define Timer_1_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_INTCNT_SHIFT)) + #define Timer_1_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_TRIG_MODE_SHIFT)) + #define Timer_1_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Timer_1_CTRL_TRIG_EN_SHIFT)) + #define Timer_1_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Timer_1_CTRL_CAP_MODE_SHIFT)) + #define Timer_1_CTRL_ENABLE ((uint8)((uint8)0x01u << Timer_1_CTRL_ENABLE_SHIFT)) + + /* Bit Counter (7-bit) Control Register Bit Definitions */ + /* As defined by the Register map for the AUX Control Register */ + #define Timer_1_CNTR_ENABLE 0x20u + + /* Status Register Bit Locations */ + #define Timer_1_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_TC_INT_MASK_SHIFT Timer_1_STATUS_TC_SHIFT + #define Timer_1_STATUS_CAPTURE_INT_MASK_SHIFT Timer_1_STATUS_CAPTURE_SHIFT + #define Timer_1_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ + #define Timer_1_STATUS_FIFOFULL_INT_MASK_SHIFT Timer_1_STATUS_FIFOFULL_SHIFT + + /* Status Register Bit Masks */ + /* Sticky TC Event Bit-Mask */ + #define Timer_1_STATUS_TC ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + /* Sticky Capture Event Bit-Mask */ + #define Timer_1_STATUS_CAPTURE ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_TC_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_CAPTURE_SHIFT)) + /* NOT-Sticky FIFO Full Bit-Mask */ + #define Timer_1_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFOFULL_SHIFT)) + /* NOT-Sticky FIFO Not Empty Bit-Mask */ + #define Timer_1_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFONEMP_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Timer_1_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Timer_1_STATUS_FIFOFULL_SHIFT)) + + #define Timer_1_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ + + /* Datapath Auxillary Control Register definitions */ + #define Timer_1_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ + #define Timer_1_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ + #define Timer_1_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ + +#endif /* Implementation Specific Registers and Register Constants */ + +#endif /* CY_Timer_v2_30_Timer_1_H */ + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1_PM.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1_PM.c new file mode 100644 index 0000000..897d3a7 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/Timer_1_PM.c @@ -0,0 +1,194 @@ +/******************************************************************************* +* File Name: Timer_1_PM.c +* Version 2.50 +* +* Description: +* This file provides the power management source code to API for the +* Timer. +* +* Note: +* None +* +******************************************************************************* +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Timer_1.h" +static Timer_1_backupStruct Timer_1_backup; + + +/******************************************************************************* +* Function Name: Timer_1_SaveConfig +******************************************************************************** +* +* Summary: +* Save the current user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup: Variables of this global structure are modified to +* store the values of non retention configuration registers when Sleep() API is +* called. +* +*******************************************************************************/ +void Timer_1_SaveConfig(void) +{ + #if (!Timer_1_UsingFixedFunction) + /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + Timer_1_backup.TimerUdb = Timer_1_ReadCounter(); + Timer_1_backup.TimerPeriod = Timer_1_ReadPeriod(); + Timer_1_backup.InterruptMaskValue = Timer_1_STATUS_MASK; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_backup.TimerCaptureCounter = Timer_1_ReadCaptureCount(); + #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + Timer_1_backup.TimerUdb = Timer_1_ReadCounter(); + Timer_1_backup.InterruptMaskValue = Timer_1_STATUS_MASK; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_backup.TimerCaptureCounter = Timer_1_ReadCaptureCount(); + #endif /* Back Up capture counter register */ + #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!Timer_1_ControlRegRemoved) + Timer_1_backup.TimerControlRegister = Timer_1_ReadControlRegister(); + #endif /* Backup the enable state of the Timer component */ + #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */ +} + + +/******************************************************************************* +* Function Name: Timer_1_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup: Variables of this global structure are used to +* restore the values of non retention registers on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_1_RestoreConfig(void) +{ + #if (!Timer_1_UsingFixedFunction) + /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + /* Interrupt State Backup for Critical Region*/ + uint8 Timer_1_interruptState; + + Timer_1_WriteCounter(Timer_1_backup.TimerUdb); + Timer_1_WritePeriod(Timer_1_backup.TimerPeriod); + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Timer_1_interruptState = CyEnterCriticalSection(); + /* Use the interrupt output of the status register for IRQ output */ + Timer_1_STATUS_AUX_CTRL |= Timer_1_STATUS_ACTL_INT_EN_MASK; + /* Exit Critical Region*/ + CyExitCriticalSection(Timer_1_interruptState); + Timer_1_STATUS_MASK =Timer_1_backup.InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_SetCaptureCount(Timer_1_backup.TimerCaptureCounter); + #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + Timer_1_WriteCounter(Timer_1_backup.TimerUdb); + Timer_1_STATUS_MASK =Timer_1_backup.InterruptMaskValue; + #if (Timer_1_UsingHWCaptureCounter) + Timer_1_SetCaptureCount(Timer_1_backup.TimerCaptureCounter); + #endif /* Restore Capture counter register*/ + #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!Timer_1_ControlRegRemoved) + Timer_1_WriteControlRegister(Timer_1_backup.TimerControlRegister); + #endif /* Restore the enable state of the Timer component */ + #endif /* Restore non retention registers in the UDB implementation only */ +} + + +/******************************************************************************* +* Function Name: Timer_1_Sleep +******************************************************************************** +* +* Summary: +* Stop and Save the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup.TimerEnableState: Is modified depending on the +* enable state of the block before entering sleep mode. +* +*******************************************************************************/ +void Timer_1_Sleep(void) +{ + #if(!Timer_1_ControlRegRemoved) + /* Save Counter's enable state */ + if(Timer_1_CTRL_ENABLE == (Timer_1_CONTROL & Timer_1_CTRL_ENABLE)) + { + /* Timer is enabled */ + Timer_1_backup.TimerEnableState = 1u; + } + else + { + /* Timer is disabled */ + Timer_1_backup.TimerEnableState = 0u; + } + #endif /* Back up enable state from the Timer control register */ + Timer_1_Stop(); + Timer_1_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: Timer_1_Wakeup +******************************************************************************** +* +* Summary: +* Restores and enables the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Timer_1_backup.enableState: Is used to restore the enable state of +* block on wakeup from sleep mode. +* +*******************************************************************************/ +void Timer_1_Wakeup(void) +{ + Timer_1_RestoreConfig(); + #if(!Timer_1_ControlRegRemoved) + if(Timer_1_backup.TimerEnableState == 1u) + { /* Enable Timer's operation */ + Timer_1_Enable(); + } /* Do nothing if Timer was disabled before */ + #endif /* Remove this code section if Control register is removed */ +} + + +/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/bitstream.txt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/bitstream.txt index a823340..497927c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/bitstream.txt +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/bitstream.txt @@ -2,7 +2,7 @@ # IDMUX (count=6) 00000000: 00 00 00 00 00 00 # IOPORT_0 (count=7) -00000006: 60 40 00 00 00 00 00 +00000006: 40 40 00 00 00 00 00 # IOPINS0_0 (count=10) 0000000d: 01 00 00 61 60 00 60 00 00 00 # IOPINS1_0 + 0x0000000B (count=5) @@ -19,9 +19,9 @@ # IOPINS1_2 + 0x00000009 (count=5) 00000042: 00 00 00 00 00 # IOPORT_3 (count=7) -00000047: 03 89 00 00 00 00 00 +00000047: 9c 85 00 00 00 00 00 # IOPINS0_3 (count=10) -0000004e: 8f 00 00 8f 80 00 8f 00 00 00 +0000004e: 9f 00 00 9f 80 00 9f 00 00 00 # IOPINS1_3 + 0x0000000B (count=5) 00000058: 00 00 00 00 00 # IOPORT_4 (count=7) @@ -84,63 +84,63 @@ # CYDEV_PM_ACT_CFG2 (count=1) 000000ec: 03 # UDB_1_5_0_CONFIG (count=128) -000000ed: 00 00 01 00 01 01 00 00 52 00 80 00 00 00 01 00 -000000fd: 86 00 38 00 06 00 88 00 86 00 68 00 01 00 00 00 -0000010d: 01 00 00 00 01 00 00 00 00 00 fc 00 40 00 00 00 -0000011d: 1e 01 01 01 70 00 80 00 00 00 22 00 00 00 44 01 -0000012d: 04 00 00 00 00 00 00 51 30 ff 07 ff 40 20 f0 05 -0000013d: 08 00 00 00 40 00 00 00 04 04 04 04 11 01 00 00 -0000014d: 40 a8 40 20 00 00 00 00 00 00 00 00 00 00 00 00 +000000ed: a4 02 00 0d a4 12 00 24 00 12 00 28 80 0d 24 40 +000000fd: 02 00 0d 00 37 4d 48 00 13 10 80 20 a4 4d 00 00 +0000010d: 80 4d 00 00 24 4d 80 00 35 01 ca 32 00 00 24 00 +0000011d: 0f 0f 00 40 f0 30 10 40 20 00 02 22 00 00 40 04 +0000012d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000013d: 00 00 00 00 09 00 00 00 04 04 00 04 00 00 00 00 +0000014d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000015d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_5_1_CONFIG (count=128) -0000016d: 30 00 4c 02 00 07 00 18 2c 2c d1 13 00 c0 00 00 -0000017d: 80 00 10 00 9c 00 22 80 00 21 03 0a 00 00 00 34 -0000018d: 14 00 00 09 00 c0 00 00 09 40 f0 00 00 00 00 00 -0000019d: 00 3f e0 00 1f 00 00 c0 00 80 08 00 00 00 00 40 -000001ad: 45 06 00 00 00 e0 0b 0c 16 ff ff ff 00 00 f0 44 -000001bd: 0c 00 00 00 00 00 00 00 04 04 04 00 01 01 00 00 -000001cd: 00 00 00 00 00 00 c0 00 00 00 40 02 00 00 00 00 +0000016d: 00 00 40 00 01 07 00 08 0c 09 33 06 18 00 26 00 +0000017d: 00 0c 00 03 e8 00 10 00 1b 0f 24 00 00 00 00 00 +0000018d: 00 00 00 00 80 00 00 00 80 00 00 00 80 00 00 00 +0000019d: 40 08 38 04 07 01 80 02 a0 aa 08 00 00 00 41 55 +000001ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001bd: 00 00 00 00 00 00 00 00 04 04 00 04 00 00 00 00 +000001cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000001dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_4_1_CONFIG (count=128) -000001ed: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001fd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000020d: 04 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 -0000021d: 02 00 00 00 04 00 01 00 00 00 00 00 00 00 11 00 +000001ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000001fd: 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 +0000020d: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 +0000021d: 00 00 01 00 02 00 00 00 00 00 00 00 00 00 10 00 0000022d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000023d: 00 00 00 00 01 00 00 00 04 00 00 04 00 10 00 00 +0000023d: 00 00 00 00 40 00 00 00 04 00 00 04 00 00 00 00 0000024d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000025d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_4_0_CONFIG (count=128) -0000026d: d4 00 20 00 07 08 08 11 18 19 21 00 00 11 00 08 -0000027d: 80 19 20 00 00 c8 05 37 28 5d 42 a2 05 01 00 0a -0000028d: 05 19 00 00 05 10 00 41 05 66 00 89 00 00 05 00 -0000029d: 00 20 00 c0 00 1c ff 03 00 00 c0 8c 00 00 00 01 -000002ad: 63 02 50 00 04 de fb 0c 1f ff ff ff 22 00 f0 0c -000002bd: 04 00 00 00 00 00 02 2c 04 04 04 04 00 00 00 00 +0000026d: 05 00 00 00 18 66 21 89 05 19 00 00 d4 11 20 08 +0000027d: 00 01 00 0a 28 c8 42 37 80 5d 20 a2 07 19 08 00 +0000028d: 05 19 00 00 00 08 05 11 05 00 00 00 00 10 05 41 +0000029d: ff 03 00 c0 00 1c 00 20 00 00 03 0e 00 00 00 40 +000002ad: 36 02 50 00 04 de fc 0b 1f ff ff ff 22 00 f0 0c +000002bd: 04 00 00 00 00 00 02 20 04 04 04 04 00 00 00 00 000002cd: 00 00 c0 00 40 01 10 11 c0 01 00 11 40 01 40 01 000002dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_3_0_CONFIG (count=128) -000002ed: a4 00 00 00 24 8d 80 00 a4 42 00 38 02 0d 0d 80 -000002fd: 00 00 24 00 80 8d 00 00 13 10 80 00 00 8d 00 00 -0000030d: a4 8d 00 00 37 31 48 42 35 02 ca 64 80 02 24 0d -0000031d: 0f 80 00 0f f0 70 10 80 20 20 02 08 00 00 40 01 -0000032d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000033d: 00 00 00 00 09 00 00 00 04 04 00 04 00 00 00 00 -0000034d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000002ed: 01 00 00 00 00 00 3c 00 06 01 28 00 26 00 08 00 +000002fd: 26 02 18 00 12 00 20 00 01 00 00 00 00 00 01 00 +0000030d: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 01 00 +0000031d: 1e 00 01 02 00 01 20 01 00 00 02 00 00 00 44 44 +0000032d: 51 04 00 00 00 ec b0 00 0b ff ff ff 00 00 f0 44 +0000033d: 0c 00 00 00 01 00 00 00 04 04 04 04 11 11 00 00 +0000034d: 00 00 00 00 00 00 c0 00 00 00 40 02 00 00 00 00 0000035d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_3_1_CONFIG (count=128) -0000036d: 00 00 00 00 09 00 16 00 08 01 10 06 40 00 00 00 -0000037d: 00 04 00 03 65 00 02 00 0b 07 14 00 00 00 00 00 -0000038d: 00 00 20 00 40 00 00 00 03 00 1c 00 00 00 00 00 -0000039d: 20 04 07 01 18 02 40 00 80 2a 28 00 00 00 41 15 -000003ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003bd: 00 00 00 00 00 00 00 00 04 04 00 04 00 00 00 00 -000003cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000036d: 00 00 00 00 9c 21 22 0a 00 00 00 02 2c 00 d1 34 +0000037d: 30 c0 4c 00 00 00 03 09 80 00 10 80 00 00 00 00 +0000038d: 00 07 00 18 09 40 f0 00 14 2c 00 13 00 c0 00 00 +0000039d: 00 00 1f c0 e0 00 00 3f 00 08 20 00 00 00 00 04 +000003ad: 02 00 00 00 00 00 10 05 18 ff 07 ff 40 20 f0 05 +000003bd: 08 00 00 00 00 00 00 00 04 04 04 00 01 01 00 00 +000003cd: 40 a8 40 20 00 00 00 00 00 00 00 00 00 00 00 00 000003dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_2_1_CONFIG (count=128) @@ -244,23 +244,23 @@ 000008dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_0_0_CONFIG (count=128) -000008ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008fd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000090d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000091d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000092d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000093d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000094d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000008ed: 00 00 00 00 01 00 08 00 00 00 00 00 00 00 00 00 +000008fd: 00 00 00 00 0f 00 00 00 00 00 00 00 02 00 18 00 +0000090d: 04 00 18 00 00 00 00 00 00 00 00 00 00 00 27 00 +0000091d: 10 00 08 00 07 00 20 00 00 00 08 00 00 00 01 00 +0000092d: 24 00 00 00 00 00 00 00 00 ff ff ff 00 00 00 01 +0000093d: 18 00 00 00 01 00 00 00 0b 00 0b 0b 09 99 00 00 +0000094d: 40 00 40 00 40 40 80 00 80 00 80 00 80 00 80 00 0000095d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_0_1_CONFIG (count=128) -0000096d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000097d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000098d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000099d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009bd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000096d: 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 +0000097d: 00 00 00 03 00 00 00 00 00 00 00 07 00 00 00 00 +0000098d: 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 05 +0000099d: 00 00 00 00 00 00 00 07 00 00 00 80 00 00 00 00 +000009ad: 64 00 00 00 00 ec 02 00 07 ff ff ff 00 83 03 01 +000009bd: 18 00 00 00 00 00 08 00 00 04 08 04 10 99 00 00 +000009cd: 40 00 40 00 40 40 80 00 80 00 80 00 80 00 80 00 000009dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_1_1_1_CONFIG (count=128) @@ -331,7 +331,7 @@ # UWRK_B0_WRK_STATCTL_BITS + 0x00000070 (count=32) 00000d2d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d3d: 00 00 0f 0f 00 00 00 00 00 00 00 00 00 00 00 00 +00000d3d: 00 00 00 0f 0f 00 00 00 00 00 00 00 00 00 00 00 # UWRK_B1_WRK_DP_BITS (count=64) 00000d4d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -341,7 +341,7 @@ # UWRK_B1_WRK_STATCTL_BITS + 0x00000070 (count=32) 00000d8d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00000d9d: 00 00 00 00 0d 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_0_0 (count=128) 00000dad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -397,10 +397,10 @@ 0000102d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000103d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000104d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000105d: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000105d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000106d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000107d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000108d: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 +0000108d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000109d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_0_3 (count=128) @@ -414,13 +414,13 @@ 0000111d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI0_3_HV_ROUTING + 0x00000080 (count=128) -0000112d: 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 -0000113d: 00 00 00 00 00 00 00 00 00 00 00 00 04 00 80 00 -0000114d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 +0000112d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000113d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000114d: 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 0000115d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000116d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000117d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000118d: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 +0000118d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000119d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_0_4 (count=128) @@ -435,7 +435,7 @@ # DSI0_4_HV_ROUTING + 0x00000080 (count=128) 0000122d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000123d: 00 00 00 00 00 00 00 00 00 00 40 00 04 00 80 00 +0000123d: 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 0000124d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000125d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000126d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -444,22 +444,22 @@ 0000129d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_0_5 (count=128) -000012ad: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 +000012ad: 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 000012bd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000012cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000012dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000012ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012fd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000130d: 00 00 00 00 04 00 80 00 00 00 00 00 00 00 00 00 +000012fd: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 +0000130d: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 0000131d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI0_5_HV_ROUTING + 0x00000080 (count=128) -0000132d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000132d: 00 01 00 00 04 00 00 00 00 00 00 00 00 00 00 00 0000133d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000134d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000135d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000136d: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000137d: 00 00 00 00 00 00 01 00 01 00 00 00 00 00 00 00 +0000137d: 00 00 00 00 00 00 02 00 01 00 00 00 00 00 00 00 0000138d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000139d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -484,22 +484,22 @@ 0000149d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_1_0 (count=128) -000014ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014bd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014fd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000150d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000151d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000014ad: 04 00 00 00 00 00 00 00 00 00 12 00 00 00 00 00 +000014bd: 82 00 00 00 00 00 00 00 04 00 52 10 00 00 00 00 +000014cd: 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 12 +000014dd: 00 00 00 00 00 00 20 01 00 00 00 00 00 08 00 00 +000014ed: 04 00 80 00 00 00 80 00 00 00 00 00 00 0a 00 20 +000014fd: 00 00 00 00 80 00 80 00 00 0a 40 00 80 00 00 00 +0000150d: 00 00 00 00 01 00 00 02 00 00 00 00 00 00 00 00 +0000151d: 02 00 00 00 00 00 00 00 01 00 00 00 00 00 00 01 # UDB_2_0_HV_ROUTING + 0x00000080 (count=128) 0000152d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000153d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000154d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000153d: 00 00 00 20 00 00 00 00 80 00 00 00 00 00 00 01 +0000154d: 00 04 20 02 00 00 00 00 00 00 00 00 00 00 00 00 0000155d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000156d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000157d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000156d: 04 00 05 00 09 00 00 00 00 00 50 00 a0 00 40 00 +0000157d: 85 00 20 00 00 00 1b 00 10 00 00 00 00 00 11 00 0000158d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000159d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -535,12 +535,12 @@ # UDB_2_1_HV_ROUTING + 0x00000080 (count=128) 0000172d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000173d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000174d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000175d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000173d: 00 00 00 20 00 00 00 00 80 00 00 00 00 00 00 01 +0000174d: 00 04 20 02 00 00 00 00 00 00 00 00 00 00 00 00 +0000175d: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 0000176d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000177d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000178d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000178d: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 0000179d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_0_2 (count=128) @@ -560,7 +560,7 @@ 0000185d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000186d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000187d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000188d: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 +0000188d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000189d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_1_2 (count=128) @@ -575,9 +575,9 @@ # UDB_2_2_HV_ROUTING + 0x00000080 (count=128) 0000192d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000193d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000194d: 00 00 00 00 00 00 00 00 00 00 00 00 00 84 00 00 -0000195d: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000193d: 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 01 +0000194d: 00 04 20 02 00 00 00 00 00 00 00 00 00 00 00 00 +0000195d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000196d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000197d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000198d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -600,27 +600,27 @@ 00001a5d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001a6d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001a7d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a8d: 00 00 00 00 20 00 00 00 00 00 08 00 00 00 00 00 +00001a8d: 00 00 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00001a9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_1_3 (count=128) -00001aad: 40 14 00 40 00 10 00 21 00 08 a4 00 00 00 24 00 -00001abd: 00 40 00 26 40 20 00 04 40 60 04 00 80 10 21 10 -00001acd: 02 24 01 00 20 00 22 00 00 a0 02 20 00 00 00 00 -00001add: 08 20 00 40 00 00 10 01 00 44 00 10 00 00 10 00 -00001aed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001afd: 00 00 00 00 00 00 00 00 00 04 22 80 00 00 00 00 -00001b0d: 00 40 00 00 00 00 00 00 00 00 00 00 00 00 10 05 +00001aad: 20 22 20 01 04 00 00 01 20 00 40 22 00 00 60 08 +00001abd: 88 40 00 00 00 20 00 08 00 48 40 02 04 00 20 10 +00001acd: 00 40 24 08 00 40 00 20 00 00 00 00 42 00 00 1a +00001add: 00 01 00 00 00 00 28 01 00 00 10 00 00 80 90 04 +00001aed: 00 40 00 01 00 00 00 20 12 01 00 00 00 00 00 00 +00001afd: 00 10 00 00 00 04 10 04 00 61 08 00 00 00 00 00 +00001b0d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001b1d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_2_3_HV_ROUTING + 0x00000080 (count=128) -00001b2d: 00 00 00 00 00 00 20 00 40 00 01 00 10 00 00 00 -00001b3d: 00 74 80 14 40 00 00 20 40 04 02 e2 00 20 00 00 -00001b4d: 08 08 00 20 01 00 02 00 00 00 00 00 00 00 00 02 +00001b2d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001b3d: 00 40 10 06 00 00 00 00 60 02 00 00 00 08 80 00 +00001b4d: 88 00 08 08 00 00 10 00 00 00 00 02 00 00 00 20 00001b5d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b6d: ef 00 6e 00 7f 00 00 00 00 00 0f 00 ae 00 2e 00 -00001b7d: 00 00 00 00 00 00 0f 00 08 00 00 00 00 00 00 00 -00001b8d: 00 00 00 00 00 00 c0 00 00 00 08 00 00 00 00 00 +00001b6d: af 00 7f 00 6b 00 00 00 00 00 f0 00 e1 00 74 00 +00001b7d: 29 00 08 00 00 00 0f 00 00 00 00 00 00 00 00 00 +00001b8d: 00 00 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00001b9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_0_4 (count=128) @@ -644,23 +644,23 @@ 00001c9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_1_4 (count=128) -00001cad: 04 20 00 80 00 00 40 00 00 00 0a a0 00 00 00 00 -00001cbd: 08 44 00 02 10 01 00 00 00 00 00 80 00 00 09 01 -00001ccd: 14 10 54 b4 00 00 00 00 00 20 06 00 00 00 00 00 -00001cdd: 00 00 55 20 00 00 00 00 00 54 00 00 00 00 00 00 -00001ced: 14 00 00 02 00 00 00 00 01 26 00 00 00 00 00 00 -00001cfd: 00 28 44 40 00 00 00 00 00 00 00 00 00 81 18 00 -00001d0d: 40 00 00 00 00 00 00 00 0c 54 02 40 00 00 00 00 -00001d1d: 00 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00 +00001cad: 60 06 00 00 00 00 00 00 40 08 00 08 00 00 20 00 +00001cbd: 88 40 20 00 00 00 04 00 40 00 00 00 00 00 10 20 +00001ccd: 00 28 42 10 00 00 00 00 20 02 42 00 00 00 00 00 +00001cdd: 80 28 02 08 00 00 00 00 08 5c 00 04 00 00 00 00 +00001ced: 08 24 00 02 00 00 00 00 01 14 00 12 00 00 00 00 +00001cfd: 00 00 5c 04 00 00 00 00 00 00 00 00 00 00 00 00 +00001d0d: 00 00 00 02 00 08 10 02 9c d0 08 00 00 00 00 00 +00001d1d: 00 00 02 00 00 00 00 00 00 00 00 00 20 00 04 00 # UDB_2_4_HV_ROUTING + 0x00000080 (count=128) -00001d2d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 -00001d3d: 00 01 10 00 00 44 03 96 50 80 00 00 00 22 00 02 -00001d4d: 00 00 00 00 04 20 00 00 00 00 00 00 00 00 00 00 -00001d5d: 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 -00001d6d: 1e 00 0f 00 3f 00 00 00 00 00 07 00 0f 00 0e 00 -00001d7d: 07 00 0c 00 00 00 f0 00 01 00 00 00 00 00 00 00 -00001d8d: 00 00 00 00 00 00 10 00 00 00 40 00 00 00 00 00 +00001d2d: 00 00 00 00 00 00 00 00 48 00 00 00 00 00 00 00 +00001d3d: 08 00 00 00 00 80 80 10 00 00 00 00 28 16 c2 00 +00001d4d: 01 00 20 01 8c 20 02 00 00 21 00 08 00 00 00 00 +00001d5d: 00 00 00 00 00 00 80 40 00 00 00 00 00 00 00 00 +00001d6d: 0f 00 27 00 4f 00 00 00 00 00 0b 00 0f 00 0e 00 +00001d7d: 07 00 0c 00 00 00 00 00 78 00 00 00 00 00 00 00 +00001d8d: 00 00 00 00 00 00 00 00 00 00 50 00 00 00 00 00 00001d9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_0_5 (count=128) @@ -680,27 +680,27 @@ 00001e5d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001e6d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001e7d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e8d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001e8d: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001e9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDBSWITCH_1_5 (count=128) -00001ead: 09 42 00 08 00 10 80 00 00 04 56 00 12 00 28 00 -00001ebd: 02 04 08 02 00 00 40 20 10 90 4c 20 00 00 28 08 -00001ecd: 00 00 08 60 00 00 00 81 00 00 00 00 00 00 00 68 -00001edd: 00 00 00 00 40 20 08 80 08 00 00 00 00 00 c1 14 -00001eed: 00 00 00 01 00 00 80 00 00 00 00 00 00 01 04 40 -00001efd: 06 00 00 00 00 04 40 00 00 00 00 00 00 00 00 00 -00001f0d: 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001ead: 48 02 00 00 04 10 80 02 48 00 48 00 00 20 20 00 +00001ebd: 10 02 42 10 00 40 00 14 08 40 48 01 04 00 20 42 +00001ecd: 02 09 20 00 00 00 80 68 38 00 02 00 00 00 00 00 +00001edd: c8 00 20 00 00 00 10 01 48 82 00 10 00 00 14 00 +00001eed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001efd: 00 00 00 00 00 00 00 00 01 24 80 00 00 00 00 00 +00001f0d: 00 40 00 00 00 00 00 00 00 00 00 00 00 40 14 15 00001f1d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UDB_2_5_HV_ROUTING + 0x00000080 (count=128) -00001f2d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001f2d: 04 00 00 00 01 08 00 02 00 00 00 40 04 00 00 22 00001f3d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001f4d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00001f5d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f6d: 5f 00 7f 00 5f 00 00 00 00 00 e0 00 70 00 f2 00 -00001f7d: 81 00 30 00 00 00 00 00 0e 00 00 00 00 00 00 00 -00001f8d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00001f6d: fd 00 6f 00 ef 00 00 00 00 00 07 00 ae 00 6f 00 +00001f7d: 00 00 00 00 00 00 0f 00 08 00 00 00 00 00 00 00 +00001f8d: 0c 00 00 00 00 00 90 00 00 00 00 00 00 00 00 00 00001f9d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_0 (count=128) @@ -737,7 +737,7 @@ 0000212d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000213d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000214d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000215d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000215d: 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 0000216d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000217d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000218d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -746,7 +746,7 @@ # DSISWITCH_1_2 (count=128) 000021ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000021bd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000021cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000021cd: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000021dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000021ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000021fd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -758,7 +758,7 @@ 0000223d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000224d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000225d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000226d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000226d: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 0000227d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000228d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000229d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -774,13 +774,13 @@ 0000231d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_3_HV_ROUTING + 0x00000080 (count=128) -0000232d: 00 00 00 00 80 00 00 00 00 00 00 10 80 00 00 00 -0000233d: 00 00 00 00 00 00 00 10 00 00 00 00 80 00 00 00 -0000234d: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 +0000232d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000233d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000234d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04 0000235d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000236d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000237d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000238d: 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 +0000238d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 0000239d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_4 (count=128) @@ -794,13 +794,13 @@ 0000241d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_4_HV_ROUTING + 0x00000080 (count=128) -0000242d: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 -0000243d: 00 00 00 00 00 00 00 10 00 00 00 00 80 00 00 00 -0000244d: 00 00 00 00 88 00 00 00 00 00 00 00 00 00 00 00 -0000245d: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00 +0000242d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000243d: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 +0000244d: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 +0000245d: 00 00 00 00 00 00 00 82 00 00 00 00 00 00 00 00 0000246d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000247d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000248d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000248d: 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 0000249d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSISWITCH_1_5 (count=128) @@ -809,23 +809,23 @@ 000024cd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000024dd: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000024ed: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024fd: 08 00 00 00 80 00 00 00 80 00 00 00 00 00 00 10 -0000250d: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 +000024fd: 80 00 00 02 00 00 00 80 00 00 00 00 00 00 00 82 +0000250d: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 0000251d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # DSI3_5_HV_ROUTING + 0x00000080 (count=128) -0000252d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0000252d: 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 80 0000253d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000254d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000255d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000256d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0000257d: 00 00 00 00 e0 00 20 00 40 00 00 00 00 00 00 00 +0000257d: 00 00 00 00 e0 00 a0 00 80 00 00 00 00 00 00 00 0000258d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000259d: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # UCFG_BCTL1 (count=16) -000025ad: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +000025ad: 02 01 10 00 00 00 00 00 00 00 02 01 00 00 00 00 # UCFG_BCTL0 (count=16) -000025bd: 03 00 10 00 00 00 00 00 03 00 01 00 00 00 00 00 +000025bd: 03 00 10 00 00 00 00 00 01 00 03 00 00 00 00 00 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cm3gcc.ld b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cm3gcc.ld index 6b98ccb..34c064c 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cm3gcc.ld +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cm3gcc.ld @@ -34,7 +34,6 @@ EXTERN(__cs3_reset Reset) EXTERN(__cs3_start_asm __cs3_start_asm_generic_m) /* Bring in the interrupt routines & vector */ INCLUDE micro-names.inc -EXTERN(__cs3_interrupt_vector_micro) EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end) /* Provide fall-back values */ @@ -50,10 +49,11 @@ SECTIONS .text : { CREATE_OBJECT_SYMBOLS - __cs3_interrupt_vector = __cs3_interrupt_vector_micro; + PROVIDE(__cs3_interrupt_vector = RomVectors); + *(.romvectors) *(.cs3.interrupt_vector) /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cs3_interrupt_vector_micro, "No interrupt vector"); + ASSERT (. != __cs3_interrupt_vector, "No interrupt vector"); PROVIDE(__cs3_reset = Reset); *(.cs3.reset) @@ -133,7 +133,7 @@ SECTIONS __cs3_regions = .; LONG (0) LONG (__cs3_region_init_ram) - LONG (__cs3_region_start_ram) + LONG (__cs3_region_start_data) LONG (__cs3_region_init_size_ram) LONG (__cs3_region_zero_size_ram) __cs3_regions_end = .; @@ -142,13 +142,23 @@ SECTIONS _etext = .; } >rom - .data : ALIGN(8) + .ramvectors (NOLOAD) : ALIGN(8) { __cs3_region_start_ram = .; *(.cs3.region-head.ram) ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted"); - *(.ramvectors) - + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cs3_region_start_data = .; + KEEP(*(.jcr)) *(.got.plt) *(.got) *(.shdata) @@ -167,12 +177,14 @@ SECTIONS _end = .; __end = .; } >ram AT>rom + __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram); __cs3_region_size_ram = LENGTH(ram); __cs3_region_init_ram = LOADADDR (.data); __cs3_region_init_size_ram = _edata - ADDR (.data); __cs3_region_zero_size_ram = _end - _edata; + .stab 0 (NOLOAD) : { *(.stab) } .stabstr 0 (NOLOAD) : { *(.stabstr) } /* DWARF debug sections. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/config.hex 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:00000001FF diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/core_cm3_psoc5.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/core_cm3_psoc5.h index 7195e81..0809bd6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/core_cm3_psoc5.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/core_cm3_psoc5.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: core_cm3_psoc5.h -* Version 3.30 +* Version 3.40 * * Description: * Provides important type information for the PSoC5. This includes types @@ -11,7 +11,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.c index d8f87b1..c9c2f3b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cyPm.c -* Version 3.30 +* Version 3.40 * * Description: * Provides an API for the power management. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -194,7 +194,7 @@ void CyPmSaveClocks(void) } /* Need to change nothing if master clock source is IMO */ /* Bus clock - save divider and set it, if needed, to divide-by-one */ - cyPmClockBackup.clkBusDiv = ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG; + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG; if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) { CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); @@ -456,7 +456,7 @@ void CyPmRestoreClocks(void) } /* Bus clock - restore divider, if needed */ - if(cyPmClockBackup.clkBusDiv != (((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG)) + if(cyPmClockBackup.clkBusDiv != ((uint16)((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG)) { CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); } @@ -861,7 +861,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * Reentrant: * No * -* Side Effects: +* Side Effects and Restrictions: * For PSoC 5 silicon the wakeup source is not selectable. In this case the * wakeupSource argument is ignored and any of the available wakeup sources will * wake the device. @@ -875,6 +875,15 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * measure Hibernate/Sleep regulator settling time after a reset. The holdoff * delay is measured using rising edges of the 1 kHz ILO. * +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then use of the CTW is not required. +* Refer to the device errata for more information. +* *******************************************************************************/ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) { @@ -912,10 +921,18 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) #if(CY_PSOC3) - /* Hardware buzz expected to be disabled below for TO6 */ + /* Silicon Revision ID is below TO6 */ if(CYDEV_CHIP_REV_ACTUAL < 5u) { + /* Hardware buzz expected to be disabled in Sleep mode */ CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + + /* LVI/HVI requires hardware buzz to be enabled */ + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + CYASSERT(0u != 0u); + } } #endif /* (CY_PSOC3) */ @@ -1399,6 +1416,21 @@ static void CyPmHibSaveSet(void) /* Make the same preparations for Hibernate and Sleep modes */ CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + } @@ -1469,6 +1501,17 @@ static void CyPmHibRestore(void) } #endif /* (!CY_PSOC5A) */ + + + /*************************************************************************** + * Restore power mode wakeup trim registers + ***************************************************************************/ + #if(CY_PSOC3 || CY_PSOC5LP) + + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ } @@ -1720,15 +1763,10 @@ void CyPmFtwSetInterval(uint8 ftwInterval) * * Save timewheels configuration * * Disable FTW and 1PPS (enable and interrupt) * * Reset CTW -* * Save and disable PICU interrupts (PSoC 5) -* * Save and disable PRES-A and PRES-D (PSoC 5) +* * Save and disable PICU interrupts +* * Save and disable PRES-A and PRES-D * - Save and disable LVI/HVI configuration (PSoC 5) * - Save and set to max buzz interval (PSoC 5) -* - If LVI/HVI is enabled than hardware buzz in required (PSoC 3): -* * Prepare wake trim registers -* * Disable LDO-A in proper way -* - If LVI/HVI is disabled than hardware buzz in not required (PSoC 3): -* * Disabled hardware buzz * - CyPmHibSlpSaveSet() function is called * * Parameters: @@ -1796,53 +1834,6 @@ static void CyPmSlpSaveSet(void) #endif /* (CY_PSOC5A) */ - #if(CY_PSOC3) - - /*************************************************************************** - * If LVI/HVI is enabled than hardware buzz in required: - * - Prepare wake trim registers - * - Disable LDO-A in proper way - * - * If LVI/HVI is disabled than hardware buzz in not required: - * - Disabled hardware buzz - ***************************************************************************/ - - cyPmBackup.wakeTr2 = CY_PM_PWRSYS_WAKE_TR2_REG; - - /* Reconfigure power mode wakeup trim registers */ - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - /* HVI/LVI is enabled - hardware buzz is required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Update entire register */ - CY_PM_PWRSYS_WAKE_TR2_REG = 0x3Bu; - - /* Prepares for disabling LDO-A by moving bandgap reference to VCCD */ - CY_PM_PWRSYS_CR1_REG = 0x01u; - - /* Disables LDO-A */ - CY_PM_PWRSYS_CR1_REG |= 0x02u; - } - else - { - /* For later revisions, just enable buzz */ - CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; - } - } - else - { - /* HVI/LVI is disabled - hardware buzz is not required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Update entire register */ - CY_PM_PWRSYS_WAKE_TR2_REG = 0x3Au; - } - } - - #endif /* (CY_PSOC3) */ - /* Apply configuration that are same for Sleep and Hibernate */ CyPmHibSlpSaveSet(); } @@ -1857,7 +1848,6 @@ static void CyPmSlpSaveSet(void) * - Restore timewheel configuration (PSoC 5) * - Restore PRES-A and PRES-D (PSoC 5) * - Restore PICU interrupts (PSoC 5) -* - Restore LVI/HVI configuration (PSoC 3) * - Restore buzz sleep trim value (PSoC 5) * - Call to CyPmHibSlpSaveRestore() * @@ -1897,28 +1887,6 @@ static void CyPmSlpRestore(void) #endif /* (CY_PSOC5A) */ - #if(CY_PSOC3) - - CY_PM_PWRSYS_WAKE_TR2_REG = cyPmBackup.wakeTr2; - - /* HVI/LVI is enabled - hardware buzz is required */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Reconfigure power mode wakeup trim registers */ - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - /* Enables LDO-A */ - CY_PM_PWRSYS_CR1_REG &= ((uint8)(~0x02u)); - - /* Moves bandgap reference back to VCCA */ - CY_PM_PWRSYS_CR1_REG &= ((uint8)(~0x01u)); - } - } - - #endif /* (CY_PSOC3) */ - - /* Restore configuration that are same for Sleep and Hibernate */ CyPmHibSlpRestore(); } diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.h index 2fe6960..6ed1b86 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyPm.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cyPm.h -* Version 3.30 +* Version 3.40 * * Description: * Provides the function definitions for the power management API. @@ -10,7 +10,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -294,8 +294,6 @@ typedef struct cyPmBackupStruct #if(CY_PSOC5A) uint8 buzzSleepTrim; - #else - uint8 wakeTr2; #endif /* (CY_PSOC5A) */ @@ -315,6 +313,14 @@ typedef struct cyPmBackupStruct #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #if(CY_PSOC3 || CY_PSOC5LP) + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) uint8 scctData[28u]; /* SC/CT routing registers */ @@ -737,6 +743,23 @@ typedef struct cyPmBackupStruct #define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC5LP) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5LP) */ + + /******************************************************************************* * Following code are OBSOLETE and must not be used starting from cy_boot 3.30 *******************************************************************************/ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice.h index f8f10d6..de859e6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice.h @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice_trm.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice_trm.h index e19ba93..6533208 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice_trm.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevice_trm.h @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevice_trm.h * -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu.inc index 284b5cd..e36a2e1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu.inc @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu_trm.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu_trm.inc index 2ebd420..d31a488 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu_trm.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicegnu_trm.inc @@ -1,13 +1,13 @@ /******************************************************************************* * FILENAME: cydevicegnu_trm.inc * -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * DESCRIPTION: * This file provides all of the address values for the entire PSoC device. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv.inc index 14ab3ab..c151e4e 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; FILENAME: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 2.2 Component Pack 5 +; PSoC Creator 2.2 Component Pack 6 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv_trm.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv_trm.inc index 25cf87f..797aeb8 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv_trm.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; FILENAME: cydevicerv_trm.inc ; -; PSoC Creator 2.2 Component Pack 5 +; PSoC Creator 2.2 Component Pack 6 ; ; DESCRIPTION: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter.h index 1892547..1047567 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter.h @@ -3,6 +3,80 @@ #include #include +/* Timer_1_TimerUDB */ +#define Timer_1_TimerUDB_nrstSts_stsreg__0__MASK 0x01u +#define Timer_1_TimerUDB_nrstSts_stsreg__0__POS 0 +#define Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define Timer_1_TimerUDB_nrstSts_stsreg__2__MASK 0x04u +#define Timer_1_TimerUDB_nrstSts_stsreg__2__POS 2 +#define Timer_1_TimerUDB_nrstSts_stsreg__3__MASK 0x08u +#define Timer_1_TimerUDB_nrstSts_stsreg__3__POS 3 +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK 0x0Du +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG CYREG_B1_UDB04_MSK +#define Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG CYREG_B1_UDB04_ST +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK 0x80u +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS 7 +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG CYREG_B1_UDB04_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG CYREG_B1_UDB04_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK 0x80u +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG CYREG_B1_UDB04_MSK +#define Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG CYREG_B1_UDB04_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG CYREG_B1_UDB04_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG CYREG_B1_UDB04_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG CYREG_B1_UDB04_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG CYREG_B1_UDB04_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG CYREG_B1_UDB04_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG CYREG_B1_UDB05_06_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG CYREG_B1_UDB05_06_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG CYREG_B1_UDB05_06_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG CYREG_B1_UDB05_06_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG CYREG_B1_UDB05_06_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG CYREG_B1_UDB05_06_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG CYREG_B1_UDB05_A0_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG CYREG_B1_UDB05_A0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG CYREG_B1_UDB05_A1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG CYREG_B1_UDB05_D0_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG CYREG_B1_UDB05_D0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG CYREG_B1_UDB05_D1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG CYREG_B1_UDB05_F0_F1 +#define Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG CYREG_B1_UDB05_F0 +#define Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG CYREG_B1_UDB05_F1 + /* SPIM_IntClock */ #define SPIM_IntClock__CFG0 CYREG_CLKDIST_DCFG0_CFG0 #define SPIM_IntClock__CFG1 CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ #define SPIM_IntClock__PM_STBY_MSK 0x01u /* UART_1_BUART */ -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB01_02_A0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB01_02_A1 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB01_02_D0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB01_02_D1 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB01_02_F0 -#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB01_02_F1 -#define UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB01_A0_A1 -#define UART_1_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB01_A0 -#define UART_1_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB01_A1 -#define UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB01_D0_D1 -#define UART_1_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB01_D0 -#define UART_1_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB01_D1 -#define UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB01_F0_F1 -#define UART_1_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB01_F0 -#define UART_1_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB01_F1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define UART_1_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB04_A0 +#define UART_1_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB04_A1 +#define UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define UART_1_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB04_D0 +#define UART_1_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB04_D1 +#define UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define UART_1_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB04_F0 +#define UART_1_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB04_F1 #define UART_1_BUART_sTX_TxSts__0__MASK 0x01u #define UART_1_BUART_sTX_TxSts__0__POS 0 -#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST #define UART_1_BUART_sTX_TxSts__1__MASK 0x02u #define UART_1_BUART_sTX_TxSts__1__POS 1 #define UART_1_BUART_sTX_TxSts__2__MASK 0x04u @@ -43,26 +117,26 @@ #define UART_1_BUART_sTX_TxSts__3__MASK 0x08u #define UART_1_BUART_sTX_TxSts__3__POS 3 #define UART_1_BUART_sTX_TxSts__MASK 0x0Fu -#define UART_1_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB02_MSK -#define UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define UART_1_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB02_ST -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB00_01_A0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB00_01_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB00_01_D0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB00_01_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB00_01_F0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB00_01_F1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB00_A0_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB00_A0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB00_A1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB00_D0_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB00_D0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB00_D1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB00_F0_F1 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB00_F0 -#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB00_F1 +#define UART_1_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB04_MSK +#define UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define UART_1_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB04_ST +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB05_06_A0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB05_06_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB05_06_D0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB05_06_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB05_06_F0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB05_06_F1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB05_A0_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB05_A0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB05_A1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB05_D0_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB05_D0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB05_D1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB05_F0_F1 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB05_F0 +#define UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB05_F1 /* LCD_LCDPort */ #define LCD_LCDPort__0__MASK 0x01u @@ -243,8 +317,8 @@ #define SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define SPIM_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB03_MSK #define SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST #define SPIM_BSPIM_RxStsReg__4__MASK 0x10u #define SPIM_BSPIM_RxStsReg__4__POS 4 #define SPIM_BSPIM_RxStsReg__5__MASK 0x20u @@ -252,13 +326,13 @@ #define SPIM_BSPIM_RxStsReg__6__MASK 0x40u #define SPIM_BSPIM_RxStsReg__6__POS 6 #define SPIM_BSPIM_RxStsReg__MASK 0x70u -#define SPIM_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB00_MSK -#define SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define SPIM_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB00_ST +#define SPIM_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB02_MSK +#define SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SPIM_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB02_ST #define SPIM_BSPIM_TxStsReg__0__MASK 0x01u #define SPIM_BSPIM_TxStsReg__0__POS 0 -#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST #define SPIM_BSPIM_TxStsReg__1__MASK 0x02u #define SPIM_BSPIM_TxStsReg__1__POS 1 #define SPIM_BSPIM_TxStsReg__2__MASK 0x04u @@ -268,9 +342,9 @@ #define SPIM_BSPIM_TxStsReg__4__MASK 0x10u #define SPIM_BSPIM_TxStsReg__4__POS 4 #define SPIM_BSPIM_TxStsReg__MASK 0x1Fu -#define SPIM_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK -#define SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SPIM_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST +#define SPIM_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB00_MSK +#define SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define SPIM_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB00_ST #define SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB03_04_A0 #define SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB03_04_A1 #define SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ #define Pin_4__SHIFT 3 #define Pin_4__SLW CYREG_PRT3_SLW +/* Pin_5 */ +#define Pin_5__0__MASK 0x10u +#define Pin_5__0__PC CYREG_PRT3_PC4 +#define Pin_5__0__PORT 3u +#define Pin_5__0__SHIFT 4 +#define Pin_5__AG CYREG_PRT3_AG +#define Pin_5__AMUX CYREG_PRT3_AMUX +#define Pin_5__BIE CYREG_PRT3_BIE +#define Pin_5__BIT_MASK CYREG_PRT3_BIT_MASK +#define Pin_5__BYP CYREG_PRT3_BYP +#define Pin_5__CTL CYREG_PRT3_CTL +#define Pin_5__DM0 CYREG_PRT3_DM0 +#define Pin_5__DM1 CYREG_PRT3_DM1 +#define Pin_5__DM2 CYREG_PRT3_DM2 +#define Pin_5__DR CYREG_PRT3_DR +#define Pin_5__INP_DIS CYREG_PRT3_INP_DIS +#define Pin_5__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define Pin_5__LCD_EN CYREG_PRT3_LCD_EN +#define Pin_5__MASK 0x10u +#define Pin_5__PORT 3u +#define Pin_5__PRT CYREG_PRT3_PRT +#define Pin_5__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define Pin_5__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define Pin_5__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define Pin_5__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define Pin_5__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define Pin_5__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define Pin_5__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define Pin_5__PS CYREG_PRT3_PS +#define Pin_5__SHIFT 4 +#define Pin_5__SLW CYREG_PRT3_SLW + /* Tx_1 */ #define Tx_1__0__MASK 0x80u #define Tx_1__0__PC CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ /* SS */ #define SS_Async_ctrl_reg__0__MASK 0x01u #define SS_Async_ctrl_reg__0__POS 0 -#define SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SS_Async_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SS_Async_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK #define SS_Async_ctrl_reg__1__MASK 0x02u #define SS_Async_ctrl_reg__1__POS 1 -#define SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SS_Async_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SS_Async_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SS_Async_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SS_Async_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define SS_Async_ctrl_reg__MASK 0x03u -#define SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SS_Async_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -#define SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SS_Async_ctrl_reg__2__MASK 0x04u +#define SS_Async_ctrl_reg__2__POS 2 +#define SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SS_Async_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SS_Async_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SS_Async_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SS_Async_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SS_Async_ctrl_reg__MASK 0x07u +#define SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SS_Async_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL /* Miscellaneous */ /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ @@ -494,16 +602,17 @@ #define CYDEV_CONFIG_FASTBOOT_ENABLED 0 #define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u -#define CYDEV_CHIP_MEMBER_5A 2u +#define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_FAMILY_PSOC5 3u -#define CYDEV_CHIP_DIE_PANTHER 2u +#define CYDEV_CHIP_DIE_PANTHER 3u #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PANTHER #define BCLK__BUS_CLK__HZ 24000000U #define BCLK__BUS_CLK__KHZ 24000U #define BCLK__BUS_CLK__MHZ 24U #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC5LP 3u +#define CYDEV_CHIP_DIE_PSOC4A 2u +#define CYDEV_CHIP_DIE_PSOC5LP 4u #define CYDEV_CHIP_DIE_UNKNOWN 0u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u @@ -511,13 +620,16 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x0E13C069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_5B 3u +#define CYDEV_CHIP_MEMBER_4A 2u +#define CYDEV_CHIP_MEMBER_5B 4u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5A #define CYDEV_CHIP_REVISION_3A_ES1 0u #define CYDEV_CHIP_REVISION_3A_ES2 1u #define CYDEV_CHIP_REVISION_3A_ES3 3u #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u @@ -530,6 +642,8 @@ #define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u #define CYDEV_CHIP_REV_PANTHER_ES0 0u #define CYDEV_CHIP_REV_PANTHER_ES1 1u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u #define CYDEV_CHIP_REV_PSOC5LP_ES0 0u #define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u #define CYDEV_CONFIGURATION_COMPRESSED 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.c index 2a4057a..b5c3dfb 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.c @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.c -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator with device @@ -8,7 +8,7 @@ * CyClockStartupError(), this file should not be modified. * ******************************************************************************** -* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -110,7 +110,7 @@ static void CyClockStartupError(uint8 errorCode) { volatile uint8 * const addr8 = (volatile uint8 *)addr; uint32 i; - for (i = 0; i < count; i++) + for (i = 0u; i < count; i++) { addr8[i] = 0u; } @@ -142,7 +142,7 @@ static void CyClockStartupError(uint8 errorCode) volatile uint8 * const dest8 = (volatile uint8 *)dest; const uint8 * const src8 = (const uint8 *)src; uint32 i; - for (i = 0; i < count; i++) + for (i = 0u; i < count; i++) { dest8[i] = src8[i]; } @@ -217,80 +217,107 @@ static void CyClockStartupError(uint8 errorCode) /* UDB_1_3_1_CONFIG Address: CYDEV_UCFG_B0_P2_U1_BASE Size (bytes): 128 */ #define BS_UDB_1_3_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000280u) +/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ +#define BS_UDB_1_0_0_CONFIG_VAL ((const uint8 CYFAR *)0x48000300u) + +/* UDB_1_0_1_CONFIG Address: CYDEV_UCFG_B1_P2_U1_BASE Size (bytes): 128 */ +#define BS_UDB_1_0_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000380u) + /* UWRK_B0_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u Size (bytes): 32 */ -#define BS_UWRK_B0_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000300u) +#define BS_UWRK_B0_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000400u) -/* DSI0_2_HV_ROUTING Address: CYDEV_UCFG_DSI7_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000320u) +/* UWRK_B1_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u Size (bytes): 32 */ +#define BS_UWRK_B1_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)0x48000420u) /* DSI0_3_HV_ROUTING Address: CYDEV_UCFG_DSI6_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480003A0u) +#define BS_DSI0_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000440u) /* DSI0_4_HV_ROUTING Address: CYDEV_UCFG_DSI5_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000420u) +#define BS_DSI0_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480004C0u) /* DSISWITCH_0_5 Address: CYDEV_UCFG_DSI4_BASE Size (bytes): 128 */ -#define BS_DSISWITCH_0_5_VAL ((const uint8 CYFAR *)0x480004A0u) +#define BS_DSISWITCH_0_5_VAL ((const uint8 CYFAR *)0x48000540u) /* DSI0_5_HV_ROUTING Address: CYDEV_UCFG_DSI4_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI0_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000520u) +#define BS_DSI0_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480005C0u) + +/* UDBSWITCH_1_0 Address: CYDEV_UCFG_B1_P2_ROUTE_BASE Size (bytes): 128 */ +#define BS_UDBSWITCH_1_0_VAL ((const uint8 CYFAR *)0x48000640u) -/* UDB_1_2_HV_ROUTING Address: CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_1_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480005A0u) +/* UDB_2_0_HV_ROUTING Address: CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_2_0_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480006C0u) + +/* UDB_2_1_HV_ROUTING Address: CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_2_1_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000740u) /* UDB_2_2_HV_ROUTING Address: CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000620u) +#define BS_UDB_2_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480007C0u) /* UDB_1_3_HV_ROUTING Address: CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_1_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480006A0u) +#define BS_UDB_1_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000840u) /* UDBSWITCH_1_3 Address: CYDEV_UCFG_B0_P2_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_3_VAL ((const uint8 CYFAR *)0x48000720u) +#define BS_UDBSWITCH_1_3_VAL ((const uint8 CYFAR *)0x480008C0u) /* UDB_2_3_HV_ROUTING Address: CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480007A0u) +#define BS_UDB_2_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000940u) /* UDBSWITCH_1_4 Address: CYDEV_UCFG_B0_P1_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_4_VAL ((const uint8 CYFAR *)0x48000820u) +#define BS_UDBSWITCH_1_4_VAL ((const uint8 CYFAR *)0x480009C0u) /* UDB_2_4_HV_ROUTING Address: CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480008A0u) +#define BS_UDB_2_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000A40u) + +/* UDB_1_5_HV_ROUTING Address: CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_UDB_1_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000AC0u) /* UDBSWITCH_1_5 Address: CYDEV_UCFG_B0_P0_ROUTE_BASE Size (bytes): 128 */ -#define BS_UDBSWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000920u) +#define BS_UDBSWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000B40u) /* UDB_2_5_HV_ROUTING Address: CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_UDB_2_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x480009A0u) +#define BS_UDB_2_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000BC0u) + +/* DSI3_1_HV_ROUTING Address: CYDEV_UCFG_DSI8_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_DSI3_1_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000C40u) + +/* DSISWITCH_1_2 Address: CYDEV_UCFG_DSI3_BASE Size (bytes): 128 */ +#define BS_DSISWITCH_1_2_VAL ((const uint8 CYFAR *)0x48000CC0u) + +/* DSI3_2_HV_ROUTING Address: CYDEV_UCFG_DSI3_BASE + 0x00000080u Size (bytes): 128 */ +#define BS_DSI3_2_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000D40u) /* DSI3_3_HV_ROUTING Address: CYDEV_UCFG_DSI2_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000A20u) +#define BS_DSI3_3_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000DC0u) /* DSI3_4_HV_ROUTING Address: CYDEV_UCFG_DSI1_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000AA0u) +#define BS_DSI3_4_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000E40u) /* DSISWITCH_1_5 Address: CYDEV_UCFG_DSI0_BASE Size (bytes): 128 */ -#define BS_DSISWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000B20u) +#define BS_DSISWITCH_1_5_VAL ((const uint8 CYFAR *)0x48000EC0u) /* DSI3_5_HV_ROUTING Address: CYDEV_UCFG_DSI0_BASE + 0x00000080u Size (bytes): 128 */ -#define BS_DSI3_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000BA0u) +#define BS_DSI3_5_HV_ROUTING_VAL ((const uint8 CYFAR *)0x48000F40u) + +/* UCFG_BCTL1 Address: CYREG_BCTL1_MDCLK_EN Size (bytes): 16 */ +#define BS_UCFG_BCTL1_VAL ((const uint8 CYFAR *)0x48000FC0u) /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ -#define BS_UCFG_BCTL0_VAL ((const uint8 CYFAR *)0x48000C20u) +#define BS_UCFG_BCTL0_VAL ((const uint8 CYFAR *)0x48000FD0u) /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ -#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000C30u) +#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000FE0u) /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ -#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000C3Cu) +#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000FECu) /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ -#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000C44u) +#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000FF4u) /* IOPORT_0 Address: CYDEV_PRTDSI_PRT0_BASE Size (bytes): 7 */ -#define BS_IOPORT_0_VAL ((const uint8 CYFAR *)0x48000C50u) +#define BS_IOPORT_0_VAL ((const uint8 CYFAR *)0x48001000u) /* IOPORT_3 Address: CYDEV_PRTDSI_PRT3_BASE Size (bytes): 7 */ -#define BS_IOPORT_3_VAL ((const uint8 CYFAR *)0x48000C58u) +#define BS_IOPORT_3_VAL ((const uint8 CYFAR *)0x48001008u) /******************************************************************************* @@ -358,44 +385,52 @@ static void cfg_dma_init(void) { 16u, 0x0Cu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYREG_PRT12_DR) }, /* TD 11 */ { 16u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYREG_PRT15_DR) }, /* TD 12 */ { 384u, 0x0Eu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_U0_BASE) }, /* TD 13 */ - { 384u, 0x0Fu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_U0_BASE) }, /* TD 14 */ - { 384u, 0x10u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_U0_BASE) }, /* TD 15 */ - { 1024u, 0x11u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P6_U0_BASE) }, /* TD 16 */ - { 2048u, 0x12u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U0_BASE) }, /* TD 17 */ + { 896u, 0x0Fu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_U0_BASE) }, /* TD 14 */ + { 896u, 0x10u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P6_U0_BASE) }, /* TD 15 */ + { 384u, 0x11u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P3_U0_BASE) }, /* TD 16 */ + { 1024u, 0x12u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P4_U0_BASE) }, /* TD 17 */ { 128u, 0x13u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE) }, /* TD 18 */ { 128u, 0x14u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE) }, /* TD 19 */ - { 256u, 0x15u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE) }, /* TD 20 */ - { 128u, 0x16u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE) }, /* TD 21 */ - { 128u, 0x17u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE) }, /* TD 22 */ - { 128u, 0x18u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE) }, /* TD 23 */ - { 512u, 0x19u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI8_BASE) }, /* TD 24 */ - { 512u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI12_BASE) }, /* TD 25 */ - { 32u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u) }, /* TD 26 */ + { 128u, 0x15u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE) }, /* TD 20 */ + { 128u, 0x16u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE) }, /* TD 21 */ + { 384u, 0x17u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE) }, /* TD 22 */ + { 256u, 0x18u, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI9_BASE) }, /* TD 23 */ + { 512u, 0xFFu, 0x22u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI12_BASE) }, /* TD 24 */ + { 32u, 0x1Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u) }, /* TD 25 */ + { 32u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u) }, /* TD 26 */ { 128u, 0x1Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_U0_BASE) }, /* TD 27 */ { 128u, 0x1Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_U1_BASE) }, /* TD 28 */ { 128u, 0x1Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_U0_BASE) }, /* TD 29 */ { 128u, 0x1Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_U1_BASE) }, /* TD 30 */ { 128u, 0x20u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_U0_BASE) }, /* TD 31 */ { 128u, 0x21u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_U1_BASE) }, /* TD 32 */ - { 128u, 0x22u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI7_BASE + 0x00000080u) }, /* TD 33 */ - { 128u, 0x23u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE + 0x00000080u) }, /* TD 34 */ - { 128u, 0x24u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE + 0x00000080u) }, /* TD 35 */ - { 128u, 0x25u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE) }, /* TD 36 */ - { 128u, 0x26u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE + 0x00000080u) }, /* TD 37 */ - { 128u, 0x27u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u) }, /* TD 38 */ - { 128u, 0x28u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u) }, /* TD 39 */ - { 128u, 0x29u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u) }, /* TD 40 */ - { 128u, 0x2Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE) }, /* TD 41 */ - { 128u, 0x2Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u) }, /* TD 42 */ - { 128u, 0x2Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE) }, /* TD 43 */ - { 128u, 0x2Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u) }, /* TD 44 */ - { 128u, 0x2Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE) }, /* TD 45 */ - { 128u, 0x2Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u) }, /* TD 46 */ - { 128u, 0x30u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE + 0x00000080u) }, /* TD 47 */ - { 128u, 0x31u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE + 0x00000080u) }, /* TD 48 */ - { 128u, 0x32u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE) }, /* TD 49 */ - { 128u, 0x33u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE + 0x00000080u) }, /* TD 50 */ - { 16u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL0_MDCLK_EN) }, /* TD 51 */ + { 128u, 0x22u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U0_BASE) }, /* TD 33 */ + { 128u, 0x23u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_U1_BASE) }, /* TD 34 */ + { 128u, 0x24u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI6_BASE + 0x00000080u) }, /* TD 35 */ + { 128u, 0x25u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI5_BASE + 0x00000080u) }, /* TD 36 */ + { 128u, 0x26u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE) }, /* TD 37 */ + { 128u, 0x27u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI4_BASE + 0x00000080u) }, /* TD 38 */ + { 128u, 0x28u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE) }, /* TD 39 */ + { 128u, 0x29u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u) }, /* TD 40 */ + { 128u, 0x2Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u) }, /* TD 41 */ + { 128u, 0x2Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u) }, /* TD 42 */ + { 128u, 0x2Cu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u) }, /* TD 43 */ + { 128u, 0x2Du, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE) }, /* TD 44 */ + { 128u, 0x2Eu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u) }, /* TD 45 */ + { 128u, 0x2Fu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE) }, /* TD 46 */ + { 128u, 0x30u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u) }, /* TD 47 */ + { 128u, 0x31u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u) }, /* TD 48 */ + { 128u, 0x32u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE) }, /* TD 49 */ + { 128u, 0x33u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u) }, /* TD 50 */ + { 128u, 0x34u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI8_BASE + 0x00000080u) }, /* TD 51 */ + { 128u, 0x35u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE) }, /* TD 52 */ + { 128u, 0x36u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI3_BASE + 0x00000080u) }, /* TD 53 */ + { 128u, 0x37u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI2_BASE + 0x00000080u) }, /* TD 54 */ + { 128u, 0x38u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI1_BASE + 0x00000080u) }, /* TD 55 */ + { 128u, 0x39u, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE) }, /* TD 56 */ + { 128u, 0x3Au, 0x23u, (uint16)(uint32)(0u), (uint16)(CYDEV_UCFG_DSI0_BASE + 0x00000080u) }, /* TD 57 */ + { 16u, 0x3Bu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL1_MDCLK_EN) }, /* TD 58 */ + { 16u, 0xFFu, 0x23u, (uint16)(uint32)(0u), (uint16)(CYREG_BCTL0_MDCLK_EN) }, /* TD 59 */ }; /* Source addresses can be relocated, but only when in 32bit addresses. @@ -428,33 +463,41 @@ static void cfg_dma_init(void) (const void *)(&DMA_ZERO_VAL), /* TD 22 */ (const void *)(&DMA_ZERO_VAL), /* TD 23 */ (const void *)(&DMA_ZERO_VAL), /* TD 24 */ - (const void *)(&DMA_ZERO_VAL), /* TD 25 */ - (const void *)(BS_UWRK_B0_WRK_STATCTL_BITS_VAL), /* TD 26 */ + (const void *)(BS_UWRK_B0_WRK_STATCTL_BITS_VAL), /* TD 25 */ + (const void *)(BS_UWRK_B1_WRK_STATCTL_BITS_VAL), /* TD 26 */ (const void *)(BS_UDB_1_5_0_CONFIG_VAL), /* TD 27 */ (const void *)(BS_UDB_1_5_1_CONFIG_VAL), /* TD 28 */ (const void *)(BS_UDB_1_4_1_CONFIG_VAL), /* TD 29 */ (const void *)(BS_UDB_1_4_0_CONFIG_VAL), /* TD 30 */ (const void *)(BS_UDB_1_3_0_CONFIG_VAL), /* TD 31 */ (const void *)(BS_UDB_1_3_1_CONFIG_VAL), /* TD 32 */ - (const void *)(BS_DSI0_2_HV_ROUTING_VAL), /* TD 33 */ - (const void *)(BS_DSI0_3_HV_ROUTING_VAL), /* TD 34 */ - (const void *)(BS_DSI0_4_HV_ROUTING_VAL), /* TD 35 */ - (const void *)(BS_DSISWITCH_0_5_VAL), /* TD 36 */ - (const void *)(BS_DSI0_5_HV_ROUTING_VAL), /* TD 37 */ - (const void *)(BS_UDB_1_2_HV_ROUTING_VAL), /* TD 38 */ - (const void *)(BS_UDB_2_2_HV_ROUTING_VAL), /* TD 39 */ - (const void *)(BS_UDB_1_3_HV_ROUTING_VAL), /* TD 40 */ - (const void *)(BS_UDBSWITCH_1_3_VAL), /* TD 41 */ - (const void *)(BS_UDB_2_3_HV_ROUTING_VAL), /* TD 42 */ - (const void *)(BS_UDBSWITCH_1_4_VAL), /* TD 43 */ - (const void *)(BS_UDB_2_4_HV_ROUTING_VAL), /* TD 44 */ - (const void *)(BS_UDBSWITCH_1_5_VAL), /* TD 45 */ - (const void *)(BS_UDB_2_5_HV_ROUTING_VAL), /* TD 46 */ - (const void *)(BS_DSI3_3_HV_ROUTING_VAL), /* TD 47 */ - (const void *)(BS_DSI3_4_HV_ROUTING_VAL), /* TD 48 */ - (const void *)(BS_DSISWITCH_1_5_VAL), /* TD 49 */ - (const void *)(BS_DSI3_5_HV_ROUTING_VAL), /* TD 50 */ - (const void *)(BS_UCFG_BCTL0_VAL), /* TD 51 */ + (const void *)(BS_UDB_1_0_0_CONFIG_VAL), /* TD 33 */ + (const void *)(BS_UDB_1_0_1_CONFIG_VAL), /* TD 34 */ + (const void *)(BS_DSI0_3_HV_ROUTING_VAL), /* TD 35 */ + (const void *)(BS_DSI0_4_HV_ROUTING_VAL), /* TD 36 */ + (const void *)(BS_DSISWITCH_0_5_VAL), /* TD 37 */ + (const void *)(BS_DSI0_5_HV_ROUTING_VAL), /* TD 38 */ + (const void *)(BS_UDBSWITCH_1_0_VAL), /* TD 39 */ + (const void *)(BS_UDB_2_0_HV_ROUTING_VAL), /* TD 40 */ + (const void *)(BS_UDB_2_1_HV_ROUTING_VAL), /* TD 41 */ + (const void *)(BS_UDB_2_2_HV_ROUTING_VAL), /* TD 42 */ + (const void *)(BS_UDB_1_3_HV_ROUTING_VAL), /* TD 43 */ + (const void *)(BS_UDBSWITCH_1_3_VAL), /* TD 44 */ + (const void *)(BS_UDB_2_3_HV_ROUTING_VAL), /* TD 45 */ + (const void *)(BS_UDBSWITCH_1_4_VAL), /* TD 46 */ + (const void *)(BS_UDB_2_4_HV_ROUTING_VAL), /* TD 47 */ + (const void *)(BS_UDB_1_5_HV_ROUTING_VAL), /* TD 48 */ + (const void *)(BS_UDBSWITCH_1_5_VAL), /* TD 49 */ + (const void *)(BS_UDB_2_5_HV_ROUTING_VAL), /* TD 50 */ + (const void *)(BS_DSI3_1_HV_ROUTING_VAL), /* TD 51 */ + (const void *)(BS_DSISWITCH_1_2_VAL), /* TD 52 */ + (const void *)(BS_DSI3_2_HV_ROUTING_VAL), /* TD 53 */ + (const void *)(BS_DSI3_3_HV_ROUTING_VAL), /* TD 54 */ + (const void *)(BS_DSI3_4_HV_ROUTING_VAL), /* TD 55 */ + (const void *)(BS_DSISWITCH_1_5_VAL), /* TD 56 */ + (const void *)(BS_DSI3_5_HV_ROUTING_VAL), /* TD 57 */ + (const void *)(BS_UCFG_BCTL1_VAL), /* TD 58 */ + (const void *)(BS_UCFG_BCTL0_VAL), /* TD 59 */ }; @@ -464,7 +507,7 @@ static void cfg_dma_init(void) CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CFGMEM0_CFG0, 0x10u); /* set burstcnt */ CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CH0_BASIC_CFG, 0x01u); /* enable ch0 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH0_BASIC_STATUS+1u), 0x00u); /* set first TD to 0 */ - CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0, 51u*8u); /* transfer size */ + CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0, 59u*8u); /* transfer size */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+2u), 0x01u); /* set next TD to 1 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+3u), 0x03u); /* set TD flags */ CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD1, (uint16)(uint32)CFG_TD_LIST0); /* set td0's src addr */ @@ -473,7 +516,7 @@ static void cfg_dma_init(void) CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_CFGMEM0_CFG1+2u), (uint16)(CYDEV_PHUB_TDMEM1_BASE >> 16)); /* set ch0's dst high addr */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH1_BASIC_STATUS+1u), 0x09u); /* ch1 first TD: 9 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH2_BASIC_STATUS+1u), 0x0Du); /* ch2 first TD: 13 */ - CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH5_BASIC_STATUS+1u), 0x1Au); /* ch5 first TD: 26 */ + CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH5_BASIC_STATUS+1u), 0x19u); /* ch5 first TD: 25 */ CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH6_BASIC_STATUS+1u), 0x1Bu); /* ch6 first TD: 27 */ CY_CFG_MEMORY_BARRIER(); @@ -484,7 +527,7 @@ static void cfg_dma_init(void) while (CY_GET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0) != 0u) { } /* Recombine TD source table (CFG_TD_ADDR0) with full TD table (CFG_TD_LIST0) */ - for (i = 0u; i < 51u; i++) + for (i = 0u; i < 59u; i++) { CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_TDMEM1_ORIG_TD1 + (sizeof(struct td_t)*i)), (uint16)(uint32)CFG_TD_ADDR0[i]); } @@ -527,15 +570,13 @@ static void cfg_dma_init(void) static void ClockSetup(void); static void ClockSetup(void) { - uint32 timeout; - uint8 pllLock; /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x000Bu); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2), 0x18u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0019u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2), 0x18u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u); @@ -548,12 +589,8 @@ static void ClockSetup(void) /* Configure PLL based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0008u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u); - /* Wait up to 250us for the PLL to lock */ - pllLock = 0u; - for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { - pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); - CyDelayCycles(10u * 12u); /* Delay 10us based on 12MHz clock */ - } + /* Wait 250us for the PLL to lock */ + CyDelayCycles(250u * 12u); /* Delay 250us based on 12MHz clock */ /* Configure Bus/Master Clock based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x03u); @@ -653,6 +690,7 @@ void SetAnalogRoutingPumps(uint8 enabled) * void * *******************************************************************************/ + void cyfitter_cfg(void) { #ifdef CYGlobalIntDisable diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.h index e3c9cdf..06bfc82 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitter_cfg.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cyfitter_cfg.h -* PSoC Creator 2.2 Component Pack 5 +* PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfittergnu.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfittergnu.inc index 96bbbe9..2c4dc87 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfittergnu.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfittergnu.inc @@ -3,6 +3,80 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" +/* Timer_1_TimerUDB */ +.set Timer_1_TimerUDB_nrstSts_stsreg__0__MASK, 0x01 +.set Timer_1_TimerUDB_nrstSts_stsreg__0__POS, 0 +.set Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set Timer_1_TimerUDB_nrstSts_stsreg__2__MASK, 0x04 +.set Timer_1_TimerUDB_nrstSts_stsreg__2__POS, 2 +.set Timer_1_TimerUDB_nrstSts_stsreg__3__MASK, 0x08 +.set Timer_1_TimerUDB_nrstSts_stsreg__3__POS, 3 +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK, 0x0D +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG, CYREG_B1_UDB04_MSK +.set Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG, CYREG_B1_UDB04_ST +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK, 0x80 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS, 7 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG, CYREG_B1_UDB04_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG, CYREG_B1_UDB04_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK, 0x80 +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG, CYREG_B1_UDB04_MSK +.set Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG, CYREG_B1_UDB05_06_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG, CYREG_B1_UDB05_06_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG, CYREG_B1_UDB05_06_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG, CYREG_B1_UDB05_06_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG, CYREG_B1_UDB05_06_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG, CYREG_B1_UDB05_06_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG, CYREG_B1_UDB05_A0_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG, CYREG_B1_UDB05_A0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG, CYREG_B1_UDB05_A1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG, CYREG_B1_UDB05_D0_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG, CYREG_B1_UDB05_D0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG, CYREG_B1_UDB05_D1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG, CYREG_B1_UDB05_F0_F1 +.set Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG, CYREG_B1_UDB05_F0 +.set Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG, CYREG_B1_UDB05_F1 + /* SPIM_IntClock */ .set SPIM_IntClock__CFG0, CYREG_CLKDIST_DCFG0_CFG0 .set SPIM_IntClock__CFG1, CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ .set SPIM_IntClock__PM_STBY_MSK, 0x01 /* UART_1_BUART */ -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG, CYREG_B0_UDB01_02_A0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG, CYREG_B0_UDB01_02_A1 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG, CYREG_B0_UDB01_02_D0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG, CYREG_B0_UDB01_02_D1 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG, CYREG_B0_UDB01_02_F0 -.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG, CYREG_B0_UDB01_02_F1 -.set UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG, CYREG_B0_UDB01_A0_A1 -.set UART_1_BUART_sTX_TxShifter_u0__A0_REG, CYREG_B0_UDB01_A0 -.set UART_1_BUART_sTX_TxShifter_u0__A1_REG, CYREG_B0_UDB01_A1 -.set UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG, CYREG_B0_UDB01_D0_D1 -.set UART_1_BUART_sTX_TxShifter_u0__D0_REG, CYREG_B0_UDB01_D0 -.set UART_1_BUART_sTX_TxShifter_u0__D1_REG, CYREG_B0_UDB01_D1 -.set UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG, CYREG_B0_UDB01_F0_F1 -.set UART_1_BUART_sTX_TxShifter_u0__F0_REG, CYREG_B0_UDB01_F0 -.set UART_1_BUART_sTX_TxShifter_u0__F1_REG, CYREG_B0_UDB01_F1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set UART_1_BUART_sTX_TxShifter_u0__A0_REG, CYREG_B0_UDB04_A0 +.set UART_1_BUART_sTX_TxShifter_u0__A1_REG, CYREG_B0_UDB04_A1 +.set UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set UART_1_BUART_sTX_TxShifter_u0__D0_REG, CYREG_B0_UDB04_D0 +.set UART_1_BUART_sTX_TxShifter_u0__D1_REG, CYREG_B0_UDB04_D1 +.set UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set UART_1_BUART_sTX_TxShifter_u0__F0_REG, CYREG_B0_UDB04_F0 +.set UART_1_BUART_sTX_TxShifter_u0__F1_REG, CYREG_B0_UDB04_F1 .set UART_1_BUART_sTX_TxSts__0__MASK, 0x01 .set UART_1_BUART_sTX_TxSts__0__POS, 0 -.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST .set UART_1_BUART_sTX_TxSts__1__MASK, 0x02 .set UART_1_BUART_sTX_TxSts__1__POS, 1 .set UART_1_BUART_sTX_TxSts__2__MASK, 0x04 @@ -43,26 +117,26 @@ .set UART_1_BUART_sTX_TxSts__3__MASK, 0x08 .set UART_1_BUART_sTX_TxSts__3__POS, 3 .set UART_1_BUART_sTX_TxSts__MASK, 0x0F -.set UART_1_BUART_sTX_TxSts__MASK_REG, CYREG_B0_UDB02_MSK -.set UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set UART_1_BUART_sTX_TxSts__STATUS_REG, CYREG_B0_UDB02_ST -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG, CYREG_B0_UDB00_01_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG, CYREG_B0_UDB00_01_D0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG, CYREG_B0_UDB00_01_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG, CYREG_B0_UDB00_01_F0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG, CYREG_B0_UDB00_01_F1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG, CYREG_B0_UDB00_A0_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG, CYREG_B0_UDB00_A0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG, CYREG_B0_UDB00_A1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG, CYREG_B0_UDB00_D0_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG, CYREG_B0_UDB00_D0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG, CYREG_B0_UDB00_D1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG, CYREG_B0_UDB00_F0_F1 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG, CYREG_B0_UDB00_F0 -.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG, CYREG_B0_UDB00_F1 +.set UART_1_BUART_sTX_TxSts__MASK_REG, CYREG_B0_UDB04_MSK +.set UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set UART_1_BUART_sTX_TxSts__STATUS_REG, CYREG_B0_UDB04_ST +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG, CYREG_B0_UDB05_A0_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG, CYREG_B0_UDB05_A0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG, CYREG_B0_UDB05_A1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG, CYREG_B0_UDB05_D0_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG, CYREG_B0_UDB05_D0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG, CYREG_B0_UDB05_D1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG, CYREG_B0_UDB05_F0_F1 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG, CYREG_B0_UDB05_F0 +.set UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG, CYREG_B0_UDB05_F1 /* LCD_LCDPort */ .set LCD_LCDPort__0__MASK, 0x01 @@ -243,8 +317,8 @@ .set SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set SPIM_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB03_MSK .set SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST .set SPIM_BSPIM_RxStsReg__4__MASK, 0x10 .set SPIM_BSPIM_RxStsReg__4__POS, 4 .set SPIM_BSPIM_RxStsReg__5__MASK, 0x20 @@ -252,13 +326,13 @@ .set SPIM_BSPIM_RxStsReg__6__MASK, 0x40 .set SPIM_BSPIM_RxStsReg__6__POS, 6 .set SPIM_BSPIM_RxStsReg__MASK, 0x70 -.set SPIM_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB00_MSK -.set SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set SPIM_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB00_ST +.set SPIM_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB02_MSK +.set SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SPIM_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB02_ST .set SPIM_BSPIM_TxStsReg__0__MASK, 0x01 .set SPIM_BSPIM_TxStsReg__0__POS, 0 -.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST .set SPIM_BSPIM_TxStsReg__1__MASK, 0x02 .set SPIM_BSPIM_TxStsReg__1__POS, 1 .set SPIM_BSPIM_TxStsReg__2__MASK, 0x04 @@ -268,9 +342,9 @@ .set SPIM_BSPIM_TxStsReg__4__MASK, 0x10 .set SPIM_BSPIM_TxStsReg__4__POS, 4 .set SPIM_BSPIM_TxStsReg__MASK, 0x1F -.set SPIM_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK -.set SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SPIM_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST +.set SPIM_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB00_MSK +.set SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set SPIM_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB00_ST .set SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 .set SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 .set SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ .set Pin_4__SHIFT, 3 .set Pin_4__SLW, CYREG_PRT3_SLW +/* Pin_5 */ +.set Pin_5__0__MASK, 0x10 +.set Pin_5__0__PC, CYREG_PRT3_PC4 +.set Pin_5__0__PORT, 3 +.set Pin_5__0__SHIFT, 4 +.set Pin_5__AG, CYREG_PRT3_AG +.set Pin_5__AMUX, CYREG_PRT3_AMUX +.set Pin_5__BIE, CYREG_PRT3_BIE +.set Pin_5__BIT_MASK, CYREG_PRT3_BIT_MASK +.set Pin_5__BYP, CYREG_PRT3_BYP +.set Pin_5__CTL, CYREG_PRT3_CTL +.set Pin_5__DM0, CYREG_PRT3_DM0 +.set Pin_5__DM1, CYREG_PRT3_DM1 +.set Pin_5__DM2, CYREG_PRT3_DM2 +.set Pin_5__DR, CYREG_PRT3_DR +.set Pin_5__INP_DIS, CYREG_PRT3_INP_DIS +.set Pin_5__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set Pin_5__LCD_EN, CYREG_PRT3_LCD_EN +.set Pin_5__MASK, 0x10 +.set Pin_5__PORT, 3 +.set Pin_5__PRT, CYREG_PRT3_PRT +.set Pin_5__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set Pin_5__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set Pin_5__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set Pin_5__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set Pin_5__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set Pin_5__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set Pin_5__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set Pin_5__PS, CYREG_PRT3_PS +.set Pin_5__SHIFT, 4 +.set Pin_5__SLW, CYREG_PRT3_SLW + /* Tx_1 */ .set Tx_1__0__MASK, 0x80 .set Tx_1__0__PC, CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ /* SS */ .set SS_Async_ctrl_reg__0__MASK, 0x01 .set SS_Async_ctrl_reg__0__POS, 0 -.set SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SS_Async_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SS_Async_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK .set SS_Async_ctrl_reg__1__MASK, 0x02 .set SS_Async_ctrl_reg__1__POS, 1 -.set SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SS_Async_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SS_Async_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SS_Async_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SS_Async_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SS_Async_ctrl_reg__MASK, 0x03 -.set SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SS_Async_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -.set SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SS_Async_ctrl_reg__2__MASK, 0x04 +.set SS_Async_ctrl_reg__2__POS, 2 +.set SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SS_Async_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SS_Async_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SS_Async_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SS_Async_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SS_Async_ctrl_reg__MASK, 0x07 +.set SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SS_Async_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL /* Miscellaneous */ /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ @@ -494,16 +602,17 @@ .set CYDEV_CONFIG_FASTBOOT_ENABLED, 0 .set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 -.set CYDEV_CHIP_MEMBER_5A, 2 +.set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_FAMILY_PSOC5, 3 -.set CYDEV_CHIP_DIE_PANTHER, 2 +.set CYDEV_CHIP_DIE_PANTHER, 3 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PANTHER .set BCLK__BUS_CLK__HZ, 24000000 .set BCLK__BUS_CLK__KHZ, 24000 .set BCLK__BUS_CLK__MHZ, 24 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC5LP, 3 +.set CYDEV_CHIP_DIE_PSOC4A, 2 +.set CYDEV_CHIP_DIE_PSOC5LP, 4 .set CYDEV_CHIP_DIE_UNKNOWN, 0 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 @@ -511,13 +620,16 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x0E13C069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_5B, 3 +.set CYDEV_CHIP_MEMBER_4A, 2 +.set CYDEV_CHIP_MEMBER_5B, 4 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5A .set CYDEV_CHIP_REVISION_3A_ES1, 0 .set CYDEV_CHIP_REVISION_3A_ES2, 1 .set CYDEV_CHIP_REVISION_3A_ES3, 3 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 @@ -530,6 +642,8 @@ .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 .set CYDEV_CHIP_REV_PANTHER_ES0, 0 .set CYDEV_CHIP_REV_PANTHER_ES1, 1 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 .set CYDEV_CONFIGURATION_COMPRESSED, 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitterrv.inc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitterrv.inc index fbcacf6..11eee07 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitterrv.inc +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyfitterrv.inc @@ -3,6 +3,80 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc +; Timer_1_TimerUDB +Timer_1_TimerUDB_nrstSts_stsreg__0__MASK EQU 0x01 +Timer_1_TimerUDB_nrstSts_stsreg__0__POS EQU 0 +Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +Timer_1_TimerUDB_nrstSts_stsreg__2__MASK EQU 0x04 +Timer_1_TimerUDB_nrstSts_stsreg__2__POS EQU 2 +Timer_1_TimerUDB_nrstSts_stsreg__3__MASK EQU 0x08 +Timer_1_TimerUDB_nrstSts_stsreg__3__POS EQU 3 +Timer_1_TimerUDB_nrstSts_stsreg__MASK EQU 0x0D +Timer_1_TimerUDB_nrstSts_stsreg__MASK_REG EQU CYREG_B1_UDB04_MSK +Timer_1_TimerUDB_nrstSts_stsreg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_nrstSts_stsreg__STATUS_REG EQU CYREG_B1_UDB04_ST +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__MASK EQU 0x80 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__7__POS EQU 7 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_REG EQU CYREG_B1_UDB04_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_REG EQU CYREG_B1_UDB04_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK EQU 0x80 +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PERIOD_REG EQU CYREG_B1_UDB04_MSK +Timer_1_TimerUDB_sCTRLReg_AsyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +Timer_1_TimerUDB_sT16_timerdp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +Timer_1_TimerUDB_sT16_timerdp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +Timer_1_TimerUDB_sT16_timerdp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +Timer_1_TimerUDB_sT16_timerdp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +Timer_1_TimerUDB_sT16_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +Timer_1_TimerUDB_sT16_timerdp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +Timer_1_TimerUDB_sT16_timerdp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +Timer_1_TimerUDB_sT16_timerdp_u1__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +Timer_1_TimerUDB_sT16_timerdp_u1__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__A0_REG EQU CYREG_B1_UDB05_A0 +Timer_1_TimerUDB_sT16_timerdp_u1__A1_REG EQU CYREG_B1_UDB05_A1 +Timer_1_TimerUDB_sT16_timerdp_u1__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__D0_REG EQU CYREG_B1_UDB05_D0 +Timer_1_TimerUDB_sT16_timerdp_u1__D1_REG EQU CYREG_B1_UDB05_D1 +Timer_1_TimerUDB_sT16_timerdp_u1__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +Timer_1_TimerUDB_sT16_timerdp_u1__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +Timer_1_TimerUDB_sT16_timerdp_u1__F0_REG EQU CYREG_B1_UDB05_F0 +Timer_1_TimerUDB_sT16_timerdp_u1__F1_REG EQU CYREG_B1_UDB05_F1 + ; SPIM_IntClock SPIM_IntClock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 SPIM_IntClock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 @@ -15,27 +89,27 @@ SPIM_IntClock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SPIM_IntClock__PM_STBY_MSK EQU 0x01 ; UART_1_BUART -UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1 -UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1 -UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0 -UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1 -UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1 -UART_1_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB01_A0 -UART_1_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB01_A1 -UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1 -UART_1_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB01_D0 -UART_1_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB01_D1 -UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1 -UART_1_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB01_F0 -UART_1_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB01_F1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +UART_1_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +UART_1_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +UART_1_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +UART_1_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +UART_1_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB04_A0 +UART_1_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB04_A1 +UART_1_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +UART_1_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB04_D0 +UART_1_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB04_D1 +UART_1_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +UART_1_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +UART_1_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB04_F0 +UART_1_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB04_F1 UART_1_BUART_sTX_TxSts__0__MASK EQU 0x01 UART_1_BUART_sTX_TxSts__0__POS EQU 0 -UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +UART_1_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +UART_1_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST UART_1_BUART_sTX_TxSts__1__MASK EQU 0x02 UART_1_BUART_sTX_TxSts__1__POS EQU 1 UART_1_BUART_sTX_TxSts__2__MASK EQU 0x04 @@ -43,26 +117,26 @@ UART_1_BUART_sTX_TxSts__2__POS EQU 2 UART_1_BUART_sTX_TxSts__3__MASK EQU 0x08 UART_1_BUART_sTX_TxSts__3__POS EQU 3 UART_1_BUART_sTX_TxSts__MASK EQU 0x0F -UART_1_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB02_MSK -UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -UART_1_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB02_ST -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB00_A0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB00_A1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB00_D0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB00_D1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB00_F0 -UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB00_F1 +UART_1_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB04_MSK +UART_1_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +UART_1_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB04_ST +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB05_A0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB05_A1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB05_D0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB05_D1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB05_F0 +UART_1_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB05_F1 ; LCD_LCDPort LCD_LCDPort__0__MASK EQU 0x01 @@ -243,8 +317,8 @@ SPIM_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SPIM_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL SPIM_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB03_MSK SPIM_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +SPIM_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SPIM_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SPIM_BSPIM_RxStsReg__4__MASK EQU 0x10 SPIM_BSPIM_RxStsReg__4__POS EQU 4 SPIM_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -252,13 +326,13 @@ SPIM_BSPIM_RxStsReg__5__POS EQU 5 SPIM_BSPIM_RxStsReg__6__MASK EQU 0x40 SPIM_BSPIM_RxStsReg__6__POS EQU 6 SPIM_BSPIM_RxStsReg__MASK EQU 0x70 -SPIM_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB00_MSK -SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SPIM_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB00_ST +SPIM_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB02_MSK +SPIM_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SPIM_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB02_ST SPIM_BSPIM_TxStsReg__0__MASK EQU 0x01 SPIM_BSPIM_TxStsReg__0__POS EQU 0 -SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SPIM_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SPIM_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST SPIM_BSPIM_TxStsReg__1__MASK EQU 0x02 SPIM_BSPIM_TxStsReg__1__POS EQU 1 SPIM_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -268,9 +342,9 @@ SPIM_BSPIM_TxStsReg__3__POS EQU 3 SPIM_BSPIM_TxStsReg__4__MASK EQU 0x10 SPIM_BSPIM_TxStsReg__4__POS EQU 4 SPIM_BSPIM_TxStsReg__MASK EQU 0x1F -SPIM_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SPIM_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST +SPIM_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB00_MSK +SPIM_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SPIM_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB00_ST SPIM_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 SPIM_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 SPIM_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 @@ -430,6 +504,38 @@ Pin_4__PS EQU CYREG_PRT3_PS Pin_4__SHIFT EQU 3 Pin_4__SLW EQU CYREG_PRT3_SLW +; Pin_5 +Pin_5__0__MASK EQU 0x10 +Pin_5__0__PC EQU CYREG_PRT3_PC4 +Pin_5__0__PORT EQU 3 +Pin_5__0__SHIFT EQU 4 +Pin_5__AG EQU CYREG_PRT3_AG +Pin_5__AMUX EQU CYREG_PRT3_AMUX +Pin_5__BIE EQU CYREG_PRT3_BIE +Pin_5__BIT_MASK EQU CYREG_PRT3_BIT_MASK +Pin_5__BYP EQU CYREG_PRT3_BYP +Pin_5__CTL EQU CYREG_PRT3_CTL +Pin_5__DM0 EQU CYREG_PRT3_DM0 +Pin_5__DM1 EQU CYREG_PRT3_DM1 +Pin_5__DM2 EQU CYREG_PRT3_DM2 +Pin_5__DR EQU CYREG_PRT3_DR +Pin_5__INP_DIS EQU CYREG_PRT3_INP_DIS +Pin_5__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +Pin_5__LCD_EN EQU CYREG_PRT3_LCD_EN +Pin_5__MASK EQU 0x10 +Pin_5__PORT EQU 3 +Pin_5__PRT EQU CYREG_PRT3_PRT +Pin_5__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +Pin_5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +Pin_5__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +Pin_5__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +Pin_5__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +Pin_5__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +Pin_5__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +Pin_5__PS EQU CYREG_PRT3_PS +Pin_5__SHIFT EQU 4 +Pin_5__SLW EQU CYREG_PRT3_SLW + ; Tx_1 Tx_1__0__MASK EQU 0x80 Tx_1__0__PC EQU CYREG_PRT3_PC7 @@ -465,26 +571,28 @@ Tx_1__SLW EQU CYREG_PRT3_SLW ; SS SS_Async_ctrl_reg__0__MASK EQU 0x01 SS_Async_ctrl_reg__0__POS EQU 0 -SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SS_Async_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SS_Async_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SS_Async_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SS_Async_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SS_Async_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SS_Async_ctrl_reg__1__MASK EQU 0x02 SS_Async_ctrl_reg__1__POS EQU 1 -SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SS_Async_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SS_Async_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SS_Async_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SS_Async_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SS_Async_ctrl_reg__MASK EQU 0x03 -SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SS_Async_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SS_Async_ctrl_reg__2__MASK EQU 0x04 +SS_Async_ctrl_reg__2__POS EQU 2 +SS_Async_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SS_Async_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SS_Async_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SS_Async_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SS_Async_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SS_Async_ctrl_reg__MASK EQU 0x07 +SS_Async_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SS_Async_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SS_Async_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL ; Miscellaneous ; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release @@ -494,16 +602,17 @@ CYDEV_CONFIGURATION_MODE_DMA EQU 2 CYDEV_CONFIG_FASTBOOT_ENABLED EQU 0 CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 -CYDEV_CHIP_MEMBER_5A EQU 2 +CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 -CYDEV_CHIP_DIE_PANTHER EQU 2 +CYDEV_CHIP_DIE_PANTHER EQU 3 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PANTHER BCLK__BUS_CLK__HZ EQU 24000000 BCLK__BUS_CLK__KHZ EQU 24000 BCLK__BUS_CLK__MHZ EQU 24 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC5LP EQU 3 +CYDEV_CHIP_DIE_PSOC4A EQU 2 +CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 @@ -511,13 +620,16 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x0E13C069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_5B EQU 3 +CYDEV_CHIP_MEMBER_4A EQU 2 +CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5A CYDEV_CHIP_REVISION_3A_ES1 EQU 0 CYDEV_CHIP_REVISION_3A_ES2 EQU 1 CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 @@ -530,6 +642,8 @@ CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 CYDEV_CONFIGURATION_COMPRESSED EQU 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cypins.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cypins.h index fcb4129..ed01434 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cypins.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cypins.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: cypins.h -* Version 3.30 +* Version 3.40 * * Description: * This file contains the function prototypes and constants used for port/pin @@ -11,7 +11,7 @@ * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cytypes.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cytypes.h index 8fdb501..0187c1b 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cytypes.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cytypes.h @@ -1,6 +1,6 @@ /******************************************************************************* * FILENAME: cytypes.h -* Version 3.30 +* Version 3.40 * * Description: * CyTypes provides register access macros and approved types for use in @@ -17,7 +17,7 @@ * (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -83,7 +83,9 @@ typedef float float32; #if(!CY_PSOC3) - typedef double float64; + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; #endif /* (!CY_PSOC3) */ @@ -167,6 +169,8 @@ typedef char char8; #define CYSMALL small #define CYXDATA xdata #define XDATA xdata + + #define CY_NOINIT #else @@ -183,6 +187,13 @@ typedef char char8; #define CYSMALL #define CYXDATA #define XDATA + + #if defined(__ARMCC_VERSION) + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #elif defined (__GNUC__) + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #endif /* (__ARMCC_VERSION) */ + #endif /* (CY_PSOC3) */ @@ -254,17 +265,17 @@ typedef volatile uint32 CYXDATA reg32; #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ - #define CY_GET_XTND_REG8(addr) cyread8(addr) - #define CY_SET_XTND_REG8(addr, value) cywrite8(addr,value) + #define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) - #define CY_GET_XTND_REG16(addr) cyread16(addr) - #define CY_SET_XTND_REG16(addr, value) cywrite16(addr,value) + #define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) - #define CY_GET_XTND_REG24(addr) cyread24(addr) - #define CY_SET_XTND_REG24(addr, value) cywrite24(addr,value) + #define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) - #define CY_GET_XTND_REG32(addr) cyread32(addr) - #define CY_SET_XTND_REG32(addr, value) cywrite32(addr,value) + #define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) #else diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyutils.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyutils.c index b064c5e..784a00f 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyutils.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/cyutils.c @@ -1,12 +1,12 @@ /******************************************************************************* * FILENAME: cyutils.c -* Version 3.30 +* Version 3.40 * * Description: * CyUtils provides function to handle 24-bit value writes. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/elab_dependencies.txt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/elab_dependencies.txt index a3df7e6..855d4b4 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/elab_dependencies.txt +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/elab_dependencies.txt @@ -1,121 +1,121 @@ -C:\Users\Tore\Desktop\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch +C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\TopDesign\TopDesign.cysch C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.cysym C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.pdf C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80\cy_pins_v1_80.cyprimitive -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80\cy_pins_v1_80.cysym -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80\cy_pins_v1_80.pdf -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80\cy_pins_v1_80.cystate -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80 -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC 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C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\UART_v2_30\UART_v2_30.cysym C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\UART_v2_30\UART_v2_30.pdf @@ -249,44 +249,44 @@ C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprim C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\API\clk.c C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\API\clk.h C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\Custom\custom.cs -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_80\cy_pins_v1_80.cyprimitive -C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC 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+C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cymappingcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyoutputcontrol.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.Designer.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC 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Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinaliasdialog.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cypinscontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyporcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cytypecontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\Resource1.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\Custom\cyclockingcontrol.resx +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\aliases.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v1_90\PSoC5\API\pins.h C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.cysym C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.pdf C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v @@ -310,158 +310,158 @@ C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprim C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_70\Custom\Resources.Designer.cs C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC 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Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\Custom\custom.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Timer_v2_50\B_Timer_v2_50.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\Custom\custom.cs +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\cy_clock_v2_0.cyprimitive +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\cy_clock_v2_0.cysym +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\cy_clock_v2_0.pdf +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\cy_clock_v2_0.cystate +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\API\clk.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\API\clk.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_clock_v2_0\Custom\custom.cs +C:\Users\SB\Dropbox\CentroPiaggio\LSM303D\LSM303D_SPI_PSOC5\PSOC5_SPI_LSM303D.cydsn\PSOC5_SPI_LSM303D.cydwr +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cm3gcc.ld +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\Cm3RealView.scat +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\Cm3Start.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\core_cm3.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\core_cm3.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\core_cm3_psoc5.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyBootAsmGnu.s +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyBootAsmRv.s +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyDmac.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyDmac.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyFlash.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyFlash.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyLib.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CyLib.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cypins.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cyPm.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cyPm.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CySpc.c +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\CySpc.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cytypes.h +C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v3_40\PSoC5\API\cyutils.c diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/generated_files.txt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/generated_files.txt index 330ef5c..28581d5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/generated_files.txt +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/generated_files.txt @@ -1,82 +1,88 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/lcpsoc3/index b/PSOC5_SPI_LSM303D.cydsn/codegentemp/lcpsoc3/index index e03dd3aa31a44361b3d273f17b68f0cae1e4d90e..c5c1de9dffafd458724a8ad7ba7df2b1c5514eaa 100644 GIT binary patch literal 1792 zcmZQzVPQZ3CI*=w5)8@@xXN9Cf&oA_2yBSYVK4x)S3Kh?XJE(zi|qi4IRM4#{&SXJ zy}hdhq&@`5j{#y1ARA=r8z375Kzw#Ei-BQX@QgB$_zoccW97-f3KR$Fg@Xrw>v*6X zMj);H?0_SP3sMt$WLF6@kOpBe0ICJiM}THcE%0El;WlF6_$k4#(H>&%ZXo^mIYd9Q ldXTvwd#`}pH`4vj3JMJv7=iH*^ZF<~8UiCR1V(uN2LKpW)|~(V literal 1792 zcmZQzVPQZ3CI*=w5)8@@ippJpf&oA_2t=f1GZ+BbE1ngVGcaU=#S(yG4nVQG|ApmO zZyzcHsSg42V}O_g$Of7E2FL~h5T6~)VqjPoTwMwh-vPvbtUMW5f#M*&aPZ)79S@Yl z2&CuRO}hi)g4Bc_IaJ0Bq(K-AfNDYX5ujO93p^NXxMwhM{FGqWXb&-WH;|6Ehv-LE k4>A{I?-h{yM!Nr5L7@QyBQXA9ULU1LLtrF^zzEO(08;7LfdBvi diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.c index 29341e2..57a4726 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.h index 273fac5..1b4b352 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin_aliases.h index a2d4f29..c6c88c2 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_miso_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_miso_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.c index 775ddf9..6eee973 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.h index 331acd5..7af1137 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin_aliases.h index 3f51ef6..1bab883 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_mosi_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_mosi_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.c index 2fbcbe2..7e79e33 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.c +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware control of a Pins component. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.h index 2a29717..03edcc5 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines @@ -25,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component cy_pins_v1_80 requires cy_boot v3.0 or later + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ /* APIs are not generated for P15[7:6] */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin_aliases.h index 3530ec1..68472d6 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin_aliases.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_sclk_pin_aliases.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: m_sclk_pin.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Control Register function prototypes and register defines diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/placer.log b/PSOC5_SPI_LSM303D.cydsn/codegentemp/placer.log index ac3d7ce..edfb7cc 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/placer.log +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/placer.log @@ -4,9 +4,9 @@ #Version: 1.1 -#Build Date: Dec 5 2012 10:19:42 +#Build Date: Mar 26 2013 11:48:29 -#File Generated: Mar 22 2013 10:33:26 +#File Generated: Jul 25 2013 16:48:56 #Purpose: @@ -18,7 +18,7 @@ Executing : C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin/sjp Softjin Techologies Placer, Version 1.1 -Build Date : Dec 5 2012 10:22:46 +Build Date : Mar 26 2013 11:50:26 D2004: Option and Settings Summary ============================================================= @@ -44,18 +44,18 @@ Phase 2 Phase 3 Design Statistics after Packing - Number of Combinational MCs : 14 - Number of Sequential MCs : 18 - Number of DPs : 3 - Number of Controls : 2 - Number of Status : 3 - Number of SyncCells : 0 + Number of Combinational MCs : 16 + Number of Sequential MCs : 21 + Number of DPs : 5 + Number of Controls : 3 + Number of Status : 4 + Number of SyncCells : 1 Number of count7cells : 1 Device Utilization Summary after Packing - Macrocells : 32/192 - UDBS : 6/24 - IOs : 15/72 + Macrocells : 37/192 + UDBS : 8/24 + IOs : 16/72 D2088: Phase 3, elapsed time : 0.0 (sec) @@ -81,7 +81,7 @@ analysis after routing. ====================================================================== Number of clocks: 7 Clock: Clock_1 | Frequency: 41.7 MHz | Target: 0.9 MHz -Clock: CyBUS_CLK | Frequency: N/A | Target: 24.0 MHz +Clock: CyBUS_CLK | Frequency: 41.7 MHz | Target: 24.0 MHz Clock: CyILO | Frequency: N/A | Target: 0.0 MHz Clock: CyIMO | Frequency: N/A | Target: 3.0 MHz Clock: CyMASTER_CLK | Frequency: N/A | Target: 24.0 MHz @@ -92,15 +92,15 @@ Clock: SPIM_IntClock | Frequency: 60.3 MHz | Target: 2.0 MHz End of Clock Summary ###################################################################### -D2088: Phase 6, elapsed time : 0.0 (sec) +D2088: Phase 6, elapsed time : 0.1 (sec) Phase 7 ###################################################################### Clock Summary ====================================================================== Number of clocks: 7 -Clock: Clock_1 | Frequency: 43.8 MHz | Target: 0.9 MHz -Clock: CyBUS_CLK | Frequency: N/A | Target: 24.0 MHz +Clock: Clock_1 | Frequency: 40.3 MHz | Target: 0.9 MHz +Clock: CyBUS_CLK | Frequency: 41.7 MHz | Target: 24.0 MHz Clock: CyILO | Frequency: N/A | Target: 0.0 MHz Clock: CyIMO | Frequency: N/A | Target: 3.0 MHz Clock: CyMASTER_CLK | Frequency: N/A | Target: 24.0 MHz @@ -113,18 +113,18 @@ Clock: SPIM_IntClock | Frequency: 61.0 MHz | Target: 2.0 MHz D2088: Phase 7, elapsed time : 0.2 (sec) Final Design Statistics - Number of Combinational MCs : 14 - Number of Sequential MCs : 18 - Number of DPs : 3 - Number of Controls : 2 - Number of Status : 3 - Number of SyncCells : 0 + Number of Combinational MCs : 16 + Number of Sequential MCs : 21 + Number of DPs : 5 + Number of Controls : 3 + Number of Status : 4 + Number of SyncCells : 1 Number of count7cells : 1 - Number of IOs : 15 + Number of IOs : 16 Device Utilization Summary - Macrocells : 32/192 - IOs : 15/72 + Macrocells : 37/192 + IOs : 16/72 @@ -141,13 +141,13 @@ analysis after routing. Clock Summary ====================================================================== Number of clocks: 7 -Clock: Clock_1 | Frequency: 43.8 MHz | Target: 1.0 MHz -Clock: CyBUS_CLK | Frequency: N/A | Target: 24.0 MHz +Clock: Clock_1 | Frequency: 38.2 MHz | Target: 1.0 MHz +Clock: CyBUS_CLK | Frequency: 41.7 MHz | Target: 26.3 MHz Clock: CyILO | Frequency: N/A | Target: 0.0 MHz Clock: CyIMO | Frequency: N/A | Target: 3.0 MHz Clock: CyMASTER_CLK | Frequency: N/A | Target: 24.0 MHz Clock: CyPLL_OUT | Frequency: N/A | Target: 24.0 MHz -Clock: SPIM_IntClock | Frequency: 61.0 MHz | Target: 2.2 MHz +Clock: SPIM_IntClock | Frequency: 58.8 MHz | Target: 2.2 MHz ====================================================================== End of Clock Summary @@ -158,5 +158,5 @@ D2088: Phase 8, elapsed time : 0.0 (sec) D2054: Placement of the design completed successfully -I2076: Total run-time: 1.0 sec. +I2076: Total run-time: 1.1 sec. diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/project.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/project.h index 63c9121..7ac38be 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/project.h +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/project.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: project.h - * PSoC Creator 2.2 Component Pack 5 + * PSoC Creator 2.2 Component Pack 6 * * Description: * This file is automatically generated by PSoC Creator and should not @@ -8,11 +8,12 @@ * * ******************************************************************************** - * Copyright 2008-2011, Cypress Semiconductor Corporation. All rights reserved. + * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. ********************************************************************************/ + #include #include #include @@ -37,6 +38,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -51,3 +55,4 @@ #include /*[]*/ + diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/warp_dependencies.txt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/warp_dependencies.txt index 287fb1e..689b9b7 100644 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/warp_dependencies.txt +++ b/PSOC5_SPI_LSM303D.cydsn/codegentemp/warp_dependencies.txt @@ -20,6 +20,10 @@ C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/psoc/content/cy C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/psoc/content/cyprimitives/CyPrimitives.cylib/not_v1_0/not_v1_0.v : +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/psoc/content/cycomponentlibrary/CyComponentLibrary.cylib/B_Timer_v2_50/B_Timer_v2_50.v : + +C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/psoc/content/cyprimitives/CyPrimitives.cylib/OneTerminal/OneTerminal.v : + C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/warp/lib/common/stdlogic/rtlpkg.vif : C:/Program\ Files\ (x86)/Cypress/PSoC\ Creator/2.2/PSoC\ Creator/warp/lib/common/stdlogic/cy_psoc3.vif : diff --git a/PSOC5_SPI_LSM303D.cydsn/main.c b/PSOC5_SPI_LSM303D.cydsn/main.c index 30cb10d..7bb9663 100644 --- a/PSOC5_SPI_LSM303D.cydsn/main.c +++ b/PSOC5_SPI_LSM303D.cydsn/main.c @@ -2,7 +2,7 @@ #include //operation codes for Control registers -#define RCR 0x80 //Read Control Register +#define RCR 0x80 //Read Control Register 0x80 #define WCR 0x00 //Write Control Register #define ADDR_MASK 0x80 @@ -16,35 +16,14 @@ uint8 ReadControlRegister(uint8 opcode, uint8 address); void WriteControlRegister(uint8 opcode,uint8 address,uint8 dta); - +void start_acc(uint8 n); +void read_acc(uint8 n); +void check_lsm(uint8 n); +uint8 Read1Byte(); +uint8 Write1Byte(uint8 ucData); void main() { - uint8 i = 0u; - uint8 value = 0; - uint8 low, high; - uint16 two_c = 0; - - uint8 low2, high2; - uint16 two_c2 = 0; - - int inc = 0; - int dir = 1; - char OutputString[7]; - char OutputString2[7]; - uint8 ch; /* Data sent on the serial port */ - - int sign; - int sign2; - - int hundreds; - int tens; - int units; - int accX; - - uint16 dec_value; - - /* Software buffers use internal interrupt functionality to interact with * hardware buffers. Thus global interrupt enable command should be called */ @@ -60,401 +39,120 @@ void main() /* We need to start Character LCD, SPI Master and Slave components */ LCD_Start(); + LCD_ClearDisplay(); + SPIM_Start(); SPIM_ClearRxBuffer(); SPIM_ClearTxBuffer(); SPIM_ClearFIFO(); - CyDelay(15);//Wait for it to finish P-O-S-T - + CyDelay(35);//Wait for it to finish P-O-S-T - // ---------- SS #1 ------------ - SS_Write(0); - CyDelay(15); - value=ReadControlRegister(RCR,0x0F); - CyDelay(15); + // check LSM code response + // check_lsm(0); + + + //Start accel + start_acc(0); + start_acc(1); + start_acc(2); + start_acc(3); + start_acc(4); - UART_1_PutString("\r\n"); - UART_1_PutString("#1 is 0x"); - sprintf(OutputString, "%02x", value); - UART_1_PutString(OutputString); - UART_1_PutString("\r\n"); - CyDelay(100); + + while(1u){ + + + + read_acc(0); + CyDelay(1); + read_acc(1); + //CyDelay(300); + read_acc(2); + //CyDelay(300); + read_acc(3); + //CyDelay(300); + //read_acc(4); + //CyDelay(300); + + //Timer_1_WriteCounter(0); + Timer_1_Start(); + CyDelay(5); + uint16 counter = Timer_1_ReadCounter(); + //Timer_1_WriteCounter(0); + //Timer_1_Stop(); + LCD_Position(0u,0u); + LCD_PrintInt16(counter); + + CyDelay(1000); + } + +} +// ######################################################################################## +// ######################################################################################## +// ######################################################################################## +// ######################################################################################## + + + +void check_lsm(uint8 n) +{ + int value; + char OutputString[7]; - // ---------- SS #2 ------------ - SS_Write(1); - CyDelay(15); - value=ReadControlRegister(RCR,0x0F); + SS_Write(n); CyDelay(15); - UART_1_PutString("#2 is 0x"); - sprintf(OutputString, "%02x", value); - UART_1_PutString(OutputString); - UART_1_PutString("\r\n"); - CyDelay(100); - // ---------- SS #3 ------------ - SS_Write(2); - CyDelay(15); - value=ReadControlRegister(RCR,0x0F); - CyDelay(15); - - UART_1_PutString("#3 is 0x"); - sprintf(OutputString, "%02x", value); - UART_1_PutString(OutputString); - UART_1_PutString("\r\n"); - CyDelay(100); + Write1Byte(0x0F); + SPIM_ClearRxBuffer(); + value = Read1Byte(); + //value = ReadControlRegister(RCR,0x0F); + CyDelay(15); - // ---------- SS #4 ------------ - SS_Write(3); - CyDelay(15); - value=ReadControlRegister(RCR,0x0F); - CyDelay(15); + UART_1_PutString("\r\n"); + UART_1_PutString("#"); + sprintf(OutputString, "%i", n); + UART_1_PutString(OutputString); + UART_1_PutString(" ..."); - UART_1_PutString("#4 is 0x"); sprintf(OutputString, "%02x", value); UART_1_PutString(OutputString); UART_1_PutString("\r\n"); - CyDelay(100); - UART_1_PutString("\r\n"); - // ------------------------------ + LCD_Position(0u,0u); + LCD_PrintString(OutputString); CyDelay(1000); - - SPIM_ClearRxBuffer(); - SPIM_ClearTxBuffer(); - SPIM_ClearFIFO(); - - LCD_ClearDisplay(); - - //Start accel - SS_Write(0); // select SS #1 - CyDelay(10); - WriteControlRegister(WCR, 0x20, 0x67); - CyDelay(10); - - SS_Write(1); // select SS #2 - CyDelay(10); - WriteControlRegister(WCR, 0x20, 0x67); - CyDelay(10); - - SS_Write(2); // select SS #3 - CyDelay(10); - WriteControlRegister(WCR, 0x20, 0x67); - CyDelay(10); - - SS_Write(3); // select SS #4 +} + +void start_acc(uint8 n) +{ + SS_Write(n); CyDelay(10); WriteControlRegister(WCR, 0x20, 0x67); CyDelay(10); - - - while(1u){ - - low = 0; - high = 0; - two_c = 0; - strcpy(OutputString, ""); - - - - // ACC #1 ----------------------------- - SS_Write(0x00); // select SS #2 - CyDelay(5); - LCD_Position(0u,0u); - LCD_PrintString(" #"); - - // READ X - - low = ReadControlRegister(RCR,LSM303D_OUT_X_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_X_H_A); // High - - - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString("1,"); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = 0; - high = 0; - two_c = 0; - strcpy(OutputString, ""); - - - - // READ Y - - low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = 0; - high = 0; - two_c = 0; - strcpy(OutputString, ""); - - // -------- - - - - // READ Z - low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - UART_1_PutString("\r\n"); - - low = high = two_c = 0; - strcpy(OutputString, ""); - - - - - // ACC #2 ----------------------------- - SS_Write(0x02); // select SS #3 - CyDelay(5); - - LCD_Position(0u,0u); - - LCD_PrintString(" #"); - - low = ReadControlRegister(RCR,LSM303D_OUT_X_L_A); // Low - CyDelay(10); - high = ReadControlRegister(RCR,LSM303D_OUT_X_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString("2,"); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = high = two_c = 0; - strcpy(OutputString, ""); - - // READ Y - - low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = 0; - high = 0; - two_c = 0; - strcpy(OutputString, ""); - - // -------- - - - - // READ Z - low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - UART_1_PutString("\r\n"); - - low = high = two_c = 0; - strcpy(OutputString, ""); - - - // ACC #3 ----------------------------- - SS_Write(0x03); // select SS #4 - CyDelay(5); - LCD_Position(0u,0u); - - LCD_PrintString(" #"); - - low = ReadControlRegister(RCR,LSM303D_OUT_X_L_A); // Low - CyDelay(10); - high = ReadControlRegister(RCR,LSM303D_OUT_X_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees +} - sprintf(OutputString, "%d", two_c); - UART_1_PutString("3,"); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = high = two_c = 0; - - // READ Y - low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High - - two_c = (low << 8 | high); - sign = low >> 7; - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - low = 0; - high = 0; - two_c = 0; - strcpy(OutputString, ""); - - // -------- - - - - // READ Z - low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low - CyDelay(5); - high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High +void read_acc (uint8 n) +{ + //uint8 i = 0u; + uint8 value = 0; + uint8 low, high; + uint16 two_c = 0; + char OutputString[7]; + int sign; - two_c = (low << 8 | high); - sign = low >> 7; - - if(sign != 0) // negative result, form two's complement - { - two_c ^= 0xFFFF; // low = low XOR 0xFF - two_c ++; - sign = 1; - } - - //two_c >>= 1; // make into whole degrees - - sprintf(OutputString, "%d", two_c); - UART_1_PutString(","); - if (sign == 1) { UART_1_PutString("-"); } - if (sign == 0) { UART_1_PutString("+"); } - UART_1_PutString(OutputString); - - UART_1_PutString("\r\n"); + //uint8 low2, high2; + //uint16 two_c2 = 0; - low = high = two_c = 0; strcpy(OutputString, ""); - - - // ACC #4 ----------------------------- - SS_Write(0x00); // select SS #1 + SS_Write(n); // select SS CyDelay(5); LCD_Position(0u,0u); @@ -464,15 +162,14 @@ void main() CyDelay(5); high = ReadControlRegister(RCR,LSM303D_OUT_X_H_A); // High - two_c = (low << 8 | high); - //two_c = (high << 8 | low) >> 4; + two_c = (high << 8 | low); LCD_Position(1u,0u); - LCD_PrintInt8(low); - LCD_Position(1u,2u); LCD_PrintInt8(high); + LCD_Position(1u,2u); + LCD_PrintInt8(low); - sign = low >> 7; + sign = high >> 7; if(sign != 0) // negative result, form two's complement { @@ -482,9 +179,14 @@ void main() } //two_c >>= 1; // make into whole degrees - + + sprintf(OutputString, "%i", n); + UART_1_PutString("#"); + UART_1_PutString(OutputString); + UART_1_PutString(","); + sprintf(OutputString, "%d", two_c); - UART_1_PutString("4,"); + if (sign == 1) { UART_1_PutString("-"); } if (sign == 0) { UART_1_PutString("+"); } UART_1_PutString(OutputString); @@ -493,6 +195,8 @@ void main() high = 0; two_c = 0; strcpy(OutputString, ""); + + // READ Y @@ -500,8 +204,13 @@ void main() CyDelay(5); high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High - two_c = (low << 8 | high); - sign = low >> 7; + LCD_Position(1u,5u); + LCD_PrintInt8(high); + LCD_Position(1u,7u); + LCD_PrintInt8(low); + + two_c = (high << 8 | low); + sign = high >> 7; if(sign != 0) // negative result, form two's complement { @@ -532,8 +241,13 @@ void main() CyDelay(5); high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High - two_c = (low << 8 | high); - sign = low >> 7; + LCD_Position(1u,10u); + LCD_PrintInt8(high); + LCD_Position(1u,12u); + LCD_PrintInt8(low); + + two_c = (high << 8 | low); + sign = high >> 7; if(sign != 0) // negative result, form two's complement { @@ -555,10 +269,10 @@ void main() low = high = two_c = 0; strcpy(OutputString, ""); + + UART_1_PutString("\r\n"); - } - -} +} // This function reads data from Control Register @@ -568,6 +282,8 @@ uint8 ReadControlRegister(uint8 opcode, uint8 address) uint8 controlreg; SPIM_WriteByte(opcode | address ); + //SPIM_WriteByte(address ); + while(!(SPIM_ReadStatus() & SPIM_STS_TX_FIFO_EMPTY)); @@ -575,11 +291,11 @@ uint8 ReadControlRegister(uint8 opcode, uint8 address) while(!(SPIM_ReadStatus() & SPIM_STS_SPI_DONE)); - controlreg=SPIM_ReadByte(); //dummy read + //controlreg=SPIM_ReadByte(); //dummy read controlreg=SPIM_ReadByte(); // real data return controlreg; - }//End of RCR + } void WriteControlRegister(uint8 opcode,uint8 address,uint8 dta){ @@ -611,5 +327,24 @@ int fromHexStr(const char *s) { return n; } +uint8 Read1Byte() +{ + SPIM_ClearRxBuffer(); + Write1Byte(0x00); + return SPIM_ReadByte(); +} + +uint8 Write1Byte(uint8 ucData) +{ + uint8 ucStatus = 0; + while (!(SPIM_ReadStatus() & SPIM_STS_TX_FIFO_EMPTY)) + { + }; + SPIM_WriteByte(ucData); + while (!(SPIM_ReadStatus() & SPIM_STS_SPI_DONE)) + { + }; +} + /* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cywrk.SB b/PSOC5_SPI_LSM303D.cywrk.SB new file mode 100644 index 0000000..baa93d0 --- /dev/null +++ b/PSOC5_SPI_LSM303D.cywrk.SB @@ -0,0 +1,337 @@ + + + + + + + + + + +Source +Components +Output + + + + +PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D.cydwr +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files\device.h +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files\main.c +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Clock_1\Clock_1.c +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Clock_1\Clock_1.h +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\cy_boot\cm3gcc.ld +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\cy_boot\Cm3RealView.scat +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\cy_boot\Cm3Start.c +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\cy_boot\core_cm3.c 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+PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Clock_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Cm3Start.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\core_cm3.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyBootAsmGnu.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyDmac.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyfitter_cfg.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyFlash.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyLib.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyPm.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CySpc.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyutils.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD_LCDPort.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_miso_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_mosi_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_sclk_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\main.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_2.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_3.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_4.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_5.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_INT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_IntClock.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SS.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Timer_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Timer_1_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_BOOT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_INT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.elf +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.hex +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.map +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D.rpt +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D_timing.html + + + + +Datasheet + + + + +PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSoC 5 Architecture TRM +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CY8C55 Family Datasheet +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\System Reference Guide v3_40 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CharLCD_v1_90 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\cy_clock_v2_0 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\cy_pins_v1_90 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CyControlReg_v1_70 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\demux_v1_10 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\not_v1_0 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\SPI_Master_v2_40 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Timer_v2_50 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\UART_v2_30 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\ZeroTerminal + + +PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSoC 5 Architecture TRM +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CY8C55 Family Datasheet +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\System Reference Guide v3_40 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CharLCD_v1_90 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\cy_clock_v2_0 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\cy_pins_v1_90 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CyControlReg_v1_70 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\demux_v1_10 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\not_v1_0 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\SPI_Master_v2_40 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Timer_v2_50 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\UART_v2_30 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\ZeroTerminal + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cywrk.Tore b/PSOC5_SPI_LSM303D.cywrk.Tore index 59f089a..aa7793e 100644 --- a/PSOC5_SPI_LSM303D.cywrk.Tore +++ b/PSOC5_SPI_LSM303D.cywrk.Tore @@ -13,7 +13,7 @@ Output - + PSOC5_SPI_LSM303D PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell7U(3,5)1Net_439Net_439/clock_0Net_439/q1.250
Route1Net_439Net_439/qNet_422/main_02.596
macrocell4U(3,5)1Net_422Net_422/main_0Net_422/q3.350
Route1Net_422Net_422/qPin_2(0)/pin_input5.506
iocell2P3[1]1Pin_2(0)Pin_2(0)/pin_inputPin_2(0)/pad_out17.068
Route1Pin_2(0)_PADPin_2(0)/pad_outPin_2(0)_PAD 0.000
Net_439/q Pin_4(0)_PAD29.91529.632
@@ -4488,7 +6105,7 @@

Static Timing Analysis

macrocell7U(3,3)U(3,5) 1 Net_439 Net_439/clock_0
macrocell5U(3,3)U(3,5) 1 Net_425 Net_425/main_0 Net_425 Net_425/q Pin_4(0)/pin_input6.6136.330
iocell4
Net_479/q m_sclk_pin(0)_PAD27.67526.767
@@ -4575,7 +6192,7 @@

Static Timing Analysis

macrocell8U(2,3)U(3,5) 1 Net_479 Net_479/clock_0 Net_479 Net_479/q m_sclk_pin(0)/pin_input8.4437.535
iocell15iocell16 P0[6] 1 m_sclk_pin(0)