From 8ccc5b85c16e0a3c0ea31cf5fcd3cbd27587d09b Mon Sep 17 00:00:00 2001 From: Balestrino Date: Thu, 6 Mar 2014 10:56:25 +0100 Subject: [PATCH] update --- .../PSOC5_SPI_LSM303D.cyprj | 39 + .../PSOC5_SPI_LSM303D.cyprj.SB | 17 + .../PSOC5_SPI_LSM303D_PSoC5lib.uvproj | 30 + .../codegentemp/SPI_Design01.bvf | 276 -- .../codegentemp/SPI_Design01.ctl | 8 - .../codegentemp/SPI_Design01.cycdx | 19 - .../codegentemp/SPI_Design01.cyfit | Bin 147389 -> 0 bytes .../codegentemp/SPI_Design01.dsf | 16 - .../codegentemp/SPI_Design01.pci | 20 - .../codegentemp/SPI_Design01.pco | 37 - .../codegentemp/SPI_Design01.plc_log | 2 - .../codegentemp/SPI_Design01.route | 603 ---- .../codegentemp/SPI_Design01.rpt | 2116 ------------- .../codegentemp/SPI_Design01.rt_log | 28 - .../codegentemp/SPI_Design01.sdc | 15 - .../codegentemp/SPI_Design01.svd | 9 - .../codegentemp/SPI_Design01.tr | 2806 ----------------- .../codegentemp/SPI_Design01.v | 421 --- .../codegentemp/SPI_Design01.vh2 | 649 ---- .../codegentemp/SPI_Design01.wde | 11 - .../codegentemp/SPI_Design01_p.lib | 2337 -------------- .../codegentemp/SPI_Design01_p.pco | 31 - .../codegentemp/SPI_Design01_p.vh2 | 1489 --------- .../codegentemp/SPI_Design01_r.lib | 2337 -------------- .../codegentemp/SPI_Design01_r.vh2 | 1479 --------- .../codegentemp/SPI_Design01_t.lib | 2337 -------------- .../codegentemp/SPI_Design01_t.vh2 | 1479 --------- .../codegentemp/SPI_Design01_timing.html | 2447 -------------- .../codegentemp/SPI_Design01_u.sdc | 3 - .../codegentemp/m_ss_pin.c | 130 - .../codegentemp/m_ss_pin.h | 125 - .../codegentemp/m_ss_pin_aliases.h | 30 - PSOC5_SPI_LSM303D.cydsn/main.c | 202 +- PSOC5_SPI_LSM303D.cywrk.SB | 86 +- 34 files changed, 306 insertions(+), 21328 deletions(-) delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.bvf delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.ctl delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.cycdx delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.cyfit delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.dsf delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.pci delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.pco delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.plc_log delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.route delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rpt delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rt_log delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.sdc delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.svd delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.tr delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.v delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.vh2 delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.wde delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.lib delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.pco delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.vh2 delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.lib delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.vh2 delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.lib delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.vh2 delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_timing.html delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_u.sdc delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.c delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.h delete mode 100644 PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin_aliases.h diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj index 6842feb..2df8dfa 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj @@ -1264,6 +1264,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj.SB b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj.SB index a258cc3..fddf41a 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj.SB +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D.cyprj.SB @@ -33,6 +33,8 @@ + + @@ -78,6 +80,8 @@ + + @@ -273,6 +277,17 @@ + + + + + + + + + + + @@ -531,6 +546,7 @@ + @@ -581,6 +597,7 @@ + diff --git a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj index 72b68ca..44ff8c3 100644 --- a/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj +++ b/PSOC5_SPI_LSM303D.cydsn/PSOC5_SPI_LSM303D_PSoC5lib.uvproj @@ -707,6 +707,21 @@ 5 .\Generated_Source\PSoC5\Pin_6.h + + Pin_7_aliases.h + 5 + .\Generated_Source\PSoC5\Pin_7_aliases.h + + + Pin_7.c + 1 + .\Generated_Source\PSoC5\Pin_7.c + + + Pin_7.h + 5 + .\Generated_Source\PSoC5\Pin_7.h + @@ -1416,6 +1431,21 @@ 5 .\Generated_Source\PSoC5\Pin_6.h + + Pin_7_aliases.h + 5 + .\Generated_Source\PSoC5\Pin_7_aliases.h + + + Pin_7.c + 1 + .\Generated_Source\PSoC5\Pin_7.c + + + Pin_7.h + 5 + .\Generated_Source\PSoC5\Pin_7.h + diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.bvf b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.bvf deleted file mode 100644 index fa9f4d8..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.bvf +++ /dev/null @@ -1,276 +0,0 @@ - ----------------------------------------------------------------------- - -Verifying bitstream. - ------------------------------------------------------------------------ - - ----------Mapping jacks.--------- - - ----------Processing bitstream.--------- - -Utilized "udb_hv_a@[UDB Pair=(0,4)]" -Utilized "udb_hc@[UDB Pair=(0,4)]" -Utilized "udb_hv_b@[UDB Pair=(0,5)]" -Utilized "udb_hc@[UDB Pair=(0,5)]" -Utilized "dsi_hv_b@[DSI=(0,4)][side=top]" -Utilized "dsi_hc@[DSI=(0,5)][side=top]" -Utilized "dsi_hv_a@[DSI=(0,5)][side=top]" - ----------Propagating signals.--------- - -Found signal "\SPIM:BSPIM:load_rx_data\" on jack "pld0:out0[UDB=(0,4)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:in3[UDB=(1,4)]" - - - -Found signal "\SPIM:BSPIM:rx_status_6\" on jack "pld0:out1[UDB=(0,4)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:inout2[UDB=(0,4)]" - - - -Found signal "\SPIM:BSPIM:load_rx_data\" on jack "pld0:out2[UDB=(0,4)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "dp:in1[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:cnt_enable\" on jack "pld0:out3[UDB=(0,4)]". -Number of connected bvjacks: 2. - - 1. Connected jack name: "pld0:in7[UDB=(0,4)]" - - 2. Connected jack name: "statctrl:inout3[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:load_cond\" on jack "pld1:out1[UDB=(0,4)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "pld1:in1[UDB=(0,4)]" - - - -Found signal "Net_30" on jack "pld1:out2[UDB=(0,4)]". -Number of connected bvjacks: 2. - - 1. Connected jack name: "io_ijack_5[IOP=(0)]" - - 2. Connected jack name: "pld1:in2[UDB=(0,4)]" - - - -Found signal "\SPIM:BSPIM:tx_status_0\" on jack "pld0:out0[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:in0[UDB=(1,4)]" - - - -Found signal "\SPIM:BSPIM:state_2\" on jack "pld0:out1[UDB=(0,5)]". -Number of connected bvjacks: 5. - - 1. Connected jack name: "pld0:in1[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in9[UDB=(0,4)]" - - 3. Connected jack name: "pld0:in1[UDB=(0,5)]" - - 4. Connected jack name: "pld1:in9[UDB=(0,5)]" - - 5. Connected jack name: "dp:in2[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:state_0\" on jack "pld0:out2[UDB=(0,5)]". -Number of connected bvjacks: 5. - - 1. Connected jack name: "pld1:in10[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in10[UDB=(0,5)]" - - 3. Connected jack name: "dp:in5[UDB=(0,5)]" - - 4. Connected jack name: "pld0:in6[UDB=(0,4)]" - - 5. Connected jack name: "pld0:in6[UDB=(0,5)]" - - - -Found signal "Net_31" on jack "pld0:out3[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "io_ijack_6[IOP=(0)]" - - - -Found signal "\SPIM:BSPIM:state_1\" on jack "pld1:out0[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "dp:in3[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:state_1\" on jack "pld1:out1[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld0:in5[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in5[UDB=(0,4)]" - - 3. Connected jack name: "pld0:in5[UDB=(0,5)]" - - 4. Connected jack name: "pld1:in5[UDB=(0,5)]" - - - -Found signal "Net_107" on jack "pld1:out2[UDB=(0,5)]". -Number of connected bvjacks: 2. - - 1. Connected jack name: "io_ijack_7[IOP=(0)]" - - 2. Connected jack name: "pld1:in6[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:tx_status_4\" on jack "pld1:out3[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:inout0[UDB=(1,4)]" - - - -Found signal "\SPIM:BSPIM:tx_status_2\" on jack "dp:out0[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:in2[UDB=(1,4)]" - - - -Found signal "\SPIM:BSPIM:mosi_from_dp\" on jack "dp:out1[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "pld1:in8[UDB=(0,4)]" - - - -Found signal "\SPIM:BSPIM:tx_status_1\" on jack "dp:out2[UDB=(0,5)]". -Number of connected bvjacks: 3. - - 1. Connected jack name: "statctrl:in1[UDB=(1,4)]" - - 2. Connected jack name: "pld1:in11[UDB=(0,5)]" - - 3. Connected jack name: "pld0:in4[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:rx_status_5\" on jack "dp:out3[UDB=(0,5)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "statctrl:inout1[UDB=(0,4)]" - - - -Found signal "\SPIM:BSPIM:rx_status_4\" on jack "dp:out5[UDB=(0,5)]". -Number of connected bvjacks: 2. - - 1. Connected jack name: "pld0:in11[UDB=(0,4)]" - - 2. Connected jack name: "statctrl:inout0[UDB=(0,4)]" - - - -Found signal "\SPIM:BSPIM:count_0\" on jack "statctrl:out0[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld0:in0[UDB=(0,4)]" - - 2. Connected jack name: "pld0:in0[UDB=(0,5)]" - - 3. Connected jack name: "pld1:in4[UDB=(0,4)]" - - 4. Connected jack name: "pld1:in4[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:count_1\" on jack "statctrl:out1[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld0:in10[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in11[UDB=(0,4)]" - - 3. Connected jack name: "pld0:in10[UDB=(0,5)]" - - 4. Connected jack name: "pld1:in2[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:count_2\" on jack "statctrl:out2[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld0:in9[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in6[UDB=(0,4)]" - - 3. Connected jack name: "pld0:in9[UDB=(0,5)]" - - 4. Connected jack name: "pld1:in1[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:count_3\" on jack "statctrl:out3[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld0:in3[UDB=(0,4)]" - - 2. Connected jack name: "pld0:in3[UDB=(0,5)]" - - 3. Connected jack name: "pld1:in7[UDB=(0,4)]" - - 4. Connected jack name: "pld1:in7[UDB=(0,5)]" - - - -Found signal "\SPIM:BSPIM:count_4\" on jack "statctrl:out4[UDB=(0,5)]". -Number of connected bvjacks: 4. - - 1. Connected jack name: "pld1:in3[UDB=(0,4)]" - - 2. Connected jack name: "pld1:in3[UDB=(0,5)]" - - 3. Connected jack name: "pld0:in8[UDB=(0,4)]" - - 4. Connected jack name: "pld0:in8[UDB=(0,5)]" - - - -Found signal "Net_20" on jack "io_ojack_0[IOP=(0)]". -Number of connected bvjacks: 1. - - 1. Connected jack name: "dp:in4[UDB=(0,5)]" - - - - ----------Verifying signals (routing).--------- - - ----------Verifying configuration.--------- - - - ----------------------------------------------------------------------- - -Bitstream verification passed. - ------------------------------------------------------------------------ - diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.ctl b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.ctl deleted file mode 100644 index b84c4ec..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.ctl +++ /dev/null @@ -1,8 +0,0 @@ --- ====================================================================== --- SPI_Design01.ctl generated from SPI_Design01 --- 01/16/2013 at 14:35 --- This file is auto generated. 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zMuxuhVk>{?{tF$qDEvRe){&e$b>+rcqz7DK8o#BnDD{=JSi+jC=Lz*gtb<`2Ck{Qh zK=xr@bQ(~0-Gc21*rvKs31^f!(oJ>-1y$`LUXNv(u$r5?lw~P6N-M#G{s`T(EG>Zs zmh`H_a3Nzq>tW(`Eeq9iee{{=0E`M{OR)YrD~uqW-)8gTaw>mnEmTd;3_{BQFglE? z^yMAt1LB+tB{UfTHPJMn9?!)mRDUT# zyxqQwHko%t^L~PYDuRZBLWN*O9E|N8Emhs@6pii8U8jCGC_<~COI+etM8-9TNs1mi zX#O;3vH}hOhs90BVwoAxi=+XJu(@F*Lv`q}B*qor$@080OieGd|M_}eOy*|hE^h`0 zdS84Fgio=_}WF0TZ!?RcjBCjQQ^`3ttUPAi7b*LfWA1|Rpn;qilEHxcP`P;cU29^q`&8f5V9aQ(@ zw9JNw&~2HF0@X~t7rfnG?p2GekIt#NxwNs$$tSGO+s8=%UnTQ=s?PEG3()=vOCSseeS0M(EDvMyAYJfmMle80BQH>kRMXM%~9-K0k@W)adm#Eykk7 zW3pJyq~AOnuX^`ke$>I^=^&7Xkzg)e;ktyueKie7Rm#O`eePgeGCA4ZxxrVmZp*z= zIzhFD`Q6`}sikY@1G_zDs@OhW7tNNa&c2-n&&@!$1;ja<7I)Eps^YtBWeXe|+XI6% z32tych|S@*IlBbR;{FwBB{2Op$7&=;Yj`-s18tF70|AV;o~6>;63&z?RRBuZ>KH(< zKDngd!C8|d7O2?ZET7m{2H>0Yt)UqahU@-QU6y)g%TyB)HRN?577N=oo9ZY3PcP7F zbp@`!{|pCa9#$APgVweGB;ivgiG|5Of9I4&oq-e7-(5`6vIugod;tuKQc0fPk-bT2 z!pg(fx7nq}a8B?r3FC!=U5Z9Kk>=t(xg_?ibBa_$d&pl5K07jl=f%pvbH(L6j2VMk zBJ?3#f?3fDXibNeT0i!au4ngco{oRS9OiRp$e=(iFQWTgep%XC@HGYN1dO)@u?1v? ztol!Ajok#{o0Br6F&R1AJ>k-gWFY@Z3mnS`_{WVeVnSRD-D}<^tJ65l1MPwM%{8I} zpdJCX?s5z?pIuAjQZpq|OP~MF-C8x#JpGH>a;N6|Y>K-QgK5g>w=8b9A1yQUFykWe z>YFnzx+Wi+DZ!+BC=iNx~FWzp^q3z;LT{c_Z5a*NS`_MfQ@JRA+ULq0^lni*|Q$Gyjb(!PUpKQZEL9 zpZ@DOOUGxAD4g3dLO*zAxlhncQ2%dF=mF^o@%?{WeUgKMBJlYH1@YDY-%ngi_5aV% zV-O?C`~?c?_WzkG0|OU|awVWKt~rTGo_T5cE>6h$%7GS5-8A8b2P*@^1O-Tui_lsT z3@m_s+~b4%LqlBSJ^kGLk@bR#Ye&N;UCzLwngeJrCqg5T^(KOW!85NUwWz4Hpah>b zRKJBqGcdULI-+anebcwl7wAT5VFm^ug#>oRGB7yjkVTrEconwUQJD@)j1Q;0DQLOr% z2h@;XR1)Bi5?!F6+b+nc2rPdY6o42ty7-D27=kl%GL!T3f>O)SExS~:udb@[UDB=(0,4)]:pld0:output_permute1.q_2" - switch ":udb@[UDB=(0,4)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v26" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v26" - switch ":udbswitch@[UDB=(0,4)][side=top]:26,12" - switch ":udbswitch@[UDB=(0,4)][side=top]:100,12_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v100" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v100==>:udb@[UDB=(0,4)]:statusicell.status_6" - term ":udb@[UDB=(0,4)]:statusicell.status_6" -end \SPIM:BSPIM:rx_status_6\ -net \SPIM:BSPIM:rx_status_4\ - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_blk_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_blk_stat_comb==>:udb@[UDB=(0,5)]:dp_wrapper:output_permute.f1_blk_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:output_permute.outs_5==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v86" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v86" - switch ":udbswitch@[UDB=(0,5)][side=top]:86,5" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_5_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:22,5_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v22" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v22==>:udb@[UDB=(0,4)]:pld0:input_permute.input_11" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_5==>:udb@[UDB=(0,4)]:pld0:mc2.main_5" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_5" - switch ":udbswitch@[UDB=(0,4)][side=top]:72,5_f" - switch ":udbswitch@[UDB=(0,4)][side=top]:72,43_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:96,43_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v96" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v96==>:udb@[UDB=(0,4)]:statusicell.status_4" - term ":udb@[UDB=(0,4)]:statusicell.status_4" -end \SPIM:BSPIM:rx_status_4\ -net \SPIM:BSPIM:count_1\ - term ":udb@[UDB=(0,5)]:count7cell.count_1" - switch ":udb@[UDB=(0,5)]:count7cell.count_1==>:udb@[UDB=(0,5)]:controlcell_control_1_permute.in_1" - switch ":udb@[UDB=(0,5)]:controlcell_control_1_permute.controlcell_control_1==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v106" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v106" - switch ":udbswitch@[UDB=(0,5)][side=top]:106,11" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_11_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:20,11_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v20" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v20==>:udb@[UDB=(0,4)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc1_main_3==>:udb@[UDB=(0,4)]:pld0:mc1.main_3" - term ":udb@[UDB=(0,4)]:pld0:mc1.main_3" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_3==>:udb@[UDB=(0,4)]:pld0:mc2.main_3" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_3" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(0,4)]:pld0:mc0.main_6" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_6" - switch ":hvswitch@[UDB=(1,4)][side=left]:30,11_f" - switch ":hvswitch@[UDB=(1,4)][side=left]:30,70_b" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_70_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:40,70_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v40" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v40==>:udb@[UDB=(0,4)]:pld1:input_permute.input_11" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(0,4)]:pld1:mc0.main_6" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_6" - switch ":udbswitch@[UDB=(0,5)][side=top]:20,11_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v20" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v20==>:udb@[UDB=(0,5)]:pld0:input_permute.input_10" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_6==>:udb@[UDB=(0,5)]:pld0:mc2.main_6" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_6" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_6==>:udb@[UDB=(0,5)]:pld0:mc0.main_6" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_6" - switch ":udbswitch@[UDB=(0,5)][side=top]:106,36" - switch ":udbswitch@[UDB=(0,5)][side=top]:58,36_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v58" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v58==>:udb@[UDB=(0,5)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_6==>:udb@[UDB=(0,5)]:pld1:mc0.main_6" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_6" -end \SPIM:BSPIM:count_1\ -net \SPIM:BSPIM:load_rx_data\ - term ":udb@[UDB=(0,4)]:pld0:mc1.q" - switch ":udb@[UDB=(0,4)]:pld0:mc1.q==>:udb@[UDB=(0,4)]:pld0:output_permute2.q_1" - switch ":udb@[UDB=(0,4)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v28" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v28" - switch ":udbswitch@[UDB=(0,4)][side=top]:28,6" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_6_f" - switch ":udbswitch@[UDB=(0,5)][side=top]:66,6_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v66" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v66==>:udb@[UDB=(0,5)]:dp_wrapper:input_permute.ina_1" - switch ":udb@[UDB=(0,5)]:dp_wrapper:input_permute.f1_load==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_load" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_load" - switch ":udb@[UDB=(0,4)]:pld0:mc1.q==>:udb@[UDB=(0,4)]:pld0:output_permute0.q_1" - switch ":udb@[UDB=(0,4)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v24" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v24" - switch ":udbswitch@[UDB=(0,4)][side=top]:24,28" - switch ":udbswitch@[UDB=(0,4)][side=top]:95,28_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v95" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v95==>:udb@[UDB=(1,4)]:statusicell.status_3" - term ":udb@[UDB=(1,4)]:statusicell.status_3" -end \SPIM:BSPIM:load_rx_data\ -net \SPIM:BSPIM:mosi_from_dp\ - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.so_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:datapath.so_comb==>:udb@[UDB=(0,5)]:dp_wrapper:output_permute.so_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:output_permute.outs_1==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v78" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v78" - switch ":udbswitch@[UDB=(0,5)][side=top]:78,25" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_25_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:46,25_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v46" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v46==>:udb@[UDB=(0,4)]:pld1:input_permute.input_8" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc1_main_4==>:udb@[UDB=(0,4)]:pld1:mc1.main_4" - term ":udb@[UDB=(0,4)]:pld1:mc1.main_4" -end \SPIM:BSPIM:mosi_from_dp\ -net \SPIM:BSPIM:count_2\ - term ":udb@[UDB=(0,5)]:count7cell.count_2" - switch ":udb@[UDB=(0,5)]:count7cell.count_2==>:udb@[UDB=(0,5)]:controlcell_control_2_permute.in_1" - switch ":udb@[UDB=(0,5)]:controlcell_control_2_permute.controlcell_control_2==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v108" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v108" - switch ":udbswitch@[UDB=(0,5)][side=top]:108,17" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_17_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:18,17_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v18" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v18==>:udb@[UDB=(0,4)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(0,4)]:pld0:mc1.main_2" - term ":udb@[UDB=(0,4)]:pld0:mc1.main_2" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_2==>:udb@[UDB=(0,4)]:pld0:mc2.main_2" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_2" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(0,4)]:pld0:mc0.main_5" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_5" - switch ":udbswitch@[UDB=(0,4)][side=top]:50,17_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v50" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v50==>:udb@[UDB=(0,4)]:pld1:input_permute.input_6" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(0,4)]:pld1:mc0.main_5" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_5" - switch ":udbswitch@[UDB=(0,5)][side=top]:18,17_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v18" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v18==>:udb@[UDB=(0,5)]:pld0:input_permute.input_9" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_5==>:udb@[UDB=(0,5)]:pld0:mc2.main_5" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_5" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_5==>:udb@[UDB=(0,5)]:pld0:mc0.main_5" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_5" - switch ":udbswitch@[UDB=(0,5)][side=top]:108,30" - switch ":udbswitch@[UDB=(0,5)][side=top]:60,30_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v60" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v60==>:udb@[UDB=(0,5)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_5==>:udb@[UDB=(0,5)]:pld1:mc0.main_5" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_5" -end \SPIM:BSPIM:count_2\ -net \SPIM:BSPIM:count_4\ - term ":udb@[UDB=(0,5)]:count7cell.count_4" - switch ":udb@[UDB=(0,5)]:count7cell.count_4==>:udb@[UDB=(0,5)]:controlcell_control_4_permute.in_1" - switch ":udb@[UDB=(0,5)]:controlcell_control_4_permute.controlcell_control_4==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v112" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v112" - switch ":udbswitch@[UDB=(0,5)][side=top]:112,76" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_76_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:16,76_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v16" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v16==>:udb@[UDB=(0,4)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(0,4)]:pld0:mc1.main_0" - term ":udb@[UDB=(0,4)]:pld0:mc1.main_0" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(0,4)]:pld0:mc2.main_0" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_0" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(0,4)]:pld0:mc0.main_3" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_3" - switch ":udbswitch@[UDB=(0,5)][side=top]:112,21" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_21_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:56,21_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v56" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v56==>:udb@[UDB=(0,4)]:pld1:input_permute.input_3" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(0,4)]:pld1:mc0.main_3" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_3" - switch ":udbswitch@[UDB=(0,5)][side=top]:16,76_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v16" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v16==>:udb@[UDB=(0,5)]:pld0:input_permute.input_8" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_3==>:udb@[UDB=(0,5)]:pld0:mc2.main_3" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_3" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_3==>:udb@[UDB=(0,5)]:pld0:mc0.main_3" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_3" - switch ":udbswitch@[UDB=(0,5)][side=top]:56,21_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v56" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v56==>:udb@[UDB=(0,5)]:pld1:input_permute.input_3" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_3==>:udb@[UDB=(0,5)]:pld1:mc0.main_3" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_3" -end \SPIM:BSPIM:count_4\ -net \SPIM:BSPIM:count_3\ - term ":udb@[UDB=(0,5)]:count7cell.count_3" - switch ":udb@[UDB=(0,5)]:count7cell.count_3==>:udb@[UDB=(0,5)]:controlcell_control_3_permute.in_1" - switch ":udb@[UDB=(0,5)]:controlcell_control_3_permute.controlcell_control_3==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v110" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v110" - switch ":udbswitch@[UDB=(0,5)][side=top]:110,20" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_20_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:6,20_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v6" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v6==>:udb@[UDB=(0,4)]:pld0:input_permute.input_3" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(0,4)]:pld0:mc1.main_1" - term ":udb@[UDB=(0,4)]:pld0:mc1.main_1" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(0,4)]:pld0:mc2.main_1" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_1" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(0,4)]:pld0:mc0.main_4" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_4" - switch ":udbswitch@[UDB=(0,5)][side=top]:110,91" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_91_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:48,91_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v48" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v48==>:udb@[UDB=(0,4)]:pld1:input_permute.input_7" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(0,4)]:pld1:mc0.main_4" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_4" - switch ":udbswitch@[UDB=(0,5)][side=top]:6,20_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v6" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v6==>:udb@[UDB=(0,5)]:pld0:input_permute.input_3" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_4==>:udb@[UDB=(0,5)]:pld0:mc2.main_4" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_4" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_4==>:udb@[UDB=(0,5)]:pld0:mc0.main_4" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_4" - switch ":udbswitch@[UDB=(0,5)][side=top]:48,91_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v48" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v48==>:udb@[UDB=(0,5)]:pld1:input_permute.input_7" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_4==>:udb@[UDB=(0,5)]:pld1:mc0.main_4" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_4" -end \SPIM:BSPIM:count_3\ -net \SPIM:BSPIM:count_0\ - term ":udb@[UDB=(0,5)]:count7cell.count_0" - switch ":udb@[UDB=(0,5)]:count7cell.count_0==>:udb@[UDB=(0,5)]:controlcell_control_0_permute.in_1" - switch ":udb@[UDB=(0,5)]:controlcell_control_0_permute.controlcell_control_0==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v104" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v104" - switch ":udbswitch@[UDB=(0,5)][side=top]:104,2" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_2_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:0,2_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v0" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v0==>:udb@[UDB=(0,4)]:pld0:input_permute.input_0" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc1_main_4==>:udb@[UDB=(0,4)]:pld0:mc1.main_4" - term ":udb@[UDB=(0,4)]:pld0:mc1.main_4" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc2_main_4==>:udb@[UDB=(0,4)]:pld0:mc2.main_4" - term ":udb@[UDB=(0,4)]:pld0:mc2.main_4" - switch ":udbswitch@[UDB=(0,5)][side=top]:104,73" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_73_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:54,73_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v54" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v54==>:udb@[UDB=(0,4)]:pld1:input_permute.input_4" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(0,4)]:pld1:mc0.main_7" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_7" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(0,4)]:pld0:mc0.main_7" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_7" - switch ":udbswitch@[UDB=(0,5)][side=top]:54,73_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v54" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v54==>:udb@[UDB=(0,5)]:pld1:input_permute.input_4" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_7==>:udb@[UDB=(0,5)]:pld1:mc0.main_7" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_7" - switch ":udbswitch@[UDB=(0,5)][side=top]:0,2_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v0" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v0==>:udb@[UDB=(0,5)]:pld0:input_permute.input_0" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_7==>:udb@[UDB=(0,5)]:pld0:mc2.main_7" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_7" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_7==>:udb@[UDB=(0,5)]:pld0:mc0.main_7" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_7" -end \SPIM:BSPIM:count_0\ -net \SPIM:BSPIM:tx_status_1\ - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f0_blk_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f0_blk_stat_comb==>:udb@[UDB=(0,5)]:dp_wrapper:output_permute.f0_blk_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:output_permute.outs_2==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v80" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v80" - switch ":udbswitch@[UDB=(0,5)][side=top]:80,93" - switch ":udbswitch@[UDB=(0,5)][side=top]:8,93_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v8" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v8==>:udb@[UDB=(0,5)]:pld0:input_permute.input_4" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_8==>:udb@[UDB=(0,5)]:pld0:mc2.main_8" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_8" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(0,5)]:pld0:mc0.main_8" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_8" - switch ":udbswitch@[UDB=(0,5)][side=top]:80,67" - switch ":udbswitch@[UDB=(0,5)][side=top]:40,67_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v40" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v40==>:udb@[UDB=(0,5)]:pld1:input_permute.input_11" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(0,5)]:pld1:mc0.main_8" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_8" - switch ":hvswitch@[UDB=(1,4)][side=left]:19,67_f" - switch ":hvswitch@[UDB=(1,4)][side=left]:19,84_b" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_84_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:91,84_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v91" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v91==>:udb@[UDB=(1,4)]:statusicell.status_1" - term ":udb@[UDB=(1,4)]:statusicell.status_1" -end \SPIM:BSPIM:tx_status_1\ -net \SPIM:BSPIM:state_2\ - term ":udb@[UDB=(0,5)]:pld0:mc0.q" - switch ":udb@[UDB=(0,5)]:pld0:mc0.q==>:udb@[UDB=(0,5)]:pld0:output_permute1.q_0" - switch ":udb@[UDB=(0,5)]:pld0:output_permute1.output_1==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v26" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v26" - switch ":udbswitch@[UDB=(0,5)][side=top]:26,34" - switch ":udbswitch@[UDB=(0,5)][side=top]:2,34_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v2" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v2==>:udb@[UDB=(0,5)]:pld0:input_permute.input_1" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc1_main_0==>:udb@[UDB=(0,5)]:pld0:mc1.main_0" - term ":udb@[UDB=(0,5)]:pld0:mc1.main_0" - switch ":udbswitch@[UDB=(0,5)][side=top]:26,60" - switch ":udbswitch@[UDB=(0,5)][side=top]:68,60_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v68" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v68==>:udb@[UDB=(0,5)]:dp_wrapper:input_permute.ina_2" - switch ":udb@[UDB=(0,5)]:dp_wrapper:input_permute.cs_addr_2==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_2" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_2" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_34_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:2,34_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v2" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v2==>:udb@[UDB=(0,4)]:pld0:input_permute.input_1" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(0,4)]:pld0:mc0.main_0" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_0" - switch ":udbswitch@[UDB=(0,4)][side=top]:44,34_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v44" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v44==>:udb@[UDB=(0,4)]:pld1:input_permute.input_9" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(0,4)]:pld1:mc1.main_1" - term ":udb@[UDB=(0,4)]:pld1:mc1.main_1" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(0,4)]:pld1:mc0.main_0" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_0" - switch ":udbswitch@[UDB=(0,5)][side=top]:44,34_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v44" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v44==>:udb@[UDB=(0,5)]:pld1:input_permute.input_9" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(0,5)]:pld1:mc1.main_0" - term ":udb@[UDB=(0,5)]:pld1:mc1.main_0" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_0==>:udb@[UDB=(0,5)]:pld1:mc0.main_0" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_0" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc3_main_0==>:udb@[UDB=(0,5)]:pld0:mc3.main_0" - term ":udb@[UDB=(0,5)]:pld0:mc3.main_0" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_0==>:udb@[UDB=(0,5)]:pld0:mc2.main_0" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_0" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_0==>:udb@[UDB=(0,5)]:pld0:mc0.main_0" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_0" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc2_main_0==>:udb@[UDB=(0,5)]:pld1:mc2.main_0" - term ":udb@[UDB=(0,5)]:pld1:mc2.main_0" -end \SPIM:BSPIM:state_2\ -net \SPIM:BSPIM:tx_status_0\ - term ":udb@[UDB=(0,5)]:pld0:mc1.q" - switch ":udb@[UDB=(0,5)]:pld0:mc1.q==>:udb@[UDB=(0,5)]:pld0:output_permute0.q_1" - switch ":udb@[UDB=(0,5)]:pld0:output_permute0.output_0==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v24" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v24" - switch ":udbswitch@[UDB=(0,5)][side=top]:24,66" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_66_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:89,66_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v89" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v89==>:udb@[UDB=(1,4)]:statusicell.status_0" - term ":udb@[UDB=(1,4)]:statusicell.status_0" -end \SPIM:BSPIM:tx_status_0\ -net \SPIM:BSPIM:state_0\ - term ":udb@[UDB=(0,5)]:pld0:mc2.q" - switch ":udb@[UDB=(0,5)]:pld0:mc2.q==>:udb@[UDB=(0,5)]:pld0:output_permute2.q_2" - switch ":udb@[UDB=(0,5)]:pld0:output_permute2.output_2==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v28" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v28" - switch ":udbswitch@[UDB=(0,5)][side=top]:28,54" - switch ":udbswitch@[UDB=(0,5)][side=top]:12,54_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v12" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v12==>:udb@[UDB=(0,5)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc1_main_2==>:udb@[UDB=(0,5)]:pld0:mc1.main_2" - term ":udb@[UDB=(0,5)]:pld0:mc1.main_2" - switch ":udbswitch@[UDB=(0,5)][side=top]:28,37" - switch ":udbswitch@[UDB=(0,5)][side=top]:74,37_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v74" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v74==>:udb@[UDB=(0,5)]:dp_wrapper:input_permute.ina_5" - switch ":udb@[UDB=(0,5)]:dp_wrapper:input_permute.cs_addr_0==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_0" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_0" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_37_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:42,37_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v42" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v42==>:udb@[UDB=(0,4)]:pld1:input_permute.input_10" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(0,4)]:pld1:mc1.main_3" - term ":udb@[UDB=(0,4)]:pld1:mc1.main_3" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(0,4)]:pld1:mc0.main_2" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_2" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_54_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:12,54_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v12" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v12==>:udb@[UDB=(0,4)]:pld0:input_permute.input_6" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(0,4)]:pld0:mc0.main_2" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_2" - switch ":udbswitch@[UDB=(0,5)][side=top]:42,37_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v42" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v42==>:udb@[UDB=(0,5)]:pld1:input_permute.input_10" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(0,5)]:pld1:mc1.main_2" - term ":udb@[UDB=(0,5)]:pld1:mc1.main_2" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_2==>:udb@[UDB=(0,5)]:pld1:mc0.main_2" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_2" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc3_main_2==>:udb@[UDB=(0,5)]:pld0:mc3.main_2" - term ":udb@[UDB=(0,5)]:pld0:mc3.main_2" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_2==>:udb@[UDB=(0,5)]:pld0:mc2.main_2" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_2" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_2==>:udb@[UDB=(0,5)]:pld0:mc0.main_2" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_2" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc2_main_2==>:udb@[UDB=(0,5)]:pld1:mc2.main_2" - term ":udb@[UDB=(0,5)]:pld1:mc2.main_2" -end \SPIM:BSPIM:state_0\ -net \SPIM:BSPIM:state_1\ - term ":udb@[UDB=(0,5)]:pld1:mc0.q" - switch ":udb@[UDB=(0,5)]:pld1:mc0.q==>:udb@[UDB=(0,5)]:pld1:output_permute1.q_0" - switch ":udb@[UDB=(0,5)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v36" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v36" - switch ":udbswitch@[UDB=(0,5)][side=top]:36,35" - switch ":udbswitch@[UDB=(0,5)][side=top]:10,35_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v10" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v10==>:udb@[UDB=(0,5)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc1_main_1==>:udb@[UDB=(0,5)]:pld0:mc1.main_1" - term ":udb@[UDB=(0,5)]:pld0:mc1.main_1" - switch ":udb@[UDB=(0,5)]:pld1:mc0.q==>:udb@[UDB=(0,5)]:pld1:output_permute0.q_0" - switch ":udb@[UDB=(0,5)]:pld1:output_permute0.output_0==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v38" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v38" - switch ":udbswitch@[UDB=(0,5)][side=top]:38,18" - switch ":udbswitch@[UDB=(0,5)][side=top]:70,18_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v70" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v70==>:udb@[UDB=(0,5)]:dp_wrapper:input_permute.ina_3" - switch ":udb@[UDB=(0,5)]:dp_wrapper:input_permute.cs_addr_1==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_1" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.cs_addr_1" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_35_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:10,35_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v10" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v10==>:udb@[UDB=(0,4)]:pld0:input_permute.input_5" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(0,4)]:pld0:mc0.main_1" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_1" - switch ":udbswitch@[UDB=(0,4)][side=top]:52,35_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v52" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v52==>:udb@[UDB=(0,4)]:pld1:input_permute.input_5" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc1_main_2==>:udb@[UDB=(0,4)]:pld1:mc1.main_2" - term ":udb@[UDB=(0,4)]:pld1:mc1.main_2" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(0,4)]:pld1:mc0.main_1" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_1" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc3_main_1==>:udb@[UDB=(0,5)]:pld0:mc3.main_1" - term ":udb@[UDB=(0,5)]:pld0:mc3.main_1" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc2_main_1==>:udb@[UDB=(0,5)]:pld0:mc2.main_1" - term ":udb@[UDB=(0,5)]:pld0:mc2.main_1" - switch ":udb@[UDB=(0,5)]:pld0:input_permute.mc0_main_1==>:udb@[UDB=(0,5)]:pld0:mc0.main_1" - term ":udb@[UDB=(0,5)]:pld0:mc0.main_1" - switch ":udbswitch@[UDB=(0,5)][side=top]:52,35_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v52" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v52==>:udb@[UDB=(0,5)]:pld1:input_permute.input_5" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc1_main_1==>:udb@[UDB=(0,5)]:pld1:mc1.main_1" - term ":udb@[UDB=(0,5)]:pld1:mc1.main_1" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc0_main_1==>:udb@[UDB=(0,5)]:pld1:mc0.main_1" - term ":udb@[UDB=(0,5)]:pld1:mc0.main_1" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc2_main_1==>:udb@[UDB=(0,5)]:pld1:mc2.main_1" - term ":udb@[UDB=(0,5)]:pld1:mc2.main_1" -end \SPIM:BSPIM:state_1\ -net Net_30 - term ":udb@[UDB=(0,4)]:pld1:mc1.q" - switch ":udb@[UDB=(0,4)]:pld1:mc1.q==>:udb@[UDB=(0,4)]:pld1:output_permute2.q_1" - switch ":udb@[UDB=(0,4)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v34" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v34" - switch ":udbswitch@[UDB=(0,4)][side=top]:34,39" - switch ":udbswitch@[UDB=(0,4)][side=top]:58,39_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v58" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v58==>:udb@[UDB=(0,4)]:pld1:input_permute.input_2" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc1_main_0==>:udb@[UDB=(0,4)]:pld1:mc1.main_0" - term ":udb@[UDB=(0,4)]:pld1:mc1.main_0" - switch ":hvswitch@[UDB=(1,4)][side=left]:14,39_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:vseg_14_bot_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:14,61_b" - switch ":hvswitch@[UDB=(0,4)][side=left]:hseg_61_f" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:98,61_f" - switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v100+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v102+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v98" - switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v100+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v102+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v98==>:ioport0:inputs2_mux.in_2" - switch ":ioport0:inputs2_mux.pin5__pin_input==>:ioport0:pin5.pin_input" - term ":ioport0:pin5.pin_input" -end Net_30 -net Net_107 - term ":udb@[UDB=(0,5)]:pld1:mc1.q" - switch ":udb@[UDB=(0,5)]:pld1:mc1.q==>:udb@[UDB=(0,5)]:pld1:output_permute2.q_1" - switch ":udb@[UDB=(0,5)]:pld1:output_permute2.output_2==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v34" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v34" - switch ":udbswitch@[UDB=(0,5)][side=top]:34,63" - switch ":udbswitch@[UDB=(0,5)][side=top]:50,63_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v50" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v50==>:udb@[UDB=(0,5)]:pld1:input_permute.input_6" - switch ":udb@[UDB=(0,5)]:pld1:input_permute.mc1_main_3==>:udb@[UDB=(0,5)]:pld1:mc1.main_3" - term ":udb@[UDB=(0,5)]:pld1:mc1.main_3" - switch ":hvswitch@[UDB=(1,4)][side=left]:25,63_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:vseg_25_bot_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:25,10_b" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:99,10_f" - switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v101+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v103+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v99" - switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v101+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v103+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v99==>:ioport0:inputs2_mux.in_3" - switch ":ioport0:inputs2_mux.pin7__pin_input==>:ioport0:pin7.pin_input" - term ":ioport0:pin7.pin_input" -end Net_107 -net \SPIM:BSPIM:cnt_enable\ - term ":udb@[UDB=(0,4)]:pld0:mc0.q" - switch ":udb@[UDB=(0,4)]:pld0:mc0.q==>:udb@[UDB=(0,4)]:pld0:output_permute3.q_0" - switch ":udb@[UDB=(0,4)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v30" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v30" - switch ":udbswitch@[UDB=(0,4)][side=top]:30,92" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_92_f" - switch ":udbswitch@[UDB=(0,5)][side=top]:102,92_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v102" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v102==>:udb@[UDB=(0,5)]:c7_en_mux.in_3" - switch ":udb@[UDB=(0,5)]:c7_en_mux.c7_en==>:udb@[UDB=(0,5)]:count7cell.enable" - term ":udb@[UDB=(0,5)]:count7cell.enable" - switch ":udbswitch@[UDB=(0,4)][side=top]:30,48" - switch ":udbswitch@[UDB=(0,4)][side=top]:14,48_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v14" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v14==>:udb@[UDB=(0,4)]:pld0:input_permute.input_7" - switch ":udb@[UDB=(0,4)]:pld0:input_permute.mc0_main_8==>:udb@[UDB=(0,4)]:pld0:mc0.main_8" - term ":udb@[UDB=(0,4)]:pld0:mc0.main_8" -end \SPIM:BSPIM:cnt_enable\ -net \SPIM:BSPIM:load_cond\ - term ":udb@[UDB=(0,4)]:pld1:mc0.q" - switch ":udb@[UDB=(0,4)]:pld1:mc0.q==>:udb@[UDB=(0,4)]:pld1:output_permute1.q_0" - switch ":udb@[UDB=(0,4)]:pld1:output_permute1.output_1==>Stub-:udbswitch@[UDB=(0,4)][side=top]:v36" - switch "OStub-:udbswitch@[UDB=(0,4)][side=top]:v36" - switch ":udbswitch@[UDB=(0,4)][side=top]:36,33" - switch ":udbswitch@[UDB=(0,4)][side=top]:60,33_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v60" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v60==>:udb@[UDB=(0,4)]:pld1:input_permute.input_1" - switch ":udb@[UDB=(0,4)]:pld1:input_permute.mc0_main_8==>:udb@[UDB=(0,4)]:pld1:mc0.main_8" - term ":udb@[UDB=(0,4)]:pld1:mc0.main_8" -end \SPIM:BSPIM:load_cond\ -net \SPIM:Net_276\ - term ":clockblockcell.dclk_glb_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,5)]:clockreset:clk_pld1_mux.in_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(0,5)]:pld1:mc1.clock_0" - term ":udb@[UDB=(0,5)]:pld1:mc1.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,4)]:clockreset:clk_pld1_mux.in_0" - switch ":udb@[UDB=(0,4)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(0,4)]:pld1:mc1.clock_0" - term ":udb@[UDB=(0,4)]:pld1:mc1.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,5)]:clockreset:clk_pld0_mux.in_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(0,5)]:pld0:mc3.clock_0" - term ":udb@[UDB=(0,5)]:pld0:mc3.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,5)]:clockreset:clk_sc_mux.in_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(0,5)]:count7cell.clock" - term ":udb@[UDB=(0,5)]:count7cell.clock" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,4)]:clockreset:clk_sc_mux.in_0" - switch ":udb@[UDB=(0,4)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(0,4)]:statusicell.clock" - term ":udb@[UDB=(0,4)]:statusicell.clock" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(1,4)]:clockreset:clk_sc_mux.in_0" - switch ":udb@[UDB=(1,4)]:clockreset:clk_sc_mux.sc_clk==>:udb@[UDB=(1,4)]:statusicell.clock" - term ":udb@[UDB=(1,4)]:statusicell.clock" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,4)]:clockreset:clk_pld0_mux.in_0" - switch ":udb@[UDB=(0,4)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(0,4)]:pld0:mc0.clock_0" - term ":udb@[UDB=(0,4)]:pld0:mc0.clock_0" - switch ":udb@[UDB=(0,4)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(0,4)]:pld1:mc0.clock_0" - term ":udb@[UDB=(0,4)]:pld1:mc0.clock_0" - switch ":clockblockcell.dclk_glb_0==>:udb@[UDB=(0,5)]:clockreset:clk_dp_mux.in_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_dp_mux.dp_clk==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.clock" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.clock" - switch ":udb@[UDB=(0,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(0,5)]:pld0:mc2.clock_0" - term ":udb@[UDB=(0,5)]:pld0:mc2.clock_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_pld1_mux.pld1_clk==>:udb@[UDB=(0,5)]:pld1:mc0.clock_0" - term ":udb@[UDB=(0,5)]:pld1:mc0.clock_0" - switch ":udb@[UDB=(0,5)]:clockreset:clk_pld0_mux.pld0_clk==>:udb@[UDB=(0,5)]:pld0:mc0.clock_0" - term ":udb@[UDB=(0,5)]:pld0:mc0.clock_0" -end \SPIM:Net_276\ -net ClockBlock_BUS_CLK - term ":clockblockcell.clk_bus_glb" - switch ":clockblockcell.clk_bus_glb==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.busclk" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.busclk" -end ClockBlock_BUS_CLK -net Net_20 - term ":ioport0:pin0.fb" - switch ":ioport0:pin0.fb==>Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v0+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v2" - switch "OStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v0+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v2" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:0,24" - switch ":hvswitch@[UDB=(0,5)][side=left]:3,24_f" - switch ":hvswitch@[UDB=(1,5)][side=left]:vseg_3_top_f" - switch ":hvswitch@[UDB=(1,5)][side=left]:3,46_b" - switch ":udbswitch@[UDB=(0,5)][side=top]:72,46_f" - switch "IStub-:udbswitch@[UDB=(0,5)][side=top]:v72" - switch "Stub-:udbswitch@[UDB=(0,5)][side=top]:v72==>:udb@[UDB=(0,5)]:dp_wrapper:input_permute.ina_4" - switch ":udb@[UDB=(0,5)]:dp_wrapper:input_permute.route_si==>:udb@[UDB=(0,5)]:dp_wrapper:datapath.route_si" - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.route_si" -end Net_20 -net Net_31 - term ":udb@[UDB=(0,5)]:pld0:mc3.q" - switch ":udb@[UDB=(0,5)]:pld0:mc3.q==>:udb@[UDB=(0,5)]:pld0:output_permute3.q_3" - switch ":udb@[UDB=(0,5)]:pld0:output_permute3.output_3==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v30" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v30" - switch ":udbswitch@[UDB=(0,5)][side=top]:30,43" - switch ":hvswitch@[UDB=(1,4)][side=left]:24,43_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:vseg_24_bot_f" - switch ":hvswitch@[UDB=(0,4)][side=left]:24,74_b" - switch ":dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:96,74_f" - switch "IStub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v92+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v94+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v96" - switch "Stub-:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v92+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v94+:dsiswitch_top@[DSI=(0,5)][side=top]:dsihc_top:v96==>:ioport0:inputs2_mux.in_0" - switch ":ioport0:inputs2_mux.pin6__pin_input==>:ioport0:pin6.pin_input" - term ":ioport0:pin6.pin_input" -end Net_31 -net \SPIM:BSPIM:rx_status_5\ - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_bus_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f1_bus_stat_comb==>:udb@[UDB=(0,5)]:dp_wrapper:output_permute.f1_bus_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:output_permute.outs_3==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v82" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v82" - switch ":udbswitch@[UDB=(0,5)][side=top]:82,41" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_41_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:98,41_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v98" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v98==>:udb@[UDB=(0,4)]:statusicell.status_5" - term ":udb@[UDB=(0,4)]:statusicell.status_5" -end \SPIM:BSPIM:rx_status_5\ -net \SPIM:BSPIM:tx_status_2\ - term ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f0_bus_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:datapath.f0_bus_stat_comb==>:udb@[UDB=(0,5)]:dp_wrapper:output_permute.f0_bus_stat_comb" - switch ":udb@[UDB=(0,5)]:dp_wrapper:output_permute.outs_0==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v76" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v76" - switch ":udbswitch@[UDB=(0,5)][side=top]:76,78" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_78_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:93,78_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v93" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v93==>:udb@[UDB=(1,4)]:statusicell.status_2" - term ":udb@[UDB=(1,4)]:statusicell.status_2" -end \SPIM:BSPIM:tx_status_2\ -net \SPIM:BSPIM:tx_status_4\ - term ":udb@[UDB=(0,5)]:pld1:mc2.q" - switch ":udb@[UDB=(0,5)]:pld1:mc2.q==>:udb@[UDB=(0,5)]:pld1:output_permute3.q_2" - switch ":udb@[UDB=(0,5)]:pld1:output_permute3.output_3==>Stub-:udbswitch@[UDB=(0,5)][side=top]:v32" - switch "OStub-:udbswitch@[UDB=(0,5)][side=top]:v32" - switch ":udbswitch@[UDB=(0,5)][side=top]:32,72" - switch ":hvswitch@[UDB=(1,4)][side=left]:hseg_72_b" - switch ":udbswitch@[UDB=(0,4)][side=top]:97,72_f" - switch "IStub-:udbswitch@[UDB=(0,4)][side=top]:v97" - switch "Stub-:udbswitch@[UDB=(0,4)][side=top]:v97==>:udb@[UDB=(1,4)]:statusicell.status_4" - term ":udb@[UDB=(1,4)]:statusicell.status_4" -end \SPIM:BSPIM:tx_status_4\ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rpt b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rpt deleted file mode 100644 index 1396ab8..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rpt +++ /dev/null @@ -1,2116 +0,0 @@ -Loading plugins phase: Elapsed time ==> 0s.212ms -Initializing data phase: Elapsed time ==> 2s.643ms - -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -d CY8C5568AXI-060 -s C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\Generated_Source\PSoC5 -- -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE - - -Elaboration phase: Elapsed time ==> 2s.140ms - - -HDL generation phase: Elapsed time ==> 0s.046ms - - - | | | | | | | - _________________ - -| |- - -| |- - -| |- - -| CYPRESS |- - -| |- - -| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41 - -| |- Copyright (C) 1991-2001 Cypress Semiconductor - |_______________| - | | | | | | | - -====================================================================== -Compiling: SPI_Design01.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 SPI_Design01.v -verilog -====================================================================== - -====================================================================== -Compiling: SPI_Design01.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 SPI_Design01.v -verilog -====================================================================== - -====================================================================== -Compiling: SPI_Design01.v -Program : vlogfe -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 -verilog SPI_Design01.v -====================================================================== - -vlogfe V6.3 IR 41: Verilog parser -Wed Jan 16 14:35:45 2013 - - -====================================================================== -Compiling: SPI_Design01.v -Program : vpp -Options : -yv2 -q10 SPI_Design01.v -====================================================================== - -vpp V6.3 IR 41: Verilog Pre-Processor -Wed Jan 16 14:35:45 2013 - -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v' -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v' -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.v' -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cy_psoc3_inc.v' - -vpp: No errors. - -Library 'work' => directory 'lcpsoc3' -General_symbol_table -General_symbol_table -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Using control file 'SPI_Design01.ctl'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. - -vlogfe: No errors. - - -====================================================================== -Compiling: SPI_Design01.v -Program : tovif -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 -verilog SPI_Design01.v -====================================================================== - -tovif V6.3 IR 41: High-level synthesis -Wed Jan 16 14:35:45 2013 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\codegentemp\SPI_Design01.ctl'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\codegentemp\SPI_Design01.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. - -tovif: No errors. - - -====================================================================== -Compiling: SPI_Design01.v -Program : topld -Options : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 -verilog SPI_Design01.v -====================================================================== - -topld V6.3 IR 41: Synthesis and optimization -Wed Jan 16 14:35:45 2013 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\codegentemp\SPI_Design01.ctl'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\codegentemp\SPI_Design01.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. - ----------------------------------------------------------- -Detecting unused logic. ----------------------------------------------------------- - User names - Net_83 - \SPIM:BSPIM:mosi_after_ld\ - \SPIM:BSPIM:so_send\ - \SPIM:BSPIM:mosi_fin\ - \SPIM:BSPIM:mosi_cpha_1\ - \SPIM:BSPIM:mosi_cpha_0\ - \SPIM:BSPIM:pre_mosi\ - \SPIM:BSPIM:dpcounter_zero\ - \SPIM:BSPIM:control_7\ - \SPIM:BSPIM:control_6\ - \SPIM:BSPIM:control_5\ - \SPIM:BSPIM:control_4\ - \SPIM:BSPIM:control_3\ - \SPIM:BSPIM:control_2\ - \SPIM:BSPIM:control_1\ - \SPIM:BSPIM:control_0\ - \SPIM:Net_253\ - - -Deleted 17 User equations/components. -Deleted 0 Synthesized equations/components. - ------------------------------------------------------- -Alias Detection ------------------------------------------------------- -Aliasing tmpOE__m_mosi_pin_net_0 to tmpOE__m_miso_pin_net_0 -Aliasing tmpOE__m_sclk_pin_net_0 to tmpOE__m_miso_pin_net_0 -Aliasing one to tmpOE__m_miso_pin_net_0 -Aliasing \SPIM:BSPIM:pol_supprt\ to tmpOE__m_miso_pin_net_0 -Aliasing \SPIM:BSPIM:tx_status_3\ to \SPIM:BSPIM:load_rx_data\ -Aliasing \SPIM:BSPIM:tx_status_6\ to zero -Aliasing \SPIM:BSPIM:tx_status_5\ to zero -Aliasing \SPIM:BSPIM:rx_status_3\ to zero -Aliasing \SPIM:BSPIM:rx_status_2\ to zero -Aliasing \SPIM:BSPIM:rx_status_1\ to zero -Aliasing \SPIM:BSPIM:rx_status_0\ to zero -Aliasing \SPIM:Net_274\ to zero -Aliasing \LCD:tmpOE__LCDPort_net_6\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_5\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_4\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_3\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_2\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_1\ to tmpOE__m_miso_pin_net_0 -Aliasing \LCD:tmpOE__LCDPort_net_0\ to tmpOE__m_miso_pin_net_0 -Aliasing tmpOE__m_ss_pin_net_0 to tmpOE__m_miso_pin_net_0 -Aliasing \SPIM:BSPIM:so_send_reg\\D\ to zero -Aliasing \SPIM:BSPIM:mosi_pre_reg\\D\ to zero -Aliasing \SPIM:BSPIM:dpcounter_one_reg\\D\ to \SPIM:BSPIM:load_rx_data\ -Aliasing \SPIM:BSPIM:ld_ident\\D\ to zero -Removing Lhs of wire tmpOE__m_mosi_pin_net_0[9] = tmpOE__m_miso_pin_net_0[2] -Removing Rhs of wire Net_30[10] = \SPIM:BSPIM:mosi_reg\[36] -Removing Lhs of wire tmpOE__m_sclk_pin_net_0[16] = tmpOE__m_miso_pin_net_0[2] -Removing Rhs of wire \SPIM:Net_276\[22] = \SPIM:Net_239\[23] -Removing Lhs of wire one[26] = tmpOE__m_miso_pin_net_0[2] -Removing Rhs of wire \SPIM:BSPIM:load_rx_data\[28] = \SPIM:BSPIM:dpcounter_one\[29] -Removing Lhs of wire \SPIM:BSPIM:pol_supprt\[30] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \SPIM:BSPIM:miso_to_dp\[31] = \SPIM:Net_244\[32] -Removing Lhs of wire \SPIM:Net_244\[32] = Net_20[4] -Removing Rhs of wire \SPIM:BSPIM:tx_status_1\[58] = \SPIM:BSPIM:dpMOSI_fifo_empty\[59] -Removing Rhs of wire \SPIM:BSPIM:tx_status_2\[60] = \SPIM:BSPIM:dpMOSI_fifo_not_full\[61] -Removing Lhs of wire \SPIM:BSPIM:tx_status_3\[62] = \SPIM:BSPIM:load_rx_data\[28] -Removing Rhs of wire \SPIM:BSPIM:rx_status_4\[64] = \SPIM:BSPIM:dpMISO_fifo_full\[65] -Removing Rhs of wire \SPIM:BSPIM:rx_status_5\[66] = \SPIM:BSPIM:dpMISO_fifo_not_empty\[67] -Removing Lhs of wire \SPIM:BSPIM:tx_status_6\[69] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:tx_status_5\[70] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:rx_status_3\[71] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:rx_status_2\[72] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:rx_status_1\[73] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:rx_status_0\[74] = zero[3] -Removing Lhs of wire \SPIM:Net_273\[85] = zero[3] -Removing Lhs of wire \SPIM:Net_274\[123] = zero[3] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_6\[125] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_5\[126] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_4\[127] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_3\[128] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_2\[129] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_1\[130] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \LCD:tmpOE__LCDPort_net_0\[131] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire tmpOE__m_ss_pin_net_0[149] = tmpOE__m_miso_pin_net_0[2] -Removing Lhs of wire \SPIM:BSPIM:so_send_reg\\D\[155] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:mosi_pre_reg\\D\[161] = zero[3] -Removing Lhs of wire \SPIM:BSPIM:dpcounter_one_reg\\D\[163] = \SPIM:BSPIM:load_rx_data\[28] -Removing Lhs of wire \SPIM:BSPIM:mosi_from_dp_reg\\D\[164] = \SPIM:BSPIM:mosi_from_dp\[42] -Removing Lhs of wire \SPIM:BSPIM:ld_ident\\D\[165] = zero[3] - ------------------------------------------------------- -Aliased 0 equations, 35 wires. ------------------------------------------------------- - ----------------------------------------------------------- -Circuit simplification ----------------------------------------------------------- - -Substituting virtuals - pass 1: - -Note: Expanding virtual equation for 'tmpOE__m_miso_pin_net_0' (cost = 0): -tmpOE__m_miso_pin_net_0 <= ('1') ; - -Note: Expanding virtual equation for 'zero' (cost = 0): -zero <= ('0') ; - -Note: Expanding virtual equation for '\SPIM:BSPIM:load_rx_data\' (cost = 1): -\SPIM:BSPIM:load_rx_data\ <= ((not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:count_0\)); - - -Substituting virtuals - pass 2: - - ----------------------------------------------------------- -Circuit simplification results: - - Expanded 3 signals. - Turned 0 signals into soft nodes. - Maximum default expansion cost was set at 5. ----------------------------------------------------------- - ------------------------------------------------------- -Alias Detection ------------------------------------------------------- - ------------------------------------------------------- -Aliased 0 equations, 0 wires. ------------------------------------------------------- - -Last attempt to remove unused logic - pass 1: - - -Last attempt to remove unused logic - pass 2: - - -topld: No errors. - -CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp -Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -dcpsoc3 SPI_Design01.v -verilog - -Warp synthesis phase: Elapsed time ==> 1s.019ms - - -cyp3fit: V2.1.0.1118, Family: PSoC3, Started at: Wednesday, 16 January 2013 14:35:46 -Options: -yv2 -v5 -yga -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -d CY8C5568AXI-060 SPI_Design01.v -verilog - - -Design parsing phase: Elapsed time ==> 0s.015ms - - - - Converted constant MacroCell: \SPIM:BSPIM:ld_ident\ from registered to combinatorial - Converted constant MacroCell: \SPIM:BSPIM:mosi_pre_reg\ from registered to combinatorial - Converted constant MacroCell: \SPIM:BSPIM:so_send_reg\ from registered to combinatorial - -Removing unused cells resulting from optimization - Removed unused cell/equation '\SPIM:BSPIM:dpcounter_one_reg\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:ld_ident\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:mosi_from_dp_reg\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:mosi_pre_reg\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:so_send_reg\:macrocell' -Done removing unused cells. - - Digital Clock 0: Automatic-assigning clock 'SPIM_IntClock'. Fanout=1, Signal=\SPIM:Net_276\ - - - UDB Clk/Enable \SPIM:BSPIM:ClkEn\: with output requested to be synchronous - ClockIn: SPIM_IntClock was determined to be a global clock that is synchronous to BUS_CLK - EnableIn: Constant 1 was determined to be synchronous to ClockIn - ClockOut: SPIM_IntClock, EnableOut: Constant 1 - - -Removing unused cells resulting from optimization - Removed unused cell/equation 'Net_107D:macrocell' - Removed unused cell/equation 'Net_31D:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:cnt_enable\\D\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:load_cond\\D\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:mosi_reg\\D\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:state_0\\D\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:state_1\\D\:macrocell' - Removed unused cell/equation '\SPIM:BSPIM:state_2\\D\:macrocell' - Removed unused cell/equation '__ZERO__:macrocell' -Done removing unused cells. - - - - - - - ------------------------------------------------------------- -Design Equations ------------------------------------------------------------- - - - ------------------------------------------------------------ - Pin listing - ------------------------------------------------------------ - - Pin : Name = \LCD:LCDPort(0)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(0)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(1)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(1)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(2)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(2)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(3)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(3)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(4)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(4)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(5)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(5)_PAD\ ); - Properties: - { - } - - Pin : Name = \LCD:LCDPort(6)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(6)_PAD\ ); - Properties: - { - } - - Pin : Name = m_miso_pin(0) - Attributes: - In Group/Port: True - In Sync Option: NOSYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: HI_Z_DIGITAL - VTrip: CMOS - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - fb => Net_20 , - pad => m_miso_pin(0)_PAD ); - Properties: - { - } - - Pin : Name = m_mosi_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_30 , - pad => m_mosi_pin(0)_PAD ); - Properties: - { - } - - Pin : Name = m_sclk_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_31 , - pad => m_sclk_pin(0)_PAD ); - Properties: - { - } - - Pin : Name = m_ss_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_107 , - pad => m_ss_pin(0)_PAD ); - Properties: - { - } - - - - ------------------------------------------------------------ - Macrocell listing - ------------------------------------------------------------ - - MacroCell: Name=Net_107, Mode=(D-Register) - Total # of inputs : 4 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * !Net_107 - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * !Net_107 - ); - Output = Net_107 (fanout=2) - - MacroCell: Name=Net_30, Mode=(D-Register) - Total # of inputs : 5 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - ( - Net_30 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + Net_30 * \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:mosi_from_dp\ - ); - Output = Net_30 (fanout=2) - - MacroCell: Name=Net_31, Mode=(D-Register) - Total # of inputs : 3 - Total # of product terms : 1 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 1 pterm - !( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = Net_31 (fanout=1) - - MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) - Total # of inputs : 9 - Total # of product terms : 5 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 5 pterms - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:cnt_enable\ - ); - Output = \SPIM:BSPIM:cnt_enable\ (fanout=2) - - MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) - Total # of inputs : 9 - Total # of product terms : 4 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - ); - Output = \SPIM:BSPIM:load_cond\ (fanout=1) - - MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(Combinatorial) - Total # of inputs : 5 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:load_rx_data\ (fanout=2) - - MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) - Total # of inputs : 6 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ - ); - Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) - - MacroCell: Name=\SPIM:BSPIM:state_0\, Mode=(T-Register) - Total # of inputs : 9 - Total # of product terms : 4 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - !( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * \SPIM:BSPIM:count_0\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:tx_status_1\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * \SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ - ); - Output = \SPIM:BSPIM:state_0\ (fanout=11) - - MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) - Total # of inputs : 9 - Total # of product terms : 5 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 5 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * \SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:state_1\ (fanout=11) - - MacroCell: Name=\SPIM:BSPIM:state_2\, Mode=(D-Register) - Total # of inputs : 9 - Total # of product terms : 2 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 2 pterms - ( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - \SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - !\SPIM:BSPIM:tx_status_1\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:state_2\ (fanout=11) - - MacroCell: Name=\SPIM:BSPIM:tx_status_0\, Mode=(Combinatorial) - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - ); - Output = \SPIM:BSPIM:tx_status_0\ (fanout=1) - - MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) - - - - ------------------------------------------------------------ - Datapath listing - ------------------------------------------------------------ - - datapathcell: Name =\SPIM:BSPIM:sR8:Dp:u0\ - PORT MAP ( - clock => \SPIM:Net_276\ , - cs_addr_2 => \SPIM:BSPIM:state_2\ , - cs_addr_1 => \SPIM:BSPIM:state_1\ , - cs_addr_0 => \SPIM:BSPIM:state_0\ , - route_si => Net_20 , - f1_load => \SPIM:BSPIM:load_rx_data\ , - so_comb => \SPIM:BSPIM:mosi_from_dp\ , - f0_bus_stat_comb => \SPIM:BSPIM:tx_status_2\ , - f0_blk_stat_comb => \SPIM:BSPIM:tx_status_1\ , - f1_bus_stat_comb => \SPIM:BSPIM:rx_status_5\ , - f1_blk_stat_comb => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - a0_init = "00000000" - a1_init = "00000000" - ce0_sync = 1 - ce1_sync = 1 - cl0_sync = 1 - cl1_sync = 1 - cmsb_sync = 1 - co_msb_sync = 1 - cy_dpconfig = "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100" - d0_init = "00000000" - d1_init = "00000000" - f0_blk_sync = 1 - f0_bus_sync = 1 - f1_blk_sync = 1 - f1_bus_sync = 1 - ff0_sync = 1 - ff1_sync = 1 - ov_msb_sync = 1 - so_sync = 1 - z0_sync = 1 - z1_sync = 1 - } - Clock Polarity: Active High - Clock Enable: True - - - - - - ------------------------------------------------------------ - StatusI register listing - ------------------------------------------------------------ - - statusicell: Name =\SPIM:BSPIM:RxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_6 => \SPIM:BSPIM:rx_status_6\ , - status_5 => \SPIM:BSPIM:rx_status_5\ , - status_4 => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "1000000" - } - Clock Polarity: Active High - Clock Enable: True - - statusicell: Name =\SPIM:BSPIM:TxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_4 => \SPIM:BSPIM:tx_status_4\ , - status_3 => \SPIM:BSPIM:load_rx_data\ , - status_2 => \SPIM:BSPIM:tx_status_2\ , - status_1 => \SPIM:BSPIM:tx_status_1\ , - status_0 => \SPIM:BSPIM:tx_status_0\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "0001001" - } - Clock Polarity: Active High - Clock Enable: True - - - - - - - - ------------------------------------------------------------ - Count7 listing - ------------------------------------------------------------ - - count7cell: Name =\SPIM:BSPIM:BitCounter\ - PORT MAP ( - clock => \SPIM:Net_276\ , - enable => \SPIM:BSPIM:cnt_enable\ , - count_6 => \SPIM:BSPIM:count_6\ , - count_5 => \SPIM:BSPIM:count_5\ , - count_4 => \SPIM:BSPIM:count_4\ , - count_3 => \SPIM:BSPIM:count_3\ , - count_2 => \SPIM:BSPIM:count_2\ , - count_1 => \SPIM:BSPIM:count_1\ , - count_0 => \SPIM:BSPIM:count_0\ , - tc => \SPIM:BSPIM:cnt_tc\ ); - Properties: - { - cy_alt_mode = 0 - cy_init_value = "0000000" - cy_period = "0001111" - cy_route_en = 1 - cy_route_ld = 0 - } - Clock Polarity: Active High - Clock Enable: True - - - - - - - - ------------------------------------------------------------- -Technology mapping summary ------------------------------------------------------------- - -Resource Type : Used : Free : Max : % Used -============================================================ -Digital domain clock dividers : 1 : 7 : 8 : 12.50% -Analog domain clock dividers : 0 : 4 : 4 : 0.00% -Pins : 14 : 56 : 70 : 20.00% -Macrocells : 12 : 180 : 192 : 6.25% -Unique Pterms : 29 : 355 : 384 : 7.55% -Total Pterms : 31 : : : -Datapath Cells : 1 : 23 : 24 : 4.17% -Status Cells : 2 : 22 : 24 : 8.33% - StatusI Registers : 2 -Control Cells : 1 : 23 : 24 : 4.17% - Count7 Cells : 1 -DMA Channels : 0 : 24 : 24 : 0.00% -Interrupts : 0 : 32 : 32 : 0.00% -DSM Fixed Blocks : 0 : 1 : 1 : 0.00% -VIDAC Fixed Blocks : 0 : 4 : 4 : 0.00% -SC Fixed Blocks : 0 : 4 : 4 : 0.00% -Comparator Fixed Blocks : 0 : 4 : 4 : 0.00% -Opamp Fixed Blocks : 0 : 4 : 4 : 0.00% -CapSense Buffers : 0 : 2 : 2 : 0.00% -CAN Fixed Blocks : 0 : 1 : 1 : 0.00% -Decimator Fixed Blocks : 0 : 1 : 1 : 0.00% -I2C Fixed Blocks : 0 : 1 : 1 : 0.00% -Timer Fixed Blocks : 0 : 4 : 4 : 0.00% -DFB Fixed Blocks : 0 : 1 : 1 : 0.00% -USB Fixed Blocks : 0 : 1 : 1 : 0.00% -LCD Fixed Blocks : 0 : 1 : 1 : 0.00% -EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% -LPF Fixed Blocks : 0 : 2 : 2 : 0.00% -SAR Fixed Blocks : 0 : 2 : 2 : 0.00% - -Technology Mapping: Elapsed time ==> 0s.043ms -Info: mpr.M0037: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details. (App=cydsfit) -Tech mapping phase: Elapsed time ==> 0s.167ms - - -Initial Analog Placement Results: -IO_0@[IOP=(2)][IoId=(0)] : \LCD:LCDPort(0)\ (fixed) -IO_1@[IOP=(2)][IoId=(1)] : \LCD:LCDPort(1)\ (fixed) -IO_2@[IOP=(2)][IoId=(2)] : \LCD:LCDPort(2)\ (fixed) -IO_3@[IOP=(2)][IoId=(3)] : \LCD:LCDPort(3)\ (fixed) -IO_4@[IOP=(2)][IoId=(4)] : \LCD:LCDPort(4)\ (fixed) -IO_5@[IOP=(2)][IoId=(5)] : \LCD:LCDPort(5)\ (fixed) -IO_6@[IOP=(2)][IoId=(6)] : \LCD:LCDPort(6)\ (fixed) -IO_0@[IOP=(0)][IoId=(0)] : m_miso_pin(0) (fixed) -IO_5@[IOP=(0)][IoId=(5)] : m_mosi_pin(0) (fixed) -IO_6@[IOP=(0)][IoId=(6)] : m_sclk_pin(0) (fixed) -IO_7@[IOP=(0)][IoId=(7)] : m_ss_pin(0) (fixed) -Analog Placement phase: Elapsed time ==> 0s.038ms - - -============ VeraRouter Final Answer Routes ============ -Analog Routing phase: Elapsed time ==> 0s.000ms - - -Analog Code Generation phase: Elapsed time ==> 0s.537ms - - - - - ------------------------------------------------------------- -PLD Packing Summary ------------------------------------------------------------- - Resource Type : Used : Free : Max : % Used - ==================================================== - PLDs : 4 : 44 : 48 : 8.33% - - - - PLD Resource Type : Average/LAB - ======================================= - Inputs : 10.00 - Pterms : 7.25 - Macrocells : 3.00 - - -Packed PLD Contents not displayed at this verbose level. - -PLD Packing: Elapsed time ==> 0s.001ms - - - -Initial Partitioning Summary not displayed at this verbose level. - -Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.022ms - - -Annealing: Elapsed time ==> 0s.001ms - -The seed used for moves was 114161200. -Inital cost was 91, final cost is 91 (0.00% improvement). - - - ------------------------------------------------------------- -Final Placement Summary ------------------------------------------------------------- - - Resource Type : Count : Avg Inputs : Avg Outputs - ======================================================== - UDB : 3 : 7.67 : 4.00 - - - ------------------------------------------------------------- -Component Placement Details ------------------------------------------------------------- -UDB [UDB=(0,0)] is empty. -UDB [UDB=(0,1)] is empty. -UDB [UDB=(0,2)] is empty. -UDB [UDB=(0,3)] is empty. -UDB [UDB=(0,4)] contents: -LAB@[UDB=(0,4)][LB=0] #macrocells=3, #inputs=10, #pterms=7 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(0,4)][LB=0][MC=0] - Total # of inputs : 9 - Total # of product terms : 5 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 5 pterms - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:cnt_enable\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:cnt_enable\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:cnt_enable\ - ); - Output = \SPIM:BSPIM:cnt_enable\ (fanout=3) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:load_rx_data\, Mode=(Combinatorial) @ [UDB=(0,4)][LB=0][MC=1] - Total # of inputs : 5 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:load_rx_data\ (fanout=2) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(0,4)][LB=0][MC=2] - Total # of inputs : 6 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ * \SPIM:BSPIM:rx_status_4\ - ); - Output = \SPIM:BSPIM:rx_status_6\ (fanout=1) - Properties : - { - } - - [McSlotId=3]: (empty) -} - -LAB@[UDB=(0,4)][LB=1] #macrocells=2, #inputs=11, #pterms=7 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(0,4)][LB=1][MC=0] - Total # of inputs : 9 - Total # of product terms : 4 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - + \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - \SPIM:BSPIM:load_cond\ - ); - Output = \SPIM:BSPIM:load_cond\ (fanout=1) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_30, Mode=(D-Register) @ [UDB=(0,4)][LB=1][MC=1] - Total # of inputs : 5 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - ( - Net_30 * !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + Net_30 * \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * \SPIM:BSPIM:mosi_from_dp\ - ); - Output = Net_30 (fanout=2) - Properties : - { - } - - [McSlotId=2]: (empty) - [McSlotId=3]: (empty) -} - -statusicell: Name =\SPIM:BSPIM:RxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_6 => \SPIM:BSPIM:rx_status_6\ , - status_5 => \SPIM:BSPIM:rx_status_5\ , - status_4 => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "1000000" - } - Clock Polarity: Active High - Clock Enable: True - -UDB [UDB=(0,5)] contents: -LAB@[UDB=(0,5)][LB=0] #macrocells=4, #inputs=9, #pterms=7 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:state_2\, Mode=(D-Register) @ [UDB=(0,5)][LB=0][MC=0] - Total # of inputs : 9 - Total # of product terms : 2 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 2 pterms - ( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - \SPIM:BSPIM:count_1\ * !\SPIM:BSPIM:count_0\ * - !\SPIM:BSPIM:tx_status_1\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:state_2\ (fanout=11) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=\SPIM:BSPIM:tx_status_0\, Mode=(Combinatorial) @ [UDB=(0,5)][LB=0][MC=1] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - ); - Output = \SPIM:BSPIM:tx_status_0\ (fanout=1) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:state_0\, Mode=(T-Register) @ [UDB=(0,5)][LB=0][MC=2] - Total # of inputs : 9 - Total # of product terms : 4 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 4 pterms - !( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ * !\SPIM:BSPIM:count_4\ * - !\SPIM:BSPIM:count_3\ * !\SPIM:BSPIM:count_2\ * - !\SPIM:BSPIM:count_1\ * \SPIM:BSPIM:count_0\ - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:state_0\ * - \SPIM:BSPIM:tx_status_1\ - + \SPIM:BSPIM:state_1\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * \SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ - ); - Output = \SPIM:BSPIM:state_0\ (fanout=11) - Properties : - { - } - - [McSlotId=3]: MacroCell: Name=Net_31, Mode=(D-Register) @ [UDB=(0,5)][LB=0][MC=3] - Total # of inputs : 3 - Total # of product terms : 1 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 1 pterm - !( - !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = Net_31 (fanout=1) - Properties : - { - } -} - -LAB@[UDB=(0,5)][LB=1] #macrocells=3, #inputs=10, #pterms=8 -{ - [McSlotId=0]: MacroCell: Name=\SPIM:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(0,5)][LB=1][MC=0] - Total # of inputs : 9 - Total # of product terms : 5 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 5 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * \SPIM:BSPIM:count_1\ * - !\SPIM:BSPIM:count_0\ * !\SPIM:BSPIM:tx_status_1\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ - + \SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_0\ - + \SPIM:BSPIM:state_1\ * \SPIM:BSPIM:state_0\ * - !\SPIM:BSPIM:count_4\ * !\SPIM:BSPIM:count_3\ * - !\SPIM:BSPIM:count_2\ * !\SPIM:BSPIM:count_1\ * - \SPIM:BSPIM:count_0\ - ); - Output = \SPIM:BSPIM:state_1\ (fanout=11) - Properties : - { - } - - [McSlotId=1]: MacroCell: Name=Net_107, Mode=(D-Register) @ [UDB=(0,5)][LB=1][MC=1] - Total # of inputs : 4 - Total # of product terms : 3 - List of special equations: - Clock = (\SPIM:Net_276\) => Global - Clock Enable: True - Main Equation : 3 pterms - !( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - \SPIM:BSPIM:state_0\ - + !\SPIM:BSPIM:state_2\ * \SPIM:BSPIM:state_1\ * !Net_107 - + \SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * !Net_107 - ); - Output = Net_107 (fanout=2) - Properties : - { - } - - [McSlotId=2]: MacroCell: Name=\SPIM:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(0,5)][LB=1][MC=2] - Total # of inputs : 3 - Total # of product terms : 1 - Clock Enable: True - Main Equation : 1 pterm - ( - !\SPIM:BSPIM:state_2\ * !\SPIM:BSPIM:state_1\ * - !\SPIM:BSPIM:state_0\ - ); - Output = \SPIM:BSPIM:tx_status_4\ (fanout=1) - Properties : - { - } - - [McSlotId=3]: (empty) -} - -datapathcell: Name =\SPIM:BSPIM:sR8:Dp:u0\ - PORT MAP ( - clock => \SPIM:Net_276\ , - cs_addr_2 => \SPIM:BSPIM:state_2\ , - cs_addr_1 => \SPIM:BSPIM:state_1\ , - cs_addr_0 => \SPIM:BSPIM:state_0\ , - route_si => Net_20 , - f1_load => \SPIM:BSPIM:load_rx_data\ , - so_comb => \SPIM:BSPIM:mosi_from_dp\ , - f0_bus_stat_comb => \SPIM:BSPIM:tx_status_2\ , - f0_blk_stat_comb => \SPIM:BSPIM:tx_status_1\ , - f1_bus_stat_comb => \SPIM:BSPIM:rx_status_5\ , - f1_blk_stat_comb => \SPIM:BSPIM:rx_status_4\ ); - Properties: - { - a0_init = "00000000" - a1_init = "00000000" - ce0_sync = 1 - ce1_sync = 1 - cl0_sync = 1 - cl1_sync = 1 - cmsb_sync = 1 - co_msb_sync = 1 - cy_dpconfig = "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100" - d0_init = "00000000" - d1_init = "00000000" - f0_blk_sync = 1 - f0_bus_sync = 1 - f1_blk_sync = 1 - f1_bus_sync = 1 - ff0_sync = 1 - ff1_sync = 1 - ov_msb_sync = 1 - so_sync = 1 - z0_sync = 1 - z1_sync = 1 - } - Clock Polarity: Active High - Clock Enable: True - -count7cell: Name =\SPIM:BSPIM:BitCounter\ - PORT MAP ( - clock => \SPIM:Net_276\ , - enable => \SPIM:BSPIM:cnt_enable\ , - count_6 => \SPIM:BSPIM:count_6\ , - count_5 => \SPIM:BSPIM:count_5\ , - count_4 => \SPIM:BSPIM:count_4\ , - count_3 => \SPIM:BSPIM:count_3\ , - count_2 => \SPIM:BSPIM:count_2\ , - count_1 => \SPIM:BSPIM:count_1\ , - count_0 => \SPIM:BSPIM:count_0\ , - tc => \SPIM:BSPIM:cnt_tc\ ); - Properties: - { - cy_alt_mode = 0 - cy_init_value = "0000000" - cy_period = "0001111" - cy_route_en = 1 - cy_route_ld = 0 - } - Clock Polarity: Active High - Clock Enable: True - -UDB [UDB=(1,0)] is empty. -UDB [UDB=(1,1)] is empty. -UDB [UDB=(1,2)] is empty. -UDB [UDB=(1,3)] is empty. -UDB [UDB=(1,4)] contents: -statusicell: Name =\SPIM:BSPIM:TxStsReg\ - PORT MAP ( - clock => \SPIM:Net_276\ , - status_4 => \SPIM:BSPIM:tx_status_4\ , - status_3 => \SPIM:BSPIM:load_rx_data\ , - status_2 => \SPIM:BSPIM:tx_status_2\ , - status_1 => \SPIM:BSPIM:tx_status_1\ , - status_0 => \SPIM:BSPIM:tx_status_0\ ); - Properties: - { - cy_force_order = 1 - cy_int_mask = "0000000" - cy_md_select = "0001001" - } - Clock Polarity: Active High - Clock Enable: True - -UDB [UDB=(1,5)] is empty. -UDB [UDB=(2,0)] is empty. -UDB [UDB=(2,1)] is empty. -UDB [UDB=(2,2)] is empty. -UDB [UDB=(2,3)] is empty. -UDB [UDB=(2,4)] is empty. -UDB [UDB=(2,5)] is empty. -UDB [UDB=(3,0)] is empty. -UDB [UDB=(3,1)] is empty. -UDB [UDB=(3,2)] is empty. -UDB [UDB=(3,3)] is empty. -UDB [UDB=(3,4)] is empty. -UDB [UDB=(3,5)] is empty. -Intr hod @ [IntrHod=(0)]: empty -Drq hod @ [DrqHod=(0)]: empty -Port 0 contains the following IO cells: -[IoId=0]: -Pin : Name = m_miso_pin(0) - Attributes: - In Group/Port: True - In Sync Option: NOSYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: HI_Z_DIGITAL - VTrip: CMOS - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - fb => Net_20 , - pad => m_miso_pin(0)_PAD ); - Properties: - { - } - -[IoId=5]: -Pin : Name = m_mosi_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_30 , - pad => m_mosi_pin(0)_PAD ); - Properties: - { - } - -[IoId=6]: -Pin : Name = m_sclk_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_31 , - pad => m_sclk_pin(0)_PAD ); - Properties: - { - } - -[IoId=7]: -Pin : Name = m_ss_pin(0) - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - input => Net_107 , - pad => m_ss_pin(0)_PAD ); - Properties: - { - } - -Port 1 is empty -Port 2 contains the following IO cells: -[IoId=0]: -Pin : Name = \LCD:LCDPort(0)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(0)_PAD\ ); - Properties: - { - } - -[IoId=1]: -Pin : Name = \LCD:LCDPort(1)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(1)_PAD\ ); - Properties: - { - } - -[IoId=2]: -Pin : Name = \LCD:LCDPort(2)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(2)_PAD\ ); - Properties: - { - } - -[IoId=3]: -Pin : Name = \LCD:LCDPort(3)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(3)_PAD\ ); - Properties: - { - } - -[IoId=4]: -Pin : Name = \LCD:LCDPort(4)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(4)_PAD\ ); - Properties: - { - } - -[IoId=5]: -Pin : Name = \LCD:LCDPort(5)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(5)_PAD\ ); - Properties: - { - } - -[IoId=6]: -Pin : Name = \LCD:LCDPort(6)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pad => \LCD:LCDPort(6)_PAD\ ); - Properties: - { - } - -Port 3 is empty -Port 4 is empty -Port 5 is empty -Port 6 is empty -Port 12 is empty -Port 15 is empty -Fixed Function block hod @ [FFB(CAN,0)]: empty -Fixed Function block hod @ [FFB(Cache,0)]: empty -Fixed Function block hod @ [FFB(CapSense,0)]: empty -Fixed Function block hod @ [FFB(Clock,0)]: - Clock Block @ [FFB(Clock,0)]: - clockblockcell: Name =ClockBlock - PORT MAP ( - clk_bus_glb => ClockBlock_BUS_CLK , - clk_bus => ClockBlock_BUS_CLK_local , - clk_sync => ClockBlock_MASTER_CLK , - clk_32k_xtal => ClockBlock_XTAL_32KHZ , - xtal => ClockBlock_XTAL , - ilo => ClockBlock_ILO , - clk_100k => ClockBlock_100k , - clk_1k => ClockBlock_1k , - clk_32k => ClockBlock_32k , - pllout => ClockBlock_PLL_OUT , - imo => ClockBlock_IMO , - dclk_glb_0 => \SPIM:Net_276\ , - dclk_0 => \SPIM:Net_276_local\ ); - Properties: - { - } -Fixed Function block hod @ [FFB(Comparator,0)]: empty -Fixed Function block hod @ [FFB(DFB,0)]: empty -Fixed Function block hod @ [FFB(DSM,0)]: empty -Fixed Function block hod @ [FFB(Decimator,0)]: empty -Fixed Function block hod @ [FFB(EMIF,0)]: empty -Fixed Function block hod @ [FFB(I2C,0)]: empty -Fixed Function block hod @ [FFB(LCD,0)]: empty -Fixed Function block hod @ [FFB(LVD,0)]: empty -Fixed Function block hod @ [FFB(PM,0)]: empty -Fixed Function block hod @ [FFB(SC,0)]: empty -Fixed Function block hod @ [FFB(SPC,0)]: empty -Fixed Function block hod @ [FFB(Timer,0)]: empty -Fixed Function block hod @ [FFB(USB,0)]: empty -Fixed Function block hod @ [FFB(VIDAC,0)]: empty -Fixed Function block hod @ [FFB(Abuf,0)]: empty -Fixed Function block hod @ [FFB(CsAbuf,0)]: empty -Fixed Function block hod @ [FFB(Vref,0)]: empty -Fixed Function block hod @ [FFB(LPF,0)]: empty -Fixed Function block hod @ [FFB(SAR,0)]: empty -Fixed Function block hod @ [FFB(TimingFault,0)]: empty - - - ------------------------------------------------------------- -Port Configuration report ------------------------------------------------------------- - | | | Interrupt | | | -Port | Pin | Fixed | Type | Drive Mode | Name | Connections ------+-----+-------+-----------+------------------+------------------+------------ - 0 | 0 | * | NONE | HI_Z_DIGITAL | m_miso_pin(0) | FB(Net_20) - | 5 | * | NONE | CMOS_OUT | m_mosi_pin(0) | In(Net_30) - | 6 | * | NONE | CMOS_OUT | m_sclk_pin(0) | In(Net_31) - | 7 | * | NONE | CMOS_OUT | m_ss_pin(0) | In(Net_107) ------+-----+-------+-----------+------------------+------------------+------------ - 2 | 0 | * | NONE | CMOS_OUT | \LCD:LCDPort(0)\ | - | 1 | * | NONE | CMOS_OUT | \LCD:LCDPort(1)\ | - | 2 | * | NONE | CMOS_OUT | \LCD:LCDPort(2)\ | - | 3 | * | NONE | CMOS_OUT | \LCD:LCDPort(3)\ | - | 4 | * | NONE | CMOS_OUT | \LCD:LCDPort(4)\ | - | 5 | * | NONE | CMOS_OUT | \LCD:LCDPort(5)\ | - | 6 | * | NONE | CMOS_OUT | \LCD:LCDPort(6)\ | ----------------------------------------------------------------------------------- - -Log: plm.M0038: The pin named m_miso_pin(0) at location P0[0] prevents usage of special purposes: OpAmp:out. (App=cydsfit) -Log: plm.M0040: The pin named m_mosi_pin(0) at location P0[5] prevents a direct input connection to an Opamp. (App=cydsfit) -Log: plm.M0039: The pin named m_sclk_pin(0) at location P0[6] prevents usage of the high current (2mA) feature of an IDAC. (App=cydsfit) -Log: plm.M0039: The pin named m_ss_pin(0) at location P0[7] prevents usage of the high current (2mA) feature of an IDAC. (App=cydsfit) -Info: plm.M0037: SPI_Design01.rpt: - Certain internal analog resources use the following pins for preferred routing: P0[0], P0[5], P0[6], P0[7]. - Please check the "Final Placement Details" section of the report file (SPI_Design01.rpt) to see what resources are impacted by your pin selections. - (File=C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.rpt(1)) - - -Digital component placer commit/Report: Elapsed time ==> 0s.004ms -Digital Placement phase: Elapsed time ==> 0s.995ms - - -Routing successful. -Digital Routing phase: Elapsed time ==> 1s.791ms - - -Bitstream and API generation phase: Elapsed time ==> 0s.258ms - - -Bitstream verification phase: Elapsed time ==> 0s.074ms - - -Timing report is in SPI_Design01_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.271ms - - -Data reporting phase: Elapsed time ==> 0s.000ms - - -Design database save phase: Elapsed time ==> 0s.190ms - -cydsfit: Elapsed time ==> 4s.355ms - -Fitter phase: Elapsed time ==> 4s.394ms -API generation phase: Elapsed time ==> 0s.324ms -Dependency generation phase: Elapsed time ==> 0s.004ms -Cleanup phase: Elapsed time ==> 0s.001ms diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rt_log b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rt_log deleted file mode 100644 index 6d7632b..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.rt_log +++ /dev/null @@ -1,28 +0,0 @@ - - SoftJin Router, Version 1.0 - -I1203: Reading Design SPI_Design01 -I1204: Reading netlist from file SPI_Design01_r.vh2 -I1206: Completed Reading of file SPI_Design01_r.vh2 -I1204: Reading placement from file SPI_Design01.pco -I1206: Completed Reading of file SPI_Design01.pco -I1204: Reading timing library from file SPI_Design01_r.lib -I1206: Completed Reading of file SPI_Design01_r.lib -I1204: Reading timing constraints from file SPI_Design01.sdc -I1206: Completed Reading of file SPI_Design01.sdc -I1204: Reading architecture from file C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\dev/psoc5/route_arch-rrg.cydata -I1206: Completed Reading of file C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\dev/psoc5/route_arch-rrg.cydata -I1209: Started routing -I1223: Total Nets : 25 -I1212: Iteration 1 : 20 unrouted : 0 seconds -I1212: Iteration 2 : 8 unrouted : 0 seconds -I1212: Iteration 3 : 4 unrouted : 0 seconds -I1212: Iteration 4 : 4 unrouted : 0 seconds -I1212: Iteration 5 : 4 unrouted : 0 seconds -I1212: Iteration 6 : 3 unrouted : 0 seconds -I1212: Iteration 7 : 0 unrouted : 0 seconds -I1215: Routing is successful -I1207: Completed routing -I1210: Writing routes -I1218: Exiting the router -I1224: Total Time : 2 seconds diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.sdc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.sdc deleted file mode 100644 index a4ef32d..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.sdc +++ /dev/null @@ -1,15 +0,0 @@ -# THIS FILE IS AUTOMATICALLY GENERATED -# Project: C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -# Date: Wed, 16 Jan 2013 13:35:46 GMT -#set_units -time ns -create_clock -name {CyIMO} -period 333.33333333333331 -waveform {0 166.666666666667} [list [get_pins {ClockBlock/imo}]] -create_clock -name {CyPLL_OUT} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/pllout}]] -create_clock -name {CyILO} -period 1000000 -waveform {0 500000} [list [get_pins {ClockBlock/ilo}] [get_pins {ClockBlock/clk_100k}] [get_pins {ClockBlock/clk_1k}] [get_pins {ClockBlock/clk_32k}]] -create_clock -name {CyMASTER_CLK} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/clk_sync}]] -create_generated_clock -name {SPIM_IntClock} -source [get_pins {ClockBlock/clk_sync}] -edges {1 13 25} [list [get_pins {ClockBlock/dclk_glb_0}]] -create_generated_clock -name {CyBUS_CLK} -source [get_pins {ClockBlock/clk_sync}] -edges {1 2 3} [list [get_pins {ClockBlock/clk_bus_glb}]] - - -# Component constraints for C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\TopDesign\TopDesign.cysch -# Project: C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -# Date: Wed, 16 Jan 2013 13:35:44 GMT diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.svd b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.svd deleted file mode 100644 index 23c06e2..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.svd +++ /dev/null @@ -1,9 +0,0 @@ - - - CY8C5568AXI_060 - 0.1 - CY8C55 - 8 - 32 - - \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.tr b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.tr deleted file mode 100644 index 76465d0..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.tr +++ /dev/null @@ -1,2806 +0,0 @@ -##################################################################### - Table of Contents -===================================================================== - 1::Clock Frequency Summary - 2::Clock Relationship Summary - 3::Datasheet Report - 3.1::Setup to Clock - 3.2::Clock to Out - 3.3::Pad to Pad - 4::Path Details for Clock Frequency Summary - 4.1::Critical Path Report for SPIM_IntClock - 5::Path Details for Clock Relationship Summary - 5.1::Critical Path Report for (SPIM_IntClock:R vs. SPIM_IntClock:R) -===================================================================== - End of Table of Contents -##################################################################### - -##################################################################### - 1::Clock Frequency Summary -===================================================================== -Number of clocks: 6 -Clock: CyBUS_CLK | N/A | Target: 24.00 MHz | -Clock: CyILO | N/A | Target: 0.00 MHz | -Clock: CyIMO | N/A | Target: 3.00 MHz | -Clock: CyMASTER_CLK | N/A | Target: 24.00 MHz | -Clock: CyPLL_OUT | N/A | Target: 24.00 MHz | -Clock: SPIM_IntClock | Frequency: 62.07 MHz | Target: 2.00 MHz | - - ===================================================================== - End of Clock Frequency Summary - ##################################################################### - - - ##################################################################### - 2::Clock Relationship Summary - ===================================================================== - -Launch Clock Capture Clock Constraint(R-R) Slack(R-R) Constraint(R-F) Slack(R-F) Constraint(F-F) Slack(F-F) Constraint(F-R) Slack(F-R) -------------- ------------- --------------- ---------- --------------- ---------- --------------- ---------- --------------- ---------- -SPIM_IntClock SPIM_IntClock 500000 483888 N/A N/A N/A N/A N/A N/A - - ===================================================================== - End of Clock Relationship Summary - ##################################################################### - - - ##################################################################### - 3::Datasheet Report - -All values are in Picoseconds - ===================================================================== - -3.1::Setup to Clock -------------------- - -Port Name Setup to Clk Clock Name:Phase ------------------ ------------ ---------------- -m_miso_pin(0)_PAD 40184 SPIM_IntClock:R - - - 3.2::Clock to Out - ----------------- - -Port Name Clock to Out Clock Name:Phase ------------------ ------------ ---------------- -m_mosi_pin(0)_PAD 26096 SPIM_IntClock:R -m_sclk_pin(0)_PAD 25455 SPIM_IntClock:R -m_ss_pin(0)_PAD 26426 SPIM_IntClock:R - - - 3.3::Pad to Pad - --------------- - -Port Name (Source) Port Name (Destination) Delay ------------------- ----------------------- ----- - -===================================================================== - End of Datasheet Report -##################################################################### -##################################################################### - 4::Path Details for Clock Frequency Summary -===================================================================== -4.1::Critical Path Report for SPIM_IntClock -******************************************* -Clock: SPIM_IntClock -Frequency: 62.07 MHz | Target: 2.00 MHz - -++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483888p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 14542 -------------------------------------- ----- -End-of-path arrival time (ps) 14542 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell7 3604 8884 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell7 3350 12234 483888 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14542 483888 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 - - - -===================================================================== - End of Path Details for Clock Frequency Summary -##################################################################### - - -##################################################################### - 5::Path Details for Clock Relationship Summary -===================================================================== - -5.1::Critical Path Report for (SPIM_IntClock:R vs. SPIM_IntClock:R) -******************************************************************* - -++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483888p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 14542 -------------------------------------- ----- -End-of-path arrival time (ps) 14542 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell7 3604 8884 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell7 3350 12234 483888 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14542 483888 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 - - - -===================================================================== - End of Path Details for Clock Relationship Summary -##################################################################### - -##################################################################### - Detailed Report for all timing paths -===================================================================== - -++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb -Path End : \SPIM:BSPIM:RxStsReg\/status_6 -Capture Clock : \SPIM:BSPIM:RxStsReg\/clock -Path slack : 483888p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 14542 -------------------------------------- ----- -End-of-path arrival time (ps) 14542 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb datapathcell1 5280 5280 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/main_5 macrocell7 3604 8884 483888 RISE 1 -\SPIM:BSPIM:rx_status_6\/q macrocell7 3350 12234 483888 RISE 1 -\SPIM:BSPIM:RxStsReg\/status_6 statusicell1 2308 14542 483888 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:RxStsReg\/clock statusicell1 0 0 RISE 1 - - - -++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:sR8:Dp:u0\/f1_load -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 484183p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1850 --------------------------------------------------------- ------ -End-of-path required time (ps) 498150 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 13967 -------------------------------------- ----- -End-of-path arrival time (ps) 13967 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_3 macrocell6 5595 7705 484183 RISE 1 -\SPIM:BSPIM:load_rx_data\/q macrocell6 3350 11055 484183 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/f1_load datapathcell1 2913 13967 484183 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - - - -++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:TxStsReg\/status_3 -Capture Clock : \SPIM:BSPIM:TxStsReg\/clock -Path slack : 485060p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 13370 -------------------------------------- ----- -End-of-path arrival time (ps) 13370 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------ ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:load_rx_data\/main_3 macrocell6 5595 7705 484183 RISE 1 -\SPIM:BSPIM:load_rx_data\/q macrocell6 3350 11055 484183 RISE 1 -\SPIM:BSPIM:TxStsReg\/status_3 statusicell2 2315 13370 485060 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 - - - -++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/so_comb -Path End : Net_30/main_4 -Capture Clock : Net_30/clock_0 -Path slack : 485272p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 11218 -------------------------------------- ----- -End-of-path arrival time (ps) 11218 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/so_comb datapathcell1 8300 8300 485272 RISE 1 -Net_30/main_4 macrocell2 2918 11218 485272 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - - - -++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_1\/main_8 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 486251p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 10239 -------------------------------------- ----- -End-of-path arrival time (ps) 10239 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486251 RISE 1 -\SPIM:BSPIM:state_1\/main_8 macrocell9 4959 10239 486251 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_0\/main_8 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 487229p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 9261 -------------------------------------- ---- -End-of-path arrival time (ps) 9261 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486251 RISE 1 -\SPIM:BSPIM:state_0\/main_8 macrocell8 3981 9261 487229 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb -Path End : \SPIM:BSPIM:state_2\/main_8 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 487229p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 9261 -------------------------------------- ---- -End-of-path arrival time (ps) 9261 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb datapathcell1 5280 5280 486251 RISE 1 -\SPIM:BSPIM:state_2\/main_8 macrocell10 3981 9261 487229 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:load_cond\/main_6 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 487687p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 8803 -------------------------------------- ---- -End-of-path arrival time (ps) 8803 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:load_cond\/main_6 macrocell5 6693 8803 487687 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:TxStsReg\/status_0 -Capture Clock : \SPIM:BSPIM:TxStsReg\/clock -Path slack : 487846p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -1570 --------------------------------------------------------- ------ -End-of-path required time (ps) 498430 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 10584 -------------------------------------- ----- -End-of-path arrival time (ps) 10584 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ------------ ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:tx_status_0\/main_0 macrocell11 3078 4328 487846 RISE 1 -\SPIM:BSPIM:tx_status_0\/q macrocell11 3350 7678 487846 RISE 1 -\SPIM:BSPIM:TxStsReg\/status_0 statusicell2 2906 10584 487846 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:TxStsReg\/clock statusicell2 0 0 RISE 1 - - - -++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 488486p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 --------------------------------------------------------- ------ -End-of-path required time (ps) 492830 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4344 -------------------------------------- ---- -End-of-path arrival time (ps) 4344 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_0 datapathcell1 3094 4344 488486 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - - - -++++ Path 11 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 488617p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 --------------------------------------------------------- ------ -End-of-path required time (ps) 492830 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4213 -------------------------------------- ---- -End-of-path arrival time (ps) 4213 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 datapathcell1 2963 4213 488617 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - - - -++++ Path 12 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:cnt_enable\/main_6 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 488785p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 7705 -------------------------------------- ---- -End-of-path arrival time (ps) 7705 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_6 macrocell4 5595 7705 488785 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 13 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 -Capture Clock : \SPIM:BSPIM:sR8:Dp:u0\/clock -Path slack : 489284p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -7170 --------------------------------------------------------- ------ -End-of-path required time (ps) 492830 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3546 -------------------------------------- ---- -End-of-path arrival time (ps) 3546 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------------------------- ------------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 datapathcell1 2296 3546 489284 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:sR8:Dp:u0\/clock datapathcell1 0 0 RISE 1 - - - -++++ Path 14 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:state_0\/main_6 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 489733p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 6757 -------------------------------------- ---- -End-of-path arrival time (ps) 6757 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:state_0\/main_6 macrocell8 4647 6757 489733 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 15 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:state_2\/main_6 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 489733p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 6757 -------------------------------------- ---- -End-of-path arrival time (ps) 6757 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:state_2\/main_6 macrocell10 4647 6757 489733 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 16 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:cnt_enable\/main_5 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490485p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 6005 -------------------------------------- ---- -End-of-path arrival time (ps) 6005 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 485882 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_5 macrocell4 3895 6005 490485 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 17 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:load_cond\/main_5 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490494p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5996 -------------------------------------- ---- -End-of-path arrival time (ps) 5996 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 485882 RISE 1 -\SPIM:BSPIM:load_cond\/main_5 macrocell5 3886 5996 490494 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 18 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:cnt_enable\/main_3 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490633p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5857 -------------------------------------- ---- -End-of-path arrival time (ps) 5857 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486030 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_3 macrocell4 3747 5857 490633 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 19 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_1 -Path End : \SPIM:BSPIM:state_1\/main_6 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 490635p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5855 -------------------------------------- ---- -End-of-path arrival time (ps) 5855 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_1 count7cell 2110 2110 484183 RISE 1 -\SPIM:BSPIM:state_1\/main_6 macrocell9 3745 5855 490635 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 20 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:load_cond\/main_4 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490642p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5848 -------------------------------------- ---- -End-of-path arrival time (ps) 5848 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486048 RISE 1 -\SPIM:BSPIM:load_cond\/main_4 macrocell5 3738 5848 490642 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 21 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:cnt_enable\/main_4 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490651p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5839 -------------------------------------- ---- -End-of-path arrival time (ps) 5839 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486048 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_4 macrocell4 3729 5839 490651 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 22 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:load_cond\/main_7 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490660p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5830 -------------------------------------- ---- -End-of-path arrival time (ps) 5830 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486060 RISE 1 -\SPIM:BSPIM:load_cond\/main_7 macrocell5 3720 5830 490660 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 23 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:cnt_enable\/main_7 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 490663p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5827 -------------------------------------- ---- -End-of-path arrival time (ps) 5827 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486060 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_7 macrocell4 3717 5827 490663 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 24 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:load_cond\/main_3 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 490671p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5819 -------------------------------------- ---- -End-of-path arrival time (ps) 5819 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486030 RISE 1 -\SPIM:BSPIM:load_cond\/main_3 macrocell5 3709 5819 490671 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 25 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_0 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 491059p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5431 -------------------------------------- ---- -End-of-path arrival time (ps) 5431 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_0 macrocell4 4181 5431 491059 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 26 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : Net_30/main_1 -Capture Clock : Net_30/clock_0 -Path slack : 491070p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5420 -------------------------------------- ---- -End-of-path arrival time (ps) 5420 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -Net_30/main_1 macrocell2 4170 5420 491070 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - - - -++++ Path 27 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:load_cond\/main_0 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 491070p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5420 -------------------------------------- ---- -End-of-path arrival time (ps) 5420 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:load_cond\/main_0 macrocell5 4170 5420 491070 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 28 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : Net_30/main_3 -Capture Clock : Net_30/clock_0 -Path slack : 491245p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5245 -------------------------------------- ---- -End-of-path arrival time (ps) 5245 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -Net_30/main_3 macrocell2 3995 5245 491245 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - - - -++++ Path 29 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:load_cond\/main_2 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 491245p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5245 -------------------------------------- ---- -End-of-path arrival time (ps) 5245 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:load_cond\/main_2 macrocell5 3995 5245 491245 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 30 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_2 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 491363p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 5127 -------------------------------------- ---- -End-of-path arrival time (ps) 5127 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_2 macrocell4 3877 5127 491363 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 31 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_1 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 491547p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4943 -------------------------------------- ---- -End-of-path arrival time (ps) 4943 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_1 macrocell4 3693 4943 491547 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 32 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:state_0\/main_3 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491558p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4932 -------------------------------------- ---- -End-of-path arrival time (ps) 4932 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486030 RISE 1 -\SPIM:BSPIM:state_0\/main_3 macrocell8 2822 4932 491558 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 33 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:state_2\/main_3 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491558p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4932 -------------------------------------- ---- -End-of-path arrival time (ps) 4932 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486030 RISE 1 -\SPIM:BSPIM:state_2\/main_3 macrocell10 2822 4932 491558 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 34 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : Net_30/main_2 -Capture Clock : Net_30/clock_0 -Path slack : 491558p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4932 -------------------------------------- ---- -End-of-path arrival time (ps) 4932 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -Net_30/main_2 macrocell2 3682 4932 491558 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - - - -++++ Path 35 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:load_cond\/main_1 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 491558p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4932 -------------------------------------- ---- -End-of-path arrival time (ps) 4932 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:load_cond\/main_1 macrocell5 3682 4932 491558 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - - -++++ Path 36 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:state_1\/main_4 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 491562p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4928 -------------------------------------- ---- -End-of-path arrival time (ps) 4928 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486048 RISE 1 -\SPIM:BSPIM:state_1\/main_4 macrocell9 2818 4928 491562 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:state_0\/main_4 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491578p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4912 -------------------------------------- ---- -End-of-path arrival time (ps) 4912 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486048 RISE 1 -\SPIM:BSPIM:state_0\/main_4 macrocell8 2802 4912 491578 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 38 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_3 -Path End : \SPIM:BSPIM:state_2\/main_4 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491578p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4912 -------------------------------------- ---- -End-of-path arrival time (ps) 4912 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_3 count7cell 2110 2110 486048 RISE 1 -\SPIM:BSPIM:state_2\/main_4 macrocell10 2802 4912 491578 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 39 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:state_1\/main_7 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 491579p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4911 -------------------------------------- ---- -End-of-path arrival time (ps) 4911 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486060 RISE 1 -\SPIM:BSPIM:state_1\/main_7 macrocell9 2801 4911 491579 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 40 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:state_0\/main_5 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491584p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4906 -------------------------------------- ---- -End-of-path arrival time (ps) 4906 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 485882 RISE 1 -\SPIM:BSPIM:state_0\/main_5 macrocell8 2796 4906 491584 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 41 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:state_2\/main_5 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491584p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4906 -------------------------------------- ---- -End-of-path arrival time (ps) 4906 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 485882 RISE 1 -\SPIM:BSPIM:state_2\/main_5 macrocell10 2796 4906 491584 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 42 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_4 -Path End : \SPIM:BSPIM:state_1\/main_3 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 491590p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4900 -------------------------------------- ---- -End-of-path arrival time (ps) 4900 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_4 count7cell 2110 2110 486030 RISE 1 -\SPIM:BSPIM:state_1\/main_3 macrocell9 2790 4900 491590 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 43 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_2 -Path End : \SPIM:BSPIM:state_1\/main_5 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 491591p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4899 -------------------------------------- ---- -End-of-path arrival time (ps) 4899 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_2 count7cell 2110 2110 485882 RISE 1 -\SPIM:BSPIM:state_1\/main_5 macrocell9 2789 4899 491591 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 44 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:state_0\/main_7 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 491592p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4898 -------------------------------------- ---- -End-of-path arrival time (ps) 4898 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486060 RISE 1 -\SPIM:BSPIM:state_0\/main_7 macrocell8 2788 4898 491592 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 45 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:BitCounter\/count_0 -Path End : \SPIM:BSPIM:state_2\/main_7 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 491592p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4898 -------------------------------------- ---- -End-of-path arrival time (ps) 4898 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:BitCounter\/count_0 count7cell 2110 2110 486060 RISE 1 -\SPIM:BSPIM:state_2\/main_7 macrocell10 2788 4898 491592 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 46 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : Net_30/q -Path End : Net_30/main_0 -Capture Clock : Net_30/clock_0 -Path slack : 491738p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4752 -------------------------------------- ---- -End-of-path arrival time (ps) 4752 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout -------------- ----------- ----- ----- ------ ---- ------ -Net_30/q macrocell2 1250 1250 491738 RISE 1 -Net_30/main_0 macrocell2 3502 4752 491738 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_30/clock_0 macrocell2 0 0 RISE 1 - - - -++++ Path 47 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : Net_107/q -Path End : Net_107/main_3 -Capture Clock : Net_107/clock_0 -Path slack : 491739p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4751 -------------------------------------- ---- -End-of-path arrival time (ps) 4751 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_107/clock_0 macrocell1 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout --------------- ----------- ----- ----- ------ ---- ------ -Net_107/q macrocell1 1250 1250 491739 RISE 1 -Net_107/main_3 macrocell1 3501 4751 491739 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_107/clock_0 macrocell1 0 0 RISE 1 - - - -++++ Path 48 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:cnt_enable\/q -Path End : \SPIM:BSPIM:BitCounter\/enable -Capture Clock : \SPIM:BSPIM:BitCounter\/clock -Path slack : 491972p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3340 --------------------------------------------------------- ------ -End-of-path required time (ps) 496660 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4688 -------------------------------------- ---- -End-of-path arrival time (ps) 4688 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:cnt_enable\/q macrocell4 1250 1250 491972 RISE 1 -\SPIM:BSPIM:BitCounter\/enable count7cell 3438 4688 491972 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:BitCounter\/clock count7cell 0 0 RISE 1 - - - -++++ Path 49 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : Net_107/main_2 -Capture Clock : Net_107/clock_0 -Path slack : 492157p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4333 -------------------------------------- ---- -End-of-path arrival time (ps) 4333 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -Net_107/main_2 macrocell1 3083 4333 492157 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_107/clock_0 macrocell1 0 0 RISE 1 - - - -++++ Path 50 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_1\/main_2 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 492157p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4333 -------------------------------------- ---- -End-of-path arrival time (ps) 4333 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:state_1\/main_2 macrocell9 3083 4333 492157 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 51 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : Net_107/main_0 -Capture Clock : Net_107/clock_0 -Path slack : 492160p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4330 -------------------------------------- ---- -End-of-path arrival time (ps) 4330 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -Net_107/main_0 macrocell1 3080 4330 492160 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_107/clock_0 macrocell1 0 0 RISE 1 - - - -++++ Path 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_1\/main_0 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 492160p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4330 -------------------------------------- ---- -End-of-path arrival time (ps) 4330 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:state_1\/main_0 macrocell9 3080 4330 492160 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : Net_31/main_0 -Capture Clock : Net_31/clock_0 -Path slack : 492162p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4328 -------------------------------------- ---- -End-of-path arrival time (ps) 4328 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -Net_31/main_0 macrocell3 3078 4328 492162 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_31/clock_0 macrocell3 0 0 RISE 1 - - - -++++ Path 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_0\/main_0 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 492162p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4328 -------------------------------------- ---- -End-of-path arrival time (ps) 4328 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:state_0\/main_0 macrocell8 3078 4328 492162 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_2\/q -Path End : \SPIM:BSPIM:state_2\/main_0 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 492162p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4328 -------------------------------------- ---- -End-of-path arrival time (ps) 4328 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_2\/q macrocell10 1250 1250 487846 RISE 1 -\SPIM:BSPIM:state_2\/main_0 macrocell10 3078 4328 492162 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : Net_31/main_2 -Capture Clock : Net_31/clock_0 -Path slack : 492290p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4200 -------------------------------------- ---- -End-of-path arrival time (ps) 4200 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -Net_31/main_2 macrocell3 2950 4200 492290 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_31/clock_0 macrocell3 0 0 RISE 1 - - - -++++ Path 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_0\/main_2 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 492290p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4200 -------------------------------------- ---- -End-of-path arrival time (ps) 4200 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:state_0\/main_2 macrocell8 2950 4200 492290 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_0\/q -Path End : \SPIM:BSPIM:state_2\/main_2 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 492290p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 4200 -------------------------------------- ---- -End-of-path arrival time (ps) 4200 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_0\/q macrocell8 1250 1250 487974 RISE 1 -\SPIM:BSPIM:state_2\/main_2 macrocell10 2950 4200 492290 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:cnt_enable\/q -Path End : \SPIM:BSPIM:cnt_enable\/main_8 -Capture Clock : \SPIM:BSPIM:cnt_enable\/clock_0 -Path slack : 492612p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3878 -------------------------------------- ---- -End-of-path arrival time (ps) 3878 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:cnt_enable\/q macrocell4 1250 1250 491972 RISE 1 -\SPIM:BSPIM:cnt_enable\/main_8 macrocell4 2628 3878 492612 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:cnt_enable\/clock_0 macrocell4 0 0 RISE 1 - - - -++++ Path 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : Net_31/main_1 -Capture Clock : Net_31/clock_0 -Path slack : 492647p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3843 -------------------------------------- ---- -End-of-path arrival time (ps) 3843 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -Net_31/main_1 macrocell3 2593 3843 492647 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_31/clock_0 macrocell3 0 0 RISE 1 - - - -++++ Path 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_0\/main_1 -Capture Clock : \SPIM:BSPIM:state_0\/clock_0 -Path slack : 492647p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3843 -------------------------------------- ---- -End-of-path arrival time (ps) 3843 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:state_0\/main_1 macrocell8 2593 3843 492647 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_0\/clock_0 macrocell8 0 0 RISE 1 - - - -++++ Path 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_2\/main_1 -Capture Clock : \SPIM:BSPIM:state_2\/clock_0 -Path slack : 492647p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3843 -------------------------------------- ---- -End-of-path arrival time (ps) 3843 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:state_2\/main_1 macrocell10 2593 3843 492647 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_2\/clock_0 macrocell10 0 0 RISE 1 - - - -++++ Path 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : Net_107/main_1 -Capture Clock : Net_107/clock_0 -Path slack : 492647p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3843 -------------------------------------- ---- -End-of-path arrival time (ps) 3843 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ----------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -Net_107/main_1 macrocell1 2593 3843 492647 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -Net_107/clock_0 macrocell1 0 0 RISE 1 - - - -++++ Path 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:state_1\/q -Path End : \SPIM:BSPIM:state_1\/main_1 -Capture Clock : \SPIM:BSPIM:state_1\/clock_0 -Path slack : 492647p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3843 -------------------------------------- ---- -End-of-path arrival time (ps) 3843 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ---------------------------- ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:state_1\/q macrocell9 1250 1250 488331 RISE 1 -\SPIM:BSPIM:state_1\/main_1 macrocell9 2593 3843 492647 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:state_1\/clock_0 macrocell9 0 0 RISE 1 - - - -++++ Path 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -Path Begin : \SPIM:BSPIM:load_cond\/q -Path End : \SPIM:BSPIM:load_cond\/main_8 -Capture Clock : \SPIM:BSPIM:load_cond\/clock_0 -Path slack : 492941p - -Capture Clock Arrival Time 0 -+ Clock path delay 0 -+ Cycle adjust (SPIM_IntClock:R#1 vs. SPIM_IntClock:R#2) 500000 -- Setup time -3510 --------------------------------------------------------- ------ -End-of-path required time (ps) 496490 - -Launch Clock Arrival Time 0 -+ Clock path delay 0 -+ Data path delay 3549 -------------------------------------- ---- -End-of-path arrival time (ps) 3549 - -Launch Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - -Data path -pin name model name delay AT slack edge Fanout ------------------------------ ----------- ----- ----- ------ ---- ------ -\SPIM:BSPIM:load_cond\/q macrocell5 1250 1250 492941 RISE 1 -\SPIM:BSPIM:load_cond\/main_8 macrocell5 2299 3549 492941 RISE 1 - -Capture Clock Path -pin name model name delay AT edge Fanout ---------------------------------------------------------- -------------- ----- ----- ---- ------ -ClockBlock/dclk_glb_0 clockblockcell 0 0 RISE 1 -\SPIM:BSPIM:load_cond\/clock_0 macrocell5 0 0 RISE 1 - - -===================================================================== - End of Detailed Report for all timing paths -##################################################################### - -##################################################################### - End of Timing Report -##################################################################### - diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.v b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.v deleted file mode 100644 index 729f27b..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.v +++ /dev/null @@ -1,421 +0,0 @@ -// ====================================================================== -// SPI_Design01.v generated from TopDesign.cysch -// 01/16/2013 at 14:35 -// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! -// ====================================================================== - -/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */ -`define CYDEV_CHIP_DIE_LEOPARD 1 -`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3 -`define CYDEV_CHIP_REV_LEOPARD_ES3 3 -`define CYDEV_CHIP_REV_LEOPARD_ES2 1 -`define CYDEV_CHIP_REV_LEOPARD_ES1 0 -`define CYDEV_CHIP_DIE_PANTHER 2 -`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1 -`define CYDEV_CHIP_REV_PANTHER_ES1 1 -`define CYDEV_CHIP_REV_PANTHER_ES0 0 -`define CYDEV_CHIP_DIE_PSOC5LP 3 -`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0 -`define CYDEV_CHIP_REV_PSOC5LP_ES 0 -`define CYDEV_CHIP_DIE_EXPECT 2 -`define CYDEV_CHIP_REV_EXPECT 1 -`define CYDEV_CHIP_DIE_ACTUAL 2 -/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */ -`define CYDEV_CHIP_FAMILY_UNKNOWN 0 -`define CYDEV_CHIP_MEMBER_UNKNOWN 0 -`define CYDEV_CHIP_FAMILY_PSOC3 1 -`define CYDEV_CHIP_MEMBER_3A 1 -`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3 -`define CYDEV_CHIP_REVISION_3A_ES3 3 -`define CYDEV_CHIP_REVISION_3A_ES2 1 -`define CYDEV_CHIP_REVISION_3A_ES1 0 -`define CYDEV_CHIP_FAMILY_PSOC5 2 -`define CYDEV_CHIP_MEMBER_5A 2 -`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1 -`define CYDEV_CHIP_REVISION_5A_ES1 1 -`define CYDEV_CHIP_REVISION_5A_ES0 0 -`define CYDEV_CHIP_MEMBER_5B 3 -`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0 -`define CYDEV_CHIP_REVISION_5B_ES 0 -`define CYDEV_CHIP_FAMILY_USED 2 -`define CYDEV_CHIP_MEMBER_USED 2 -`define CYDEV_CHIP_REVISION_USED 1 -// Component: ZeroTerminal -`ifdef CY_BLK_DIR -`undef CY_BLK_DIR -`endif - -`ifdef WARP -`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal" -`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v" -`else -`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal" -`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v" -`endif - -// Component: cy_virtualmux_v1_0 -`ifdef CY_BLK_DIR -`undef CY_BLK_DIR -`endif - -`ifdef WARP -`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0" -`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v" -`else -`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0" -`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v" -`endif - -// Component: B_SPI_Master_v2_30 -`ifdef CY_BLK_DIR -`undef CY_BLK_DIR -`endif - -`ifdef WARP -`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30" -`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v" -`else -`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30" -`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v" -`endif - -// SPI_Master_v2_30(BidirectMode=false, ClockInternal=true, CtlModeReplacementString=AsyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DesiredBitRate=1000000, HighSpeedMode=false, InternalClockUsed=1, InternalInterruptEnabled=0, InternalRxInterruptEnabled=0, InternalTxInterruptEnabled=0, InterruptOnByteComplete=false, InterruptOnRXFull=false, InterruptOnRXNotEmpty=false, InterruptOnRXOverrun=false, InterruptOnSPIDone=false, InterruptOnSPIIdle=false, InterruptOnTXEmpty=false, InterruptOnTXNotFull=false, IntOnByteComp=0, IntOnRXFull=0, IntOnRXNotEmpty=0, IntOnRXOver=0, IntOnSPIDone=0, IntOnSPIIdle=0, IntOnTXEmpty=0, IntOnTXNotFull=0, Mode=4, ModeUseZero=0, NumberOfDataBits=8, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, RxBufferSize=4, ShiftDir=0, TxBufferSize=4, UseInternalInterrupt=false, UseRxInternalInterrupt=false, UseTxInternalInterrupt=false, VerilogSectionReplacementString=sR8, CY_COMPONENT_NAME=SPI_Master_v2_30, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=SPIM, CY_INSTANCE_SHORT_NAME=SPIM, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=SPIM, ) -module SPI_Master_v2_30_0 ( - clock, - reset, - miso, - sclk, - mosi, - ss, - rx_interrupt, - sdat, - tx_interrupt); - input clock; - input reset; - input miso; - output sclk; - output mosi; - output ss; - output rx_interrupt; - inout sdat; - output tx_interrupt; - - parameter BidirectMode = 0; - parameter HighSpeedMode = 0; - parameter NumberOfDataBits = 8; - parameter ShiftDir = 0; - - wire Net_257; - wire Net_273; - wire Net_274; - wire Net_244; - wire Net_239; - wire Net_253; - wire Net_161; - wire Net_276; - - // VirtualMux_1 (cy_virtualmux_v1_0) - assign Net_276 = Net_239; - - - cy_clock_v1_0 - #(.id("65364cec-b381-43b3-8265-0ffcbc3d9007/426fcbe0-714d-4404-8fa8-581ff40c30f1"), - .source_clock_id(""), - .divisor(0), - .period("500000000"), - .is_direct(0), - .is_digital(1)) - IntClock - (.clock_out(Net_239)); - - - B_SPI_Master_v2_30 BSPIM ( - .sclk(sclk), - .ss(ss), - .miso(Net_244), - .clock(Net_276), - .reset(Net_273), - .rx_interpt(rx_interrupt), - .tx_enable(Net_253), - .mosi(mosi), - .tx_interpt(tx_interrupt)); - defparam BSPIM.BidirectMode = 0; - defparam BSPIM.HighSpeedMode = 0; - defparam BSPIM.ModeCPHA = 1; - defparam BSPIM.ModePOL = 1; - defparam BSPIM.NumberOfDataBits = 8; - defparam BSPIM.ShiftDir = 0; - - // VirtualMux_2 (cy_virtualmux_v1_0) - assign Net_244 = miso; - - // VirtualMux_3 (cy_virtualmux_v1_0) - assign Net_273 = Net_274; - - ZeroTerminal ZeroTerminal_1 ( - .z(Net_274)); - - - -endmodule - -// CharLCD_v1_70(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, CY_COMPONENT_NAME=CharLCD_v1_70, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=70, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD, ) -module CharLCD_v1_70_1 ; - - - - wire [6:0] tmpOE__LCDPort_net; - wire [6:0] tmpFB_6__LCDPort_net; - wire [6:0] tmpIO_6__LCDPort_net; - wire [0:0] tmpINTERRUPT_0__LCDPort_net; - electrical [0:0] tmpSIOVREF__LCDPort_net; - - cy_psoc3_pins_v1_10 - #(.id("923198f5-05eb-4681-ae86-b3593c234480/ed092b9b-d398-4703-be89-cebf998501f6"), - .drive_mode(21'b110_110_110_110_110_110_110), - .ibuf_enabled(7'b1_1_1_1_1_1_1), - .init_dr_st(7'b0_0_0_0_0_0_0), - .input_sync(7'b1_1_1_1_1_1_1), - .intr_mode(14'b00_00_00_00_00_00_00), - .io_voltage(", , , , , , "), - .layout_mode("CONTIGUOUS"), - .oe_conn(7'b0_0_0_0_0_0_0), - .output_conn(7'b0_0_0_0_0_0_0), - .output_sync(7'b0_0_0_0_0_0_0), - .pin_aliases(",,,,,,"), - .pin_mode("OOOOOOO"), - .por_state(4), - .use_annotation(7'b0_0_0_0_0_0_0), - .sio_group_cnt(0), - .sio_hyst(7'b0_0_0_0_0_0_0), - .sio_ibuf(""), - .sio_info(14'b00_00_00_00_00_00_00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(7'b0_0_0_0_0_0_0), - .spanning(0), - .vtrip(14'b10_10_10_10_10_10_10), - .width(7)) - LCDPort - (.oe(tmpOE__LCDPort_net), - .y({7'b0}), - .fb({tmpFB_6__LCDPort_net[6:0]}), - .io({tmpIO_6__LCDPort_net[6:0]}), - .siovref(tmpSIOVREF__LCDPort_net), - .interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]})); - - assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111}; - - - -endmodule - -// top -module top ; - - wire Net_14; - wire Net_85; - wire Net_84; - wire Net_110; - wire Net_83; - wire Net_107; - wire Net_31; - wire Net_30; - wire Net_20; - - ZeroTerminal ZeroTerminal_1 ( - .z(Net_83)); - - wire [0:0] tmpOE__m_miso_pin_net; - wire [0:0] tmpIO_0__m_miso_pin_net; - wire [0:0] tmpINTERRUPT_0__m_miso_pin_net; - electrical [0:0] tmpSIOVREF__m_miso_pin_net; - - cy_psoc3_pins_v1_10 - #(.id("1425177d-0d0e-4468-8bcc-e638e5509a9b"), - .drive_mode(3'b001), - .ibuf_enabled(1'b1), - .init_dr_st(1'b0), - .input_sync(1'b0), - .intr_mode(2'b00), - .io_voltage(""), - .layout_mode("CONTIGUOUS"), - .oe_conn(1'b0), - .output_conn(1'b0), - .output_sync(1'b0), - .pin_aliases(""), - .pin_mode("I"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(0), - .vtrip(2'b00), - .width(1)) - m_miso_pin - (.oe(tmpOE__m_miso_pin_net), - .y({1'b0}), - .fb({Net_20}), - .io({tmpIO_0__m_miso_pin_net[0:0]}), - .siovref(tmpSIOVREF__m_miso_pin_net), - .interrupt({tmpINTERRUPT_0__m_miso_pin_net[0:0]})); - - assign tmpOE__m_miso_pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - wire [0:0] tmpOE__m_mosi_pin_net; - wire [0:0] tmpFB_0__m_mosi_pin_net; - wire [0:0] tmpIO_0__m_mosi_pin_net; - wire [0:0] tmpINTERRUPT_0__m_mosi_pin_net; - electrical [0:0] tmpSIOVREF__m_mosi_pin_net; - - cy_psoc3_pins_v1_10 - #(.id("ed092b9b-d398-4703-be89-cebf998501f6"), - .drive_mode(3'b110), - .ibuf_enabled(1'b1), - .init_dr_st(1'b0), - .input_sync(1'b1), - .intr_mode(2'b00), - .io_voltage(""), - .layout_mode("CONTIGUOUS"), - .oe_conn(1'b0), - .output_conn(1'b1), - .output_sync(1'b0), - .pin_aliases(""), - .pin_mode("O"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(0), - .vtrip(2'b10), - .width(1)) - m_mosi_pin - (.oe(tmpOE__m_mosi_pin_net), - .y({Net_30}), - .fb({tmpFB_0__m_mosi_pin_net[0:0]}), - .io({tmpIO_0__m_mosi_pin_net[0:0]}), - .siovref(tmpSIOVREF__m_mosi_pin_net), - .interrupt({tmpINTERRUPT_0__m_mosi_pin_net[0:0]})); - - assign tmpOE__m_mosi_pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - wire [0:0] tmpOE__m_sclk_pin_net; - wire [0:0] tmpFB_0__m_sclk_pin_net; - wire [0:0] tmpIO_0__m_sclk_pin_net; - wire [0:0] tmpINTERRUPT_0__m_sclk_pin_net; - electrical [0:0] tmpSIOVREF__m_sclk_pin_net; - - cy_psoc3_pins_v1_10 - #(.id("640f8e70-5666-4015-9ac8-6ed7f71d8e01"), - .drive_mode(3'b110), - .ibuf_enabled(1'b1), - .init_dr_st(1'b0), - .input_sync(1'b1), - .intr_mode(2'b00), - .io_voltage(""), - .layout_mode("CONTIGUOUS"), - .oe_conn(1'b0), - .output_conn(1'b1), - .output_sync(1'b0), - .pin_aliases(""), - .pin_mode("O"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(0), - .vtrip(2'b10), - .width(1)) - m_sclk_pin - (.oe(tmpOE__m_sclk_pin_net), - .y({Net_31}), - .fb({tmpFB_0__m_sclk_pin_net[0:0]}), - .io({tmpIO_0__m_sclk_pin_net[0:0]}), - .siovref(tmpSIOVREF__m_sclk_pin_net), - .interrupt({tmpINTERRUPT_0__m_sclk_pin_net[0:0]})); - - assign tmpOE__m_sclk_pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - SPI_Master_v2_30_0 SPIM ( - .mosi(Net_30), - .sclk(Net_31), - .ss(Net_107), - .miso(Net_20), - .clock(1'b0), - .reset(Net_83), - .rx_interrupt(Net_84), - .sdat(Net_85), - .tx_interrupt(Net_14)); - defparam SPIM.BidirectMode = 0; - defparam SPIM.HighSpeedMode = 0; - defparam SPIM.NumberOfDataBits = 8; - defparam SPIM.ShiftDir = 0; - - CharLCD_v1_70_1 LCD (); - - wire [0:0] tmpOE__m_ss_pin_net; - wire [0:0] tmpFB_0__m_ss_pin_net; - wire [0:0] tmpIO_0__m_ss_pin_net; - wire [0:0] tmpINTERRUPT_0__m_ss_pin_net; - electrical [0:0] tmpSIOVREF__m_ss_pin_net; - - cy_psoc3_pins_v1_10 - #(.id("5ec2583b-d6a1-4a86-ac3e-b170e6f000fd"), - .drive_mode(3'b110), - .ibuf_enabled(1'b1), - .init_dr_st(1'b0), - .input_sync(1'b1), - .intr_mode(2'b00), - .io_voltage(""), - .layout_mode("CONTIGUOUS"), - .oe_conn(1'b0), - .output_conn(1'b1), - .output_sync(1'b0), - .pin_aliases(""), - .pin_mode("O"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(0), - .vtrip(2'b10), - .width(1)) - m_ss_pin - (.oe(tmpOE__m_ss_pin_net), - .y({Net_107}), - .fb({tmpFB_0__m_ss_pin_net[0:0]}), - .io({tmpIO_0__m_ss_pin_net[0:0]}), - .siovref(tmpSIOVREF__m_ss_pin_net), - .interrupt({tmpINTERRUPT_0__m_ss_pin_net[0:0]})); - - assign tmpOE__m_ss_pin_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - - -endmodule - diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.vh2 deleted file mode 100644 index ff81fbe..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.vh2 +++ /dev/null @@ -1,649 +0,0 @@ --- --- Conversion of SPI_Design01.v to vh2: --- --- Cypress Semiconductor - WARP Version 6.3 IR 41 --- Wed Jan 16 14:35:45 2013 --- - -USE cypress.cypress.all; -USE cypress.rtlpkg.all; -ENTITY top_RTL IS -ATTRIBUTE part_name of top_RTL:TYPE IS "cpsoc3"; -END top_RTL; --------------------------------------------------------- -ARCHITECTURE R_T_L OF top_RTL IS -SIGNAL Net_83 : bit; -SIGNAL tmpOE__m_miso_pin_net_0 : bit; -SIGNAL zero : bit; -SIGNAL Net_20 : bit; -SIGNAL tmpIO_0__m_miso_pin_net_0 : bit; -TERMINAL tmpSIOVREF__m_miso_pin_net_0 : bit; -SIGNAL tmpINTERRUPT_0__m_miso_pin_net_0 : bit; -SIGNAL tmpOE__m_mosi_pin_net_0 : bit; -SIGNAL Net_30 : bit; -SIGNAL tmpFB_0__m_mosi_pin_net_0 : bit; -SIGNAL tmpIO_0__m_mosi_pin_net_0 : bit; -TERMINAL tmpSIOVREF__m_mosi_pin_net_0 : bit; -SIGNAL tmpINTERRUPT_0__m_mosi_pin_net_0 : bit; -SIGNAL tmpOE__m_sclk_pin_net_0 : bit; -SIGNAL Net_31 : bit; -SIGNAL tmpFB_0__m_sclk_pin_net_0 : bit; -SIGNAL tmpIO_0__m_sclk_pin_net_0 : bit; -TERMINAL tmpSIOVREF__m_sclk_pin_net_0 : bit; -SIGNAL tmpINTERRUPT_0__m_sclk_pin_net_0 : bit; -SIGNAL \SPIM:Net_276\ : bit; -SIGNAL \SPIM:Net_239\ : bit; -SIGNAL one : bit; -SIGNAL \SPIM:BSPIM:clk_fin\ : bit; -SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; -SIGNAL \SPIM:BSPIM:dpcounter_one\ : bit; -SIGNAL \SPIM:BSPIM:pol_supprt\ : bit; -SIGNAL \SPIM:BSPIM:miso_to_dp\ : bit; -SIGNAL \SPIM:Net_244\ : bit; -SIGNAL \SPIM:BSPIM:mosi_after_ld\ : bit; -SIGNAL \SPIM:BSPIM:so_send\ : bit; -SIGNAL \SPIM:BSPIM:so_send_reg\ : bit; -SIGNAL \SPIM:BSPIM:mosi_reg\ : bit; -SIGNAL \SPIM:BSPIM:mosi_fin\ : bit; -SIGNAL \SPIM:BSPIM:mosi_cpha_1\ : bit; -SIGNAL \SPIM:BSPIM:state_2\ : bit; -SIGNAL \SPIM:BSPIM:state_1\ : bit; -SIGNAL \SPIM:BSPIM:state_0\ : bit; -SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; -SIGNAL \SPIM:BSPIM:mosi_cpha_0\ : bit; -SIGNAL Net_107 : bit; -SIGNAL \SPIM:BSPIM:mosi_hs_reg\ : bit; -SIGNAL \SPIM:BSPIM:pre_mosi\ : bit; -SIGNAL \SPIM:BSPIM:count_4\ : bit; -SIGNAL \SPIM:BSPIM:count_3\ : bit; -SIGNAL \SPIM:BSPIM:count_2\ : bit; -SIGNAL \SPIM:BSPIM:count_1\ : bit; -SIGNAL \SPIM:BSPIM:count_0\ : bit; -SIGNAL \SPIM:BSPIM:mosi_pre_reg\ : bit; -SIGNAL \SPIM:BSPIM:dpcounter_zero\ : bit; -SIGNAL \SPIM:BSPIM:load_cond\ : bit; -SIGNAL \SPIM:BSPIM:dpcounter_one_reg\ : bit; -SIGNAL \SPIM:BSPIM:mosi_from_dp_reg\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; -SIGNAL \SPIM:BSPIM:dpMOSI_fifo_empty\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; -SIGNAL \SPIM:BSPIM:dpMOSI_fifo_not_full\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_3\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; -SIGNAL \SPIM:BSPIM:dpMISO_fifo_full\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; -SIGNAL \SPIM:BSPIM:dpMISO_fifo_not_empty\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_6\ : bit; -SIGNAL \SPIM:BSPIM:tx_status_5\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_3\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_2\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_1\ : bit; -SIGNAL \SPIM:BSPIM:rx_status_0\ : bit; -SIGNAL \SPIM:BSPIM:control_7\ : bit; -SIGNAL \SPIM:BSPIM:control_6\ : bit; -SIGNAL \SPIM:BSPIM:control_5\ : bit; -SIGNAL \SPIM:BSPIM:control_4\ : bit; -SIGNAL \SPIM:BSPIM:control_3\ : bit; -SIGNAL \SPIM:BSPIM:control_2\ : bit; -SIGNAL \SPIM:BSPIM:control_1\ : bit; -SIGNAL \SPIM:BSPIM:control_0\ : bit; -SIGNAL \SPIM:Net_253\ : bit; -SIGNAL \SPIM:BSPIM:ld_ident\ : bit; -SIGNAL \SPIM:Net_273\ : bit; -SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; -SIGNAL \SPIM:BSPIM:count_6\ : bit; -SIGNAL \SPIM:BSPIM:count_5\ : bit; -SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; -SIGNAL Net_14 : bit; -SIGNAL Net_84 : bit; -SIGNAL \SPIM:BSPIM:sR8:Dp:ce0\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ce0\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cl0\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cl0\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:z0\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:z0\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ff0\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ff0\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ce1\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ce1\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cl1\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cl1\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:z1\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:z1\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ff1\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ff1\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ov_msb\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ov_msb\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:co_msb\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:co_msb\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cmsb\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cmsb\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ce0_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ce0_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cl0_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cl0_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:z0_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:z0_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ff0_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ff0_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ce1_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ce1_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cl1_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cl1_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:z1_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:z1_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ff1_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ff1_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:ov_msb_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:ov_msb_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:co_msb_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:co_msb_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:cmsb_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:cmsb_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:so_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:so_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:f0_bus_stat_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:f0_bus_stat_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:f0_blk_stat_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:f0_blk_stat_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:f1_bus_stat_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:f1_bus_stat_reg\:SIGNAL IS 2; -SIGNAL \SPIM:BSPIM:sR8:Dp:f1_blk_stat_reg\ : bit; -ATTRIBUTE port_state_att of \SPIM:BSPIM:sR8:Dp:f1_blk_stat_reg\:SIGNAL IS 2; -SIGNAL \SPIM:Net_274\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_6\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_5\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_4\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_3\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_2\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_1\ : bit; -SIGNAL \LCD:tmpOE__LCDPort_net_0\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_6\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_5\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_4\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_3\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_2\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_1\ : bit; -SIGNAL \LCD:tmpFB_6__LCDPort_net_0\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_6\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_5\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_4\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_3\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_2\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_1\ : bit; -SIGNAL \LCD:tmpIO_6__LCDPort_net_0\ : bit; -TERMINAL \LCD:tmpSIOVREF__LCDPort_net_0\ : bit; -SIGNAL \LCD:tmpINTERRUPT_0__LCDPort_net_0\ : bit; -SIGNAL tmpOE__m_ss_pin_net_0 : bit; -SIGNAL tmpFB_0__m_ss_pin_net_0 : bit; -SIGNAL tmpIO_0__m_ss_pin_net_0 : bit; -TERMINAL tmpSIOVREF__m_ss_pin_net_0 : bit; -SIGNAL tmpINTERRUPT_0__m_ss_pin_net_0 : bit; -SIGNAL Net_31D : bit; -SIGNAL \SPIM:BSPIM:so_send_reg\\D\ : bit; -SIGNAL \SPIM:BSPIM:mosi_reg\\D\ : bit; -SIGNAL \SPIM:BSPIM:state_2\\D\ : bit; -SIGNAL \SPIM:BSPIM:state_1\\D\ : bit; -SIGNAL \SPIM:BSPIM:state_0\\D\ : bit; -SIGNAL Net_107D : bit; -SIGNAL \SPIM:BSPIM:mosi_pre_reg\\D\ : bit; -SIGNAL \SPIM:BSPIM:load_cond\\D\ : bit; -SIGNAL \SPIM:BSPIM:dpcounter_one_reg\\D\ : bit; -SIGNAL \SPIM:BSPIM:mosi_from_dp_reg\\D\ : bit; -SIGNAL \SPIM:BSPIM:ld_ident\\D\ : bit; -SIGNAL \SPIM:BSPIM:cnt_enable\\D\ : bit; -BEGIN - -zero <= ('0') ; - -tmpOE__m_miso_pin_net_0 <= ('1') ; - -\SPIM:BSPIM:load_rx_data\ <= ((not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:count_0\)); - -\SPIM:BSPIM:load_cond\\D\ <= ((not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_2\) - OR (\SPIM:BSPIM:count_0\ and \SPIM:BSPIM:load_cond\) - OR (\SPIM:BSPIM:count_1\ and \SPIM:BSPIM:load_cond\) - OR (\SPIM:BSPIM:count_2\ and \SPIM:BSPIM:load_cond\) - OR (\SPIM:BSPIM:count_3\ and \SPIM:BSPIM:load_cond\) - OR (\SPIM:BSPIM:count_4\ and \SPIM:BSPIM:load_cond\)); - -\SPIM:BSPIM:tx_status_0\ <= ((not \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\)); - -\SPIM:BSPIM:tx_status_4\ <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\)); - -\SPIM:BSPIM:rx_status_6\ <= ((not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:count_0\ and \SPIM:BSPIM:rx_status_4\)); - -\SPIM:BSPIM:state_2\\D\ <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_0\ and not \SPIM:BSPIM:tx_status_1\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_1\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_0\)); - -\SPIM:BSPIM:state_1\\D\ <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:count_1\ and not \SPIM:BSPIM:count_0\ and \SPIM:BSPIM:state_1\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_0\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_1\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:count_0\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:tx_status_1\) - OR (not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_2\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:state_0\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_2\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_3\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_4\)); - -\SPIM:BSPIM:state_0\\D\ <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:tx_status_1\ and \SPIM:BSPIM:count_4\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:tx_status_1\ and \SPIM:BSPIM:count_3\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:tx_status_1\ and \SPIM:BSPIM:count_2\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:count_1\ and not \SPIM:BSPIM:tx_status_1\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:tx_status_1\ and \SPIM:BSPIM:count_0\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:count_4\ and not \SPIM:BSPIM:count_3\ and not \SPIM:BSPIM:count_2\ and not \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:count_0\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:tx_status_1\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\ and not \SPIM:BSPIM:tx_status_1\)); - -Net_107D <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\) - OR (\SPIM:BSPIM:state_1\ and Net_107) - OR (\SPIM:BSPIM:state_2\ and Net_107) - OR (\SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_1\)); - -\SPIM:BSPIM:cnt_enable\\D\ <= ((not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_4\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_3\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_2\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:count_1\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:count_0\ and \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_2\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:cnt_enable\) - OR (not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:state_0\)); - -\SPIM:BSPIM:mosi_reg\\D\ <= ((not \SPIM:BSPIM:state_2\ and not \SPIM:BSPIM:state_0\ and \SPIM:BSPIM:state_1\ and \SPIM:BSPIM:mosi_from_dp\) - OR (not \SPIM:BSPIM:state_1\ and not \SPIM:BSPIM:state_0\ and Net_30 and \SPIM:BSPIM:state_2\) - OR (not \SPIM:BSPIM:state_2\ and Net_30 and \SPIM:BSPIM:state_0\)); - -Net_31D <= (\SPIM:BSPIM:state_0\ - OR not \SPIM:BSPIM:state_1\ - OR \SPIM:BSPIM:state_2\); - -m_miso_pin:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"1425177d-0d0e-4468-8bcc-e638e5509a9b", - drive_mode=>"001", - ibuf_enabled=>"1", - init_dr_st=>"0", - input_sync=>"0", - intr_mode=>"00", - io_voltage=>"", - layout_mode=>"CONTIGUOUS", - output_conn=>"0", - output_sync=>"0", - oe_conn=>"0", - pin_aliases=>"", - pin_mode=>"I", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'0', - sw_only=>'0', - vtrip=>"00", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0") - PORT MAP(oe=>(tmpOE__m_miso_pin_net_0), - y=>(zero), - fb=>Net_20, - analog=>(open), - io=>(tmpIO_0__m_miso_pin_net_0), - siovref=>(tmpSIOVREF__m_miso_pin_net_0), - annotation=>(open), - interrupt=>tmpINTERRUPT_0__m_miso_pin_net_0); -m_mosi_pin:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"ed092b9b-d398-4703-be89-cebf998501f6", - drive_mode=>"110", - ibuf_enabled=>"1", - init_dr_st=>"0", - input_sync=>"1", - intr_mode=>"00", - io_voltage=>"", - layout_mode=>"CONTIGUOUS", - output_conn=>"1", - output_sync=>"0", - oe_conn=>"0", - pin_aliases=>"", - pin_mode=>"O", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'0', - sw_only=>'0', - vtrip=>"10", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0") - PORT MAP(oe=>(tmpOE__m_miso_pin_net_0), - y=>Net_30, - fb=>(tmpFB_0__m_mosi_pin_net_0), - analog=>(open), - io=>(tmpIO_0__m_mosi_pin_net_0), - siovref=>(tmpSIOVREF__m_mosi_pin_net_0), - annotation=>(open), - interrupt=>tmpINTERRUPT_0__m_mosi_pin_net_0); -m_sclk_pin:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"640f8e70-5666-4015-9ac8-6ed7f71d8e01", - drive_mode=>"110", - ibuf_enabled=>"1", - init_dr_st=>"0", - input_sync=>"1", - intr_mode=>"00", - io_voltage=>"", - layout_mode=>"CONTIGUOUS", - output_conn=>"1", - output_sync=>"0", - oe_conn=>"0", - pin_aliases=>"", - pin_mode=>"O", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'0', - sw_only=>'0', - vtrip=>"10", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0") - PORT MAP(oe=>(tmpOE__m_miso_pin_net_0), - y=>Net_31, - fb=>(tmpFB_0__m_sclk_pin_net_0), - analog=>(open), - io=>(tmpIO_0__m_sclk_pin_net_0), - siovref=>(tmpSIOVREF__m_sclk_pin_net_0), - annotation=>(open), - interrupt=>tmpINTERRUPT_0__m_sclk_pin_net_0); -\SPIM:IntClock\:cy_clock_v1_0 - GENERIC MAP(cy_registers=>"", - id=>"65364cec-b381-43b3-8265-0ffcbc3d9007/426fcbe0-714d-4404-8fa8-581ff40c30f1", - source_clock_id=>"", - divisor=>0, - period=>"500000000", - is_direct=>'0', - is_digital=>'1') - PORT MAP(clock_out=>\SPIM:Net_276\, - dig_domain_out=>open); -\SPIM:BSPIM:ClkEn\:cy_psoc3_udb_clock_enable_v1_0 - GENERIC MAP(sync_mode=>'1') - PORT MAP(clock_in=>\SPIM:Net_276\, - enable=>tmpOE__m_miso_pin_net_0, - clock_out=>\SPIM:BSPIM:clk_fin\); -\SPIM:BSPIM:BitCounter\:cy_psoc3_count7 - GENERIC MAP(cy_period=>"0001111", - cy_init_value=>"0000000", - cy_route_ld=>'0', - cy_route_en=>'1', - cy_alt_mode=>'0') - PORT MAP(clock=>\SPIM:BSPIM:clk_fin\, - reset=>zero, - load=>zero, - enable=>\SPIM:BSPIM:cnt_enable\, - count=>(\SPIM:BSPIM:count_6\, \SPIM:BSPIM:count_5\, \SPIM:BSPIM:count_4\, \SPIM:BSPIM:count_3\, - \SPIM:BSPIM:count_2\, \SPIM:BSPIM:count_1\, \SPIM:BSPIM:count_0\), - tc=>\SPIM:BSPIM:cnt_tc\); -\SPIM:BSPIM:TxStsReg\:cy_psoc3_statusi - GENERIC MAP(cy_force_order=>'1', - cy_md_select=>"0001001", - cy_int_mask=>"0000000") - PORT MAP(reset=>zero, - clock=>\SPIM:BSPIM:clk_fin\, - status=>(zero, zero, \SPIM:BSPIM:tx_status_4\, \SPIM:BSPIM:load_rx_data\, - \SPIM:BSPIM:tx_status_2\, \SPIM:BSPIM:tx_status_1\, \SPIM:BSPIM:tx_status_0\), - interrupt=>Net_14); -\SPIM:BSPIM:RxStsReg\:cy_psoc3_statusi - GENERIC MAP(cy_force_order=>'1', - cy_md_select=>"1000000", - cy_int_mask=>"0000000") - PORT MAP(reset=>zero, - clock=>\SPIM:BSPIM:clk_fin\, - status=>(\SPIM:BSPIM:rx_status_6\, \SPIM:BSPIM:rx_status_5\, \SPIM:BSPIM:rx_status_4\, zero, - zero, zero, zero), - interrupt=>Net_84); -\SPIM:BSPIM:sR8:Dp:u0\:cy_psoc3_dp - GENERIC MAP(cy_dpconfig=>"0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100", - d0_init=>"00000000", - d1_init=>"00000000", - a0_init=>"00000000", - a1_init=>"00000000", - ce0_sync=>'1', - cl0_sync=>'1', - z0_sync=>'1', - ff0_sync=>'1', - ce1_sync=>'1', - cl1_sync=>'1', - z1_sync=>'1', - ff1_sync=>'1', - ov_msb_sync=>'1', - co_msb_sync=>'1', - cmsb_sync=>'1', - so_sync=>'1', - f0_bus_sync=>'1', - f0_blk_sync=>'1', - f1_bus_sync=>'1', - f1_blk_sync=>'1') - PORT MAP(reset=>zero, - clk=>\SPIM:BSPIM:clk_fin\, - cs_addr=>(\SPIM:BSPIM:state_2\, \SPIM:BSPIM:state_1\, \SPIM:BSPIM:state_0\), - route_si=>Net_20, - route_ci=>zero, - f0_load=>zero, - f1_load=>\SPIM:BSPIM:load_rx_data\, - d0_load=>zero, - d1_load=>zero, - ce0=>open, - cl0=>open, - z0=>open, - ff0=>open, - ce1=>open, - cl1=>open, - z1=>open, - ff1=>open, - ov_msb=>open, - co_msb=>open, - cmsb=>open, - so=>\SPIM:BSPIM:mosi_from_dp\, - f0_bus_stat=>\SPIM:BSPIM:tx_status_2\, - f0_blk_stat=>\SPIM:BSPIM:tx_status_1\, - f1_bus_stat=>\SPIM:BSPIM:rx_status_5\, - f1_blk_stat=>\SPIM:BSPIM:rx_status_4\, - ce0_reg=>open, - cl0_reg=>open, - z0_reg=>open, - ff0_reg=>open, - ce1_reg=>open, - cl1_reg=>open, - z1_reg=>open, - ff1_reg=>open, - ov_msb_reg=>open, - co_msb_reg=>open, - cmsb_reg=>open, - so_reg=>open, - f0_bus_stat_reg=>open, - f0_blk_stat_reg=>open, - f1_bus_stat_reg=>open, - f1_blk_stat_reg=>open, - ci=>zero, - co=>open, - sir=>zero, - sor=>open, - sil=>zero, - sol=>open, - msbi=>zero, - msbo=>open, - cei=>(zero, zero), - ceo=>open, - cli=>(zero, zero), - clo=>open, - zi=>(zero, zero), - zo=>open, - fi=>(zero, zero), - fo=>open, - capi=>(zero, zero), - capo=>open, - cfbi=>zero, - cfbo=>open, - pi=>(zero, zero, zero, zero, - zero, zero, zero, zero), - po=>open); -\LCD:LCDPort\:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"923198f5-05eb-4681-ae86-b3593c234480/ed092b9b-d398-4703-be89-cebf998501f6", - drive_mode=>"110110110110110110110", - ibuf_enabled=>"1111111", - init_dr_st=>"0000000", - input_sync=>"1111111", - intr_mode=>"00000000000000", - io_voltage=>", , , , , , ", - layout_mode=>"CONTIGUOUS", - output_conn=>"0000000", - output_sync=>"0000000", - oe_conn=>"0000000", - pin_aliases=>",,,,,,", - pin_mode=>"OOOOOOO", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0000000", - sio_ibuf=>"00000000", - sio_info=>"00000000000000", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0000000", - spanning=>'0', - sw_only=>'0', - vtrip=>"10101010101010", - width=>7, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0000000") - PORT MAP(oe=>(tmpOE__m_miso_pin_net_0, tmpOE__m_miso_pin_net_0, tmpOE__m_miso_pin_net_0, tmpOE__m_miso_pin_net_0, - tmpOE__m_miso_pin_net_0, tmpOE__m_miso_pin_net_0, tmpOE__m_miso_pin_net_0), - y=>(zero, zero, zero, zero, - zero, zero, zero), - fb=>(\LCD:tmpFB_6__LCDPort_net_6\, \LCD:tmpFB_6__LCDPort_net_5\, \LCD:tmpFB_6__LCDPort_net_4\, \LCD:tmpFB_6__LCDPort_net_3\, - \LCD:tmpFB_6__LCDPort_net_2\, \LCD:tmpFB_6__LCDPort_net_1\, \LCD:tmpFB_6__LCDPort_net_0\), - analog=>(open, open, open, open, - open, open, open), - io=>(\LCD:tmpIO_6__LCDPort_net_6\, \LCD:tmpIO_6__LCDPort_net_5\, \LCD:tmpIO_6__LCDPort_net_4\, \LCD:tmpIO_6__LCDPort_net_3\, - \LCD:tmpIO_6__LCDPort_net_2\, \LCD:tmpIO_6__LCDPort_net_1\, \LCD:tmpIO_6__LCDPort_net_0\), - siovref=>(\LCD:tmpSIOVREF__LCDPort_net_0\), - annotation=>(open, open, open, open, - open, open, open), - interrupt=>\LCD:tmpINTERRUPT_0__LCDPort_net_0\); -m_ss_pin:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"5ec2583b-d6a1-4a86-ac3e-b170e6f000fd", - drive_mode=>"110", - ibuf_enabled=>"1", - init_dr_st=>"0", - input_sync=>"1", - intr_mode=>"00", - io_voltage=>"", - layout_mode=>"CONTIGUOUS", - output_conn=>"1", - output_sync=>"0", - oe_conn=>"0", - pin_aliases=>"", - pin_mode=>"O", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'0', - sw_only=>'0', - vtrip=>"10", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0") - PORT MAP(oe=>(tmpOE__m_miso_pin_net_0), - y=>Net_107, - fb=>(tmpFB_0__m_ss_pin_net_0), - analog=>(open), - io=>(tmpIO_0__m_ss_pin_net_0), - siovref=>(tmpSIOVREF__m_ss_pin_net_0), - annotation=>(open), - interrupt=>tmpINTERRUPT_0__m_ss_pin_net_0); -Net_31:cy_dff - PORT MAP(d=>Net_31D, - clk=>\SPIM:BSPIM:clk_fin\, - q=>Net_31); -\SPIM:BSPIM:so_send_reg\:cy_dff - PORT MAP(d=>zero, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:so_send_reg\); -\SPIM:BSPIM:mosi_reg\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:mosi_reg\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>Net_30); -\SPIM:BSPIM:state_2\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:state_2\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:state_2\); -\SPIM:BSPIM:state_1\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:state_1\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:state_1\); -\SPIM:BSPIM:state_0\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:state_0\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:state_0\); -Net_107:cy_dff - PORT MAP(d=>Net_107D, - clk=>\SPIM:BSPIM:clk_fin\, - q=>Net_107); -\SPIM:BSPIM:mosi_pre_reg\:cy_dff - PORT MAP(d=>zero, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:mosi_pre_reg\); -\SPIM:BSPIM:load_cond\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:load_cond\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:load_cond\); -\SPIM:BSPIM:dpcounter_one_reg\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:load_rx_data\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:dpcounter_one_reg\); -\SPIM:BSPIM:mosi_from_dp_reg\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:mosi_from_dp\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:mosi_from_dp_reg\); -\SPIM:BSPIM:ld_ident\:cy_dff - PORT MAP(d=>zero, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:ld_ident\); -\SPIM:BSPIM:cnt_enable\:cy_dff - PORT MAP(d=>\SPIM:BSPIM:cnt_enable\\D\, - clk=>\SPIM:BSPIM:clk_fin\, - q=>\SPIM:BSPIM:cnt_enable\); - -END R_T_L; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.wde b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.wde deleted file mode 100644 index 06bbd52..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01.wde +++ /dev/null @@ -1,11 +0,0 @@ -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\ieee\work\stdlogic.vif -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif -SPI_Design01.ctl -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v -SPI_Design01.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_30\B_SPI_Master_v2_30.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cypress.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\cy_psoc3_inc.v -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif -C:\Program Files (x86)\Cypress\PSoC Creator\2.1\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.lib deleted file mode 100644 index 5402b07..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.lib +++ /dev/null @@ -1,2337 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (macrocell1) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell2) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell3) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (iocell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.499; - intrinsic_fall : 17.499; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 18.989; - intrinsic_fall : 18.989; - } - } - } - cell (iocell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.253; - intrinsic_fall : 16.253; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 16.490; - intrinsic_fall : 16.490; - } - } - } - cell (iocell3) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 21.315; - intrinsic_fall : 21.315; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 17.470; - intrinsic_fall : 17.470; - } - } - } - cell (iocell4) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 24.720; - intrinsic_fall : 24.720; - } - } - } - cell (iocell5) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 20.119; - intrinsic_fall : 20.119; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.475; - intrinsic_fall : 23.475; - } - } - } - cell (iocell6) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.998; - intrinsic_fall : 16.998; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.553; - intrinsic_fall : 25.553; - } - } - } - cell (iocell7) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.701; - intrinsic_fall : 19.701; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.795; - intrinsic_fall : 23.795; - } - } - } - cell (statusicell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (interrupt) { - direction : output; - } - } - cell (statusicell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - } - pin (interrupt) { - direction : output; - } - } - cell (macrocell4) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell5) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell6) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell7) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (datapathcell1) { - pin (clk_en) { - direction : input; - } - pin (reset) { - direction : input; - } - pin (cs_addr_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_1) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_2) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_si) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.77; - intrinsic_fall : 6.77; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.78; - intrinsic_fall : 6.78; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.65; - intrinsic_fall : 7.65; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_ci) { - direction : input; - } - pin (f0_load) { - direction : input; - } - pin (f1_load) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.85; - intrinsic_fall : 1.85; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (d0_load) { - direction : input; - } - pin (d1_load) { - direction : input; - } - pin (p_in_0) { - direction : input; - } - pin (p_in_1) { - direction : input; - } - pin (p_in_2) { - direction : input; - } - pin (p_in_3) { - direction : input; - } - pin (p_in_4) { - direction : input; - } - pin (p_in_5) { - direction : input; - } - pin (p_in_6) { - direction : input; - } - pin (p_in_7) { - direction : input; - } - pin (ce0i) { - direction : input; - } - pin (cl0i) { - direction : input; - } - pin (z0i) { - direction : input; - } - pin (ff0i) { - direction : input; - } - pin (ce1i) { - direction : input; - } - pin (cl1i) { - direction : input; - } - pin (z1i) { - direction : input; - } - pin (ff1i) { - direction : input; - } - pin (cap0i) { - direction : input; - } - pin (cap1i) { - direction : input; - } - pin (ci) { - direction : input; - } - pin (sir) { - direction : input; - } - pin (cfbi) { - direction : input; - } - pin (sil) { - direction : input; - } - pin (cmsbi) { - direction : input; - } - pin (busclk) { - direction : input; - clock : true; - } - pin (clock) { - direction : input; - clock : true; - } - pin (ce0_reg) { - direction : output; - } - pin (cl0_reg) { - direction : output; - } - pin (z0_reg) { - direction : output; - } - pin (f0_reg) { - direction : output; - } - pin (ce1_reg) { - direction : output; - } - pin (cl1_reg) { - direction : output; - } - pin (z1_reg) { - direction : output; - } - pin (f1_reg) { - direction : output; - } - pin (ov_msb_reg) { - direction : output; - } - pin (co_msb_reg) { - direction : output; - } - pin (cmsb_reg) { - direction : output; - } - pin (so_reg) { - direction : output; - } - pin (f0_bus_stat_reg) { - direction : output; - } - pin (f0_blk_stat_reg) { - direction : output; - } - pin (f1_bus_stat_reg) { - direction : output; - } - pin (f1_blk_stat_reg) { - direction : output; - } - pin (ce0_comb) { - direction : output; - } - pin (cl0_comb) { - direction : output; - } - pin (z0_comb) { - direction : output; - } - pin (f0_comb) { - direction : output; - } - pin (ce1_comb) { - direction : output; - } - pin (cl1_comb) { - direction : output; - } - pin (z1_comb) { - direction : output; - } - pin (f1_comb) { - direction : output; - } - pin (ov_msb_comb) { - direction : output; - } - pin (co_msb_comb) { - direction : output; - } - pin (cmsb_comb) { - direction : output; - } - pin (so_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.16; - intrinsic_fall : 8.16; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.30; - intrinsic_fall : 8.30; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.78; - intrinsic_fall : 5.78; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 6.12; - intrinsic_fall : 6.12; - } - } - pin (f0_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f0_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (f1_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f1_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (p_out_0) { - direction : output; - } - pin (p_out_1) { - direction : output; - } - pin (p_out_2) { - direction : output; - } - pin (p_out_3) { - direction : output; - } - pin (p_out_4) { - direction : output; - } - pin (p_out_5) { - direction : output; - } - pin (p_out_6) { - direction : output; - } - pin (p_out_7) { - direction : output; - } - pin (ce0) { - direction : output; - } - pin (cl0) { - direction : output; - } - pin (z0) { - direction : output; - } - pin (ff0) { - direction : output; - } - pin (ce1) { - direction : output; - } - pin (cl1) { - direction : output; - } - pin (z1) { - direction : output; - } - pin (ff1) { - direction : output; - } - pin (cap0) { - direction : output; - } - pin (cap1) { - direction : output; - } - pin (co_msb) { - direction : output; - } - pin (sol_msb) { - direction : output; - } - pin (cfbo) { - direction : output; - } - pin (sor) { - direction : output; - } - pin (cmsbo) { - direction : output; - } - } - cell (macrocell8) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell9) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell10) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell11) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell12) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (iocell8) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.103; - intrinsic_fall : 19.103; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 26.840; - intrinsic_fall : 26.840; - } - } - } - cell (iocell9) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.971; - intrinsic_fall : 17.971; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.711; - intrinsic_fall : 25.711; - } - } - } - cell (iocell10) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.982; - intrinsic_fall : 17.982; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.772; - intrinsic_fall : 25.772; - } - } - } - cell (iocell11) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 18.672; - intrinsic_fall : 18.672; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.214; - intrinsic_fall : 25.214; - } - } - } -} diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.pco b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.pco deleted file mode 100644 index 3e59adf..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.pco +++ /dev/null @@ -1,31 +0,0 @@ -dont_use_io iocell 1 0 -dont_use_io iocell 1 1 -dont_use_io iocell 1 3 -set_location "\SPIM:BSPIM:tx_status_4\" macrocell 0 5 1 2 -set_location "\SPIM:BSPIM:RxStsReg\" statusicell 0 4 4 -set_location "\SPIM:BSPIM:state_2\" macrocell 0 5 0 0 -set_location "\SPIM:BSPIM:state_1\" macrocell 0 5 1 0 -set_location "\SPIM:BSPIM:sR8:Dp:u0\" datapathcell 0 5 2 -set_location "\SPIM:BSPIM:tx_status_0\" macrocell 0 5 0 1 -set_location "\SPIM:BSPIM:TxStsReg\" statusicell 1 4 4 -set_location "Net_107" macrocell 0 5 1 1 -set_location "\SPIM:BSPIM:cnt_enable\" macrocell 0 4 0 0 -set_location "\SPIM:BSPIM:load_rx_data\" macrocell 0 4 0 1 -set_location "Net_30" macrocell 0 4 1 1 -set_location "\SPIM:BSPIM:state_0\" macrocell 0 5 0 2 -set_location "\SPIM:BSPIM:rx_status_6\" macrocell 0 4 0 2 -set_location "\SPIM:BSPIM:BitCounter\" count7cell 0 5 7 -set_location "Net_31" macrocell 0 5 0 3 -set_location "\SPIM:BSPIM:load_cond\" macrocell 0 4 1 0 -set_io "\LCD:LCDPort(3)\" iocell 2 3 -set_io "\LCD:LCDPort(2)\" iocell 2 2 -set_io "\LCD:LCDPort(5)\" iocell 2 5 -set_io "\LCD:LCDPort(4)\" iocell 2 4 -set_io "\LCD:LCDPort(1)\" iocell 2 1 -set_io "\LCD:LCDPort(0)\" iocell 2 0 -set_io "\LCD:LCDPort(6)\" iocell 2 6 -set_io "m_ss_pin(0)" iocell 0 7 -set_io "m_miso_pin(0)" iocell 0 0 -set_io "m_sclk_pin(0)" iocell 0 6 -set_io "m_mosi_pin(0)" iocell 0 5 -set_location "ClockBlock" clockblockcell -1 -1 0 diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.vh2 deleted file mode 100644 index 7d26a68..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_p.vh2 +++ /dev/null @@ -1,1489 +0,0 @@ --- Project: SPI_Design01 --- Generated: 01/16/2013 14:35:46 --- - -ENTITY SPI_Design01 IS - PORT( - \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(2)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(3)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(4)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(5)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(6)_PAD\ : OUT std_ulogic; - m_miso_pin(0)_PAD : IN std_ulogic; - m_mosi_pin(0)_PAD : OUT std_ulogic; - m_sclk_pin(0)_PAD : OUT std_ulogic; - m_ss_pin(0)_PAD : OUT std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 3.3e0; -END SPI_Design01; - -ARCHITECTURE __DEFAULT__ OF SPI_Design01 IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_107 : bit; - SIGNAL Net_20 : bit; - SIGNAL Net_30 : bit; - SIGNAL Net_31 : bit; - SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; - SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; - SIGNAL \SPIM:BSPIM:count_0\ : bit; - SIGNAL \SPIM:BSPIM:count_1\ : bit; - SIGNAL \SPIM:BSPIM:count_2\ : bit; - SIGNAL \SPIM:BSPIM:count_3\ : bit; - SIGNAL \SPIM:BSPIM:count_4\ : bit; - SIGNAL \SPIM:BSPIM:count_5\ : bit; - SIGNAL \SPIM:BSPIM:count_6\ : bit; - SIGNAL \SPIM:BSPIM:load_cond\ : bit; - SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; - SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; - SIGNAL \SPIM:BSPIM:state_0\ : bit; - SIGNAL \SPIM:BSPIM:state_1\ : bit; - SIGNAL \SPIM:BSPIM:state_2\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; - SIGNAL \SPIM:Net_276\ : bit; - ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; - SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL tmpOE__m_miso_pin_net_0 : bit; - ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE lib_model OF Net_107 : LABEL IS "macrocell1"; - ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; - ATTRIBUTE lib_model OF Net_31 : LABEL IS "macrocell3"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell1"; - ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell2"; - ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell3"; - ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell4"; - ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell5"; - ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell6"; - ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell7"; - ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell4"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell5"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell6"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell7"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell8"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell9"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell10"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell11"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell12"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell8"; - ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell9"; - ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell10"; - ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF m_ss_pin(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF m_ss_pin(0) : LABEL IS "P0[7]"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF controlcell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF controlcell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF controlcell : COMPONENT IS "reset"; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF count7cell : COMPONENT IS "clock,clock_n,extclk,extclk_n"; - ATTRIBUTE udb_clken OF count7cell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF count7cell : COMPONENT IS "reset"; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF datapathcell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF datapathcell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF datapathcell : COMPONENT IS "reset"; - ATTRIBUTE udb_chain OF datapathcell : COMPONENT IS "ce0i,ce0,cl0i,cl0,z0i,z0,ff0i,ff0,ce1i,ce1,cl1i,cl1,z1i,z1,ff1i,ff1,cap0i,cap0,cap1i,cap1,ci,co_msb,sir,sol_msb,cfbi,cfbo,sil,sor,cmsbi,cmsbo"; - ATTRIBUTE chain_lsb OF datapathcell : COMPONENT IS "ce0i,cl0i,z0i,ff0i,ce1i,cl1i,z1i,ff1i,cap0i,cap1i,ci,sir,cfbi,sor,cmsbo"; - ATTRIBUTE chain_msb OF datapathcell : COMPONENT IS "ce0,cl0,z0,ff0,ce1,cl1,z1,ff1,cap0,cap1,co_msb,sol_msb,cfbo,sil,cmsbi"; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - clock : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pad_out : OUT std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF macrocell : COMPONENT IS "clock_0"; - ATTRIBUTE udb_clken OF macrocell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF macrocell : COMPONENT IS "ar_0"; - ATTRIBUTE udb_preset OF macrocell : COMPONENT IS "ap_0"; - ATTRIBUTE udb_chain OF macrocell : COMPONENT IS "cin,cout"; - ATTRIBUTE chain_lsb OF macrocell : COMPONENT IS "cin"; - ATTRIBUTE chain_msb OF macrocell : COMPONENT IS "cout"; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidaccell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic); - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF statuscell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF statuscell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF statuscell : COMPONENT IS "reset"; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF statusicell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF statusicell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF statusicell : COMPONENT IS "reset"; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF synccell : COMPONENT IS "clock,clock_n,extclk,extclk_n"; - ATTRIBUTE udb_clken OF synccell : COMPONENT IS "clk_en"; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open, - dclk_glb_0 => \SPIM:Net_276\, - dclk_0 => \SPIM:Net_276_local\); - - Net_107:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2) + (!main_0 * main_1 * !main_3) + (main_0 * !main_1 * !main_3)", - clk_inv => '0') - PORT MAP( - q => Net_107, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => Net_107); - - Net_30:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_3) + (main_0 * main_1 * !main_2 * !main_3) + (!main_1 * main_2 * !main_3 * main_4)", - clk_inv => '0') - PORT MAP( - q => Net_30, - clock_0 => \SPIM:Net_276\, - main_0 => Net_30, - main_1 => \SPIM:BSPIM:state_2\, - main_2 => \SPIM:BSPIM:state_1\, - main_3 => \SPIM:BSPIM:state_0\, - main_4 => \SPIM:BSPIM:mosi_from_dp\); - - Net_31:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)", - clk_inv => '0') - PORT MAP( - q => Net_31, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \LCD:LCDPort(0)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(0)_PAD\); - - \LCD:LCDPort(1)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(1)_PAD\); - - \LCD:LCDPort(2)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(2)_PAD\); - - \LCD:LCDPort(3)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(3)_PAD\); - - \LCD:LCDPort(4)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(4)_PAD\); - - \LCD:LCDPort(5)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(5)_PAD\); - - \LCD:LCDPort(6)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(6)_PAD\); - - \LCD:LCDPort\:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110", - ibuf_enabled => "1111111", - id => "923198f5-05eb-4681-ae86-b3593c234480/ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0000000", - input_sync => "1111111", - intr_mode => "00000000000000", - io_voltage => ", , , , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "0000000", - output_conn => "0000000", - output_sync => "0000000", - pin_aliases => ",,,,,,", - pin_mode => "OOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000", - sio_ibuf => "00000000", - sio_info => "00000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000", - spanning => 0, - sw_only => 0, - use_annotation => "0000000", - vtrip => "10101010101010", - width => 7); - - \SPIM:BSPIM:BitCounter\:count7cell - GENERIC MAP( - cy_alt_mode => 0, - cy_init_value => "0000000", - cy_period => "0001111", - cy_route_en => 1, - cy_route_ld => 0, - clk_inv => '0') - PORT MAP( - clock => \SPIM:Net_276\, - load => open, - enable => \SPIM:BSPIM:cnt_enable\, - count_6 => \SPIM:BSPIM:count_6\, - count_5 => \SPIM:BSPIM:count_5\, - count_4 => \SPIM:BSPIM:count_4\, - count_3 => \SPIM:BSPIM:count_3\, - count_2 => \SPIM:BSPIM:count_2\, - count_1 => \SPIM:BSPIM:count_1\, - count_0 => \SPIM:BSPIM:count_0\, - tc => \SPIM:BSPIM:cnt_tc\); - - \SPIM:BSPIM:RxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "1000000", - clk_inv => '0') - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => \SPIM:BSPIM:rx_status_6\, - status_5 => \SPIM:BSPIM:rx_status_5\, - status_4 => \SPIM:BSPIM:rx_status_4\, - status_3 => open, - status_2 => open, - status_1 => open, - status_0 => open); - - \SPIM:BSPIM:TxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "0001001", - clk_inv => '0') - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => open, - status_5 => open, - status_4 => \SPIM:BSPIM:tx_status_4\, - status_3 => \SPIM:BSPIM:load_rx_data\, - status_2 => \SPIM:BSPIM:tx_status_2\, - status_1 => \SPIM:BSPIM:tx_status_1\, - status_0 => \SPIM:BSPIM:tx_status_0\); - - \SPIM:BSPIM:cnt_enable\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * main_8) + (!main_0 * !main_1 * main_2 * !main_8) + (main_0 * main_1 * main_8) + (main_0 * main_2 * main_8) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7 * main_8)", - clk_inv => '0') - PORT MAP( - q => \SPIM:BSPIM:cnt_enable\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:cnt_enable\); - - \SPIM:BSPIM:load_cond\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_0 * !main_1 * !main_2 * !main_8) + (main_1 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_2 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8)", - clk_inv => '0') - PORT MAP( - q => \SPIM:BSPIM:load_cond\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:load_cond\); - - \SPIM:BSPIM:load_rx_data\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4)") - PORT MAP( - q => \SPIM:BSPIM:load_rx_data\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\); - - \SPIM:BSPIM:rx_status_6\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)") - PORT MAP( - q => \SPIM:BSPIM:rx_status_6\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\, - main_5 => \SPIM:BSPIM:rx_status_4\); - - \SPIM:BSPIM:sR8:Dp:u0\:datapathcell - GENERIC MAP( - a0_init => "00000000", - a1_init => "00000000", - ce0_sync => 1, - ce1_sync => 1, - cl0_sync => 1, - cl1_sync => 1, - cmsb_sync => 1, - co_msb_sync => 1, - cy_dpconfig => "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100", - d0_init => "00000000", - d1_init => "00000000", - f0_blk_sync => 1, - f0_bus_sync => 1, - f1_blk_sync => 1, - f1_bus_sync => 1, - ff0_sync => 1, - ff1_sync => 1, - ov_msb_sync => 1, - so_sync => 1, - z0_sync => 1, - z1_sync => 1, - uses_p_in => '0', - uses_p_out => '0', - clk_inv => '0') - PORT MAP( - clock => \SPIM:Net_276\, - cs_addr_2 => \SPIM:BSPIM:state_2\, - cs_addr_1 => \SPIM:BSPIM:state_1\, - cs_addr_0 => \SPIM:BSPIM:state_0\, - route_si => Net_20, - f1_load => \SPIM:BSPIM:load_rx_data\, - so_comb => \SPIM:BSPIM:mosi_from_dp\, - f0_bus_stat_comb => \SPIM:BSPIM:tx_status_2\, - f0_blk_stat_comb => \SPIM:BSPIM:tx_status_1\, - f1_bus_stat_comb => \SPIM:BSPIM:rx_status_5\, - f1_blk_stat_comb => \SPIM:BSPIM:rx_status_4\, - busclk => ClockBlock_BUS_CLK); - - \SPIM:BSPIM:state_0\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7) + (main_0 * !main_2) + (!main_1 * !main_2 * main_8) + (main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8)", - clk_inv => '0') - PORT MAP( - q => \SPIM:BSPIM:state_0\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_1\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (main_0 * main_1) + (main_0 * main_2) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)", - clk_inv => '0') - PORT MAP( - q => \SPIM:BSPIM:state_1\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_2\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)", - clk_inv => '0') - PORT MAP( - q => \SPIM:BSPIM:state_2\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:tx_status_0\:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_0\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \SPIM:BSPIM:tx_status_4\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_4\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - m_miso_pin:logicalport - GENERIC MAP( - drive_mode => "001", - ibuf_enabled => "1", - id => "1425177d-0d0e-4468-8bcc-e638e5509a9b", - init_dr_st => "0", - input_sync => "0", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "0", - output_sync => "0", - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1); - - m_miso_pin(0):iocell - GENERIC MAP( - logicalport => "m_miso_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - fb => Net_20, - pad_in => m_miso_pin(0)_PAD); - - m_mosi_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_mosi_pin(0):iocell - GENERIC MAP( - logicalport => "m_mosi_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_30, - pad_out => m_mosi_pin(0)_PAD, - pad_in => m_mosi_pin(0)_PAD); - - m_sclk_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "640f8e70-5666-4015-9ac8-6ed7f71d8e01", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_sclk_pin(0):iocell - GENERIC MAP( - logicalport => "m_sclk_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_31, - pad_out => m_sclk_pin(0)_PAD, - pad_in => m_sclk_pin(0)_PAD); - - m_ss_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "5ec2583b-d6a1-4a86-ac3e-b170e6f000fd", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_ss_pin(0):iocell - GENERIC MAP( - logicalport => "m_ss_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_107, - pad_out => m_ss_pin(0)_PAD, - pad_in => m_ss_pin(0)_PAD); - -END __DEFAULT__; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.lib deleted file mode 100644 index 5402b07..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.lib +++ /dev/null @@ -1,2337 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (macrocell1) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell2) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell3) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (iocell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.499; - intrinsic_fall : 17.499; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 18.989; - intrinsic_fall : 18.989; - } - } - } - cell (iocell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.253; - intrinsic_fall : 16.253; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 16.490; - intrinsic_fall : 16.490; - } - } - } - cell (iocell3) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 21.315; - intrinsic_fall : 21.315; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 17.470; - intrinsic_fall : 17.470; - } - } - } - cell (iocell4) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 24.720; - intrinsic_fall : 24.720; - } - } - } - cell (iocell5) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 20.119; - intrinsic_fall : 20.119; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.475; - intrinsic_fall : 23.475; - } - } - } - cell (iocell6) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.998; - intrinsic_fall : 16.998; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.553; - intrinsic_fall : 25.553; - } - } - } - cell (iocell7) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.701; - intrinsic_fall : 19.701; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.795; - intrinsic_fall : 23.795; - } - } - } - cell (statusicell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (interrupt) { - direction : output; - } - } - cell (statusicell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - } - pin (interrupt) { - direction : output; - } - } - cell (macrocell4) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell5) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell6) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell7) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (datapathcell1) { - pin (clk_en) { - direction : input; - } - pin (reset) { - direction : input; - } - pin (cs_addr_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_1) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_2) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_si) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.77; - intrinsic_fall : 6.77; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.78; - intrinsic_fall : 6.78; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.65; - intrinsic_fall : 7.65; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_ci) { - direction : input; - } - pin (f0_load) { - direction : input; - } - pin (f1_load) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.85; - intrinsic_fall : 1.85; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (d0_load) { - direction : input; - } - pin (d1_load) { - direction : input; - } - pin (p_in_0) { - direction : input; - } - pin (p_in_1) { - direction : input; - } - pin (p_in_2) { - direction : input; - } - pin (p_in_3) { - direction : input; - } - pin (p_in_4) { - direction : input; - } - pin (p_in_5) { - direction : input; - } - pin (p_in_6) { - direction : input; - } - pin (p_in_7) { - direction : input; - } - pin (ce0i) { - direction : input; - } - pin (cl0i) { - direction : input; - } - pin (z0i) { - direction : input; - } - pin (ff0i) { - direction : input; - } - pin (ce1i) { - direction : input; - } - pin (cl1i) { - direction : input; - } - pin (z1i) { - direction : input; - } - pin (ff1i) { - direction : input; - } - pin (cap0i) { - direction : input; - } - pin (cap1i) { - direction : input; - } - pin (ci) { - direction : input; - } - pin (sir) { - direction : input; - } - pin (cfbi) { - direction : input; - } - pin (sil) { - direction : input; - } - pin (cmsbi) { - direction : input; - } - pin (busclk) { - direction : input; - clock : true; - } - pin (clock) { - direction : input; - clock : true; - } - pin (ce0_reg) { - direction : output; - } - pin (cl0_reg) { - direction : output; - } - pin (z0_reg) { - direction : output; - } - pin (f0_reg) { - direction : output; - } - pin (ce1_reg) { - direction : output; - } - pin (cl1_reg) { - direction : output; - } - pin (z1_reg) { - direction : output; - } - pin (f1_reg) { - direction : output; - } - pin (ov_msb_reg) { - direction : output; - } - pin (co_msb_reg) { - direction : output; - } - pin (cmsb_reg) { - direction : output; - } - pin (so_reg) { - direction : output; - } - pin (f0_bus_stat_reg) { - direction : output; - } - pin (f0_blk_stat_reg) { - direction : output; - } - pin (f1_bus_stat_reg) { - direction : output; - } - pin (f1_blk_stat_reg) { - direction : output; - } - pin (ce0_comb) { - direction : output; - } - pin (cl0_comb) { - direction : output; - } - pin (z0_comb) { - direction : output; - } - pin (f0_comb) { - direction : output; - } - pin (ce1_comb) { - direction : output; - } - pin (cl1_comb) { - direction : output; - } - pin (z1_comb) { - direction : output; - } - pin (f1_comb) { - direction : output; - } - pin (ov_msb_comb) { - direction : output; - } - pin (co_msb_comb) { - direction : output; - } - pin (cmsb_comb) { - direction : output; - } - pin (so_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.16; - intrinsic_fall : 8.16; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.30; - intrinsic_fall : 8.30; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.78; - intrinsic_fall : 5.78; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 6.12; - intrinsic_fall : 6.12; - } - } - pin (f0_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f0_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (f1_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f1_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (p_out_0) { - direction : output; - } - pin (p_out_1) { - direction : output; - } - pin (p_out_2) { - direction : output; - } - pin (p_out_3) { - direction : output; - } - pin (p_out_4) { - direction : output; - } - pin (p_out_5) { - direction : output; - } - pin (p_out_6) { - direction : output; - } - pin (p_out_7) { - direction : output; - } - pin (ce0) { - direction : output; - } - pin (cl0) { - direction : output; - } - pin (z0) { - direction : output; - } - pin (ff0) { - direction : output; - } - pin (ce1) { - direction : output; - } - pin (cl1) { - direction : output; - } - pin (z1) { - direction : output; - } - pin (ff1) { - direction : output; - } - pin (cap0) { - direction : output; - } - pin (cap1) { - direction : output; - } - pin (co_msb) { - direction : output; - } - pin (sol_msb) { - direction : output; - } - pin (cfbo) { - direction : output; - } - pin (sor) { - direction : output; - } - pin (cmsbo) { - direction : output; - } - } - cell (macrocell8) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell9) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell10) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell11) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell12) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (iocell8) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.103; - intrinsic_fall : 19.103; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 26.840; - intrinsic_fall : 26.840; - } - } - } - cell (iocell9) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.971; - intrinsic_fall : 17.971; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.711; - intrinsic_fall : 25.711; - } - } - } - cell (iocell10) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.982; - intrinsic_fall : 17.982; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.772; - intrinsic_fall : 25.772; - } - } - } - cell (iocell11) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 18.672; - intrinsic_fall : 18.672; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.214; - intrinsic_fall : 25.214; - } - } - } -} diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.vh2 deleted file mode 100644 index d1b0407..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_r.vh2 +++ /dev/null @@ -1,1479 +0,0 @@ --- Project: SPI_Design01 --- Generated: 01/16/2013 14:35:47 --- - -ENTITY SPI_Design01 IS - PORT( - \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(2)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(3)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(4)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(5)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(6)_PAD\ : OUT std_ulogic; - m_miso_pin(0)_PAD : IN std_ulogic; - m_mosi_pin(0)_PAD : OUT std_ulogic; - m_sclk_pin(0)_PAD : OUT std_ulogic; - m_ss_pin(0)_PAD : OUT std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 3.3e0; -END SPI_Design01; - -ARCHITECTURE __DEFAULT__ OF SPI_Design01 IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_107 : bit; - ATTRIBUTE placement_force OF Net_107 : SIGNAL IS "U(0,5,B)1"; - SIGNAL Net_20 : bit; - SIGNAL Net_30 : bit; - ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(0,4,B)1"; - SIGNAL Net_31 : bit; - ATTRIBUTE placement_force OF Net_31 : SIGNAL IS "U(0,5,A)3"; - SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(0,4,A)0"; - SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; - SIGNAL \SPIM:BSPIM:count_0\ : bit; - SIGNAL \SPIM:BSPIM:count_1\ : bit; - SIGNAL \SPIM:BSPIM:count_2\ : bit; - SIGNAL \SPIM:BSPIM:count_3\ : bit; - SIGNAL \SPIM:BSPIM:count_4\ : bit; - SIGNAL \SPIM:BSPIM:count_5\ : bit; - SIGNAL \SPIM:BSPIM:count_6\ : bit; - SIGNAL \SPIM:BSPIM:load_cond\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(0,4,B)0"; - SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(0,4,A)1"; - SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(0,4,A)2"; - SIGNAL \SPIM:BSPIM:state_0\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_0\ : SIGNAL IS "U(0,5,A)2"; - SIGNAL \SPIM:BSPIM:state_1\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(0,5,B)0"; - SIGNAL \SPIM:BSPIM:state_2\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_2\ : SIGNAL IS "U(0,5,A)0"; - SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_0\ : SIGNAL IS "U(0,5,A)1"; - SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(0,5,B)2"; - SIGNAL \SPIM:Net_276\ : bit; - ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; - SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL tmpOE__m_miso_pin_net_0 : bit; - ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; - ATTRIBUTE lib_model OF Net_107 : LABEL IS "macrocell1"; - ATTRIBUTE Location OF Net_107 : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; - ATTRIBUTE Location OF Net_30 : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF Net_31 : LABEL IS "macrocell3"; - ATTRIBUTE Location OF Net_31 : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell1"; - ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell2"; - ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell3"; - ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell4"; - ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell5"; - ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell6"; - ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell7"; - ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; - ATTRIBUTE Location OF \SPIM:BSPIM:BitCounter\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(1,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell4"; - ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell5"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell6"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell7"; - ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell8"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell9"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell10"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_2\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell11"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell12"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell8"; - ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell9"; - ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell10"; - ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF m_ss_pin(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF m_ss_pin(0) : LABEL IS "P0[7]"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - clock : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pad_out : OUT std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidaccell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic); - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open, - dclk_glb_0 => \SPIM:Net_276\, - dclk_0 => \SPIM:Net_276_local\); - - Net_107:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2) + (!main_0 * main_1 * !main_3) + (main_0 * !main_1 * !main_3)") - PORT MAP( - q => Net_107, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => Net_107); - - Net_30:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_3) + (main_0 * main_1 * !main_2 * !main_3) + (!main_1 * main_2 * !main_3 * main_4)") - PORT MAP( - q => Net_30, - clock_0 => \SPIM:Net_276\, - main_0 => Net_30, - main_1 => \SPIM:BSPIM:state_2\, - main_2 => \SPIM:BSPIM:state_1\, - main_3 => \SPIM:BSPIM:state_0\, - main_4 => \SPIM:BSPIM:mosi_from_dp\); - - Net_31:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)") - PORT MAP( - q => Net_31, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \LCD:LCDPort(0)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(0)_PAD\); - - \LCD:LCDPort(1)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(1)_PAD\); - - \LCD:LCDPort(2)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(2)_PAD\); - - \LCD:LCDPort(3)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(3)_PAD\); - - \LCD:LCDPort(4)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(4)_PAD\); - - \LCD:LCDPort(5)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(5)_PAD\); - - \LCD:LCDPort(6)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(6)_PAD\); - - \LCD:LCDPort\:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110", - ibuf_enabled => "1111111", - id => "923198f5-05eb-4681-ae86-b3593c234480/ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0000000", - input_sync => "1111111", - intr_mode => "00000000000000", - io_voltage => ", , , , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "0000000", - output_conn => "0000000", - output_sync => "0000000", - pin_aliases => ",,,,,,", - pin_mode => "OOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000", - sio_ibuf => "00000000", - sio_info => "00000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000", - spanning => 0, - sw_only => 0, - use_annotation => "0000000", - vtrip => "10101010101010", - width => 7); - - \SPIM:BSPIM:BitCounter\:count7cell - GENERIC MAP( - cy_alt_mode => 0, - cy_init_value => "0000000", - cy_period => "0001111", - cy_route_en => 1, - cy_route_ld => 0) - PORT MAP( - clock => \SPIM:Net_276\, - load => open, - enable => \SPIM:BSPIM:cnt_enable\, - count_6 => \SPIM:BSPIM:count_6\, - count_5 => \SPIM:BSPIM:count_5\, - count_4 => \SPIM:BSPIM:count_4\, - count_3 => \SPIM:BSPIM:count_3\, - count_2 => \SPIM:BSPIM:count_2\, - count_1 => \SPIM:BSPIM:count_1\, - count_0 => \SPIM:BSPIM:count_0\, - tc => \SPIM:BSPIM:cnt_tc\); - - \SPIM:BSPIM:RxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "1000000") - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => \SPIM:BSPIM:rx_status_6\, - status_5 => \SPIM:BSPIM:rx_status_5\, - status_4 => \SPIM:BSPIM:rx_status_4\, - status_3 => open, - status_2 => open, - status_1 => open, - status_0 => open); - - \SPIM:BSPIM:TxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "0001001") - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => open, - status_5 => open, - status_4 => \SPIM:BSPIM:tx_status_4\, - status_3 => \SPIM:BSPIM:load_rx_data\, - status_2 => \SPIM:BSPIM:tx_status_2\, - status_1 => \SPIM:BSPIM:tx_status_1\, - status_0 => \SPIM:BSPIM:tx_status_0\); - - \SPIM:BSPIM:cnt_enable\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * main_8) + (!main_0 * !main_1 * main_2 * !main_8) + (main_0 * main_1 * main_8) + (main_0 * main_2 * main_8) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7 * main_8)") - PORT MAP( - q => \SPIM:BSPIM:cnt_enable\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:cnt_enable\); - - \SPIM:BSPIM:load_cond\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_0 * !main_1 * !main_2 * !main_8) + (main_1 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_2 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8)") - PORT MAP( - q => \SPIM:BSPIM:load_cond\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:load_cond\); - - \SPIM:BSPIM:load_rx_data\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4)") - PORT MAP( - q => \SPIM:BSPIM:load_rx_data\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\); - - \SPIM:BSPIM:rx_status_6\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)") - PORT MAP( - q => \SPIM:BSPIM:rx_status_6\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\, - main_5 => \SPIM:BSPIM:rx_status_4\); - - \SPIM:BSPIM:sR8:Dp:u0\:datapathcell - GENERIC MAP( - a0_init => "00000000", - a1_init => "00000000", - ce0_sync => 1, - ce1_sync => 1, - cl0_sync => 1, - cl1_sync => 1, - cmsb_sync => 1, - co_msb_sync => 1, - cy_dpconfig => "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100", - d0_init => "00000000", - d1_init => "00000000", - f0_blk_sync => 1, - f0_bus_sync => 1, - f1_blk_sync => 1, - f1_bus_sync => 1, - ff0_sync => 1, - ff1_sync => 1, - ov_msb_sync => 1, - so_sync => 1, - z0_sync => 1, - z1_sync => 1, - uses_p_in => '0', - uses_p_out => '0') - PORT MAP( - clock => \SPIM:Net_276\, - cs_addr_2 => \SPIM:BSPIM:state_2\, - cs_addr_1 => \SPIM:BSPIM:state_1\, - cs_addr_0 => \SPIM:BSPIM:state_0\, - route_si => Net_20, - f1_load => \SPIM:BSPIM:load_rx_data\, - so_comb => \SPIM:BSPIM:mosi_from_dp\, - f0_bus_stat_comb => \SPIM:BSPIM:tx_status_2\, - f0_blk_stat_comb => \SPIM:BSPIM:tx_status_1\, - f1_bus_stat_comb => \SPIM:BSPIM:rx_status_5\, - f1_blk_stat_comb => \SPIM:BSPIM:rx_status_4\, - busclk => ClockBlock_BUS_CLK); - - \SPIM:BSPIM:state_0\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7) + (main_0 * !main_2) + (!main_1 * !main_2 * main_8) + (main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8)") - PORT MAP( - q => \SPIM:BSPIM:state_0\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_1\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (main_0 * main_1) + (main_0 * main_2) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)") - PORT MAP( - q => \SPIM:BSPIM:state_1\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_2\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)") - PORT MAP( - q => \SPIM:BSPIM:state_2\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:tx_status_0\:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_0\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \SPIM:BSPIM:tx_status_4\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_4\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - m_miso_pin:logicalport - GENERIC MAP( - drive_mode => "001", - ibuf_enabled => "1", - id => "1425177d-0d0e-4468-8bcc-e638e5509a9b", - init_dr_st => "0", - input_sync => "0", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "0", - output_sync => "0", - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1); - - m_miso_pin(0):iocell - GENERIC MAP( - logicalport => "m_miso_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - fb => Net_20, - pad_in => m_miso_pin(0)_PAD); - - m_mosi_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_mosi_pin(0):iocell - GENERIC MAP( - logicalport => "m_mosi_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_30, - pad_out => m_mosi_pin(0)_PAD, - pad_in => m_mosi_pin(0)_PAD); - - m_sclk_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "640f8e70-5666-4015-9ac8-6ed7f71d8e01", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_sclk_pin(0):iocell - GENERIC MAP( - logicalport => "m_sclk_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_31, - pad_out => m_sclk_pin(0)_PAD, - pad_in => m_sclk_pin(0)_PAD); - - m_ss_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "5ec2583b-d6a1-4a86-ac3e-b170e6f000fd", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_ss_pin(0):iocell - GENERIC MAP( - logicalport => "m_ss_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_107, - pad_out => m_ss_pin(0)_PAD, - pad_in => m_ss_pin(0)_PAD); - -END __DEFAULT__; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.lib b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.lib deleted file mode 100644 index 5402b07..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.lib +++ /dev/null @@ -1,2337 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (macrocell1) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell2) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell3) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (iocell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.231; - intrinsic_fall : 15.231; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.499; - intrinsic_fall : 17.499; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 18.989; - intrinsic_fall : 18.989; - } - } - } - cell (iocell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.254; - intrinsic_fall : 15.254; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.253; - intrinsic_fall : 16.253; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 16.490; - intrinsic_fall : 16.490; - } - } - } - cell (iocell3) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.219; - intrinsic_fall : 16.219; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 21.315; - intrinsic_fall : 21.315; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 17.470; - intrinsic_fall : 17.470; - } - } - } - cell (iocell4) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.844; - intrinsic_fall : 16.844; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 24.720; - intrinsic_fall : 24.720; - } - } - } - cell (iocell5) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.776; - intrinsic_fall : 15.776; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 20.119; - intrinsic_fall : 20.119; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.475; - intrinsic_fall : 23.475; - } - } - } - cell (iocell6) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.458; - intrinsic_fall : 16.458; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.998; - intrinsic_fall : 16.998; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.553; - intrinsic_fall : 25.553; - } - } - } - cell (iocell7) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.998; - intrinsic_fall : 15.998; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.701; - intrinsic_fall : 19.701; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 23.795; - intrinsic_fall : 23.795; - } - } - } - cell (statusicell1) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (interrupt) { - direction : output; - } - } - cell (statusicell2) { - pin (clock) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - pin (reset) { - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_fall : 0.000; - } - } - pin (status_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_1) { - direction : input; - } - pin (status_2) { - direction : input; - } - pin (status_3) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.570; - intrinsic_fall : 1.570; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 2.000; - intrinsic_fall : 2.000; - } - } - pin (status_4) { - direction : input; - } - pin (status_5) { - direction : input; - } - pin (status_6) { - direction : input; - } - pin (interrupt) { - direction : output; - } - } - cell (macrocell4) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell5) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell6) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell7) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (datapathcell1) { - pin (clk_en) { - direction : input; - } - pin (reset) { - direction : input; - } - pin (cs_addr_0) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_1) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (cs_addr_2) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.29; - intrinsic_fall : 6.29; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.30; - intrinsic_fall : 6.30; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.17; - intrinsic_fall : 7.17; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_si) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.77; - intrinsic_fall : 6.77; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 6.78; - intrinsic_fall : 6.78; - } - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 7.65; - intrinsic_fall : 7.65; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (route_ci) { - direction : input; - } - pin (f0_load) { - direction : input; - } - pin (f1_load) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 1.85; - intrinsic_fall : 1.85; - } - timing () { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (d0_load) { - direction : input; - } - pin (d1_load) { - direction : input; - } - pin (p_in_0) { - direction : input; - } - pin (p_in_1) { - direction : input; - } - pin (p_in_2) { - direction : input; - } - pin (p_in_3) { - direction : input; - } - pin (p_in_4) { - direction : input; - } - pin (p_in_5) { - direction : input; - } - pin (p_in_6) { - direction : input; - } - pin (p_in_7) { - direction : input; - } - pin (ce0i) { - direction : input; - } - pin (cl0i) { - direction : input; - } - pin (z0i) { - direction : input; - } - pin (ff0i) { - direction : input; - } - pin (ce1i) { - direction : input; - } - pin (cl1i) { - direction : input; - } - pin (z1i) { - direction : input; - } - pin (ff1i) { - direction : input; - } - pin (cap0i) { - direction : input; - } - pin (cap1i) { - direction : input; - } - pin (ci) { - direction : input; - } - pin (sir) { - direction : input; - } - pin (cfbi) { - direction : input; - } - pin (sil) { - direction : input; - } - pin (cmsbi) { - direction : input; - } - pin (busclk) { - direction : input; - clock : true; - } - pin (clock) { - direction : input; - clock : true; - } - pin (ce0_reg) { - direction : output; - } - pin (cl0_reg) { - direction : output; - } - pin (z0_reg) { - direction : output; - } - pin (f0_reg) { - direction : output; - } - pin (ce1_reg) { - direction : output; - } - pin (cl1_reg) { - direction : output; - } - pin (z1_reg) { - direction : output; - } - pin (f1_reg) { - direction : output; - } - pin (ov_msb_reg) { - direction : output; - } - pin (co_msb_reg) { - direction : output; - } - pin (cmsb_reg) { - direction : output; - } - pin (so_reg) { - direction : output; - } - pin (f0_bus_stat_reg) { - direction : output; - } - pin (f0_blk_stat_reg) { - direction : output; - } - pin (f1_bus_stat_reg) { - direction : output; - } - pin (f1_blk_stat_reg) { - direction : output; - } - pin (ce0_comb) { - direction : output; - } - pin (cl0_comb) { - direction : output; - } - pin (z0_comb) { - direction : output; - } - pin (f0_comb) { - direction : output; - } - pin (ce1_comb) { - direction : output; - } - pin (cl1_comb) { - direction : output; - } - pin (z1_comb) { - direction : output; - } - pin (f1_comb) { - direction : output; - } - pin (ov_msb_comb) { - direction : output; - } - pin (co_msb_comb) { - direction : output; - } - pin (cmsb_comb) { - direction : output; - } - pin (so_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.16; - intrinsic_fall : 8.16; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 8.30; - intrinsic_fall : 8.30; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.78; - intrinsic_fall : 5.78; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 6.12; - intrinsic_fall : 6.12; - } - } - pin (f0_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f0_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (f1_bus_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - timing () { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.21; - intrinsic_fall : 7.21; - } - } - pin (f1_blk_stat_comb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - timing () { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 5.28; - intrinsic_fall : 5.28; - } - } - pin (p_out_0) { - direction : output; - } - pin (p_out_1) { - direction : output; - } - pin (p_out_2) { - direction : output; - } - pin (p_out_3) { - direction : output; - } - pin (p_out_4) { - direction : output; - } - pin (p_out_5) { - direction : output; - } - pin (p_out_6) { - direction : output; - } - pin (p_out_7) { - direction : output; - } - pin (ce0) { - direction : output; - } - pin (cl0) { - direction : output; - } - pin (z0) { - direction : output; - } - pin (ff0) { - direction : output; - } - pin (ce1) { - direction : output; - } - pin (cl1) { - direction : output; - } - pin (z1) { - direction : output; - } - pin (ff1) { - direction : output; - } - pin (cap0) { - direction : output; - } - pin (cap1) { - direction : output; - } - pin (co_msb) { - direction : output; - } - pin (sol_msb) { - direction : output; - } - pin (cfbo) { - direction : output; - } - pin (sor) { - direction : output; - } - pin (cmsbo) { - direction : output; - } - } - cell (macrocell8) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell9) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell10) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 3.510; - intrinsic_fall : 3.510; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - pin (q_fixed) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "clock_0"; - intrinsic_rise : 1.250; - intrinsic_fall : 1.250; - } - } - } - cell (macrocell11) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((main_0 * !main_1 * main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (macrocell12) { - pin (cin) { - direction : input; - } - bundle (cpt0) { - members (cpt0_0, cpt0_1, cpt0_2, cpt0_3, cpt0_4, cpt0_5, cpt0_6, cpt0_7, cpt0_8, cpt0_9, cpt0_10, cpt0_11); - direction : input; - } - bundle (cpt1) { - members (cpt1_0, cpt1_1, cpt1_2, cpt1_3, cpt1_4, cpt1_5, cpt1_6, cpt1_7, cpt1_8, cpt1_9, cpt1_10, cpt1_11); - direction : input; - } - bundle (main) { - members (main_0, main_1, main_2, main_3, main_4, main_5, main_6, main_7, main_8, main_9, main_10, main_11); - direction : input; - } - bundle (clock) { - members (clock_0); - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing () { - timing_type : setup_rising; - related_pin : "clock_0"; - intrinsic_rise : 2.100; - intrinsic_fall : 2.100; - } - timing () { - timing_type : hold_rising; - related_pin : "clock_0"; - intrinsic_rise : 0.000; - intrinsic_fall : 0.000; - } - } - bundle (ar) { - members (ar_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - bundle (ap) { - members (ap_0); - direction : input; - timing () { - timing_type : recovery_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - timing () { - timing_type : removal_rising; - related_pin : "clock_0"; - intrinsic_fall : 0.000; - } - } - pin (cout) { - direction : output; - } - pin (q) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - pin (q_fixed) { - direction : output; - function : "((!main_0 * !main_1 * !main_2)) ^ 0"; - timing () { - timing_type : combinational; - related_pin : "main_0 main_1 main_2 main_3 main_4 main_5 main_6 main_7 main_8 main_9 main_10 main_11"; - intrinsic_rise : 3.350; - intrinsic_fall : 3.350; - } - } - } - cell (iocell8) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.689; - intrinsic_fall : 16.689; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.103; - intrinsic_fall : 19.103; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 26.840; - intrinsic_fall : 26.840; - } - } - } - cell (iocell9) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.119; - intrinsic_fall : 17.119; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.971; - intrinsic_fall : 17.971; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.711; - intrinsic_fall : 25.711; - } - } - } - cell (iocell10) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.630; - intrinsic_fall : 15.630; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 17.982; - intrinsic_fall : 17.982; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.772; - intrinsic_fall : 25.772; - } - } - } - cell (iocell11) { - pin (clock) { - direction : input; - clock : true; - } - pin (pin_input) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 15.393; - intrinsic_fall : 15.393; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 18.672; - intrinsic_fall : 18.672; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 25.214; - intrinsic_fall : 25.214; - } - } - } -} diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.vh2 b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.vh2 deleted file mode 100644 index 20f155b..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_t.vh2 +++ /dev/null @@ -1,1479 +0,0 @@ --- Project: C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj --- Generated: 01/16/2013 14:35:49 --- - -ENTITY SPI_Design01 IS - PORT( - \LCD:LCDPort(0)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(1)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(2)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(3)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(4)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(5)_PAD\ : OUT std_ulogic; - \LCD:LCDPort(6)_PAD\ : OUT std_ulogic; - m_miso_pin(0)_PAD : IN std_ulogic; - m_mosi_pin(0)_PAD : OUT std_ulogic; - m_sclk_pin(0)_PAD : OUT std_ulogic; - m_ss_pin(0)_PAD : OUT std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 3.3e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 3.3e0; -END SPI_Design01; - -ARCHITECTURE __DEFAULT__ OF SPI_Design01 IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_107 : bit; - ATTRIBUTE placement_force OF Net_107 : SIGNAL IS "U(0,5,B)1"; - SIGNAL Net_20 : bit; - SIGNAL Net_30 : bit; - ATTRIBUTE placement_force OF Net_30 : SIGNAL IS "U(0,4,B)1"; - SIGNAL Net_31 : bit; - ATTRIBUTE placement_force OF Net_31 : SIGNAL IS "U(0,5,A)3"; - SIGNAL \SPIM:BSPIM:cnt_enable\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:cnt_enable\ : SIGNAL IS "U(0,4,A)0"; - SIGNAL \SPIM:BSPIM:cnt_tc\ : bit; - SIGNAL \SPIM:BSPIM:count_0\ : bit; - SIGNAL \SPIM:BSPIM:count_1\ : bit; - SIGNAL \SPIM:BSPIM:count_2\ : bit; - SIGNAL \SPIM:BSPIM:count_3\ : bit; - SIGNAL \SPIM:BSPIM:count_4\ : bit; - SIGNAL \SPIM:BSPIM:count_5\ : bit; - SIGNAL \SPIM:BSPIM:count_6\ : bit; - SIGNAL \SPIM:BSPIM:load_cond\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_cond\ : SIGNAL IS "U(0,4,B)0"; - SIGNAL \SPIM:BSPIM:load_rx_data\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:load_rx_data\ : SIGNAL IS "U(0,4,A)1"; - SIGNAL \SPIM:BSPIM:mosi_from_dp\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_4\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_5\ : bit; - SIGNAL \SPIM:BSPIM:rx_status_6\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:rx_status_6\ : SIGNAL IS "U(0,4,A)2"; - SIGNAL \SPIM:BSPIM:state_0\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_0\ : SIGNAL IS "U(0,5,A)2"; - SIGNAL \SPIM:BSPIM:state_1\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_1\ : SIGNAL IS "U(0,5,B)0"; - SIGNAL \SPIM:BSPIM:state_2\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:state_2\ : SIGNAL IS "U(0,5,A)0"; - SIGNAL \SPIM:BSPIM:tx_status_0\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_0\ : SIGNAL IS "U(0,5,A)1"; - SIGNAL \SPIM:BSPIM:tx_status_1\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_2\ : bit; - SIGNAL \SPIM:BSPIM:tx_status_4\ : bit; - ATTRIBUTE placement_force OF \SPIM:BSPIM:tx_status_4\ : SIGNAL IS "U(0,5,B)2"; - SIGNAL \SPIM:Net_276\ : bit; - ATTRIBUTE global_signal OF \SPIM:Net_276\ : SIGNAL IS true; - SIGNAL \SPIM:Net_276_local\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL tmpOE__m_miso_pin_net_0 : bit; - ATTRIBUTE POWER OF tmpOE__m_miso_pin_net_0 : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; - ATTRIBUTE lib_model OF Net_107 : LABEL IS "macrocell1"; - ATTRIBUTE Location OF Net_107 : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF Net_30 : LABEL IS "macrocell2"; - ATTRIBUTE Location OF Net_30 : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF Net_31 : LABEL IS "macrocell3"; - ATTRIBUTE Location OF Net_31 : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \LCD:LCDPort(0)\ : LABEL IS "iocell1"; - ATTRIBUTE Location OF \LCD:LCDPort(0)\ : LABEL IS "P2[0]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(1)\ : LABEL IS "iocell2"; - ATTRIBUTE Location OF \LCD:LCDPort(1)\ : LABEL IS "P2[1]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(2)\ : LABEL IS "iocell3"; - ATTRIBUTE Location OF \LCD:LCDPort(2)\ : LABEL IS "P2[2]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(3)\ : LABEL IS "iocell4"; - ATTRIBUTE Location OF \LCD:LCDPort(3)\ : LABEL IS "P2[3]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(4)\ : LABEL IS "iocell5"; - ATTRIBUTE Location OF \LCD:LCDPort(4)\ : LABEL IS "P2[4]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(5)\ : LABEL IS "iocell6"; - ATTRIBUTE Location OF \LCD:LCDPort(5)\ : LABEL IS "P2[5]"; - ATTRIBUTE lib_model OF \LCD:LCDPort(6)\ : LABEL IS "iocell7"; - ATTRIBUTE Location OF \LCD:LCDPort(6)\ : LABEL IS "P2[6]"; - ATTRIBUTE Location OF \SPIM:BSPIM:BitCounter\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "statusicell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:RxStsReg\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "statusicell2"; - ATTRIBUTE Location OF \SPIM:BSPIM:TxStsReg\ : LABEL IS "U(1,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "macrocell4"; - ATTRIBUTE Location OF \SPIM:BSPIM:cnt_enable\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_cond\ : LABEL IS "macrocell5"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_cond\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "macrocell6"; - ATTRIBUTE Location OF \SPIM:BSPIM:load_rx_data\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "macrocell7"; - ATTRIBUTE Location OF \SPIM:BSPIM:rx_status_6\ : LABEL IS "U(0,4)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "datapathcell1"; - ATTRIBUTE Location OF \SPIM:BSPIM:sR8:Dp:u0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_0\ : LABEL IS "macrocell8"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_1\ : LABEL IS "macrocell9"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_1\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:state_2\ : LABEL IS "macrocell10"; - ATTRIBUTE Location OF \SPIM:BSPIM:state_2\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "macrocell11"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_0\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "macrocell12"; - ATTRIBUTE Location OF \SPIM:BSPIM:tx_status_4\ : LABEL IS "U(0,5)"; - ATTRIBUTE lib_model OF m_miso_pin(0) : LABEL IS "iocell8"; - ATTRIBUTE Location OF m_miso_pin(0) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF m_mosi_pin(0) : LABEL IS "iocell9"; - ATTRIBUTE Location OF m_mosi_pin(0) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF m_sclk_pin(0) : LABEL IS "iocell10"; - ATTRIBUTE Location OF m_sclk_pin(0) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF m_ss_pin(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF m_ss_pin(0) : LABEL IS "P0[7]"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - clock : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pad_out : OUT std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidaccell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic); - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open, - dclk_glb_0 => \SPIM:Net_276\, - dclk_0 => \SPIM:Net_276_local\); - - Net_107:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * main_2) + (!main_0 * main_1 * !main_3) + (main_0 * !main_1 * !main_3)") - PORT MAP( - q => Net_107, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => Net_107); - - Net_30:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_3) + (main_0 * main_1 * !main_2 * !main_3) + (!main_1 * main_2 * !main_3 * main_4)") - PORT MAP( - q => Net_30, - clock_0 => \SPIM:Net_276\, - main_0 => Net_30, - main_1 => \SPIM:BSPIM:state_2\, - main_2 => \SPIM:BSPIM:state_1\, - main_3 => \SPIM:BSPIM:state_0\, - main_4 => \SPIM:BSPIM:mosi_from_dp\); - - Net_31:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2)") - PORT MAP( - q => Net_31, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \LCD:LCDPort(0)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(0)_PAD\); - - \LCD:LCDPort(1)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(1)_PAD\); - - \LCD:LCDPort(2)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(2)_PAD\); - - \LCD:LCDPort(3)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(3)_PAD\); - - \LCD:LCDPort(4)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(4)_PAD\); - - \LCD:LCDPort(5)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(5)_PAD\); - - \LCD:LCDPort(6)\:iocell - GENERIC MAP( - logicalport => "\LCD:LCDPort\", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pad_in => \LCD:LCDPort(6)_PAD\); - - \LCD:LCDPort\:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110", - ibuf_enabled => "1111111", - id => "923198f5-05eb-4681-ae86-b3593c234480/ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0000000", - input_sync => "1111111", - intr_mode => "00000000000000", - io_voltage => ", , , , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "0000000", - output_conn => "0000000", - output_sync => "0000000", - pin_aliases => ",,,,,,", - pin_mode => "OOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000", - sio_ibuf => "00000000", - sio_info => "00000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000", - spanning => 0, - sw_only => 0, - use_annotation => "0000000", - vtrip => "10101010101010", - width => 7); - - \SPIM:BSPIM:BitCounter\:count7cell - GENERIC MAP( - cy_alt_mode => 0, - cy_init_value => "0000000", - cy_period => "0001111", - cy_route_en => 1, - cy_route_ld => 0) - PORT MAP( - clock => \SPIM:Net_276\, - load => open, - enable => \SPIM:BSPIM:cnt_enable\, - count_6 => \SPIM:BSPIM:count_6\, - count_5 => \SPIM:BSPIM:count_5\, - count_4 => \SPIM:BSPIM:count_4\, - count_3 => \SPIM:BSPIM:count_3\, - count_2 => \SPIM:BSPIM:count_2\, - count_1 => \SPIM:BSPIM:count_1\, - count_0 => \SPIM:BSPIM:count_0\, - tc => \SPIM:BSPIM:cnt_tc\); - - \SPIM:BSPIM:RxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "1000000") - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => \SPIM:BSPIM:rx_status_6\, - status_5 => \SPIM:BSPIM:rx_status_5\, - status_4 => \SPIM:BSPIM:rx_status_4\, - status_3 => open, - status_2 => open, - status_1 => open, - status_0 => open); - - \SPIM:BSPIM:TxStsReg\:statusicell - GENERIC MAP( - cy_force_order => 1, - cy_int_mask => "0000000", - cy_md_select => "0001001") - PORT MAP( - clock => \SPIM:Net_276\, - status_6 => open, - status_5 => open, - status_4 => \SPIM:BSPIM:tx_status_4\, - status_3 => \SPIM:BSPIM:load_rx_data\, - status_2 => \SPIM:BSPIM:tx_status_2\, - status_1 => \SPIM:BSPIM:tx_status_1\, - status_0 => \SPIM:BSPIM:tx_status_0\); - - \SPIM:BSPIM:cnt_enable\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * main_8) + (!main_0 * !main_1 * main_2 * !main_8) + (main_0 * main_1 * main_8) + (main_0 * main_2 * main_8) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7 * main_8)") - PORT MAP( - q => \SPIM:BSPIM:cnt_enable\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:cnt_enable\); - - \SPIM:BSPIM:load_cond\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_0 * !main_1 * !main_2 * !main_8) + (main_1 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8) + (main_2 * !main_3 * !main_4 * !main_5 * !main_6 * !main_7 * main_8)") - PORT MAP( - q => \SPIM:BSPIM:load_cond\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:load_cond\); - - \SPIM:BSPIM:load_rx_data\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4)") - PORT MAP( - q => \SPIM:BSPIM:load_rx_data\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\); - - \SPIM:BSPIM:rx_status_6\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2 * !main_3 * main_4 * main_5)") - PORT MAP( - q => \SPIM:BSPIM:rx_status_6\, - main_0 => \SPIM:BSPIM:count_4\, - main_1 => \SPIM:BSPIM:count_3\, - main_2 => \SPIM:BSPIM:count_2\, - main_3 => \SPIM:BSPIM:count_1\, - main_4 => \SPIM:BSPIM:count_0\, - main_5 => \SPIM:BSPIM:rx_status_4\); - - \SPIM:BSPIM:sR8:Dp:u0\:datapathcell - GENERIC MAP( - a0_init => "00000000", - a1_init => "00000000", - ce0_sync => 1, - ce1_sync => 1, - cl0_sync => 1, - cl1_sync => 1, - cmsb_sync => 1, - co_msb_sync => 1, - cy_dpconfig => "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001100111100000000000000000100", - d0_init => "00000000", - d1_init => "00000000", - f0_blk_sync => 1, - f0_bus_sync => 1, - f1_blk_sync => 1, - f1_bus_sync => 1, - ff0_sync => 1, - ff1_sync => 1, - ov_msb_sync => 1, - so_sync => 1, - z0_sync => 1, - z1_sync => 1, - uses_p_in => '0', - uses_p_out => '0') - PORT MAP( - clock => \SPIM:Net_276\, - cs_addr_2 => \SPIM:BSPIM:state_2\, - cs_addr_1 => \SPIM:BSPIM:state_1\, - cs_addr_0 => \SPIM:BSPIM:state_0\, - route_si => Net_20, - f1_load => \SPIM:BSPIM:load_rx_data\, - so_comb => \SPIM:BSPIM:mosi_from_dp\, - f0_bus_stat_comb => \SPIM:BSPIM:tx_status_2\, - f0_blk_stat_comb => \SPIM:BSPIM:tx_status_1\, - f1_bus_stat_comb => \SPIM:BSPIM:rx_status_5\, - f1_blk_stat_comb => \SPIM:BSPIM:rx_status_4\, - busclk => ClockBlock_BUS_CLK); - - \SPIM:BSPIM:state_0\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7) + (main_0 * !main_2) + (!main_1 * !main_2 * main_8) + (main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8)") - PORT MAP( - q => \SPIM:BSPIM:state_0\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_1\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2) + (!main_0 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (main_0 * main_1) + (main_0 * main_2) + (main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)") - PORT MAP( - q => \SPIM:BSPIM:state_1\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:state_2\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * main_1 * !main_2 * !main_3 * !main_4 * !main_5 * main_6 * !main_7 * !main_8) + (!main_0 * main_1 * main_2 * !main_3 * !main_4 * !main_5 * !main_6 * main_7)") - PORT MAP( - q => \SPIM:BSPIM:state_2\, - clock_0 => \SPIM:Net_276\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\, - main_3 => \SPIM:BSPIM:count_4\, - main_4 => \SPIM:BSPIM:count_3\, - main_5 => \SPIM:BSPIM:count_2\, - main_6 => \SPIM:BSPIM:count_1\, - main_7 => \SPIM:BSPIM:count_0\, - main_8 => \SPIM:BSPIM:tx_status_1\); - - \SPIM:BSPIM:tx_status_0\:macrocell - GENERIC MAP( - eqn_main => "(main_0 * !main_1 * main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_0\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - \SPIM:BSPIM:tx_status_4\:macrocell - GENERIC MAP( - eqn_main => "(!main_0 * !main_1 * !main_2)") - PORT MAP( - q => \SPIM:BSPIM:tx_status_4\, - main_0 => \SPIM:BSPIM:state_2\, - main_1 => \SPIM:BSPIM:state_1\, - main_2 => \SPIM:BSPIM:state_0\); - - m_miso_pin:logicalport - GENERIC MAP( - drive_mode => "001", - ibuf_enabled => "1", - id => "1425177d-0d0e-4468-8bcc-e638e5509a9b", - init_dr_st => "0", - input_sync => "0", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "0", - output_sync => "0", - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1); - - m_miso_pin(0):iocell - GENERIC MAP( - logicalport => "m_miso_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - fb => Net_20, - pad_in => m_miso_pin(0)_PAD); - - m_mosi_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "ed092b9b-d398-4703-be89-cebf998501f6", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_mosi_pin(0):iocell - GENERIC MAP( - logicalport => "m_mosi_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_30, - pad_out => m_mosi_pin(0)_PAD, - pad_in => m_mosi_pin(0)_PAD); - - m_sclk_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "640f8e70-5666-4015-9ac8-6ed7f71d8e01", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_sclk_pin(0):iocell - GENERIC MAP( - logicalport => "m_sclk_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_31, - pad_out => m_sclk_pin(0)_PAD, - pad_in => m_sclk_pin(0)_PAD); - - m_ss_pin:logicalport - GENERIC MAP( - drive_mode => "110", - ibuf_enabled => "1", - id => "5ec2583b-d6a1-4a86-ac3e-b170e6f000fd", - init_dr_st => "0", - input_sync => "1", - intr_mode => "00", - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - output_conn => "1", - output_sync => "0", - pin_aliases => "", - pin_mode => "O", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1); - - m_ss_pin(0):iocell - GENERIC MAP( - logicalport => "m_ss_pin", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - oe => open, - pin_input => Net_107, - pad_out => m_ss_pin(0)_PAD, - pad_in => m_ss_pin(0)_PAD); - -END __DEFAULT__; diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_timing.html b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_timing.html deleted file mode 100644 index e2529d6..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_timing.html +++ /dev/null @@ -1,2447 +0,0 @@ - - - - -Static Timing Analysis Report - - - - - - -

Static Timing Analysis

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Project : SPI_Design01
Build Time : 01/16/13 14:35:50
Device : CY8C5568AXI-060
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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No Timing Violations
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ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
CyILOCyILO1.000 kHz1.000 kHz N/A
CyIMOCyIMO3.000 MHz3.000 MHz N/A
CyMASTER_CLKCyMASTER_CLK24.000 MHz24.000 MHz N/A
SPIM_IntClockCyMASTER_CLK2.000 MHz2.000 MHz62.066 MHz
CyBUS_CLKCyMASTER_CLK24.000 MHz24.000 MHz N/A
CyPLL_OUTCyPLL_OUT24.000 MHz24.000 MHz N/A
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Path Delay Requirement : 500ns(2 MHz)
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SourceDestinationFMaxDelay (ns)Slack (ns)Violation
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:RxStsReg\/status_662.066 MHz16.112483.888
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb5.280
Route 1\SPIM:BSPIM:rx_status_4\\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb\SPIM:BSPIM:rx_status_6\/main_53.604
macrocell7U(0,4)1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_5\SPIM:BSPIM:rx_status_6\/q3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308
statusicell1U(0,4)1\SPIM:BSPIM:RxStsReg\SETUP1.570
Clock Skew0.000
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\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:sR8:Dp:u0\/f1_load63.219 MHz15.818484.182
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:load_rx_data\/main_35.595
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_3\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:sR8:Dp:u0\/f1_load2.913
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\SETUP1.850
Clock Skew0.000
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\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:TxStsReg\/status_366.934 MHz14.940485.060
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:load_rx_data\/main_35.595
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_3\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:TxStsReg\/status_32.315
statusicell2U(1,4)1\SPIM:BSPIM:TxStsReg\SETUP1.570
Clock Skew0.000
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\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:RxStsReg\/status_666.966 MHz14.933485.067
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_12.110
Route 1\SPIM:BSPIM:count_1\\SPIM:BSPIM:BitCounter\/count_1\SPIM:BSPIM:rx_status_6\/main_35.595
macrocell7U(0,4)1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/main_3\SPIM:BSPIM:rx_status_6\/q3.350
Route 1\SPIM:BSPIM:rx_status_6\\SPIM:BSPIM:rx_status_6\/q\SPIM:BSPIM:RxStsReg\/status_62.308
statusicell1U(0,4)1\SPIM:BSPIM:RxStsReg\SETUP1.570
Clock Skew0.000
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\SPIM:BSPIM:sR8:Dp:u0\/so_combNet_30/main_467.898 MHz14.728485.272
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/so_comb8.300
Route 1\SPIM:BSPIM:mosi_from_dp\\SPIM:BSPIM:sR8:Dp:u0\/so_combNet_30/main_42.918
macrocell2U(0,4)1Net_30SETUP3.510
Clock Skew0.000
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\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:sR8:Dp:u0\/f1_load70.832 MHz14.118485.882
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_22.110
Route 1\SPIM:BSPIM:count_2\\SPIM:BSPIM:BitCounter\/count_2\SPIM:BSPIM:load_rx_data\/main_23.895
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_2\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:sR8:Dp:u0\/f1_load2.913
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\SETUP1.850
Clock Skew0.000
-
\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:sR8:Dp:u0\/f1_load71.582 MHz13.970486.030
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_42.110
Route 1\SPIM:BSPIM:count_4\\SPIM:BSPIM:BitCounter\/count_4\SPIM:BSPIM:load_rx_data\/main_03.747
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_0\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:sR8:Dp:u0\/f1_load2.913
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\SETUP1.850
Clock Skew0.000
-
\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:sR8:Dp:u0\/f1_load71.674 MHz13.952486.048
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_32.110
Route 1\SPIM:BSPIM:count_3\\SPIM:BSPIM:BitCounter\/count_3\SPIM:BSPIM:load_rx_data\/main_13.729
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_1\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:sR8:Dp:u0\/f1_load2.913
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\SETUP1.850
Clock Skew0.000
-
\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:sR8:Dp:u0\/f1_load71.736 MHz13.940486.060
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
count7cellU(0,5)1\SPIM:BSPIM:BitCounter\\SPIM:BSPIM:BitCounter\/clock\SPIM:BSPIM:BitCounter\/count_02.110
Route 1\SPIM:BSPIM:count_0\\SPIM:BSPIM:BitCounter\/count_0\SPIM:BSPIM:load_rx_data\/main_43.717
macrocell6U(0,4)1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/main_4\SPIM:BSPIM:load_rx_data\/q3.350
Route 1\SPIM:BSPIM:load_rx_data\\SPIM:BSPIM:load_rx_data\/q\SPIM:BSPIM:sR8:Dp:u0\/f1_load2.913
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\SETUP1.850
Clock Skew0.000
-
\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_872.733 MHz13.749486.251
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\\SPIM:BSPIM:sR8:Dp:u0\/clock\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb5.280
Route 1\SPIM:BSPIM:tx_status_1\\SPIM:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb\SPIM:BSPIM:state_1\/main_84.959
macrocell9U(0,5)1\SPIM:BSPIM:state_1\SETUP3.510
Clock Skew0.000
-
-
-
-
-
-
-
-
-
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SourceDestinationSlack (ns)Violation
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_13.546
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:sR8:Dp:u0\/cs_addr_12.296
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:load_cond\/q\SPIM:BSPIM:load_cond\/main_83.549
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell5U(0,4)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/clock_0\SPIM:BSPIM:load_cond\/q1.250
macrocell5U(0,4)1\SPIM:BSPIM:load_cond\\SPIM:BSPIM:load_cond\/q\SPIM:BSPIM:load_cond\/main_82.299
macrocell5U(0,4)1\SPIM:BSPIM:load_cond\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/qNet_107/main_13.843
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/qNet_107/main_12.593
macrocell1U(0,5)1Net_107 HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_1\/main_13.843
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_1\/main_12.593
macrocell9U(0,5)1\SPIM:BSPIM:state_1\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/qNet_31/main_13.844
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/qNet_31/main_12.594
macrocell3U(0,5)1Net_31 HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_0\/main_13.844
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_0\/main_12.594
macrocell8U(0,5)1\SPIM:BSPIM:state_0\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_2\/main_13.844
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell9U(0,5)1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/clock_0\SPIM:BSPIM:state_1\/q1.250
Route1\SPIM:BSPIM:state_1\\SPIM:BSPIM:state_1\/q\SPIM:BSPIM:state_2\/main_12.594
macrocell10U(0,5)1\SPIM:BSPIM:state_2\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_83.879
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell4U(0,4)1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/clock_0\SPIM:BSPIM:cnt_enable\/q1.250
macrocell4U(0,4)1\SPIM:BSPIM:cnt_enable\\SPIM:BSPIM:cnt_enable\/q\SPIM:BSPIM:cnt_enable\/main_82.629
macrocell4U(0,4)1\SPIM:BSPIM:cnt_enable\ HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_0\/qNet_31/main_24.201
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TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell8U(0,5)1\SPIM:BSPIM:state_0\\SPIM:BSPIM:state_0\/clock_0\SPIM:BSPIM:state_0\/q1.250
Route1\SPIM:BSPIM:state_0\\SPIM:BSPIM:state_0\/qNet_31/main_22.951
macrocell3U(0,5)1Net_31 HOLD0.000
Clock Skew0.000
-
\SPIM:BSPIM:state_0\/q\SPIM:BSPIM:state_0\/main_24.201
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell8U(0,5)1\SPIM:BSPIM:state_0\\SPIM:BSPIM:state_0\/clock_0\SPIM:BSPIM:state_0\/q1.250
macrocell8U(0,5)1\SPIM:BSPIM:state_0\\SPIM:BSPIM:state_0\/q\SPIM:BSPIM:state_0\/main_22.951
macrocell8U(0,5)1\SPIM:BSPIM:state_0\ HOLD0.000
Clock Skew0.000
-
-
-
-
-
-
-
-
-
-
-
-
- - - - - - - - - - - - - - - - - -
SourceDestinationDelay (ns)
m_miso_pin(0)_PAD\SPIM:BSPIM:sR8:Dp:u0\/route_si40.183
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
Route1m_miso_pin(0)_PADm_miso_pin(0)_PADm_miso_pin(0)/pad_in0.000
iocell8P0[0]1m_miso_pin(0)m_miso_pin(0)/pad_inm_miso_pin(0)/fb26.840
Route1Net_20m_miso_pin(0)/fb\SPIM:BSPIM:sR8:Dp:u0\/route_si5.693
datapathcell1U(0,5)1\SPIM:BSPIM:sR8:Dp:u0\ SETUP7.650
Clock Clock path delay0.000
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-
-
-
-
-
-
-
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SourceDestinationDelay (ns)
Net_107/qm_ss_pin(0)_PAD25.727
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell1U(0,5)1Net_107Net_107/clock_0Net_107/q1.250
Route1Net_107Net_107/qm_ss_pin(0)/pin_input5.805
iocell11P0[7]1m_ss_pin(0)m_ss_pin(0)/pin_inputm_ss_pin(0)/pad_out18.672
Route1m_ss_pin(0)_PADm_ss_pin(0)/pad_outm_ss_pin(0)_PAD0.000
Clock Clock path delay0.000
-
Net_30/qm_mosi_pin(0)_PAD25.403
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell2U(0,4)1Net_30Net_30/clock_0Net_30/q1.250
Route1Net_30Net_30/qm_mosi_pin(0)/pin_input6.182
iocell9P0[5]1m_mosi_pin(0)m_mosi_pin(0)/pin_inputm_mosi_pin(0)/pad_out17.971
Route1m_mosi_pin(0)_PADm_mosi_pin(0)/pad_outm_mosi_pin(0)_PAD0.000
Clock Clock path delay0.000
-
Net_31/qm_sclk_pin(0)_PAD24.764
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell3U(0,5)1Net_31Net_31/clock_0Net_31/q1.250
Route1Net_31Net_31/qm_sclk_pin(0)/pin_input5.532
iocell10P0[6]1m_sclk_pin(0)m_sclk_pin(0)/pin_inputm_sclk_pin(0)/pad_out17.982
Route1m_sclk_pin(0)_PADm_sclk_pin(0)/pad_outm_sclk_pin(0)_PAD0.000
Clock Clock path delay0.000
-
-
-
-
-
- - \ No newline at end of file diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_u.sdc b/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_u.sdc deleted file mode 100644 index 5fc7dd3..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/SPI_Design01_u.sdc +++ /dev/null @@ -1,3 +0,0 @@ -# Component constraints for C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\TopDesign\TopDesign.cysch -# Project: C:\Users\Tore\Dropbox\CentroPiaggio\SPI_LSM303D\SPI_Design01\SPI_Design01.cydsn\SPI_Design01.cyprj -# Date: Wed, 16 Jan 2013 13:35:44 GMT diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.c b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.c deleted file mode 100644 index d8f3f98..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.c +++ /dev/null @@ -1,130 +0,0 @@ -/******************************************************************************* -* File Name: m_ss_pin.c -* Version 1.70 -* -* Description: -* This file contains API to enable firmware control of a Pins component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#include "cytypes.h" -#include "m_ss_pin.h" - -/* APIs are not generated for P15[7:6] */ -#if !(CY_PSOC5A &&\ - m_ss_pin__PORT == 15 && (m_ss_pin__MASK & 0xC0)) - -/******************************************************************************* -* Function Name: m_ss_pin_Write -******************************************************************************** -* Summary: -* Assign a new value to the digital port's data output register. -* -* Parameters: -* prtValue: The value to be assigned to the Digital Port. -* -* Return: -* void -* -*******************************************************************************/ -void m_ss_pin_Write(uint8 value) -{ - uint8 staticBits = m_ss_pin_DR & ~m_ss_pin_MASK; - m_ss_pin_DR = staticBits | ((value << m_ss_pin_SHIFT) & m_ss_pin_MASK); -} - - -/******************************************************************************* -* Function Name: m_ss_pin_SetDriveMode -******************************************************************************** -* Summary: -* Change the drive mode on the pins of the port. -* -* Parameters: -* mode: Change the pins to this drive mode. -* -* Return: -* void -* -*******************************************************************************/ -void m_ss_pin_SetDriveMode(uint8 mode) -{ - CyPins_SetPinDriveMode(m_ss_pin_0, mode); -} - - -/******************************************************************************* -* Function Name: m_ss_pin_Read -******************************************************************************** -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. -* -* Parameters: -* void -* -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro m_ss_pin_ReadPS calls this function. -* -*******************************************************************************/ -uint8 m_ss_pin_Read(void) -{ - return (m_ss_pin_PS & m_ss_pin_MASK) >> m_ss_pin_SHIFT; -} - - -/******************************************************************************* -* Function Name: m_ss_pin_ReadDataReg -******************************************************************************** -* Summary: -* Read the current value assigned to a Digital Port's data output register -* -* Parameters: -* void -* -* Return: -* Returns the current value assigned to the Digital Port's data output register -* -*******************************************************************************/ -uint8 m_ss_pin_ReadDataReg(void) -{ - return (m_ss_pin_DR & m_ss_pin_MASK) >> m_ss_pin_SHIFT; -} - - -/* If Interrupts Are Enabled for this Pins component */ -#if defined(m_ss_pin_INTSTAT) - - /******************************************************************************* - * Function Name: m_ss_pin_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. - * - * Parameters: - * void - * - * Return: - * Returns the value of the interrupt status register - * - *******************************************************************************/ - uint8 m_ss_pin_ClearInterrupt(void) - { - return (m_ss_pin_INTSTAT & m_ss_pin_MASK) >> m_ss_pin_SHIFT; - } - -#endif /* If Interrupts Are Enabled for this Pins component */ - -#endif -/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.h deleted file mode 100644 index 4520034..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin.h +++ /dev/null @@ -1,125 +0,0 @@ -/******************************************************************************* -* File Name: m_ss_pin.h -* Version 1.70 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#if !defined(CY_PINS_m_ss_pin_H) /* Pins m_ss_pin_H */ -#define CY_PINS_m_ss_pin_H - -#include "cytypes.h" -#include "cyfitter.h" -#include "cypins.h" -#include "m_ss_pin_aliases.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v1_70 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - -/* APIs are not generated for P15[7:6] */ -#if !(CY_PSOC5A &&\ - m_ss_pin__PORT == 15 && (m_ss_pin__MASK & 0xC0)) - -/*************************************** -* Function Prototypes -***************************************/ - -void m_ss_pin_Write(uint8 value) ; -void m_ss_pin_SetDriveMode(uint8 mode) ; -uint8 m_ss_pin_ReadDataReg(void) ; -uint8 m_ss_pin_Read(void) ; -uint8 m_ss_pin_ClearInterrupt(void) ; - -/*************************************** -* API Constants -***************************************/ - -/* Drive Modes */ -#define m_ss_pin_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define m_ss_pin_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define m_ss_pin_DM_RES_UP PIN_DM_RES_UP -#define m_ss_pin_DM_RES_DWN PIN_DM_RES_DWN -#define m_ss_pin_DM_OD_LO PIN_DM_OD_LO -#define m_ss_pin_DM_OD_HI PIN_DM_OD_HI -#define m_ss_pin_DM_STRONG PIN_DM_STRONG -#define m_ss_pin_DM_RES_UPDWN PIN_DM_RES_UPDWN - -/* Digital Port Constants */ -#define m_ss_pin_MASK m_ss_pin__MASK -#define m_ss_pin_SHIFT m_ss_pin__SHIFT -#define m_ss_pin_WIDTH 1u - -/*************************************** -* Registers -***************************************/ - -/* Main Port Registers */ -/* Pin State */ -#define m_ss_pin_PS (* (reg8 *) m_ss_pin__PS) -/* Data Register */ -#define m_ss_pin_DR (* (reg8 *) m_ss_pin__DR) -/* Port Number */ -#define m_ss_pin_PRT_NUM (* (reg8 *) m_ss_pin__PRT) -/* Connect to Analog Globals */ -#define m_ss_pin_AG (* (reg8 *) m_ss_pin__AG) -/* Analog MUX bux enable */ -#define m_ss_pin_AMUX (* (reg8 *) m_ss_pin__AMUX) -/* Bidirectional Enable */ -#define m_ss_pin_BIE (* (reg8 *) m_ss_pin__BIE) -/* Bit-mask for Aliased Register Access */ -#define m_ss_pin_BIT_MASK (* (reg8 *) m_ss_pin__BIT_MASK) -/* Bypass Enable */ -#define m_ss_pin_BYP (* (reg8 *) m_ss_pin__BYP) -/* Port wide control signals */ -#define m_ss_pin_CTL (* (reg8 *) m_ss_pin__CTL) -/* Drive Modes */ -#define m_ss_pin_DM0 (* (reg8 *) m_ss_pin__DM0) -#define m_ss_pin_DM1 (* (reg8 *) m_ss_pin__DM1) -#define m_ss_pin_DM2 (* (reg8 *) m_ss_pin__DM2) -/* Input Buffer Disable Override */ -#define m_ss_pin_INP_DIS (* (reg8 *) m_ss_pin__INP_DIS) -/* LCD Common or Segment Drive */ -#define m_ss_pin_LCD_COM_SEG (* (reg8 *) m_ss_pin__LCD_COM_SEG) -/* Enable Segment LCD */ -#define m_ss_pin_LCD_EN (* (reg8 *) m_ss_pin__LCD_EN) -/* Slew Rate Control */ -#define m_ss_pin_SLW (* (reg8 *) m_ss_pin__SLW) - -/* DSI Port Registers */ -/* Global DSI Select Register */ -#define m_ss_pin_PRTDSI__CAPS_SEL (* (reg8 *) m_ss_pin__PRTDSI__CAPS_SEL) -/* Double Sync Enable */ -#define m_ss_pin_PRTDSI__DBL_SYNC_IN (* (reg8 *) m_ss_pin__PRTDSI__DBL_SYNC_IN) -/* Output Enable Select Drive Strength */ -#define m_ss_pin_PRTDSI__OE_SEL0 (* (reg8 *) m_ss_pin__PRTDSI__OE_SEL0) -#define m_ss_pin_PRTDSI__OE_SEL1 (* (reg8 *) m_ss_pin__PRTDSI__OE_SEL1) -/* Port Pin Output Select Registers */ -#define m_ss_pin_PRTDSI__OUT_SEL0 (* (reg8 *) m_ss_pin__PRTDSI__OUT_SEL0) -#define m_ss_pin_PRTDSI__OUT_SEL1 (* (reg8 *) m_ss_pin__PRTDSI__OUT_SEL1) -/* Sync Output Enable Registers */ -#define m_ss_pin_PRTDSI__SYNC_OUT (* (reg8 *) m_ss_pin__PRTDSI__SYNC_OUT) - - -#if defined(m_ss_pin__INTSTAT) /* Interrupt Registers */ - - #define m_ss_pin_INTSTAT (* (reg8 *) m_ss_pin__INTSTAT) - #define m_ss_pin_SNAP (* (reg8 *) m_ss_pin__SNAP) - -#endif /* Interrupt Registers */ - -#endif /* End Pins m_ss_pin_H */ - -#endif -/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin_aliases.h b/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin_aliases.h deleted file mode 100644 index 754ab30..0000000 --- a/PSOC5_SPI_LSM303D.cydsn/codegentemp/m_ss_pin_aliases.h +++ /dev/null @@ -1,30 +0,0 @@ -/******************************************************************************* -* File Name: m_ss_pin.h -* Version 1.70 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#if !defined(CY_PINS_m_ss_pin_ALIASES_H) /* Pins m_ss_pin_ALIASES_H */ -#define CY_PINS_m_ss_pin_ALIASES_H - -#include "cytypes.h" -#include "cyfitter.h" - -/*************************************** -* Constants -***************************************/ -#define m_ss_pin_0 m_ss_pin__0__PC - -#endif /* End Pins m_ss_pin_ALIASES_H */ - -/* [] END OF FILE */ diff --git a/PSOC5_SPI_LSM303D.cydsn/main.c b/PSOC5_SPI_LSM303D.cydsn/main.c index ef7daf4..3421ec1 100644 --- a/PSOC5_SPI_LSM303D.cydsn/main.c +++ b/PSOC5_SPI_LSM303D.cydsn/main.c @@ -30,7 +30,7 @@ void main() //isr_1_Start(); /* Initializing the ISR */ UART_1_Start(); /* Enabling the UART */ - UART_1_PutString("START\n"); + //UART_1_PutString("START\n"); LCD_Position(0u,0u); LCD_PrintString("START.."); @@ -63,35 +63,40 @@ void main() start_acc(5); start_acc(6); + int i; + + UART_1_PutString("START\r\n"); while(1u){ - - - read_acc(0); + Iread_acc(0); //CyDelay(300); - read_acc(1); + Iread_acc(1); //CyDelay(300); - read_acc(2); + Iread_acc(2); //CyDelay(300); - read_acc(3); + Iread_acc(3); //CyDelay(300); - read_acc(4); + Iread_acc(4); //CyDelay(300); - read_acc(5); + Iread_acc(5); //CyDelay(300); - read_acc(6); + Iread_acc(6); + + CyDelay(200); + UART_1_PutString("\r\n"); + //Timer_1_WriteCounter(0); //Timer_1_Start(); //CyDelay(5); //uint16 counter = Timer_1_ReadCounter(); //Timer_1_WriteCounter(0); //Timer_1_Stop(); - LCD_Position(0u,0u); - LCD_PrintInt16(counter); + //LCD_Position(0u,0u); + //LCD_PrintInt16(counter); - CyDelay(1000); + //CyDelay(1000); } } @@ -161,6 +166,150 @@ void read_acc (uint8 n) SS_Write(n); // select SS CyDelay(5); + low = ReadControlRegister(RCR,LSM303D_OUT_X_L_A); // Low + CyDelay(5); + high = ReadControlRegister(RCR,LSM303D_OUT_X_H_A); // High + + two_c = (high << 8 | low); + + /* + LCD_Position(1u,0u); + LCD_PrintInt8(high); + LCD_Position(1u,2u); + LCD_PrintInt8(low); + + + sign = high >> 7; + + if(sign != 0) // negative result, form two's complement + { + two_c ^= 0xFFFF; // low = low XOR 0xFF + two_c++; + sign = 1; + } + + //two_c >>= 1; // make into whole degrees + + */ + + sprintf(OutputString, "%i", n); + //UART_1_PutString("#"); + UART_1_PutString(OutputString); + UART_1_PutString(","); + + sprintf(OutputString, "%04X", two_c); + + //if (sign == 1) { UART_1_PutString("-"); } + //if (sign == 0) { UART_1_PutString("+"); } + UART_1_PutString(OutputString); + + low = 0; + high = 0; + two_c = 0; + strcpy(OutputString, ""); + + + + // READ Y + + low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low + CyDelay(5); + high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High + + two_c = (high << 8 | low); + + /* + LCD_Position(1u,5u); + LCD_PrintInt8(high); + LCD_Position(1u,7u); + LCD_PrintInt8(low); + + + + sign = high >> 7; + + if(sign != 0) // negative result, form two's complement + { + two_c ^= 0xFFFF; // low = low XOR 0xFF + two_c ++; + sign = 1; + } + + //two_c >>= 1; // make into whole degrees + */ + sprintf(OutputString, "%04X", two_c); + UART_1_PutString(","); + //if (sign == 1) { UART_1_PutString("-"); } + //if (sign == 0) { UART_1_PutString("+"); } + UART_1_PutString(OutputString); + + low = 0; + high = 0; + two_c = 0; + strcpy(OutputString, ""); + + // -------- + + + + // READ Z + low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low + CyDelay(5); + high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High + + two_c = (high << 8 | low); + + /* + LCD_Position(1u,10u); + LCD_PrintInt8(high); + LCD_Position(1u,12u); + LCD_PrintInt8(low); + + sign = high >> 7; + + if(sign != 0) // negative result, form two's complement + { + two_c ^= 0xFFFF; // low = low XOR 0xFF + two_c ++; + sign = 1; + } + + //two_c >>= 1; // make into whole degrees + */ + + sprintf(OutputString, "%04X", two_c); + UART_1_PutString(","); + //if (sign == 1) { UART_1_PutString("-"); } + //if (sign == 0) { UART_1_PutString("+"); } + UART_1_PutString(OutputString); + + UART_1_PutString("\r\n"); + + low = high = two_c = 0; + strcpy(OutputString, ""); + + //UART_1_PutString("\r\n"); +} + + + +void Iread_acc (uint8 n) +{ + //uint8 i = 0u; + uint8 value = 0; + uint8 low, high; + uint16 two_c = 0; + char OutputString[7]; + int sign; + + //uint8 low2, high2; + //uint16 two_c2 = 0; + + strcpy(OutputString, ""); + + SS_Write(n); // select SS + CyDelay(5); + LCD_Position(0u,0u); LCD_PrintString("#"); @@ -206,7 +355,7 @@ void read_acc (uint8 n) // READ Y - low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low + low = ReadControlRegister(RCR,LSM303D_OUT_Y_L_A); // Low CyDelay(5); high = ReadControlRegister(RCR,LSM303D_OUT_Y_H_A); // High @@ -232,18 +381,18 @@ void read_acc (uint8 n) if (sign == 1) { UART_1_PutString("-"); } if (sign == 0) { UART_1_PutString("+"); } UART_1_PutString(OutputString); - - low = 0; + + low = 0; high = 0; two_c = 0; strcpy(OutputString, ""); - - // -------- - - - - // READ Z - low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low + + // -------- + + + + // READ Z + low = ReadControlRegister(RCR,LSM303D_OUT_Z_L_A); // Low CyDelay(5); high = ReadControlRegister(RCR,LSM303D_OUT_Z_H_A); // High @@ -269,18 +418,17 @@ void read_acc (uint8 n) if (sign == 1) { UART_1_PutString("-"); } if (sign == 0) { UART_1_PutString("+"); } UART_1_PutString(OutputString); - + UART_1_PutString("\r\n"); low = high = two_c = 0; strcpy(OutputString, ""); - + - UART_1_PutString("\r\n"); + UART_1_PutString("\r\n"); } - // This function reads data from Control Register // Depending on register set bank before uint8 ReadControlRegister(uint8 opcode, uint8 address) diff --git a/PSOC5_SPI_LSM303D.cywrk.SB b/PSOC5_SPI_LSM303D.cywrk.SB index dde0891..7e1bfa8 100644 --- a/PSOC5_SPI_LSM303D.cywrk.SB +++ b/PSOC5_SPI_LSM303D.cywrk.SB @@ -13,16 +13,14 @@ Output - + PSOC5_SPI_LSM303D PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D.cydwr -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files\device.h PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files\main.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5 PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Clock_1\Clock_1.c PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Clock_1\Clock_1.h @@ -136,46 +134,9 @@ PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\TopDesign.cysch PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D.cydwr PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Header Files\device.h PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Source Files\main.c PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5 -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Clock_1 -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\cy_boot -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD\LCD.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD\LCD.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD\LCD_PM.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD_LCDPort -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD_LCDPort\LCD_LCDPort.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD_LCDPort\LCD_LCDPort.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\LCD_LCDPort\LCD_LCDPort_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_miso_pin -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_miso_pin\m_miso_pin.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_miso_pin\m_miso_pin.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_miso_pin\m_miso_pin_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_mosi_pin -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_mosi_pin\m_mosi_pin.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_mosi_pin\m_mosi_pin.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_mosi_pin\m_mosi_pin_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_sclk_pin -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_sclk_pin\m_sclk_pin.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_sclk_pin\m_sclk_pin.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\m_sclk_pin\m_sclk_pin_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_1 -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_1\Pin_1.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_1\Pin_1.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_1\Pin_1_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_2 -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_2\Pin_2.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_2\Pin_2.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_2\Pin_2_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_3 -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_3\Pin_3.c -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_3\Pin_3.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_3\Pin_3_aliases.h -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\Generated_Source\PSoC5\Pin_4 @@ -224,6 +185,7 @@ PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_4.lst PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_5.lst PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_6.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_7.lst PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM.lst PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_INT.lst PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_IntClock.lst @@ -244,7 +206,49 @@ PSOC5_SPI_LSM303D PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D -PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D.rpt +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441 +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Clock_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Cm3Start.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\core_cm3.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyBootAsmGnu.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyDmac.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyfitter_cfg.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyFlash.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CyLib.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyPm.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\CySpc.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\cyutils.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD_LCDPort.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\LCD_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_miso_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_mosi_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\m_sclk_pin.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\main.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_2.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_3.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_4.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_5.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_6.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Pin_7.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_INT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_IntClock.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SPIM_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\SS.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Timer_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\Timer_1_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_BOOT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_INT.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\Listing Files\UART_1_PM.lst +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.elf +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.hex +PSOC5_SPI_LSM303D\PSOC5_SPI_LSM303D\CortexM3\ARM_GCC_441\Debug\PSOC5_SPI_LSM303D.map