lhs.txt

; Listing all replacements for main
; Using solver: Z3 + external cache + internal cache

; *****
; For LLVM instruction:
;  %current.0 = phi i32 [ 0, %0 ], [ %inc, %1 ]
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
infer %0

; *****
; For LLVM instruction:
;  %mul = mul nsw i32 %current.0, %current.0
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = mulnsw %0, %0
infer %1

; *****
; For LLVM instruction:
;  %rem = urem i32 %mul, 1000000
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = mulnsw %0, %0 (hasExternalUses)
%2:i32 = urem %1, 1000000:i32
infer %2

; *****
; For LLVM instruction:
;  %cmp = icmp ne i32 %rem, 269696
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = mulnsw %0, %0 (hasExternalUses)
%2:i32 = urem %1, 1000000:i32
%3:i1 = ne 269696:i32, %2
infer %3

; *****
; For LLVM instruction:
;  %cmp1 = icmp ne i32 %mul, 2147483647
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = mulnsw %0, %0 (hasExternalUses)
%2:i1 = ne 2147483647:i32, %1
infer %2

; *****
; For LLVM instruction:
;  %2 = and i1 %cmp1, %cmp
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = mulnsw %0, %0
%2:i32 = urem %1, 1000000:i32
%3:i1 = ne 269696:i32, %2
%4:i1 = ne 2147483647:i32, %1
%5:i1 = and %3, %4
infer %5

; *****
; For LLVM instruction:
;  %inc = add nuw nsw i32 %current.0, 1
; Generating replacement:
%0:i32 = var (knownBits=0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) (nonNegative) (range=[0,-2147483648))
%1:i32 = addnw 1:i32, %0
infer %1